LMH7220 High Speed Comparator with LVDS Output General Description Features The LMH7220 is a high speed, low power comparator with an operating supply voltage range of 2.7V to 12V. The LMH7220 has a differential, LVDS output, driving 325 mV into a 100Ω symmetrical transmission line. The LMH7220 has a 2.9 ns propagation delay and 0.6 ns rise and fall times while the supply current is only 6.8 mA at 5V (load current excluded). (VS = 5V TA = 25˚C, Typical values unless otherwise specified) n Propagation delay @ 100 mV overdrive 2.9 ns n Rise and fall times 0.6 ns n Supply voltage 2.7V to 12V n Supply current 6.8 mA n Temperature range −40˚C to 125˚C n LVDS output The LMH7220 inputs have a voltage range that extends 200 mV below ground, allowing ground sensing applications. The LMH7220 is available in the 6-Pin TSOT package. ThIs package is ideal where space is a critical item. Applications n n n n n n n Acquisition trigger Fast differential line receiver Pulse height analyzer Peak detector Pulse width modulator Remote threshold detection Oscilloscope triggering Typical Schematic 20137603 © 2006 National Semiconductor Corporation DS201376 www.national.com LMH7220 High Speed Comparator with LVDS Output September 2006 LMH7220 Absolute Maximum Ratings (Note 1) Storage Temperature Range If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Junction Temperature (Note 3) Voltage on any I/O Pin ESD Tolerance (Note 2) Human Body Model Machine Model Supply Voltage (VCC - GND) Differential Input Voltage −65˚C to +150˚C GND−0.2V to VCC+0.2V 150˚C max Operating Ratings (Note 1) 2.5 kV 250V Temperature Range (Note 3) 13.5V Supply Voltage ± 13V Package Thermal Resistance (θJA ) Output Shorted to GND (Note 4) Continuous Output Shorted Together (Note 4) Continuous −40˚C to +125˚C 2.7V to 13V 6-Pin TSOT 189˚C/W +12V DC Electrical Characteristics Unless otherwise specified, all limits are guaranteed for TJ = 25˚C, VCM = 300 mV, −50 mV < VID < +50 mV and RL = 100Ω. Boldface limits apply at the temperature extremes. (Note 6) Symbol Parameter Conditions Min (Note 6) Typ (Note 5) Max (Note 6) −2.1 −0.5 IB Input Bias Current VIN Differential = 0 −5 −7 −500 IOS Input Offset Current VIN Differential = 0 TC IOS Input Offset Current TC VIN Differential = 0 VOS Input Offset Voltage −9.5 Input Offset Voltage TC Input Voltage Range CMRR > 50 dB +9.5 CMRR Common-Mode Rejection Ratio VCM = 0 to VCC−2.2V PSRR Power Supply Rejection Ratio AV Open Loop Gain VO Output Offset Voltage VIN Differential = 50 mV 1125 ∆VO VO Change Between ‘0’ and ‘1’ VIN Differential = ± 50 mV −25 −0.2 mV µV/˚C VCC−2 V 60 70 dB 63 74 dB 59 1225 dB 1325 mV +25 mV 1475 mV 400 mV +25 mV VOH Output Voltage High VIN Differential = 50 mV VOL Output Voltage Low VIN Differential = 50 mV 925 1060 VOD Output Voltage Differential VIN Differential = 50 mV 250 330 ∆VOD VOD Change between ‘0’ to ‘1’ VIN Differential = ± 50 mV −25 ISC Short Circuit Current Output to GND Pin (Note 4) OUT Q to GND Pin VIN Differential = 50 mV 5 OUT Q to GND Pin VIN Differential = 50 mV 5 Output Shorted Together (Note 4) OUT Q to OUT Q VIN Differential = 50 mV 5 Supply Current Load Current Excluded VIN Differential = 50 mV IS nA nA/˚C ± 50 TC VOS µA +500 ±2 VRI Units 1390 7.5 mV 10.0 14.0 mA mA +12V AC Electrical Characteristics Unless otherwise specified, all limits guaranteed for TJ = 25˚C, VCM = 300 mV, −50 mV < VID < +50 mV and RL = 100Ω. Boldface limits apply at the temperature extremes. (Note 6) Symbol TR Parameter Toggle Rate www.national.com Conditions Min (Note 6) Typ (Note 5) Overdrive = ± 50 mV; CL = 2 pF @ 50% Output Swing 860 1080 2 Max (Note 6) Units Mb/s LMH7220 +12V AC Electrical Characteristics (Continued) Unless otherwise specified, all limits guaranteed for TJ = 25˚C, VCM = 300 mV, −50 mV < VID < +50 mV and RL = 100Ω. Boldface limits apply at the temperature extremes. (Note 6) Symbol tPDLH tOD-disp Parameter Propagation Delay tPDLH = (tPDH + tPDL ) / 2 (see figure 3 application note) Input SR = Constant VID start value = −100 mV Input Overdrive Dispersion Conditions Min (Note 6) Typ (Note 5) Overdrive 20 mV 3.56 Overdrive 50 mV 2.98 Overdrive 100 mV 2.7 Overdrive 1V 2.24 @ Overdrive 20 - 100 mV 0.86 @ Overdrive 100 mV - 1V 0.46 Max (Note 6) Units ns 7 ns tSR-disp Input Slew Rate Dispersion 0.05 V/ns to 1 V/ns Overdrive 100 mV 0.24 ns tCM-disp Input Common Mode dispersion SR = 4 V/ns; Overdrive 100 mV VCM = 0 to 10V 0.55 ns ∆tPDLH Q to Q Time Skew | tPDH - tPDL | (Note 8) Overdrive = 100 mV; CL = 2 pF 0 ns ∆tPDHL Q to Q Time Skew | tPDL - tPDH | (Note 8) Overdrive = 100 mV; CL = 2 pF 0.06 ns tr Output Rise Time (20% - 80%) (Note 9) Overdrive = 100 mV; CL = 2 pF 0.56 ns tf Output Fall Time (20% - 80%) (Note 9) Overdrive = 100 mV; CL = 2 pF 0.49 ns +5V DC Electrical Characteristics Unless otherwise specified, all limits guaranteed for TJ = 25˚C, VCM = 300 mV, −50 mV < VID < +50 mV and RL = 100Ω. Boldface limits apply at the temperature extremes. (Note 6) Symbol Parameter Conditions Min (Note 6) Typ (Note 5) Max (Note 6) −1.5 −0.5 IB Input Bias Current VIN Differential = 0 −5 −7 IOS Input Offset Current VIN Differential = 0 −500 TC IOS Input Offset Current TC VIN Differential = 0 VOS Input Offset Voltage TC VOS Input Offset Voltage TC VRI Input Voltage Range CMRR > 50 dB CMRR Common-Mode Rejection Ratio VCM = 0 to VCC−2.2V PSRR Power Supply Rejection Ratio AV Open Loop Gain +500 ±2 −9.5 ± 50 mV VCC−2 V 60 70 dB 63 74 dB 59 dB VO Output Offset Voltage VIN Differential = 50 mV 1125 VO Change Between ‘0’ and ‘1’ VIN Differential = ± 50 mV −25 VOH Output Voltage High VIN Differential = 50 mV VOL Output Voltage Low VIN Differential = 50 mV 925 1060 VOD Output Voltage Differential VIN Differential = 50 mV 250 320 ∆VOD VOD Change between ‘0’ to ‘1’ VIN Differential = ± 50 mV −25 ISC Short Circuit Current Output to GND Pin (Note 4) OUT Q to GND Pin VIN Differential = 50 mV 5 OUT Q to GND Pin VIN Differential = 50 mV 5 OUT Q to OUT Q VIN Differential = 50 mV 5 3 nA µV/˚C ∆VO Output Shorted Together (Note 4) µA nA/˚C +9.5 −0.2 Units 1217 1380 1325 mV +25 mV 1475 mV 400 mV +25 mV mV mA www.national.com LMH7220 +5V DC Electrical Characteristics (Continued) Unless otherwise specified, all limits guaranteed for TJ = 25˚C, VCM = 300 mV, −50 mV < VID < +50 mV and RL = 100Ω. Boldface limits apply at the temperature extremes. (Note 6) Symbol Parameter Supply Current IS Conditions Min (Note 6) Load Current Excluded VIN Differential = 50 mV Typ (Note 5) Max (Note 6) 6.8 9 12.6 Units mA +5V AC Electrical Characteristics Unless otherwise specified, all limits guaranteed for TJ = 25˚C, VCM = 300 mV, −50 mV < VID < +50 mV and RL = 100Ω. Boldface limits apply at the temperature extremes. (Note 6) Symbol Parameter Conditions Min (Note 6) Typ (Note 5) 750 940 TR Toggle Rate Overdrive = ± 50 mV; CL = 2 pF @ 50% Output Swing tPDLH Propagation Delay tPDLH = (tPDH + tPDL ) / 2 (see figure 3 application note) Input SR = Constant VID start value = -100mV Overdrive 20 mV 3.63 Overdrive 50 mV 3.09 Overdrive 100 mV 2.9 Overdrive 1V 2.41 Input Overdrive Dispersion @ Overdrive 20 - 100 mV 0.79 @ Overdrive 100 mV - 1V 0.43 tOD-disp Max (Note 6) Units Mb/s ns 7 ns tSR-disp Input Slew Rate Dispersion 0.05 V/ns to 1 V/ns Overdrive 100 mV 0.20 ns tCM-disp Input Common Mode Dispersion SR = 4 V/ns; Overdrive 100 mV VCM = 0 to 3V 0.21 ns ∆tPDLH Q to Q Time Skew | tPDH - tPDL | (Note 8) Overdrive = 100 mV; CL = 2 pF 0.09 ns ∆tPDHL Q to Q Time Skew | tPDL - tPDH | (Note 8) Overdrive = 100 mV; CL = 2 pF 0.07 ns tr Output Rise Time (20% - 80%) (Note 9) Overdrive = 100 mV; CL = 2 pF 0.59 ns tf Output Fall Time (20% - 80%) (Note 9) Overdrive = 100 mV; CL = 2 pF 0.55 ns +2.7V DC Electrical Characteristics Unless otherwise specified, all limits guaranteed for TJ = 25˚C, VCM = 300 mV, −50 mV < VID < +50 mV and RL = 100Ω. Boldface limits apply at the temperature extremes. (Note 6) Symbol Parameter Conditions Min (Note 6) Typ (Note 5) Max (Note 6) −1.3 −0.5 IB Input Bias Current VIN Differential = 0 −5 −7 −500 IOS Input Offset Current VIN Differential = 0 TC IOS Input Offset Current TC VIN Differential = 0 VOS Input Offset Voltage −9.5 Input Offset Voltage TC Input Voltage Range CMRR > 50 dB +9.5 CMRR Common-Mode Rejection Ratio VCM = 0 to VCC−2.2V PSRR Power Supply Rejection Ratio AV Open Loop Gain VO Output Offset Voltage VIN Differential = 50 mV 1125 ∆VO VO Change Between ‘0’ and ‘1’ VIN Differential = ± 50 mV −25 −0.2 nA mV µV/˚C VCC−2 V 56 70 dB 63 74 dB 59 4 µA nA/˚C ± 50 TC VOS VRI www.national.com +500 ±2 Units 1213 dB 1325 mV +25 mV LMH7220 +2.7V DC Electrical Characteristics (Continued) Unless otherwise specified, all limits guaranteed for TJ = 25˚C, VCM = 300 mV, −50 mV < VID < +50 mV and RL = 100Ω. Boldface limits apply at the temperature extremes. (Note 6) Symbol Parameter Conditions Min (Note 6) Typ (Note 5) Max (Note 6) Units 1370 1475 mV VOH Output Voltage High Average of ‘0’ to ‘1’ VIN Differential = 50 mV VOL Output Voltage Low Average of ‘0’ to ‘1’ VIN Differential = 50 mV 925 1060 VOD Output Voltage Differential VIN Differential = 50 mV 250 315 ∆VOD VOD Change between ‘0’ to ‘1’ VIN Differential = ± 50 mV −25 ISC Short Circuit Current Output to GND Pin (Note 4) OUT Q to GND Pin VIN Differential = 50 mV 5 OUT Q to GND Pin VIN Differential = 50 mV 5 Output Shorted Together (Note 4) OUT Q to OUT Q VIN Differential = 50 mV 5 Supply Current Load Current Excluded VIN Differential = 50 mV IS 6.6 mV 400 mV +25 mV mA 9 12.6 mA +2.7V AC Electrical Characteristics Unless otherwise specified, all limits guaranteed for TJ = 25˚C, VCM = 300 mV, −50 mV < VID < +50 mV and RL = 100Ω. Boldface limits apply at the temperature extremes. (Note 6) Symbol Parameter Conditions Min (Note 6) Typ (Note 5) 700 880 TR Toggle Rate Overdrive = ± 50 mV; CL = 2 pF @ 50% Output Swing tPDLH Propagation Delay tPDLH = (tPDH + tPDL ) / 2 (see figure 3 application note) Input SR = Constant VID start value = -100mV Overdrive 20 mV 3.80 Overdrive 50 mV 3.29 Overdrive 100 mV 3.0 tOD-disp Input Overdrive Dispersion Overdrive 1V 2.60 @ Overdrive 20 - 100 mV 0.83 @ Overdrive 100 mV - 1V 0.37 Max (Note 6) Units Mb/s 7 ns ns tSR-disp Input Slew Rate Dispersion 0.05 V/ns to 1 V/ns Overdrive 100 mV 0.23 ns tCM-disp Input Common Mode dispersion SR = 4 V/ns; Overdrive 100 mV VCM = 0 to 1.5V 0.16 ns ∆tPDLH Q to Q Time Skew | tPDH - tPDL | (Note 8) Overdrive = 100 mV; CL = 2 pF 0.09 ns ∆tPDHL Q to Q Time Skew | tPDL - tPDH | (Note 8) Overdrive = 100 mV; CL = 2 pF 0.09 ns tr Output Rise Time (20% - 80%) (Note 9) Overdrive = 100 mV; CL = 2 pF 0.64 ns tf Output Fall Time (20% - 80%) (Note 9) Overdrive = 100 mV; CL = 2 pF 0.59 ns 5 www.national.com LMH7220 Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Conditions indicate specifications for which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test conditions, see the Electrical Characteristics. Note 2: Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC) Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC) Note 3: The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board. Note 4: Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150˚C. Note 5: Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not guaranteed on shipped production material. Note 6: All limits are guaranteed by testing or statistical analysis. Note 7: Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables under conditions of internal self heating where TJ > TA. See applications section for information on temperature de-rating of this device. Note 8: Propagation Delay Skew, ∆tPD, is defined as the average of ∆tPDLH and ∆tPDHL. Note 9: The rise or fall time is the average of the Q and Q rise or fall time. Diagrams Schematic Diagram Connection Diagram 20137601 20137602 Ordering Information Package 6-Pin TSOT www.national.com Part Number Temperature Range (TA) −40˚C to +85˚C LMH7220MK LMH7220MKX Package Marking C29A 6 Transport Media 1k Units Tape and Reel 3k Units Tape and Reel NSC Drawing MK06A LMH7220 Typical Performance Characteristics At TJ = 25˚C; unless otherwise specified: VCM = 0.3V, VOVERDRIVE = 100 mV, RL = 100Ω. Input Current vs. Differential Input Voltage Bias Current vs. Supply Voltage 20137621 20137636 Bias Current vs. Temperature Output Offset Voltage vs. Supply Voltage 20137623 20137624 Output Offset Voltage vs. Temperature Differential Output Voltage vs. Supply Voltage 20137625 20137626 7 www.national.com LMH7220 Typical Performance Characteristics (Continued) Differential Output Voltage vs. Temperature Supply Current vs. Supply Voltage 20137627 20137628 Supply Current vs. Temperature Rise & Fall Time vs. Temperature 20137629 20137630 Propagation Delay vs. Temperature Propagation Delay vs. Overdrive Voltage 20137631 www.national.com 20137632 8 LMH7220 Typical Performance Characteristics (Continued) Propagation Delay vs. Common Mode Voltage Propagation Delay vs. Slew Rate 20137633 20137634 Pulse Response Over Temperature 20137635 9 www.national.com LMH7220 Application Information INTRODUCTION The LMH7220 is a high speed comparator with LVDS outputs. The LVDS (Low Voltage Differential Signaling) standard uses differential outputs with a voltage swing of approximately 325 mV on each output. The most widely used setup for LVDS outputs consists of a switched current source of 3.25 mA. The output pins need to be differentially terminated with an external 100Ω resistor, producing the standardized output voltage swing of 325 mV. The common mode level of both outputs is about 1.2V, and is independent of the power supply voltage. The use of complementary outputs gives a high level of suppression for common mode noise. The very fast rise and fall times of the LMH7220 enable data transmission rates up to several hundreds of Megabits per second (Mbps). Due to the current-nature of the outputs the power consumption remains at a very low level even if the data transmission rate is rising. Power delivered to a load resistance of 100Ω is only 1.2 mW. More information about the LVDS standard can be found on the National site: 20137610 FIGURE 1. Equivalent Input Circuitry The output can be seen as a bridge configuration in which switches are crosswise closed, producing the differential LVDS logic high and low levels (see Figure 2). The output switches are fed at top and bottom by two current sources. The top one is fixed and determines the differential voltage across the external load resistor. The other one is regulated and determines the common-mode voltage on the outputs. It is essential to keep the output common-mode voltage at the defined standardized LVDS level under all circumstances. To realize this, both outputs are internally connected together via two equal resistors. At the midpoint this produces the common mode output voltage, which is made equal to VREF (1.2V) by means of the CM feedback loop. http://www.national.com/appinfo/lvds/0,1798,100,00.html The LMH7220 inputs have a common mode voltage range that extends 200 mV below the negative supply voltage thus allowing ground sensing in case of single supply. The rise and fall times of the LMH7220 are about 0.6 ns, while the propagation delay time is about 2.7 ns. The LMH7220 can operate over the full supply voltage range of 2.7V to 12V, while using single or dual supply voltages. The LVDS outputs refer to the negative supply rail. The supply current is 6.8 mA at 5V (load current excluded). The LMH7220 is available in the 6-Pin TSOT package. This package is ideal where space is an important issue. In the next sections the following issues are discussed: • In- and output topology • Definition of terms of used specifications • Propagation delay and dispersion • Hysteresis and oscillations • The output • Applying transmission lines • PCB layout INPUT & OUTPUT TOPOLOGY All input and output pins are protected against excessive voltages by ESD diodes. These diodes are connected from the negative supply to the positive supply. As can be seen in Figure 1, both inputs are connected to these diodes. Protection against excessive supply voltages is provided by a power clamp between VCC and GND. Both inputs are also connected to the bases of the input transistors of the differential pair via 1.5 kΩ resistors. The input transistors cannot withstand high reverse voltages between bases and emitter, due to their high frequency properties. To protect the input stage against damage, both bases are connected together by a string of anti-parallel diodes. Be aware of situations in which differential input voltage level is such that these diodes are conducting. In this case the input current is raised far above the normal value stated in the datasheet tables. www.national.com 20137611 FIGURE 2. Equivalent Output Circuitry 10 supply voltages containing a separate set of data per supply voltage. In the table below is a list of abbreviations of the measured parameters and a short description of the conditions which are applied for measuring them . Following this table several parameters are highlighted to explain more clearly what it means exactly and what effects such a phenomena can have for any applied electronic circuit. (Continued) DEFINITIONS For a good understanding of many parameters of the LMH7220 it is necessary to perform a lot of measurements. All of those parameters are listed in the data tables in the first part of the datasheet. There are different tables for several Symbol Text Description IB Input Bias Current Current flowing in or out the input pins, when both biased at 0.3 Volt above GND IOS Input Offset Current Difference between the positive- and the negative input currents needed to make the outputs change state, averaged for H to L and L to H transitions TC IOS Average Input Offset Current Drift Temperature Coefficient of IOS VOS Input Offset Voltage Voltage difference needed between IN+ and IN− to make the outputs change state, averaged for H to L and L to H transitions TC VOS Average Input Offset Voltage Drift Temperature Coefficient of VOS CMRR Common Mode Rejection Ratio Ratio of input offset voltage change and input common mode voltage change VRI Input Voltage Range Upper and lower limits of the input voltage are defined as where CMRR drops below 50 dB. PSRR Power Supply Rejection Ratio Ratio of input offset voltage change and supply voltage change from VS-MIN to VS-MAX VO Output Offset Voltage Output Common Mode Voltage averaged for logic ‘0’ and logic ‘1’ levels (See Figure 12) ∆VO Change in Output Offset Voltage Difference in Output Common Mode Voltage between logic ‘0’ and logic ‘1’ levels (See Figure 13) VOH Output Voltage High High state single ended output voltage (Q or Q) (See Figure 12) VOL Output Voltage Low Low state single ended output voltage (Q or Q) (See Figure 12) VODH Output Differential Voltage logic ‘1’ VOH(Q) – VOL(Q) (logic level ‘1’) (See Figure 13) VODL Output Differential Voltage logic ‘0’ VOH(Q) – VOL(Q) (logic level ‘0’) (See Figure 13) VOD Average of VODH and VODL (VODH + VODL) / 2 ∆VOD Change in VOD between ‘0’ and ‘1’ |VODH – VODL| (See Figure 13) Hyst Hysteresis Difference in input switching levels for L to H and H to L transitions. (See Figure 11) ISQG, ISQG Short Circuit Current one output to GND Current that flows from one output to GND if shorted single ended ISQQ Short Circuit Current outputs together Current flowing between output Q and output Q if shorted differentially TR Maximum Toggle Rate Maximum frequency at which the outputs can toggle before VOD drops under 50% of the nominal value. PW Pulse Width Time from 50% of the rising edge of a signal to 50% of the falling edge tPDH resp tPDL Propagation Delay Delay time between the moment the input signal crosses the switching level L to H and the moment the output signal crosses 50% of the rising edge of Q output (tPDH), or delay time between the moment the input signal crosses the switching level H to L and the moment the output signal crosses 50% of the falling edge of Q output (tPDL) tPDL resp tPDH Delay time between the moment the input signal crosses the switching level L to H and the moment the output signal crosses 50% of the falling edge of Q output (tPDL), or delay time between the moment the input signal crosses the switching level H to L and the moment the output signal crosses 50% of the rising edge of Q output (tPDH) 11 www.national.com LMH7220 Application Information LMH7220 Application Information Symbol (Continued) Text Description tPDLH Average of tPDH and tPDL tPDHL Average of tPDL and tPDH tPD Average of tPDLH and tPDHL tPDHd resp tPDLd Delay time between the moment the input signal crosses the switching level L to H and the zero crossing of the rising edge of the differential output signal (tPDHd), or delay time between the moment the input signal crosses the switching level H to L and the zero crossing of the falling edge of the differential output signal (tPDLd) ∆tPDLH resp ∆tPDHL Q to Q time skew Time skew between 50% levels of rising edge of Q output and falling edge of Q output (∆tPDLH ), or time skew between 50% levels of falling edge of Q output and rising edge of Q output (∆tPDHL) ∆tPD Average Q to Q time skew Average of tPDLH and tPDHL for L to H and H to L transients ∆tPDd Average diff. time skew Average of tPDHd and tPDLd for L to H and H to L transients tOD-disp Input overdrive dispersion Change in tPD for different overdrive voltages at the input pins tSR-disp Input slew rate dispersion Change in tPD for different slew rates at the input pins tCM-disp Input Common Mode dispersion Change in tPD for different common mode voltages at the input pins tr / trd Output rise time (20% - 80%) Time needed for the (single ended or differential) output voltage to change from 20% of its nominal value to 80% tf / tfd Output fall time (20% - 80%) Time needed for the (single ended or differential) output voltage to change from 80% of its nominal value to 20% 20137620 FIGURE 3. Propagation Delay Definition DELAY AND DISPERSION Comparators are widely used to connect the analog world to the digital one. The accuracy of a comparator is dictated by its DC properties such as offset voltage and hysteresis and by its timing aspects such as rise and fall times and delay. For low frequency applications most comparators are much faster than the analog input signals they handle. The timing www.national.com aspects are less important here than the accuracy of the input switching levels. The higher the frequency, the more important the timing properties of the comparator become, because the response of the comparator can give e.g. a noticeable change in time frame or duty cycle. A designer has to know these effects in order to deal with them. In order to predict what the output signal will do compared to the 12 LMH7220 Application Information (Continued) input signal, several parameters are defined which describe the behavior of the comparator. For a good understanding of the timing parameters discussed in the following section, a brief explanation is given and several timing diagrams are shown for clarification. PROPAGATION DELAY The propagation delay parameter is defined as the time it takes for the comparator to change the output level halfway in its transition from L to H or H to L, in reaction to the moment the input signal crosses the switching level. Due to this definition there are two parameters, tPDH and tPDL (Figure 4). Both parameters don’t necessarily have the same value. It is possible that differences will occur due to a different response of the internal circuitry. As a result of this effect another parameter is defined: ∆tPD. This parameter is defined as the absolute value of the difference between tPDH and tPDL. 20137612 FIGURE 5. Propagation Delay Both output circuits should be symmetrical. At the moment one output is switching ‘on’ the other is switching ‘off’ with ideally no skew between them. The design of the LMH7220 is optimized to minimize this timing difference. Propagation delay tPD is defined as the average delay of both outputs at both slopes: (tPDLH + tPDHL) / 2. DISPERSION There are several circumstances that will produce a variation of the propagation delay time. This effect is called dispersion. 20137604 FIGURE 4. Pulse Parameter Amplitude Overdrive Dispersion One of the parameters that causes dispersion is the amplitude variation of the input signal. Figure 6 shows the dispersion due to a variation of the input overdrive voltage. The overdrive is defined as the ‘goto’ differential voltage applied to the inputs. Figure 6 shows the impact it has on the propagation delay time if overdrive is varied from 10 millivolts to 100 millivolts. This parameter is measured with a constant slew rate of the input signal. If ∆tPD isn’t zero, duty cycle distortion will occur. For example when applying a symmetrical waveform (e.g. a sinewave) at the input, it is expected that the comparator produces a symmetrical square wave at the output with a duty cycle of 50%. In case of different tPDH and tPDL the duty cycle of the output signal will not remain at 50%, but will be lower or higher. In addition to the propagation delay parameters for single ended outputs discussed before, there are other parameters in case of complementary outputs. These parameters describe the delay from input to each of the outputs and the difference between both delay times (see Figure 5). When the differential input signal crosses the reference level from L to H, both outputs will switch to their new state with some delay. This is defined as tPDH for the Q output and tPDL for the Q output, while the difference between both signals is defined as ∆tPDLH. similar definitions for the falling slope of the input signal can be seen in Figure 3. 13 www.national.com LMH7220 Application Information change per time unit (dV/dt) but also a small maximum switching current (overdrive) in the input transistors. High amplitudes produce a high dV/dt and a bigger overdrive. (Continued) Common Mode Dispersion Dispersion will also occur when changing the common mode level of the input signal (Figure 8). When VREF is swept through the CMVR (Common Mode Voltage Range), this results in a variation of the propagation delay time. This variation is called Common Mode Dispersion. 20137607 FIGURE 6. Overdrive Dispersion The overdrive dispersion is caused by the fact that switching currents in the input stage depend on the level of the differential input signal. Slew Rate Dispersion The slew rate is another parameter that affects propagation delay. The higher the input slew rate, the faster the input stage switches (Figure 7). 20137609 FIGURE 8. Common Mode Dispersion All of the dispersion effects discussed before influence the propagation delay. In practice the dispersion is often caused by a combination of more than one varied parameter. It is good to realize this if there is the need to predict how much dispersion a circuit will show. HYSTERESIS & OSCILLATIONS In contrast to an op amp, the output of a comparator has only two defined states ‘0’ or ‘1’. Due to finite comparator gain however, there will be a small band of input differential voltage where the output is in an undefined state. An input signal with fast slopes will pass this band very quickly without problems. During slow slopes however, passing the band of uncertainty can be relatively long. This enables the comparator outputs to switch back and forth several times between ‘0’ and ‘1’ on a single slope. The comparator will switch on its input noise, ground bounce (possible oscillations), ringing etc. Noise in the input signal will also contribute to these undesired switching effects. In the next sections an explanation follows about these phenomena in situations where no hysteresis is applied, and the possible improvement hysteresis can give. 20137608 FIGURE 7. Slew Rate Dispersion Using No Hysteresis In Figure 9 can be seen what happens when the input signal rises from just under the threshold VREF to a level just above it. From the moment the input reaches the lowest dotted line around VREF at t=0, the output toggles on noise etc. Toggling ends when the input signal leaves the undefined area at t=1. A combination of overdrive- and slew rate dispersion occurs when applying signals with different amplitude at constant frequency. A small amplitude will produce a small voltage www.national.com 14 The divider RF-RP feeds back a portion of the output voltage to the positive input. Only a small part of the output voltage is needed, just enough to avoid the area at which the input is in an undefined state. Assuming this is only a few millivolts, it is sufficient to add (plus or minus) 10 mV to the positive input to prevent the circuit from oscillations. If the output switches between 0V and 5V and the choice for one of the resistors is done the other can be calculated. Assume RP is 50Ω then RF is 25 kΩ for 10 mV threshold on the positive input. The situation of Figure 11 is now created. (Continued) In this example the output was fast enough to toggle three times. Due to this behavior digital circuitry connected to the output will count a wrong number of pulses. One way to prevent this is to choose a very slow comparator with an output that is not able to switch more than once between ‘0’ and ‘1’ during the time the input state is undefined. 20137615 20137614 FIGURE 11. Hysteresis FIGURE 9. Oscillations & Noise In this picture there are two dotted lines A and B, both indicating the resulting level at the positive input. When the signal at the negative input is low, the state of the input stage is well defined with the negative input much lower than the positive input. As a result the output will be in the high state. The positive input is at level A. With the input signal sloping up, this situation remains until VIN crosses level A at t=1. Now the output toggles, and the voltage at the positive input is lowered to level B. So before the output has the possibility to toggle again, the difference between both inputs is made sufficient to have a stable situation again. When the input signal comes down from high to low, the situation is stable until level B is reached at t=0. At this moment the output will toggle back, and the circuit is back in the start situation with the negative input at a much lower level than the positive one. In the situation without hysteresis, the output would toggle exactly at VREF. With hysteresis this happens at the introduced levels A and B, as can be seen in Figure 11. Varying the levels A and B will also vary the timing of t=0 and t=1. When designing a circuit be aware of this effect. Introducing hysteresis will cause some time shifts between output and input (e.g. duty cycle variations), but eliminates undesired switching of the output. In most circumstances this is not an option because the slew rate of the input signal will vary. Using Hysteresis A good way to avoid oscillations and noise during slow slopes is the use of hysteresis. For this purpose a threshold is introduced that pushes the input switching level back at the moment the output switches (See Figure 10). In this simple setup, a comparator with a single output and a resistive divider to the positive input is drawn. Parasitic Capacitors In the simple schematic of Figure 10 some capacitors are drawn. The capacitors CP. represent the parasitic (board) capacitance at the input of the part. This capacity will slow down the change of the level of the positive input in reaction to the changing output voltage. As a result of this, the output may have the time to switch over more than once. Actually the parasitic capacity represented by CP makes the attenuation circuit of RF and RP frequency dependent. The only action to take is to create a frequency independent circuit. This is simply done by placing the compensation capacitor 20137613 FIGURE 10. Simplified Schematic 15 www.national.com LMH7220 Application Information LMH7220 Application Information In case the outputs aren’t symmetrical or are a-symmetrically loaded, the output voltages differ from the situation of Figure 12. For this non-ideal situation there are two additional parameters defined, ∆VO and ∆VOD, as can be seen in Figure 13. (Continued) CC in parallel with RF. The capacitor CC can be calculated with the formula RF *CC = RP *CP, this means that both of the time constants must be the same to create a frequency independent network. A simple example gives the following assuming that CP is in total 2.5 pF and as already calculated RF = 25 kΩ in combination with RP = 50Ω. These input data gives: CC = RP * CP/RF CC = 50*2.5e-12/25e3 CC = 5e-15 = 0.005 pF This is not a practical value and different conclusions are possible: • No capacitor CC needed • Place a capacitor CC of 1 pF and accept a big overshoot at the positive input being sure that the input stage is in a secure new position • Place an extra CP of such a value that CC has a realistic value of say 1 pF (extra CP = ± 500 pF). 20137606 FIGURE 13. LVDS Output Signals with Different Amplitude Position of Feedback Resistors ∆VO is the difference in VO between the ‘1’ state and the ‘0’ state. This variation is acceptable if it is below 50 mV following the ANSI/TIA/EIA-644 LVDS standard. It is also possible that VOD in the ‘1’ state isn’t the same as in the ‘0’ state. This parameter is specified as ∆VOD, and is calculated as the absolute value of the difference of VODH and VODL. Another important issue while using positive feedback is the placement of the resistors RP and RF. These resistors must be placed as near as possible to the positive input, because this input is most sensitive for picking up spurious signals, noise etc. This connection must be very clean for the best performance of the overall circuit. With raising speeds the total PCB design becomes more and more critical, the LMH7220 comparator doesn’t have built in hysteresis, so the input signal must meet minimum requirements to make the output switch over properly. In the following sections some aspects concerning the load connected to the outputs and transmission lines will be discussed. LOADING THE OUTPUT The output structure creates a current (ILOOP see Figure 14) through an external differential load resistor of 100Ω nominal. This results in a differential output voltage of 325 mV. The outputs of the comparator are connected to tracks on a PCB. These tracks can be seen as a differential transmission line. The differential load resistor act as a high frequency termination at the end of the transmission line. This means that for a proper signal behavior the PCB tracks have to be dimensioned for a characteristic impedance of 100Ω as well. Changing the load resistor also implies a change of the transmission line impedance. More about transmission lines and termination can be found in the next section. The signal across the 100Ω termination resistor is fed into the inputs of subsequent circuitry that processes the data. Any connection to input circuitry of course draws current from the comparator’s outputs. In the case of a balanced input connected to the load resistance, current IP is drawn from both output connection points to ground. Keep in mind that the LMH7220’s ability to source currents is much higher than to sink them. The connected input circuitry also forms a differential load to the outputs of the comparator (see Figure 14). This will cause the voltage across the termination resistor to differ from its nominal value. THE OUTPUT OUTPUT SWING PROPERTIES LVDS has differential outputs which means that both outputs have the same swing but in opposite direction (Figure 12). Both outputs swing around a voltage called the common mode output voltage (VO). This voltage can be measured at the midpoint of two equal resistors connected to both outputs as discussed in the section ‘Input and Output Topology’. The absolute value of the difference between both voltages is called VOD. LVDS outputs cannot be held at the VO level because of their digital nature. They only cross this level during a transition. Due to the symmetrical structure of the circuit, both output voltages cross at VO regardless if the output changes from ‘0’ to ‘1’ or vise versa. 20137605 FIGURE 12. LVDS Output Signals www.national.com 16 is , it is required to recalculate the rise- and fall times to 100% swing in stead of 60%. TR is defined as the bitrate at which the differential output voltage drops to 50% of its nominal value. TR can be calculated from the rise & fall times: TR=60/50 * 2/(Tr + Tf) So the fastest rise / fall (0.26 ns both) leads to: max. TR=60/50 * 2e9/(0.26 + 0.26) = 4.62 Gb/s The slowest edges (1.5 ns both) yield: min. TR=60/50 * 2e9/(1.5 + 1.5) = 0.8 Gb/s (Continued) 20137616 FIGURE 14. Load 20137617 In general one single connection only draws a few µA’s, and doesn’t have much effect on the LVDS output voltage. For multiple inputs on one output pair, load currents must not exceed the specified limits, as described in the ANSI or IEEE LVDS standards. Below a specified value of VOD, the functioning of subsequent circuitry becomes uncertain. However under normal conditions there is no need to worry. Another point of practice is load capacitances. Capacitances are applied differentially (CLOAD) and also to ground (CP). All of these capacitors will disturb the pulse shape. The edges of the output pulse become slower, and in reaction the detection of the transition comes at a later moment. Be aware of this effect when measuring with probes. Both single ended and differential probes have these capacitances. A standard probe commonly has a load capacity of about 8 to 10 pF. This will cause some degradation of the pulse shape and will add some time delay. FIGURE 15. Bitrate Need for Terminated Transmission Lines During the ‘80’s and ‘90’s National fabricated the 100k ECL logic family. The rise and fall time specification was 0.75 ns which was very fast and will easily introduce errors in digital circuits if insufficient care has been taken to the transmission lines and terminations used for these signals. To be helpful to designers that use ECL with “old” PCB-techniques, the 10k ECL family was introduced with a rise and fall time specification of 2 ns. This was much slower and more easy to use. LVDS signals have transition times that exceed the fastest ECL family. A careful PCB design is needed using RF techniques for transmission and termination. Transmission lines can be formed in several ways. The most commonly used types are the coaxial cable and the twisted pair telephony cable (Figure 16). TRANSMISSION LINES & TERMINATION TECHNOLOGIES The LMH7220 uses LVDS technology. LVDS is a way to communicate data using low voltage swing and low power consumption. Nowadays data rates are growing, requiring increasing speed. Data isn’t only connected to other IC’s on a single PCB board but in many cases there are interconnections from board to board or from equipment to equipment. Distances can be short or long but it is always necessary to have a reliable connection, consume low power and to be able to handle high data rates. LVDS is a differential signal protocol. The advantage over single ended signal transmission is its higher immunity to common mode noise. Common mode signals are signals that are equally apparent on both lines and because the receiver only looks at the difference between both lines, this noise is canceled. 20137618 FIGURE 16. Cable Configuration These cables have a characteristic impedance determined by their geometric parameters. Widely used impedances for the coaxial cable are 50Ω and 75Ω. Twisted pair cables have impedances of about 120Ω to 150Ω. Other types of transmission lines are the strip line and the micro strip. These last types are used on PCB boards. They have the characteristic impedance dictated by the physical dimensions of a track placed over a metal ground plane (See Figure 17). Maximum Bitrates A very important specification in high speed circuits are the rise and fall times. In fact these determine the maximum toggle rate (TR) of the part. The LVDS standard specifies them at 0.26 ns to 1.5 ns. Rise and fall times are normally specified at 20% and 80% of the signal amplitude (60% difference). In order to know what the maximum toggle rate 17 www.national.com LMH7220 Application Information LMH7220 Application Information the PCB manufacturer can produce reliable boards with narrow track spacing the track width for a given impedance is also small. The wider the spacing, the wider tracks are needed for a certain impedance. For example two tracks of 0.2 mm width and 0.1 mm spacing have the same impedance as two tracks of 0.8 mm width and 0.4 mm spacing. With high-end PCB processes, it is possible to design very narrow differential microstrip transmission lines. It is desirable to use these phenomena to create optimal connections to the receiving part or the terminating resistor, in accordance with their physical dimensions. Seen from the comparator, the termination resistor must be connected at the far end of the line. Open connections after the termination resistor (e.g. to an input of a receiver) must be as short as possible. The allowed length of such connections varies with the received transients. The faster the transients the shorter open lines must be to prevent signal degradation. (Continued) PCB LAYOUT CONSIDERATIONS AND COMPONENT VALUES SELECTION High frequency designs require that both active- and passive components are selected that are specially designed for this purpose. The LMH7220 is fabricated in two different small packages intended for surface mount design. For reliable high speed design it is highly recommended also to use small surface mount passive components because these packages have low parasitic capacitance and low inductance simply because they have no leads to connect them to the PCB. It is possible to amplify signals at frequencies of several hundreds of MHz using standard through- hole resistors. Surface mount devices however are better suited for this purpose. Another important issue is the PCB itself, which is no longer a simple carrier for all the parts and a medium to interconnect them. The PCB becomes a real component itself and consequently contributes its own high frequency properties to the overall performance of the circuit. Practice dictates that a high frequency design at least has one ground plane, providing a low impedance path for all decoupling capacitors and other ground connections. Care should be taken especially that on-board transmission lines have the same impedance as the cables to which they are connected. Most single ended applications have 50Ω impedance (75Ω for video and cable TV applications). On PCBs, such low impedance single ended microstrip transmission lines usually require much wider traces (2 to 3 mm) on a standard double sided PCB board than needed for a ‘normal’ trace. Another important issue is that inputs and outputs shouldn’t ‘see’ each other. This occurs if input- and output tracks are routed in parallel over the PCB with only a small amount of physical separation, and particularly when the difference in signal level is high. Furthermore components should be placed as flat and low as possible on the surface of the PCB. For higher frequencies a long lead can act as a coil, a capacitor or an antenna. A pair of leads can even form a transformer. Careful design of the PCB minimizes oscillations, ringing and other unwanted behavior. For ultra high frequency designs only surface mount components will give acceptable results. (for more information see OA-15). NSC suggests the following evaluation boards as a guide for high frequency layout and as an aid in device testing and characterization. 20137619 FIGURE 17. PCB Transmission Lines Differential Microstrip Line The transmission line which is ideally suited for LVDS signals is the differential micro strip line. This is a double micro strip line with a narrow space in between. This means both lines have a strong coupling and this determines mainly the characteristic impedance. The fact that they are routed above a copper plane doesn’t affect differential impedance, only CMcapacitance is added. Each of the structures above has its own geometric parameters so for each structure there is another formula to calculate the right impedance. For calculations of these transmission lines visit the National website or feel free to order the RAPIDESIGNER. For some formula’s given in the ‘LVDS owners manual’ see chapter 3 (see the ‘Introduction’ section for the URL). At the end of the transmission line there must be a termination having the same impedance as of the transmission line itself. It doesn’t matter what impedance the line has, if the load has the same value no reflections will occur. When designing a PCB board with transmission lines on it, space becomes an important item especially on high density boards. With a single micro strip line, line width is fixed for given impedance and a board material. Other line widths will result in different impedances. Advantage of Differential Microstrip Impedances of transmission lines are always dictated by their geometric parameters. This is also true for differential micro strip lines. Using this type of transmission lines, track distance determines mainly the resulting impedance. So, if www.national.com 18 LMH7220 High Speed Comparator with LVDS Output Physical Dimensions inches (millimeters) unless otherwise noted 6-Pin TSOT NS Package Number MK06A National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. 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