TI SN65LVDS34

 SLLS490B − MARCH 2001 − REVISED NOVEMBER 2004
D 400-Mbps Signaling Rate1 and 200-Mxfr/s
D
D
D
D
D
D
D
D
D
D
D
Data Transfer Rate
Operates With a Single 3.3-V Supply
−4-V to 5-V Common-Mode Input Voltage
Range
Differential Input Thresholds <±50 mV With
50 mV of Hysteresis Over Entire
Common-Mode Input Voltage Range
Integrated 110-Ω Line Termination
Resistors On LVDT Products
TSSOP Packaging (33 Only)
Complies With TIA/EIA-644 (LVDS)
Active Failsafe Assures a High-Level
Output With No Input
Bus-Pin ESD Protection Exceeds
15 kV HBM
Input Remains High-Impedance on Power
Down
TTL Inputs Are 5-V Tolerant
Pin-Compatible With the AM26LS32,
SN65LVDS32B, µA9637, SN65LVDS9637B
SN65LVDS33D
SN65LVDT33D
SN65LVDS33PW
SN65LVDT33PW
D OR PW PACKAGE
(TOP VIEW)
1B
1A
1Y
G
2Y
2A
2B
GND
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
VCC
4B
4A
4Y
G
3Y
3A
3B
The high-speed switching of LVDS signals usually
necessitates the use of a line impedance
matching resistor at the receiving-end of the cable
or transmission media. The SN65LVDT series of
receivers eliminates this external resistor by
integrating it with the receiver. The nonterminated
SN65LVDS series is also available for multidrop
or other termination circuits.
G
SN65LVDT33 ONLY
1A
1Y
1B
2A
2Y
2B
3Y
3B
4A
4Y
4B
SN65LVDS34D
SN65LVDT34D
D PACKAGE
(TOP VIEW)
Precise control of the differential input voltage
thresholds allows for inclusion of 50 mV of input
voltage hysteresis to improve noise rejection on
slowly changing input signals. The input thresholds are still no more than ±50 mV over the full
input common-mode voltage range.
G
3A
description
This family of four LVDS data line receivers offers
the widest common-mode input voltage range in
the industry. These receivers provide an input
voltage range specification compatible with a 5-V
PECL signal as well as an overall increased
ground-noise tolerance. They are in industry
standard footprints with integrated termination as
an option.
logic diagram (positive logic)
VCC
1Y
2Y
GND
1
8
2
7
3
6
4
5
logic diagram (positive logic)
1A
1B
2A
2B
1A
1Y
1B
SN65LVDT34 ONLY
2A
2Y
2B
AVAILABLE OPTIONS
PART NUMBER†
NUMBER
TERMINATION
OF
RESISTOR
RECEIVERS
SYMBOLIZATION
SN65LVDS33D
4
No
LVDS33
SN65LVDS33PW
4
No
LVDS33
SN65LVDT33D
4
Yes
LVDT33
SN65LVDT33PW
4
Yes
LVDT33
SN65LVDS34D
2
No
LVDS34
SN65LVDT34D
2
Yes
LVDT34
† Add the suffix R for taped and reeled carrier.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1The signalling rate of a line, is the number of voltage transitions that are made per second expressed in the units bps (bits per second).
Copyright  2001 − 2004, Texas Instruments Incorporated
! "#$ ! %#&'" ($)
(#"! " !%$""! %$ *$ $! $+! !#$!
!(( ,-) (#" %"$!!. ($! $"$!!'- "'#($
$!. '' %$$!)
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1
SLLS490B − MARCH 2001 − REVISED NOVEMBER 2004
description (continued)
The receivers can withstand ±15 kV human-body model (HBM) and ±600 V machine model (MM) electrostatic
discharges to the receiver input pins with respect to ground without damage. This provides reliability in cabled
and other connections where potentially damaging noise is always a threat.
The receivers also include a (patent pending) failsafe circuit that will provide a high-level output within 600 ns
after loss of the input signal. The most common causes of signal loss are disconnected cables, shorted lines,
or powered-down transmitters. The failsafe circuit prevents noise from being received as valid data under these
fault conditions. This feature may also be used for Wired-Or bus signaling. See The Active Failsafe Feature of
the SN65LVDS32B application note.
The intended application and signaling technique of these devices is point-to-point baseband data transmission
over controlled impedance media of approximately 100 Ω. The transmission media may be printed-circuit board
traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent upon the attenuation
characteristics of the media and the noise coupling to the environment.
The SN65LVDS33, SN65LVDT33, SN65LVDS34 and SN65LVDT34 are characterized for operation from −40°C
to 85°C.
Function Tables
SN65LVDS33 and SN65LVDT33
DIFFERENTIAL INPUT
VID = VA − VB
VID ≥ -32 mV
−100 mV < VID ≤ −32 mV
VID ≤ −100 mV
X
Open
ENABLES
SN65LVDS34 and SN65LVDT34
OUTPUT
DIFFERENTIAL INPUT
OUTPUT
G
G
Y
H
X
H
VID = VA − VB
VID ≥ -32 mV
H
X
L
H
−100 mV < VID ≤ −32 mV
?
H
X
?
X
L
?
VID ≤ -100 mV
Open
H
H
X
L
X
L
L
L
H
Z
H
X
H
X
L
H
H = high level, L = low level, X = irrelevant,
Z = high impedance (off), ? = indeterminate
2
Y
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H = high level, L = low level,
? = indeterminate
L
SLLS490B − MARCH 2001 − REVISED NOVEMBER 2004
equivalent input and output schematic diagrams
VCC
Attenuation
Network
Attenuation
Network
1 pF
60 kΩ
A Input
200 kΩ
3 pF
250 kΩ
6.5 kΩ
Attenuation
Network
6.5 kΩ
VCC
B Input
7V
7V
7V
7V
LVDT Only 110 Ω
VCC
VCC
300 kΩ
(G Only)
Enable
Inputs
100 Ω
37 Ω
Y Output
7V
7V
300 kΩ
(G Only)
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3
SLLS490B − MARCH 2001 − REVISED NOVEMBER 2004
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4 V
Voltage range: Enables or Y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −1 V to 6 V
A or B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −5 V to 6 V
VA − VB (LVDT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 V
Electrostatic discharge: A, B, and GND (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . Class 3, A: 15 kV, B: 500 V
Charged-device mode: All pins (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±500 V
Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
2. Tested in accordance with JEDEC Standard 22, Test Method A114-A.
3. Tested in accordance with JEDEC Standard 22, Test Method C101.
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
OPERATING FACTOR‡
ABOVE TA = 25°C
TA = 85°C
POWER RATING
D8
725 mW
5.8 mW/°C
377 mW
PW16
774 mW
6.2 mW/°C
402 mW
D16
950 mW
7.6 mW/°C
494 mW
‡ This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with
no air flow.
recommended operating conditions
Supply voltage, VCC
MIN
NOM
MAX
3
3.3
UNIT
3.6
V
High-level input voltage, VIH
Enables
2
5
V
Low-level input voltage, VIL
Enables
0
0.8
V
Magnitude of differential input voltage,  VID
LVDS
0.1
LVDT
Voltage at any bus terminal (separately or common-mode), VI or VIC
Operating free-air temperature, TA
4
3
0.8
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V
−4
5
V
−40
85
°C
SLLS490B − MARCH 2001 − REVISED NOVEMBER 2004
electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
VIT1
Positive-going differential input voltage threshold
VIT2
Negative-going differential input voltage
threshold
VIB = −4 V or 5 V, See Figures 1 and 2
−50
VIT3
Differential input failsafe voltage threshold
See Table 1 and Figure 5
−32
VID(HYS)
Differential input voltage hysteresis,
VIT1 − VIT2
VOH
VOL
ICC
High-level output voltage
Supply current
SN65LVDx33
SN65LVDx34
SN65LVDS
II
Input current (A or B inputs)
SN65LVDT
IID
Differential input current
(IIA − IIB)
II(OFF)
Power-off input current
(A or B inputs)
SN65LVDS
SN65LVDT
−100
50
2.4
V
0.4
G at VCC, No load, Steady-state
16
23
G at GND
1.1
5
No load,
Steady-state
VI = 0 V,
VI = 2.4 V,
Other input open
8
±20
Other input open
±20
VI = −4 V,
VI = 5 V,
Other input open
±75
Other input open
±40
VI = 0 V,
VI = 2.4 V,
Other input open
±40
Other input open
±40
VI = −4 V,
VI = 5 V,
Other input open
±150
Other input open
±80
VID = 100 mV,
VID = 200 mV,
VIC= −4 V or 5 V
VIC= −4 V or 5 V
1.55
µA
A
µA
A
±3
µA
mA
High-level input current (enables)
Low-level input current (enables)
VIL = 0.8 V
±50
µA
A
±100
−10
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mA
2.22
±30
VI = 0.4 sin (4E6πt) + 0.5 V
V
12
VA or VB =0 V or 2.4 V, VCC = 0 V
VA or VB = −4 V or 5 V, VCC = 0 V
VIH = 2 V
IOZ
High-impedance output current
CI
Input capacitance, A or B input to GND
† All typical values are at 25°C and with a 3.3 V supply.
mV
mV
±20
SN65LVDT
UNIT
mV
VA or VB = 0 V or 2.4 V, VCC = 0 V
VA or VB = −4 or 5 V, VCC = 0 V
SN65LVDS
IIH
IIL
MAX
50
IOH = −4 mA
IOL = 4 mA
Low-level output voltage
TYP†
5
10
µA
10
µA
10
µA
pF
5
SLLS490B − MARCH 2001 − REVISED NOVEMBER 2004
switching characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP†
MAX
2.5
4
6
ns
2.5
4
6
ns
9
ns
1.5
µs
UNIT
tPLH(1)
tPHL(1)
Propagation delay time, low-to-high-level output
td1
td2
Delay time, failsafe deactivate time
tsk(p)
tsk(o)
Pulse skew (|tPHL(1) – tPLH(1)|)
Output skew‡
tsk(pp)
tr
Part-to-part skew§
Output signal rise time
0.8
ns
tf
tPHZ
Output signal fall time
0.8
ns
Propagation delay time, high-level-to-high-impedance output
5.5
9
ns
tPLZ
tPZH
Propagation delay time, low-level-to-high-impedance output
4.4
9
ns
3.8
9
ns
See Figure 3
Propagation delay time, high-to-low-level output
CL = 10 pF,
See Figures 3 and 6
Delay time, failsafe activate time
0.3
200
ps
150
ps
1
See Figure 3
Propagation delay time, high-impedance -to-high-level output
See Figure 4
ns
tPZL
Propagation delay time, high-impedance-to-low-level output
7
9
ns
† All typical values are at 25°C and with a 3.3-V supply.
‡ tsk(o) is the magnitude of the time difference between the tPLH or tPHL of all receivers of a single device with all of their inputs driven together.
§ tsk(pp) is the magnitude of the time difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
6
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SLLS490B − MARCH 2001 − REVISED NOVEMBER 2004
PARAMETER MEASUREMENT INFORMATION
IIA
A
VO
Y
VID
B
(VIA + VIB)/2
VIA
VIC
IIB
VO
VIB
Figure 1. Voltage and Current Definitions
1000 Ω
100 Ω
VIC
+
−
100 Ω†
VID
1000 Ω
10 pF,
2 Places
VO
10 pF
† Remove for testing LVDT device.
VIT1
0V
VID
−100 mV
VO
100 mV
VID
0V
VIT2
VO
NOTE: Input signal of 3 Mpps, duration of 167 ns, and transition time of <1 ns.
Figure 2. VIT1 and VIT2 Input Voltage Threshold Test Circuit and Definitions
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7
SLLS490B − MARCH 2001 − REVISED NOVEMBER 2004
PARAMETER MEASUREMENT INFORMATION
VID
VIA
CL = 10 pF
VIB
VO
VIA
1.4 V
VIB
1V
0.4 V
VID
0V
−0.4 V
tPHL
tPLH
80%
VO
20%
tf
VOH
1.4 V
VOL
80%
20%
tr
NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps,
pulsewidth = 10 ±0.2 ns . CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T.
Figure 3. Timing Test Circuit and Waveforms
8
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SLLS490B − MARCH 2001 − REVISED NOVEMBER 2004
PARAMETER MEASUREMENT INFORMATION
1.2 V
B
500 Ω
A
10 pF
Inputs
±
VO
G
VTEST
G
NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse
repetition rate (PRR) = 0.5 Mpps, pulsewidth = 500 ±10 ns . CL includes instrumentation and fixture
capacitance within 0,06 mm of the D.U.T.
2.5 V
VTEST
A
1V
2V
1.4 V
0.8 V
G
2V
1.4 V
0.8 V
tPLZ
G
tPLZ
tPZL
tPZL
Y
VTEST
2.5 V
1.4 V
VOL +0.5 V
VOL
0
1.4 V
A
G
2V
1.4 V
0.8 V
G
2V
1.4 V
0.8 V
tPHZ
tPHZ
tPZH
tPZH
Y
VOH
VOH −0.5 V
1.4 V
0
Figure 4. Enable/Disable Time Test Circuit and Waveforms
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9
SLLS490B − MARCH 2001 − REVISED NOVEMBER 2004
PARAMETER MEASUREMENT INFORMATION
Table 1. Receiver Minimum and Maximum VIT3
Input Threshold Test Voltages
APPLIED VOLTAGES†
RESULTANT INPUTS
VIA (mV)
−4000
VIB (mV)
−3900
VID (mV)
−100
VIC (mV)
−3950
Output
−4000
−3968
−32
−3984
H
4900
5000
−100
4950
L
4968
5000
−32
4984
H
L
† These voltages are applied for a minimum of 1.5 µs.
VIA
−100 mV @ 250 KHz
VIB
VO
a) No Failsafe
VIA
−32 mV @ 250 KHz
VIB
VO
Failsafe Asserted
b) Failsafe Asserted
Figure 5. VIT3 Failsafe Threshold Test
1.4 V
1V
0.4 V
>1.5 µs
0V
−0.2 V
−0.4 V
td1
td2
VOH
1.4 V
VOL
Figure 6. Waveforms for Failsafe Activate and Deactivate
10
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SLLS490B − MARCH 2001 − REVISED NOVEMBER 2004
TYPICAL CHARACTERISTICS
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
4
VCC = 3.3 V
TA = 25°C
VOH − High-Level Output Voltage − V
VOL − Low-Level Output Voltage − V
5
4
3
2
1
VCC = 3.3 V
TA = 25°C
3
2
1
0
0
0
10
20
30
−40
40
5
4.5
VCC = 3 V
VCC = 3.3 V
VCC = 3.6 V
3.5
0
50
TA − Free-Air Temperature − °C
−10
0
HIGH-TO-LOW PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
t PHL− High-To-Low Propagation Delay Time − ns
t PLH − Low-To-High Propagation Delay Time − ns
LOW-TO-HIGH PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
3
−50
−20
Figure 8
Figure 7
4
−30
IOH − High-Level Output Current − mA
IOL − Low-Level Output Current − mA
100
Figure 9
5
4.5
VCC = 3 V
4
VCC = 3.3 V
VCC = 3.6 V
3.5
3
−50
0
50
TA − Free-Air Temperature − °C
100
Figure 10
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11
SLLS490B − MARCH 2001 − REVISED NOVEMBER 2004
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
FREQUENCY
140
I CC − Supply Current − mA
120
VCC = 3.3 V
100
80
VCC = 3.6 V
60
VCC = 3 V
40
20
0
0
150
100
f − Switching Frequency − MHz
Figure 11
12
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200
SLLS490B − MARCH 2001 − REVISED NOVEMBER 2004
APPLICATION INFORMATION
0.01 µF
1
VCC
16
0.1 µF
(see Note A)
1B
100 Ω
2
3
VCC 4
5
6
1A
4B
2Y
4Y
G
2A
100 Ω
7
4A
2B
3Y
3A
5V
1N645
(2 places)
15
1Y
G
≈3.6 V
14
100 Ω
(see Note B)
13
12
11
See Note C
10
100 Ω
8
GND
3B
9
NOTES: A. Place a 0.1-µF Z5U ceramic, mica or polystyrene dielectric, 0805 size, chip capacitor between VCC and the ground plane. The
capacitor should be located as close as possible to the device terminals.
B. The termination resistance value should match the nominal characteristic impedance of the transmission media with ±10%.
C. Unused enable inputs should be tied to VCC or GND as appropriate.
Figure 12. Operation With 5-V Supply
related information
IBIS modeling is available for this device. Please contact the local TI sales office or the TI Web site at www.ti.com
for more information.
For more application guidelines, please see the following documents:
D
D
D
D
D
D
Low-Voltage Differential Signalling Design Notes (TI literature number SLLA014)
Interface Circuits for TIA/EIA-644 (LVDS) (SLLA038)
Reducing EMI With LVDS (SLLA030)
Slew Rate Control of LVDS Circuits (SLLA034)
Using an LVDS Receiver With RS-422 Data (SLLA031)
Evaluating the LVDS EVM (SLLA033)
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13
SLLS490B − MARCH 2001 − REVISED NOVEMBER 2004
APPLICATION INFORMATION
active failsafe feature
A differential line receiver commonly has a failsafe circuit to prevent it from switching on input noise. Current
LVDS failsafe solutions require either external components with subsequent reductions in signal quality or
integrated solutions with limited application. This family of receivers has a new integrated failsafe that solves
the limitations seen in present solutions. A detailed theory of operation is presented in application note The
Active Failsafe Feature of the SN65LVDS32B, literature number SLLA082A.
The following figure shows one receiver channel with active failsafe. It consists of a main receiver that can
respond to a high-speed input differential signal. Also connected to the input pair are two failsafe receivers that
form a window comparator. The window comparator has a much slower response than the main receiver and
it detects when the input differential falls below 80 mV. A 600-ns failsafe timer filters the window comparator
outputs. When failsafe is asserted, the failsafe logic drives the main receiver output to logic high.
Output
Buffer
Main Receiver
A
B
+
_
R
Reset
Failsafe
Timer
A > B + 80 mV
+
_
Failsafe
B > A + 80 mV
+
_
Window Comparator
Figure 13. Receiver With Active Failsafe
14
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SLLS490B − MARCH 2001 − REVISED NOVEMBER 2004
APPLICATION INFORMATION
ECL/PECL-to-LVTTL conversion with TI’s LVDS receiver
The various versions of emitter-coupled logic (i.e. ECL, PECL and LVPECL) are often the physical layer of
choice for system designers. Designers know of the established technology and that it is capable of high-speed
data transmission. In the past, system requirements often forced the selection of ECL. Now technologies like
LVDS provide designers with another alternative. While the total exchange of ECL for LVDS may not be a design
option, designers have been able to take advantage of LVDS by implementing a small resistor divider network
at the input of the LVDS receiver. TI has taken the next step by introducing a wide common-mode LVDS receiver
(no divider network required) which can be connected directly to an ECL driver with only the termination bias
voltage required for ECL termination (VCC – 2 V).
Figures 14 and 15 show the use of an LV/PECL driver driving 5 meters of CAT−5 cable and being received by
TI’s wide common-mode receiver and the resulting eye-pattern. The values for R3 are required in order to
provide a resistor path to ground for the LV/PECL driver. With no resistor divider, R1 simply needs to match the
characteristic load impedance of 50 Ω. The R2 resistor is a small value and is intended to minimize any possible
common-mode current reflections.
VCC
ICC
R1 = 50 Ω
R2 = 50 Ω
5 Meters
of CAT-5
LV/PECL
R3
R3
VB
LVDS
VB
R1
VEE
VCC
ICC
R1
R2
R3 = 240 Ω
Figure 14. LVPECL or PECL to Remote Wide Common-Mode LVDS Receiver
Figure 15. LV/PECL to Remote SN65LVDS33 at 500 Mbps Receiver Output (CH1)
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15
SLLS490B − MARCH 2001 − REVISED NOVEMBER 2004
APPLICATION INFORMATION
test conditions
D VCC = 3.3 V
D TA = 25°C (ambient temperature)
D All four channels switching simultaneously with NRZ data. Scope is pulse-triggered simultaneously with
NRZ data.
equipment
D Tektronix PS25216 programmable power supply
D Tektronix HFS 9003 stimulus system
D Tektronix TDS 784D 4-channel digital phosphor oscilloscope − DPO
Tektronix PS25216
Programmable
Power Supply
Tektronix HFS 9003
Stimulus System
Trigger
Bench Test Board
Tektronix TDS 784D 4-Channel
Digital Phosphor
Oscilloscope − DPO
Figure 16. Equipment Setup
100 Mbit/s
200 Mbit/s
Figure 17. Typical Eye Pattern SN65LVDS33
16
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MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
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