LMH7322 Dual 700 ps High Speed Comparator with RSPECL Outputs General Description Features The LMH7322 is a dual comparator with 700 ps propagation delay, low dispersion of 75 ps and an input voltage range that extends from VCC-1.5V to VEE. The devices can be operated from a wide supply voltage range of 2.7V to 12V. The adjustable hysteresis adds flexibility and prevents oscillations. Both the outputs and latch inputs of the LMH7322 are RSPECL compatible. When used in combination with a VCCO supply voltage of 2.5V the outputs have LVDS compatible levels. The LMH7322 is available in a 24-pin LLP package. (VCCI = +5V, VCCO = +5V) 700 ps ■ Propagation delay 75 ps ■ Overdrive dispersion 20 mV-1V 160 ps ■ Fast rise and fall times 2.7V to 12V ■ Wide supply range ■ Input common mode range extends 200 mV below negative rail ■ Adjustable hysteresis ■ (RS)PECL outputs (see application note) ■ (RS)PECL latch inputs (see application note) Applications ■ ■ ■ ■ ■ ■ Digital receivers High-speed signal restoration Zero-crossing detectors High-speed sampling Window comparators High-speed signal triggering Typical Application (RS)ECL to RSPECL Converter 20183205 © 2008 National Semiconductor Corporation 201832 www.national.com LMH7322 Dual 700 ps High Speed Comparator with RSPECL Outputs November 21, 2008 LMH7322 Soldering Information Infrared or Convection (20 sec) Wave Soldering (10 sec) Storage Temperature Range Junction Temperature (Note 7) Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. ESD Tolerance (Note 2) Human Body Model Machine Model Output Short Circuit Duration Supply Voltages (VCCx–VEE) Differential Voltage at Input Pins Voltage at Input Pins Voltage at LE Pins Current at Output Pins 2.5 kV 250V (Notes 3, 4) 13.2V ±13V VEE-0.2V to VCCI + 0.2V VEE-0.2V to VCCO+0.2V 25mA Operating Conditions 235°C 260°C −65°C to +150°C +150°C (Note 1) Supply Voltage (VCCx–VEE) Operating Temperature Range (Notes 5, 6) Package Thermal Resistance (Notes 5, 6) 24-Pin LLP 2.7V to 12V −40°C to +125°C 38°C/W 12V DC Electrical Characteristics Unless otherwise specified, all limits are guaranteed for TJ = 25°C, VCCI = VCCO = 12V, VEE = 0V, RL = 50Ω to VCCO-2V, VCM = 300 mV, RHYS = 1 kΩ. Boldface limits apply at temperature extremes. Symbol Parameter Conditions Min (Note 8) Typ (Note 7) −5 −2.9 −250 40 Max (Note 8) Units INPUT CHARACTERISTICS IB Input Bias Current VIN Differential = 0V; RHYS = 8 kΩ Biased at VCM IOS Input Offset Current VIN Differential = 0V TC IOS Input Offset Current TC VIN Differential = 0V VOS Input Offset Voltage TC VOS Input Offset Voltage TC VRI Input Voltage Range VRID Input Differential Voltage Range CMRR Common Mode Rejection Ratio PSRR µA +250 0.2 −8 −2 nA/°C +8 12 for CMRR ≥ 50 dB VEE−0.2 0V ≤ VCM ≤ VCC1−0.2 mV µV/°C VCCI−1.5 −1 nA +1 V V 80 dB Power Supply Rejection Ratio 80 dB AV Active Gain 53 dB Hyst Hysteresis RHYS = 0Ω 55 100 10 mV LATCH ENABLE CHARACTERISTICS IB-LE Latch Enable Bias Current Biased at RSPECL Level 3 VOS-LE Latch Enable Offset Voltage Biased at RSPECL Level −5 VRI-LE Latch Enable Voltage Range for CMRR ≥ 50 dB VRID-LE Latch Enable Differential Voltage Range VEE+1.4 µA mV VCCO-0.8 V ±0.4 V OUTPUT CHARACTERISTICS VOH Output Voltage High VIN Differential = 50 mV VCCO−1.1V mV VOL Output Voltage Low VIN Differential = 50 mV VCCO−1.5V mV VOD Output Voltage Differential VIN Differential = 50 mV 360 mV POWER SUPPLIES IVCCI VCCI Supply Current/ Channel IVCCO VCCO Supply Current/ Channel www.national.com Load Current Excluded 2 6.5 10 12 16.3 20 25 mA mA Unless otherwise specified, all limits are guaranteed for TJ = 25°C, VCCI = VCCO = 12V, VEE = 0V, RL = 50Ω to VCCO-2V, VCM = 300 mV, RHYS = none.Boldface limits apply at temperature extremes. Symbol TR tjitter-RMS tPDH tOD-disp Parameter Conditions Min (Note 8) Typ (Note 7) Max (Note 8) Units Maximum Toggle Rate Overdrive = ±50 mV; CL = 2 pF @ 50% of Output Swing 4 Gb/s Minimum Pulse Width Overdrive = ±50 mV; CL = 2 pF @ 50% of Output Swing 255 ps RMS Random Jitter Overdrive = ±100 mV; CL = 2 pF Center Frequency = 140 MHz Bandwidth = 10 Hz–20 MHz 702 fs Propagation Delay. (see Figure 3 application note) Overdrive 20 mV 818 Overdrive 50 mV 723 Input SR = Constant VIN Startvalue = VREF −100 mV Overdrive 100 mV 708 Overdrive 1V 703 Input Overdrive Dispersion tPDH @ Overdrive 20 mV ↔ 100 mV 110 ps ps ps tPDH @ Overdrive 100 mV ↔ 1V 5 0.1 V/ns to 1 V/ns; Overdrive = 100 mV 48 ps 43 ps tSR-disp Input Slew Rate Dispersion tCM-disp Input Common Mode Dispersion SR = 1 V/ns; Overdrive = 100 mV; ΔtPDLH Q to Q Time Skew |tPDH – tPDL| Overdrive = 100 mV; CL = 2 pF 24 ps ΔtPDHL Q to Q Time Skew |tPDL – tPDH| Overdrive = 100 mV; CL = 2 pF 45 ps tr Output Rise Time (20%–80%) Overdrive = 100 mV; CL = 2 pF 155 ps tf Output Fall Time (20%–80%) Overdrive = 100 mV; CL = 2 pF 155 ps tsLE Latch Setup Time 77 ps thLE Latch Hold Time 33 ps tPD_LE Latch to Output Delay Time 944 ps 0V ≤ VCM ≤ VCCI- 1.5V 5V DC Electrical Characteristics Unless otherwise specified, all limits are guaranteed for TJ = 25°C, VCCI = VCCO = 5V, VEE = 0V, RL = 50Ω to VCCO-2V, VCM = 300 mV, RHYS = 1 kΩ.Boldface limits apply at temperature extremes. Symbol Parameter Conditions Min (Note 8) Typ (Note 7) −5 −2.6 −250 40 Max (Note 8) Units INPUT CHARACTERISTICS IB Input Bias Current VIN Differential = 0V; RHYS = 8 kΩ Biased at VCM µA IOS Input Offset Current VIN Differential = 0V TC IOS Input Offset Current TC VIN Differential = 0V VOS Input Offset Voltage TC VOS Input Offset Voltage TC VRI Input Voltage Range VRID Input Differential Voltage Range CMRR Common Mode Rejection Ratio 0V ≤ VCM ≤ VCC1−0.2 80 dB PSRR Power Supply Rejection Ratio 80 dB AV Active Gain 53 dB Hyst Hysteresis +250 0.3 −8 −2 nA/°C +8 mV 12 for CMRR ≥ 50 dB nA µV/°C VEE−0.2 VCCI−1.5 V −1 +1 V RHYS = 0Ω 55 100 10 mV LATCH ENABLE CHARACTERISTICS IB-LE Latch Enable Bias Current Biased at RSPECL Level 3 VOS-LE Latch Enable Offset Voltage Biased at RSPECL Level +5 VRI-LE Latch Enable Voltage Range for CMRR ≥ 50 dB VEE+1.4 3 µA mV VCCO-0.8 V www.national.com LMH7322 12 AC Electrical Characteristics LMH7322 Symbol VRID-LE Parameter Conditions Min (Note 8) Latch Enable Differential Voltage Range Typ (Note 7) Max (Note 8) Units ±0.4 V OUTPUT CHARACTERISTICS VOH Output Voltage High VCCO−1.1V mV VOL Output Voltage Low VCCO−1.5V mV VOD Output Voltage Differential 355 mV POWER SUPPLIES IVCCI VCCI Supply Current/ Channel 6.3 10 12 mA IVCCO VCCO Supply Current/ Channel Load Current Excluded 15.8 20 25 mA 5V AC Electrical Characteristics Unless otherwise specified, all limits are guaranteed for TJ = 25°C, VCCI = VCCO = 5V, VEE = 0V, RL = 50Ω to VCCO-2V, VCM = 300 mV, RHYS = none. Boldface limits apply at temperature extremes. Symbol TR tjitter_RMS tPDLH Parameter Conditions Min (Note 8) Max (Note 8) Units Maximum Toggle Rate Overdrive = ±50 mV; CL = 2 pF @ 50% of Output Swing 3.9 Gb/s Minimum Pulse Width Overdrive = ±50 mV; CL = 2 pF @ 50% of Output Swing 260 ps RMS Random Jitter Overdrive = ±100 mV; CL = 2 pF Center Frequency = 140 MHz Bandwidth = 10 Hz–20 MHz 572 fs Propagation Delay. (see Figure 3 application note) Overdrive 20 mV 783 Overdrive 50 mV 718 Input SR = Constant Overdrive 100 mV VIN startvalue = VREF – 100 mV Overdrive 1V tOD-disp Typ (Note 7) Input Overdrive Dispersion ps 708 ps 708 tPDH @ Overdrive 20 mV ↔ 100 mV 75 tPDH @ Overdrive 100 mV ↔ 1V 5 0.1 V/ns to 1 V/ns; Overdrive = 100 mV 50 ps 24 ps ps tSR-disp Input Slew Rate Dispersion tCM-disp Input Common Mode Dispersion SR = 1 V/ns; Overdrive = 100 mV; ΔtPDLH Q to Q Time Skew |tPDH – tPDL| Overdrive = 100 mV; CL = 2 pF 29 ps ΔtPDHL Q to Q Time Skew |tPDL – tPDH| Overdrive = 100 mV; CL = 2 pF 47 ps tr Output Rise Time (20%–80%) Overdrive = 100 mV; CL = 2 pF 160 ps tf Output Fall Time (20%–80%) Overdrive = 100 mV; CL = 2 pF 160 ps tsLE Latch Setup Time 95 ps thLE Latch Hold Time 29 ps tPD_LE Latch to Output Delay Time 893 ps 0V ≤ VCM ≤ VCCI- 1.5V 2.7V DC Electrical Characteristics Unless otherwise specified, all limits are guaranteed for TJ = 25°C, VCCI = VCCO = 2.7V, VEE = 0V, RL = 50Ω to VCCO-2V, VCM = 300 mV, RHYS = 1 kΩ. Boldface limits apply at temperature extremes. Symbol Parameter Conditions Min (Note 8) Typ (Note 7) −5 −2.5 −250 40 Max (Note 8) Units INPUT CHARACTERISTICS IB Input Bias Current VIN Differential = 0V; RHYS = 8 kΩ Biased at VCM IOS Input Offset Current VIN Differential = 0V TC IOS Input Offset Current TC VIN Differential = 0V www.national.com 0.2 4 µA +250 nA nA/°C Parameter VOS Input Offset Voltage TC VOS Input Offset Voltage TC VRI Input Voltage Range VRID Input Differential Voltage Range CMRR Common Mode Rejection Ratio PSRR AV Hyst Hysteresis Conditions Min (Note 8) Typ (Note 7) Max (Note 8) −8 −2 +8 mV 12 for CMRR ≥ 50 dB Units µV/°C VEE−0.2 VCCI−1.5 V −1 +1 V 0V ≤ VCM ≤ VCC1−2 80 dB Power Supply Rejection Ratio 80 dB Active Gain 53 dB RHYS = 0Ω 55 100 mV 3 10 µA LATCH ENABLE CHARACTERISTICS IB-LE Latch Enable Bias Current Biased at RSPECL Level VOS-LE Latch Enable Offset Voltage Biased at RSPECL Level VRI-LE Latch Enable Voltage Range for CMRR ≥ 50 dB VRID-LE Latch Enable Differential Voltage Range −5 VEE+1.4 mV VCCO-0.8 V ±0.4 V OUTPUT CHARACTERISTICS VOH Output Voltage High VCCO−1.1V mV VOL Output Voltage Low VCCO−1.5V mV VOD Output Voltage Differential 350 mV POWER SUPPLIES IVCCI VCCI Supply Current/ Channel 6.2 10 12 mA IVCCO VCCO Supply Current/ Channel Load Current Excluded 15.5 20 25 mA 2.7V AC Electrical Characteristics Unless otherwise specified, all limits are guaranteed for TJ = 25°C, VCCI = VCCO = 2.7V, VEE = 0V, RL = 50Ω to VCCO-2V, VCM = 300 mV, RHYS = none. Boldface limits apply at temperature extremes. Symbol TR tjitter_RMS tPDH tOD-disp Parameter Conditions Min (Note 8) Typ (Note 7) Max (Note 8) Units Maximum Toggle Rate Overdrive = ±50 mV; CL = 2 pF @ 50% of Output Swing 3.8 Gb/s Minimum Pulse Width Overdrive = ±50 mV; CL = 2 pF @ 50% of Output Swing 265 ps RMS Random Jitter Overdrive = ±50 mV; CL = 2 pF Center Frequency = 140 MHz Bandwidth = 10 Hz–20 MHz 551 fs Propagation Delay. Overdrive 20 mV (see Figure 3 application note) Overdrive 50 mV 783 Input SR = Constant Overdrive 100 mV VIN startvalue = VREF – 100 mV Overdrive 1V 713 Input Overdrive Dispersion 728 718 tPDH @ Overdrive 20 mV ↔ 100 mV 70 tPDH @ Overdrive 100 mV ↔ 1V 5 ps ps ps tSR-disp Input Slew Rate Dispersion 0.1 V/ns to 1 V/ns; Overdrive = 100 mV 54 ps tCM-disp Input Common Mode Dispersion SR = 1 V/ns; Overdrive = 100 mV; 12 ps ΔtPDLH Q to Q Time Skew |tPDH – tPDL| Overdrive = 100 mV; CL = 2 pF 35 ps ΔtPDHL Q to Q Time Skew |tPDL – tPDH| Overdrive = 100 mV; CL = 2 pF 53 ps tr Output Rise Time (20%–80%) Overdrive = 100 mV; CL = 2 pF 165 ps 0V ≤ VCM ≤ VCCI- 1.5V 5 www.national.com LMH7322 Symbol LMH7322 Symbol Parameter tf Output Fall Time (20%–80%) tsLE Latch Setup Time thLE tPD_LE Conditions Min (Note 8) Typ (Note 7) Overdrive = 100 mV; CL = 2 pF Max (Note 8) Units 165 ps 102 ps Latch Hold Time 37 ps Latch to Output Delay Time 906 ps Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test conditions, see the Electrical Characteristics. Note 2: Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC) Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC). Note 3: Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150°C. Note 4: Short circuit test is a momentary test. See next note. Note 5: The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board. Note 6: Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. See Applications section for information on temperature de-rating of this device. Note 7: Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not guaranteed on shipped production material. Note 8: All limits are guaranteed by testing or statistical analysis. Note 9: Positive current corresponds to current flowing into the device. Note 10: Slew rate is the average of the positive and negative slew rate. Note 11: Average Temperature Coefficient is determined by dividing the change in a parameter at temperature extremes by the total temperature change. Connection Diagrams Schematic Footprint 20183202 20183201 Ordering Information Package Part Number 24-Pin LLP NOPB LMH7322SQE www.national.com Package Marking Transport Media L7322SQ 250 Units Tape and Reel LMH7322SQ NSC Drawing 1k Units Tape and Reel LMH7322SQX 4.5 Units Tape and Reel 6 SQA24A At TJ = 25°C; VCCI = +5V; VCCO = +3.3V; VEE = −5V; unless otherwise specified. Propagation Delay vs. Supply Voltage Propagation Delay vs. Temperature 20183226 20183227 Propagation Delay vs. Supply Voltage Propagation Delay vs. Overdrive Voltage 20183228 20183229 Propagation Delay vs. Common Mode Voltage Propagation Delay vs. Slew Rate 20183230 20183231 7 www.national.com LMH7322 Typical Performance Characteristics LMH7322 TPD Dispersion vs. Supply Voltage Slew Rate Dispersion vs. Voltage Supply 20183232 20183233 Common Mode Dispersion vs. Supply Voltage Bias Current vs. Temperature 20183234 20183235 Input Current vs. Differential Input Voltage Maximum Toggle Rate 20183236 www.national.com 20183237 8 Hysteresis Voltage vs. Hysteresis Resistor 20183239 20183238 9 www.national.com LMH7322 Output Voltage vs. Input Voltage LMH7322 Application Information INTRODUCTION The LMH7322 is a high speed comparator with RS(P)ECL (Reduced Swing Positive Emitter Coupled Logic) outputs, and is compatible with LVDS (Low Voltage Differential Signaling) if VCCO is set to 2.5V. The use of complementary outputs gives a high level of suppression for common mode noise. The very fast rise and fall times of the LMH7322 enable data transmission rates up to several Gigabits per second (Gbps). The LMH7322 inputs have a common mode voltage range that extends 200 mV below the negative supply voltage thus allowing ground sensing in case of single supply. The rise and fall times of the LMH7322 are about 160 ps, while the propagation delay time is about 700 ps. The LMH7322 can operate over the full supply voltage range of 2.7V to 12V, while using single or dual supply voltages. This is a very useful feature because it provides a flexible way to interface between several high speed logic families. Several setups are shown in the application information section “INTERFACE BETWEEN LOGIC FAMILIES”. The outputs are referenced to the positive VCCO supply rail. The supply current is 23 mA at 5V (per comparator, load current excluded.) The LMH7322 is available in a 24-Pin LLP package. The following topics will be discussed in this application section. • Input and output topology • Specification definitions • Propagation delay and dispersion • Hysteresis and oscillations • Output • Applying transmission lines • PCB layout 20183209 FIGURE 1. Equivalent Input Circuitry The output stage of the LMH7322 is built using two emitter followers, which are referenced to the VCCO (see Figure 2.) Each of the output transistors is active when a current is flowing through any external output resistor connected to a lower supply rail. The output structure is actually the same as for all other ECL devices. Activating the outputs is done by connecting the emitters to a termination voltage which lies 2V below the VCCO. In this case a termination resistor of 50Ω can be used and a transmission line of 50Ω can be driven. Another method is to connect the emitters through a resistor to the most negative supply by calculating the right value for the emitter current in accordance with the datasheet tables. Both methods are useful, and it is up to the customer which method is used. Using 50Ω to the termination voltage means the introduction of an extra supply in the system, while using resistors to a negative supply means the use of resistors that are much larger than 50Ω and a more constant output current per stage. The following calculation will show the difference. In this example a VCCO of 2.5V is used and a VT of VCCO-2V and a negative supply of −5V. When connecting the outputs through a 50Ω resistor to the VT, the output currents for the high and the low state are respectively 18 mA and 10 mA. Connecting the outputs through a 400Ω resistor to the −5V supply the output currents for the high and the low state are respectively 16 mA and 15 mA. Higher resistor values to the VEE will further reduce power consumption but will cause a slower transition of the output stage. In the case that this will not harm your application it is a useful method to reduce power consumption. INPUT & OUTPUT TOPOLOGY All input and output pins are protected against excessive voltages by ESD diodes. These diodes are conducting from the negative supply to the positive supply. As can be seen in Figure 1, both inputs are connected to these diodes. Further protection of the inputs is provided by the two resistors of 250Ω, in conjunction with the string of anti-parallel diodes connected between both bases of the input stage. This combination of resistors and diodes reduces excessive input voltages over the input stage, but is low enough to maintain switching speed to the output signal. Protection against excessive supply voltages is provided by a power clamp between VCC and GND. When using this part be aware of situations in which the differential input voltage level is such that these diodes are conducting. In this case the input current is raised far above the normal value stated in the datasheet tables because input current is flowing through the bypass diode string between both inputs. www.national.com 10 20183210 FIGURE 2. Equivalent Output Circuitry DEFINITIONS Symbol Text Description IB Input Bias Current Current flowing in or out of the input pins, when both are biased at the VCM voltage as specified in the tables. IOS Input Offset Current Difference between the input bias current of the inverting and non-inverting inputs. TC IOS Average Input Offset Current Drift Temperature coefficient of IOS. VOS Input Offset Voltage Voltage difference needed between IN+ and IN- to make the outputs change state, averaged for H to L and L to H transitions. TC VOS Average Input Offset Voltage Drift Temperature coefficient of VOS . VRI Input Voltage Range Voltage which can be applied to the input pin maintaining normal operation. VRID Input Differential Voltage Range Differential voltage between positive and negative input at which the input clamp is not working. The difference can be as high as the supply voltage but excessive input currents are flowing through the clamp diodes and protection resistors. CMRR Common Mode Rejection Ratio Ratio of input offset voltage change and input common mode voltage change. PSRR Power Supply Rejection Ratio Ratio of input offset voltage change and supply voltage change from VS-MIN to VS-MAX. AV Active Gain Overall gain of the circuit. Hyst Hysteresis Difference between the switching point ‘0’ to ‘1’ and vice versa. IB-LE Latch Enable Bias Current Current flowing in or out of the input pins, when both are biased at normal PECL levels. IOS-LE Latch Enable Offset Current Difference between the input bias current of the LE and LE pin. TC IOS-LE Temp Coefficient Latch Enable Offset Temperature coefficient of IOS-LE. Current VOS-LE Latch Enable Offset Voltage TC VOS-LE Temp Coefficient Latch Enable Offset Temperature coefficient of VOS-LE. Voltage VRI-LE Latch Enable Voltage Range Voltage which can be applied to the LE input pins without damaging the device. VRID-LE Latch Enable Differential Voltage Range Differential Voltage between LE and LE at which the clamp isn’t working. The difference can be as high as the supply voltage but excessive input currents are flowing through the clamp diodes and protection resistors. VOH Output Voltage High High state single ended output voltage (Q or Q) (see Figure 17). Voltage difference needed between LE and LE to place the part in the latched or the transparent state. 11 www.national.com LMH7322 The output voltages for ‘1’ and ‘0’ have a difference of approximately 400 mV and are respectively 1.1V (for the ‘1’) and 1.5V (for the ‘0’) below the VCCO. This swing of 400 mV is enough to drive any LVDS input but can also be used to drive any ECL or PECL input, when the right supply voltage is chosen, especially the right level for the VCCO. LMH7322 Symbol Text Description VOL Output Voltage Low Low state single ended output voltage (Q or Q) (see Figure 17). VOD average of VODH and VODL (VODH + VODL)/2. IVCCI Supply Current Input Stage Supply current into the input stage. IVCCO Supply Current Output Stage Supply current into the output stage while current through the load resistors is excluded. IVEE Supply Current VEE pin Current flowing to the negative supply pin. TR Maximum Toggle Rate Maximum frequency at which the outputs can toggle between the nominal VOH and VOL. PW Pulse Width Time from 50% of the rising edge of a signal to 50% of the falling edge. tPDH resp tPDL Propagation Delay Delay time between the moment the input signal crosses the switching level L to H and the moment the output signal crosses 50% of the rising edge of Q output (tPDH), or delay time between the moment the input signal crosses the switching level H to L and the moment the output signal crosses 50% of the falling edge of Q output (tPDL). tPDL resp tPDH Delay time between the moment the input signal crosses the switching level L to H and the moment the output signal crosses 50% of the falling edge of Q output (tPDL), or delay time between the moment the input signal crosses the switching level H to L and the moment the output signal crosses 50% of the rising edge of Q output (tPDH). tPDLH Average of tPDH and tPDL . tPDHL Average of tPDL and tPDH. tPD Average of tPDLH and tPDHL. tPDHd resp tPDLd Delay time between the moment the input signal crosses the switching level L to H and the zero crossing of the rising edge of the differential output signal (tPDHd), or delay time between the moment the input signal crosses the switching level H to L and the zero crossing of the falling edge of the differential output signal (tPDLd). tOD-disp Input Overdrive Dispersion Change in tPD for different overdrive voltages at the input pins. tSR-disp Input Slew Rate Dispersion Change in tPD for different slew rates at the input pins. tCM-disp Input Common Mode Dispersion Change in tPD for different common mode voltages at the input pins. ΔtPDLH resp Q to Q Time Skew Time skew between 50% levels of the rising edge of Q output and the falling edge of output (ΔtPDLH), or time skew between 50% levels of falling edge of ΔtPDHL Q output and rising edge of Q output (ΔtPDHL). ΔtPD Average Q to Q Time Skew Average of tPDLH and tPDHL for L to H and H to L transients. ΔtPDd Average Diff. Time Skew Average of tPDHd and tPDLd for L to H and H to L transients. tr / trd Output Rise Time (20% - 80%) Time needed for the (single ended or differential) output voltage to change from 20% of its nominal value to 80%. tf / tfd Output Fall Time (20% - 80%) Time needed for the (single ended or differential) output voltage to change from 80% of its nominal value to 20%. tsLE Latch Setup Time Time the input signal has to be stable before enabling the latch functionality. thLE Latch Hold Time Time the input signal has to remain stable after enabling the latch functionality. tPD-LE Latch to Output Delay Time Delay time between the moment the latch input crosses the switching level H to L and the moment the differential output signal crosses the 50% level. Note: input signal is opposite to output signal when latch becomes enabled. www.national.com 12 LMH7322 20183204 FIGURE 3. Timing Definitions 20183203 FIGURE 4. LE Timing 13 www.national.com LMH7322 Pin Descriptions Pin Name Description Comment 1. VCCOA Positive Supply Output Stage part A The supply pin for the output stage is independent of the supply pin for the input pin. This allows output levels of different logic families. 2. LEA Latch Enable Input part A Logic ‘1’ sets the part on hold. Logic levels are RSPECL (Reduced Swing PECL) compatible. 3. LEA Latch Enable Input Not part A Logic ‘0’ sets the part on hold. Logic levels are RSPECL compatible. 4. VEEA Negative Supply part A The supply pin for the negative supply is connected to the VEEB via a string of two anti-parallel diodes (see Figure 1) 5. VCCIA Positive Supply for Input Stage part A The supply pin for the input stage is independent of the supply for the output stage. 6. RHYSA Hysteresis Resistor part A The hysteresis voltage is determined by connecting a resistor from this pin to RHREFA. 7. INA- Negative Input part A Input for analog voltages between 200 mV below VEEA and 2V below VCCIA. 8. INA+ Positive Input part A Input for analog voltages between 200 mV below VEEA and 2V below VCCIA. 9. RHREFA Reference Voltage Hysteresis part A Resistor The hysteresis voltage is determined by connecting a resistor from this pin to RHYSA. 10. RHREFB Reference Voltage Hysteresis part B Resistor The hysteresis voltage is determined by connecting a resistor from this pin to RHYSB. 11. INB+ Positive Input part B Input for analog voltages between 200 mV below VEEB and 2V below VCCIB. 12. INB− Negative Input part B Input for analog voltages between 200 mV below VEEB and 2V below VCCIB. 13. RHYSB Hysteresis Resistor part B The hysteresis voltage is determined by connecting a resistor from this pin to RHREFB. 14. VCCIB Positive Supply for Input Stage part B The supply pin for the input stage is independent of the supply for the output stage. 15. VEEB Negative Supply part B The supply pin for the negative supply is connected to the VEEA via a string of two anti-parallel diodes (see Figure 1). 16. LEB Latch Enable Input Not part B Logic ‘0’ sets the part on hold. Logic levels are RSPECL compatible. 17. LEB Latch Enable Input Logic part B ‘1’ sets the part on hold. Logic levels are RSPECL compatible. 18. VCCOB Positive Supply for Output Stage part B The supply pin for the output stage is independent of the supply pin for the input pin. This allows output levels of different logic families. 19. QB Inverted Output part B Output levels are determined by the choice of VCCOB. 20. QB Output part B Output levels are determined by the choice of VCCOB. 21. VCCOB Positive Supply for Output Stage part B See other VCCOB 22. VCCOA Positive Supply for Output Stage part A See other VCCOA. 23. QA Output part A Output levels are determined by the choice of VCCOA. 24. QA Inverted Output part A Output levels are determined by the choice of VCCOA. 25. DAP Central pad at the bottom of the package A&B This pad is connected to the VEE pins and its purpose is to transfer heat outside the part. www.national.com 14 THE LATCH ENABLE PINS The latch function is intended to stop the device from comparing the signals on both input pins. If the latch function is enabled, the output is frozen and the logic information on the output pins, present at that moment, is held until the latch function is disabled. The timing of this process can be seen in Figure 4. The input levels for the latch pins should comply with RSPECL, but can also be driven with PECL type of signals if the minimum supply (VCCO –V EE) is larger or equal to 3.3V. The minimum differential latch input voltage should be 100 mV. Another possibility to set the LE function in a steady state is to connect the pins via a resistor to the power supply. If the LE pin is connected to VEE via a resistor of 10 kΩ and the LE-not pin is connected via 10 kΩ to the VCCO pin the part is continuously on. Since the latch input stage is referenced to VCCO, the resistors to set the LE function should be connected to this voltage. This is very important when working with different voltages for VCCI and VCCO. If connected to the wrong supply, the latch function will not work. 20183225 FIGURE 5. DAP Connection INTERFACE BETWEEN LOGIC FAMILIES As can be seen in the typical schematics (see the first part of the datasheet) the LMH7322 can be used to interface between different logic families. The feature that facilitates this property is the fact that the input stage and the output stage use different positive power supply pins which can be used at different supply voltages. The negative supply pins are connected together for both parts. Using the power pins at different supply voltages makes it possible to create several translations for logic families. It is possible to translate from logic at negative voltage levels such as ECL to logic at positive levels such as RSPECL and LVDS and vice versa. The drawings in the next paragraphs do not show the output resistors except the first one. This is intentionally done for simplicity. All outputs need an output resistor to a termination voltage or to the negative rail as can be seen on the front page in the typical application of an ECL to RSPECL converter. THE DAP AND THE VEE PINS To ensure that both VEE pins are operating at the same voltage, both pins are connected to the DAP, and thus to each other, through bond wires. As a consequence, the DAP is at the same potential as the VEE pins and can be used to connect the device to the minimum supply voltage. A more solid VEE connection is obtained if the two VEE pins and the DAP are all connected to the minimum supply on the PCB, rather than an indirect connection through the internal bond wires. To protect the device during handling and production two antiparallel connected diodes are connected between both VEE pins. Under normal operating conditions these diodes are shorted via the DAP. Interface from ECL to RSPECL The supply pin VCCI can be connected to ground because the input levels are negative and the VCCO pin must operate at 5V to create the RSPECL levels (see Figure 6). When working with ECL, the negative supply pin (VEE) can be connected to the −5.2V ECL supply voltage. 20183205 FIGURE 6. ECL TO RSPECL 15 www.national.com LMH7322 The DAP (Die Attach Paddle) functions as a heat sink which means that heat can be transferred using vias below this pad to the copper plane VEE is connected to. TIPS & TRICKS USING THE LMH7322 In this section several aspects are discussed concerning special applications using the LMH7322. This concerns the LE function, the connection of the DAP in conjunction to the VEE pins and the use of this part as an interface between several logic families. LMH7322 high level of the output of the LMH7322 is normally 1.1V below the VCCO supply voltage, and the low level is 1.5V below this supply. The output levels are now −1100 mV for the logic ‘1’ and −1500 mV for the logic ‘0’ (see Figure 7). In the same way the VEE can be connected to the ECL supply voltage of −5.2V. Interface from PECL to (RS)ECL The conversion from PECL to RS-ECL is possible when connecting the VCCI pin to +5V, which allows the input stage to handle these positive levels. The VCCO pin must be connected to the ground level in order to create the RSECL levels. The 20183206 FIGURE 7. PECL TO RSECL need to use different positive supply voltages. The input signal is AC coupled to the positive input. To maintain reliable results the input pins IN+ and IN− are biased at 1.4V through a resistive divider using a resistor of 1 kΩ to ground and a resistor of 2.5 kΩ to the VCC and by adding two decoupling capacitors. Both inputs are connected to the bias level by the use of a 10 kΩ resistor. With this input configuration the input stage can work in a linear area with signals of approximately 3 VPP (see input level restrictions in the data tables.) Interface from Analog to LVDS As seen in Figure 8, the LMH7322 can be configured to create LVDS levels. This is done by connecting the VCCO to 2.5V. As discussed before the output levels are now at VCCO –1.1V for the logic ‘1’ and at VCCO −1.5V for the logic ‘0’. These levels of 1000 mV and 1400 mV comply with the LVDS levels. As can be seen in this setup, an AC coupled signal via a transmission line is used. This signal is terminated with 50Ω. 20183207 FIGURE 8. ANALOG TO LVDS Figure 9 shows a standard comparator setup which creates RSPECL levels because the VCCO supply voltage is +5V. In this case the VEE pin is connected to the ground level. The VCCI pin is connected to the VCCO pin because there is no www.national.com 20183208 FIGURE 9. Standard Setup 16 LMH7322 DELAY AND DISPERSION Comparators are widely used to connect the analog world to the digital one. The accuracy of a comparator is dictated by its DC properties, such as offset voltage and hysteresis, and by its timing aspects, such as rise and fall times and delay. For low frequency applications most comparators are much faster than the analog input signals they handle. The timing aspects are less important here than the accuracy of the input switching levels. The higher the frequencies, the more important the timing properties of the comparator become, because the response of the comparator can make a noticeable change in critical parameters such as time frame or duty cycle. A designer has to know these effects and has to deal with them. In order to predict what the output signal will do, several parameters are defined which describe the behavior of the comparator. For a good understanding of the timing parameters discussed in the following section, a brief explanation is given and several timing diagrams are shown for clarification. PROPAGATION DELAY The propagation delay parameter is described in the definition section. Due to this definition there are two parameters, tPDH and tPDL (Figure 10). Both parameters do not necessarily have the same value. It is possible that differences will occur due to a different response of the internal circuitry. As a derivative of this effect another parameter is defined: ΔtPD. This parameter is defined as the absolute value of the difference between tPDH and tPDL. 20183212 FIGURE 11. tPD with Complementary Outputs Both output circuits should be symmetrical. At the moment one output is switching ‘on’ the other is switching ‘off’ with ideally no skew between both outputs. The design of the LMH7322 is optimized so that this timing difference is minimized. The propagation delay, tPD, is defined as the average delay of both outputs at both slopes: (tPDLH + tPDHL)/2. Both overdrive and starting point should be equally divided around the VREF (absolute values). DISPERSION There are several circumstances that will produce a variation of the propagation delay time. This effect is called dispersion. Amplitude Overdrive Dispersion One of the parameters that causes dispersion is the amplitude variation of the input signal. Figure 12 shows the dispersion due to a variation of the input overdrive voltage. The overdrive is defined as the ‘go to’ differential voltage applied to the inputs. Figure 12 shows the impact it has on the propagation delay time if the overdrive is varied from 10 mV to 100 mV. This parameter is measured with a constant slew rate of the input signal. 20183211 FIGURE 10. Propagation Delay If ΔtPD is not zero, duty cycle distortion will occur. For example when applying a symmetrical waveform (e.g. a sinewave) at the input, it is expected that the comparator will produce a symmetrical square wave at the output with a duty cycle of 50%. When tPDH and tPDL are different, the duty cycle of the output signal will not remain at 50%, but will be increased or decreased. In addition to the propagation delay parameters for single ended outputs discussed before, there are other parameters in the case of complementary outputs. These parameters describe the delay from input to each of the outputs and the difference between both delay times (See Figure 11.) When the differential input signal crosses the reference level from L to H, both outputs will switch to their new state with some delay. This is defined as tPDH for the Q output and tPDL for the Q output, while the difference between both signals is defined as ΔtPDLH. Similar definitions for the falling slope of the input signal can be seen in Figure 3. 17 www.national.com LMH7322 Common Mode Dispersion Dispersion will also occur when changing the common mode level of the input signal (Figure 14). When VREF is swept through the CMVR (Common Mode Voltage Range), It results in a variation of the propagation delay time. This variation is called Common Mode Dispersion. 20183213 FIGURE 12. Overdrive Dispersion The overdrive dispersion is caused by the switching currents in the input stage which is dependent on the level of the differential input signal. 20183215 Slew Rate Dispersion The slew rate is another parameter that affects propagation delay. The higher the input slew rate, the faster the input stage switches (See Figure 13). FIGURE 14. Common Mode Dispersion All of the dispersion effects described previously influence the propagation delay. In practice the dispersion is often caused by a combination of more than one varied parameter. HYSTERESIS & OSCILLATIONS In contrast to an op amp, the output of a comparator has only two defined states ‘0’ or ‘1.’ Due to finite comparator gain however, there will be a small band of input differential voltage where the output is in an undefined state. An input signal with fast slopes will pass this band very quickly without problems. During slow slopes however, passing the band of uncertainty can take a relatively long time. This enables the comparators output to switch back and forth several times between ‘0’ and ‘1’ on a single slope. The comparator will switch on its input noise, ground bounce (possible oscillations), ringing etc. Noise in the input signal will also contribute to these undesired switching actions. The next sections explain these phenomena in situations where no hysteresis is applied, and discuss the possible improvement hysteresis can give. Using No Hysteresis Figure 15 shows what happens when the input signal rises from just under the threshold VREF to a level just above it. From the moment the input reaches the lowest dotted line around VREF at t=0, the output toggles on noise etc. Toggling ends when the input signal leaves the undefined area at t=1. In this example the output was fast enough to toggle three times. Due to this behavior digital circuitry connected to the output will count a wrong number of pulses. One way to prevent this is to choose a very slow comparator with an output that is not able to switch more than once between ‘0’ and ‘1’ during the time the input state is undefined. 20183214 FIGURE 13. Slew Rate Dispersion A combination of overdrive and slew rate dispersion occurs when applying signals with different amplitudes at constant frequency. A small amplitude will produce a small voltage change per time unit (dV/dt) but also a small maximum switching current (overdrive) in the input transistors. High amplitudes produce a high dV/dt and a larger overdrive. www.national.com 18 The Output 20183216 OUTPUT SWING PROPERTIES The LMH7322 has differential outputs which means that both outputs have the same swing but in opposite directions (See Figure 17). Both outputs swing around the common mode output voltage (VO). This voltage can be measured at the midpoint between two equal resistors connected to each output. The absolute value of the difference between both voltages is called VOD. The outputs cannot be held at the VO level because of their digital nature. They only cross this level during a transition. Due to the symmetrical structure of the circuit, both output voltages cross at VO regardless of whether the output changes from ‘0’ to ‘1’ or vise versa. FIGURE 15. Oscillations on Output Signal In most circumstances this is not an option because the slew rate of the input signal will vary. Using Hysteresis A good way to avoid oscillations and noise during slow slopes is the use of hysteresis. For this purpose the switching level is forced to a new level at the moment the input signal crosses this level. This can be seen in Figure 16. 20183219 FIGURE 17. Output Swing LOADING THE OUTPUT Both outputs are activated when current is flowing through a resistor that is externally connected to VT. The termination voltage should be set 2V below the VCCO. This makes it possible to terminate each of the outputs directly with 50Ω, and if needed to connect through a transmission line with the same impedance (see Figure 18). Due to the low ohmic nature of the output emitter followers and the 50Ω load resistor, a capacitive load of several pF does not dramatically affect the speed and shape of the signal. When transmitting the signal from one output to any input the termination resistor should match the transmission line. The capacitive load (CP) will distort the received signal. When measuring this input with a probe, a certain amount of capacitance from the probe is parallel to the termination resistor. The total capacitance can be as large as 10 pF. In this case there is a pole at: f = 1/(2*π*C*R) f = 1e9/ π f = 318 MHz 20183218 FIGURE 16. Hysteresis In this picture there are two dotted lines A and B, both indicating the resulting level at which the comparator output will switch over. Assume that for this situation the input signal is connected to the negative input and the switching level (VREF) to the positive input. The LMH7322 has a hysteresis pin, so a resistor connected to this pin determines the variation of the VREF level dependent on the state of the output. The hysteresis pin must be connected to the VEE and can be varied from a short to an open pin. A short to VEE means the highest hysteresis voltage variation and an open pin means no level variation. The input level of Figure 16 starts much lower as the reference level and this means that the state of the input stage is well defined with the inverting input much lower than the non-inverting input. As a result the output will be in the high state. Internally the switching level is at A, with the input signal sloping up, this situation remains until VIN 19 www.national.com LMH7322 crosses level A at t=1. Now the output toggles, and the internal switching level is lowered to level B. So before the output has the possibility to toggle again, the difference between the inputs is made sufficient to have a stable situation again. When the input signal comes down from high to low, the situation is stable until level B is reached at t=0. At this moment the output will toggle back, and the circuit is back in the starting situation with the inverting input at a much lower level than the non inverting input. In the situation without hysteresis, the output will toggle exactly at VREF. With hysteresis this happens at the internally introduced levels A and B, as can be seen in Figure 16. Varying the levels A and B due to the change of the hysteresis resistor will also vary the timing of t=0 and t=1. When designing a circuit be aware of this effect. Introducing hysteresis will cause some time shift between output and input (e.g. duty cycle variations), but will eliminate undesired switching of the output. LMH7322 In this case the current IP has the same value as the current through the termination resistor. This means that the voltage drops at the input and the rise and fall times are dramatically different from the specified numbers for this part. Another parasitic capacitance that can affect the output signal is the capacitance directly between both outputs, called CPAR (see Figure 18). The LMH7322 has two complementary outputs so there is the possibility to transport the output signal by a symmetrical transmission line. In this case both output tracks form a coupled line with their own parasitics and both receiver inputs connected to the transmission line. Actually the line termination looks like 100Ω and the input capacitances, which are in series, are parallel to the 100Ω termination. The best way to measure the input signal is to use a differential probe directly across both inputs. Such a probe is very suitable for measuring these fast signals because it has good high frequency characteristics and low parasitic capacitance. Maximum Bit Rates The maximum toggle rate is defined at an amplitude of 50% of the nominal output signal. This toggle rate is a number for the maximum transfer rate of the part and can be given in Hz or in Bps. When transmitting signals in a NRZ (Non Return to Zero) format the bitrate is double this frequency number, because during one period two bits can be transmitted. (See Figure 19.) The rise and fall times are very important specifications in high speed circuits. In fact these times determine the maximum toggle rate of the part. Rise and fall times are normally specified at 20% and 80% of the signal amplitude (60% difference). Assuming that the edges at 50% amplitude are coming up and down like a sawtooth it is possible to calculate the maximum toggle rate but this number is too optimistic. In practice the edges are not linear while the pulse shape is more or less a sinewave. 20183222 FIGURE 19. Bit Rates Need for Terminated Transmission Lines During the 1980’s and 90’s, National fabricated the 100K ECL logic family. The rise and fall time specifications were 0.75 ns, which are considered very fast. If sufficient care has not been given in designing the transmission lines and choosing the correct terminations, then errors in digital circuits are introduced. To be helpful to designers that use ECL with “old” PCB-techniques, the 10K ECL family was introduced with a rise and fall time specification of 2 ns. This was much slower and easier to use. The RSPECL output signals of the LMH7322 have transition times that extend the fastest ECL family. A careful PCB design is needed using RF techniques for transmission and termination. Transmission lines can be formed in several ways. The most commonly used types are the coaxial cable and the twisted pair telephony cable (Figure 20). 20183221 FIGURE 18. Parasitic Capacitance TRANSMISSION LINES & TERMINATION TECHNOLOGIES The LMH7322 uses complementary RSPECL outputs and emitter followers, which means high output current capability and low sensitivity to parasitic capacitance. The use of Reduced Swing Positive Emitter Coupled Logic reduces the supply voltage to 2.7V, being the lowest possible value, and raises the maximum frequency response. Data rates are growing, which requires increasing speed. Data is not only connected to other IC’s on a single PCB board but, in many cases, there are interconnections from board to board or from equipment to equipment. Distances can be short or long but it is always necessary to have a reliable connection, which consumes low power and is able to handle high data rates. The complementary outputs of the LMH7322 make it possible to use symmetrical transmission lines The advantage over single ended signal transmission is that the LMH7322 has higher immunity to common mode noise. Common mode signals are signals that are equally apparent on both lines and because the receiver only looks at the difference between both lines, this noise is canceled. www.national.com 20183223 FIGURE 20. Cable Types 20 of the track determines the resulting impedance. So, if the PCB manufacturer can produce reliable boards with low track spacing the track width for a given impedance is also small. The wider the spacing, the wider tracks are needed for a specific impedance. For example two tracks of 0.2 mm width and 0.1 mm spacing have the same impedance as two tracks of 0.8 mm width and 0.4 mm spacing. With high-end PCB processes, it is possible to design very narrow differential microstrip transmission lines. It is desirable to use these to create optimal connections to the receiving part or the terminating resistor, in accordance to their physical dimensions. Seen from the comparator, the termination resistor must be connected at the far end of the line. Open connections after the termination resistor (e.g. to an input of a receiver) must be as short as possible. The allowed length of such connections varies with the received transients. The faster the transients, the shorter the open lines must be to prevent signal degradation. PCB LAYOUT CONSIDERATIONS AND COMPONENT VALUE SELECTION High frequency designs require that both active and passive components be selected from those that are specially designed for this purpose. The LMH7322 is fabricated in a 24pin LLP package intended for surface mount design. For reliable high speed design it is highly recommended to use small surface mount passive components because these packages have low parasitic capacitance and low inductance simply because they have no leads to connect them to the PCB. It is possible to amplify signals at frequencies of several hundreds of MHz using standard through-hole resistors. Surface mount devices however, are better suited for this purpose. Another important issue is the PCB itself, which is no longer a simple carrier for all the parts and a medium to interconnect them. The PCB becomes a real component itself and consequently contributes its own high frequency properties to the overall performance of the circuit. Good practice dictates that a high frequency design have at least one ground plane, providing a low impedance path for all decoupling capacitors and other ground connections. Care should be given especially that on-board transmission lines have the same impedance as the cables to which they are connected. Most single ended applications have 50Ω impedance (75Ω for video and cable TV applications). Such low impedance, single ended microstrip transmission lines usually require much wider traces (2 to 3 mm) on a standard double sided PCB board than needed for a ‘normal’ trace. Another important issue is that inputs and outputs should not ‘see’ each other. This occurs if input and output tracks are routed in parallel over the PCB with only a small amount of physical separation, particularly when the difference in signal level is high. Furthermore, components should be placed as flat and low as possible on the surface of the PCB. For higher frequencies a long lead can act as a coil, a capacitor or an antenna. A pair of leads can even form a transformer. Careful design of the PCB minimizes oscillations, ringing and other unwanted behavior. For ultra high frequency designs only surface mount components will give acceptable results. (For more information see OA-15). 20183224 FIGURE 21. PBC Lines Differential Microstrip Line The transmission line which is ideally suited for complementary signals is the differential microstrip line. This is a double microstrip line with a narrow space in between. This means both lines have strong coupling and this determines the characteristic impedance. The fact that they are routed above a copper plane does not affect differential impedance, only CM-capacitance is added. Each of the structures above has its own geometric parameters, so for each structure there is different formula to calculate the right impedance. For calculations on these transmission lines visit the National website or order RAPIDESIGNER. At the end of the transmission line there must be a termination having the same impedance as that of the transmission line itself. It does not matter what impedance the line has, if the load has the same value no reflections will occur. When designing a PCB board with transmission lines on it, space becomes an important item especially on high density boards. With a single microstrip line, line width is fixed for given impedance and a board material. Other line widths will result in different impedances. Advantages of Differential MicrostripLines Impedances of transmission lines are always dictated by their geometric parameters. This is also true for differential microstrip lines. Using this type of transmission line, the distance NSC suggests the following evaluation board as a guide for high frequency layout and as an aid in device testing ULV94V-0 551013148-001 Rev A 21 www.national.com LMH7322 These cables have a characteristic impedance determined by their geometric parameters. Widely used impedances for the coaxial cable are 50Ω and 75Ω. Twisted pair cables have impedances of about 120Ω to 150Ω. Other types of transmission lines are the strip line and the micro strip line. These last types are used on PCB boards. They have the characteristic impedance dictated by the physical dimensions of a track placed over a metal ground plane (see Figure 21). LMH7322 Physical Dimensions inches (millimeters) unless otherwise noted 24-Pin LLP Package NS Package Number SQA24A www.national.com 22 LMH7322 Notes 23 www.national.com LMH7322 Dual 700 ps High Speed Comparator with RSPECL Outputs Notes For more National Semiconductor product information and proven design tools, visit the following Web sites at: Products Design Support Amplifiers www.national.com/amplifiers WEBENCH® Tools www.national.com/webench Audio www.national.com/audio App Notes www.national.com/appnotes Clock and Timing www.national.com/timing Reference Designs www.national.com/refdesigns Data Converters www.national.com/adc Samples www.national.com/samples Interface www.national.com/interface Eval Boards www.national.com/evalboards LVDS www.national.com/lvds Packaging www.national.com/packaging Power Management www.national.com/power Green Compliance www.national.com/quality/green Switching Regulators www.national.com/switchers Distributors www.national.com/contacts LDOs www.national.com/ldo Quality and Reliability www.national.com/quality LED Lighting www.national.com/led Feedback/Support www.national.com/feedback Voltage Reference www.national.com/vref Design Made Easy www.national.com/easy PowerWise® Solutions www.national.com/powerwise Solutions www.national.com/solutions Serial Digital Interface (SDI) www.national.com/sdi Mil/Aero www.national.com/milaero Temperature Sensors www.national.com/tempsensors Solar Magic® www.national.com/solarmagic Wireless (PLL/VCO) www.national.com/wireless Analog University® www.national.com/AU THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. 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