AOZ8001A Ultra-Low Capacitance TVS Diode Array General Description Features The AOZ8001A is a transient voltage suppressor array designed to protect high speed data lines from ESD and lightning. ● This device incorporates four surge rated, low capacitance steering diodes and a TVS in a single package. During transient conditions, the steering diodes direct the transient to either the positive side of the power supply line or to ground. They may be used to meet the ESD immunity requirements of IEC 61000-4-2, Level 4. The TVS diodes provide effective suppression of ESD voltages up to ±30kV (air discharge) and ±30kV (contact discharge). ● The AOZ8001A comes in RoHS compliant, SOT-143 package and is rated over a -40°C to +85°C ambient temperature range. It is compatible with both lead free and SnPb assembly techniques. ● ● ● ● The very small SOT-143 package is ideal for applications where PCB space is a premium. The small size, low capacitance and high ESD protection makes it ideal for protecting high speed video and data communication interfaces. ● ESD protection for high-speed data lines: AOZ8001AJI 5V: – IEC 61000-4-2, level 4 (ESD) immunity test – ±30kV (air discharge) and ±30kV (contact discharge) – IEC 61000-4-5 (Lightning) 18A (8/20µs) – Human Body Model (HBM) ±30kV AOZ8001AJI 12V: – IEC61000-4-2, Level 4 (ESD) immunity test – ±30kV (air discharge) and ±30kV (contact discharge) – IEC61000-4-5 (Lightning) ±13A (8/20µs) – Human Body Model (HBM) ±30kV Small package saves board space Low insertion loss Protects two I/O lines Low capacitance from IO to Ground: 1.8pF Low clamping voltage Low operating voltages: 5V, 12V Applications ● ● ● ● ● ● USB 2.0 power and data line protection Video graphics cards Monitors and flat panel displays Digital Video Interface (DVI) 10/100/1000 Ethernet Notebook computers Typical Application +12V USB Controller USB Controller +5V D+ DGND +5V D+ DGND 1 4 Tip +12V xDSL Controller 1 +12V RJ11 Connector 2 2 3 Ring AOZ8001AJI-12 AOZ8001AJI-05 Figure 1. USB 2.0 High Speed Port Rev. 3.0 October 2010 Figure 2. xDSL Application www.aosmd.com Page 1 of 10 AOZ8001A Ordering Information Part Number Ambient Temperature Range Package Environmental AOZ8001AJI-05 -40°C to +85°C SOT-143 RoHS Compliant Green Product AOZ8001AJI-12 -40°C to +85°C SOT-143 RoHS Compliant Green Product AOS Green Products use reduced levels of Halogens, and are also RoHS compliant. Please visit www.aosmd.com/web/quality/rohs_compliant.jsp for additional information. Pin Configuration VN 1 CH1 2 4 VP 3 CH2 SOT-143 (Top View) Absolute Maximum Ratings Exceeding the Absolute Maximum ratings may damage the device. Parameter Rating Storage Temperature (TS) -65°C to +150°C Maximum Transient Rating Device HBM(1) ESD (Contact)(2) ESD (Air)(2) Surge (8/20µs) AOZ8001AJI-05 ±30kV ±30kV ±30kV ±18A AOZ8001AJI-12 ±30kV ±30KV ±30kV ±13A Notes: 1. Human Body Discharge per MIL-STD-883, Method 3015 CDischarge = 100pF, RDischarge = 1.5kΩ. 2. IEC 61000-4-2 discharge with CDischarge = 150pF, RDischarge = 330Ω. Maximum Operating Ratings Parameter Rating Junction Temperature (TJ) Rev. 3.0 October 2010 -40°C to +125°C www.aosmd.com Page 2 of 10 AOZ8001A Electrical Characteristics TA = 25°C unless otherwise specified. Symbol IPP Parameter Reverse Peak Pulse Current I VCL(5)(7) Clamping Voltage @ IPP VRWM(3) Working Peak Reverse Voltage IR VBR(4) Diagram IF Maximum Reverse Leakage Current @ VRWM Breakdown Voltage VCL VBR VRWM IF Forward Current VF Forward Voltage PPK Peak Power Dissipation CJ(6) I/O–GND Capacitance @ VR = 0 and f = 1MHz V IR VF IT IPP Device Device Marking VRWM (V) Max. VBR (V) Typ. @ 1mA IR (µA) Max. VF (V) Typ. VCL Max. IPP = 1A IPP = 5A IPP = 12A CJ (pF) Typ. CJ (pF) Max. AOZ8001AJI-05 AD 5.5 8.5 1.0 0.85 12.50 15.00 16.00 1.80 2.50 AOZ8001AJI-12 AD 12.5 15.0 1.0 0.85 16.00 18.00 19.00 1.80 2.50 Notes: 3. The working peak reverse voltage, VRWM, should be equal to or greater than the DC or continuous peak operating voltage level. 4. VBR is measured at the pulse test current IT. 5. Measurements performed with no external capacitor on VP (pin 4 floating). 6. Measurements performed with VP biased to 3.3 Volts (pin 4 @ 3.3V). 7. Measurements performed using a 100ns Transmission Line Pulse (TLP) system. Rev. 3.0 October 2010 www.aosmd.com Page 3 of 10 AOZ8001A Typical Performance Characteristics Typical Variation of CIN vs VR 1.0 0.8 5V 0.6 12V 0.4 0.2 0.0 0 1 2 3 4 5 6 7 (tperiod = 100ns, tr = 1ns) 20 Clamping Voltage, VCL (V) 1.2 Normalized Input Capacitance (pF) Clamping Voltage vs. Peak Pulse Current (VP = 3.3V, f = 1MHz, T = 25 oC) 8 9 16 5V 14 12 10 8 6 4 2 0 10 12V 18 0 Forward Voltage vs. Forward Current 5 Insertion Loss (dB) Forward Voltage (V) 15 0 4 2 -5 -10 -15 -20 0 0 2 4 6 8 10 12 -25 14 1 10 Forward Current (A) 1000 1000 I/O – I/O Insertion Loss (S21) vs. Frequency 5 0 Insertion Loss (dB) -20 -40 -60 -80 -100 -120 100 Frequency (MHz) Crosstalk (I/O–I/O) vs. Frequency 0 Insertion Loss (dB) 10 I/O – Gnd Insertion Loss (S21) vs. Frequency (tperiod = 100ns, tr = 1ns) 6 5 Peak Pulse Current, IPP (A) Input Voltage (V) 1 10 100 1000 10000 -10 -15 -20 -25 1 10 100 1000 1000 Frequency (MHz) Frequency (MHz) Rev. 3.0 October 2010 -5 www.aosmd.com Page 4 of 10 AOZ8001A Application Information The AOZ8001A TVS is design to protect two data lines from fast damaging transient over-voltage by clamping it to a reference. When the transient on a protected data line exceed the reference voltage the steering diode is forward bias thus, conducting the harmful ESD transient away from the sensitive circuitry under protection. PCB Layout Guidelines Printed circuit board layout is the key to achieving the highest level of surge immunity on power and data lines. The location of the protection devices on the PCB is the simplest and most important design rule to follow. The AOZ8001A devices should be located as close as possible to the noise source. The placement of the AOZ8001A devices should be used on all data and power lines that enter or exit the PCB at the I/O connector. In most systems, surge pulses occur on data and power lines that enter the PCB through the I/O connector. Placing the AOZ8001A devices as close as possible to the noise source ensures that a surge voltage will be clamped before the pulse can be coupled into adjacent PCB traces. In addition, the PCB should use the shortest possible traces. A short trace length equates to low impedance, which ensures that the surge energy will be dissipated by the AOZ8001A device. Long signal traces will act as antennas to receive energy from fields that are produced by the ESD pulse. By keeping line lengths as short as possible, the efficiency of the line to act as an antenna for ESD related fields is reduced. Minimize interconnecting line lengths by placing devices with the most interconnect as close together as possible. The protection circuits should shunt the surge voltage to either the reference or chassis ground. Shunting the surge voltage directly to the IC’s signal ground can cause ground bounce. The clamping performance of TVS diodes on a single ground PCB can be improved by minimizing the impedance with relatively short and wide ground traces. The PCB layout and IC package parasitic inductances can cause significant overshoot to the TVS’s clamping voltage. The inductance of the PCB can be reduced by Rev. 3.0 October 2010 using short trace lengths and multiple layers with separate ground and power planes. One effective method to minimize loop problems is to incorporate a ground plane in the PCB design. The AOZ8001A ultralow capacitance TVS is designed to protect four high speed data transmission lines from transient over-voltages by clamping them to a fixed reference. The low inductance and construction minimizes voltage overshoot during high current surges. When the voltage on the protected line exceeds the reference voltage the internal steering diodes are forward biased, conducting the transient current away from the sensitive circuitry. Good circuit board layout is critical for the suppression of ESD induced transients. The following guidelines are recommended: 1. Place the TVS near the IO terminals or connectors to restrict transient coupling. 2. Fill unused portions of the PCB with ground plane. 3. Minimize the path length between the TVS and the protected line. 4. Minimize all conductive loops including power and ground loops. 5. The ESD transient return path to ground should be kept as short as possible. 6. Never run critical signals near board edges. 7. Use ground planes whenever possible. 8. Avoid running critical signal traces (clocks, resets, etc.) near PCB edges. 9. Separate chassis ground traces from components and signal traces by at least 4mm. 10. Keep the chassis ground trace length-to-width ratio <5:1 to minimize inductance. 11. Protect all external connections with TVS diodes. www.aosmd.com Page 5 of 10 AOZ8001A AOZ8001A VCC 4 1 3 2 VCC Reset Clock SIM I/O GND 3 2 VCC 1 4 AOZ8001A SIM Card Port Connection AOZ8001A TPBIASx 4 3 TPAx+ TPAx- IEEE 1394 PHY 1 4 2 IEEE 1394 Connector 3 TPBx+ TPBx- GND 1 2 AOZ8001A IEEE1394 Port Connection Rev. 3.0 October 2010 www.aosmd.com Page 6 of 10 AOZ8001A AOZ8001A 4 3 TRD0+ TRD0- 1 2 AOZ8001A 4 3 TRD1+ TRD1- 1 Ethernet Controller 2 AOZ8001A 4 RJ45 Connector 3 TRD2+ TRD2- 1 2 AOZ8001A 4 3 TRD3+ TRD3- 1 2 10/100 Ethernet Port Connection Rev. 3.0 October 2010 www.aosmd.com Page 7 of 10 AOZ8001A Package Dimensions, SOT143-4L D e c S L1 E E1 e1 b2 θ b A A1 RECOMMENDED LAND PATTERN 1.92 0.70 0.60 1.90 0.70 1.05 0.76 UNIT: mm Dimensions in millimeters Symbols A A1 b Min. 0.890 0.013 0.370 b2 c D E E1 e e1 L1 S θ 0.760 0.085 2.800 2.100 1.200 Nom. — — — Max. 1.120 0.100 0.510 — 0.940 — 0.180 — 3.040 —— 2.640 — 1.400 1.920 BSC 0.200 BSC 0.550 REF 0.450 — 0.600 0° — 8° Dimensions in inches Symbols A A1 b Min. 0.035 0.001 0.015 b2 c D E E1 e e1 L1 S θ 0.030 0.003 0.110 0.083 0.047 Nom. — — — Max. 0.044 0.004 0.020 — 0.037 — 0.007 — 0.120 —— 0.104 — 0.055 0.076 BSC 0.008 BSC 0.022 REF 0.018 — 0.024 0° — 8° Notes: 1. All dimensions are in millimeters. 2. Tolerances are 0.10mm unless otherwise specified. 3. Package body sizes exclude mold flash and gate burrs. 4. Controlling dimension is millimeter, converted inch dimensions are not necessarily exact. Rev. 3.0 October 2010 www.aosmd.com Page 8 of 10 AOZ8001A Tape and Reel Dimensions, SOT143-4L Tape P2 E1 D1 P1 D0 K0 E2 E B0 A0 P0 T Feeding Direction UNIT: mm Package A0 B0 K0 SOT-143 3.10 ±0.10 2.69 ±0.10 1.30 ±0.10 D0 D1 E 1.00 8.00 1.50 ±0.10 +0.25/-0.00 +0.30/-0.10 Reel E1 E2 P0 P1 P2 T 1.75 ±0.10 3.50 ±0.05 4.00 ±0.10 4.00 ±0.10 2.00 ±0.05 0.254 ±0.013 W1 S K R M N J H UNIT: mm Tape Size Reel Size M N 8mm ø177.8 ø177.8 Max. 55.0 Min. W1 H 8.4 13.0 +1.50 / -0.0 +0.5 / -0.2 S K R J 1.5 Min 10.1 Min. 12.7 4.0 ±0.1 Leader/Trailer and Orientation Trailer Tape 300mm min. Rev. 3.0 October 2010 Components Tape Orientation in Pocket www.aosmd.com Leader Tape 500mm min. Page 9 of 10 AOZ8001A Part Marking AOZ8001AJI (SOT-143) Top Marking ADOA Part Number Code Assembly Location Code Option Code Bottom Marking YWLT Year & Week Code Assembly Lot Code This datasheet contains preliminary data; supplementary data may be published at a later date. Alpha & Omega Semiconductor reserves the right to make changes at any time without notice. LIFE SUPPORT POLICY ALPHA & OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. Rev. 3.0 October 2010 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.aosmd.com Page 10 of 10