CS1630 CS1631 2-Channel TRIAC Dimmable LED Driver IC Features Overview • Best-in-class Dimmer Compatibility - Leading-edge (TRIAC) Dimmers - Trailing-edge Dimmers - Digital Dimmers (with Integrated Power Supply) • Correlated Color Temperature (CCT) Control System • Up to 85% Efficiency • Flicker-free Dimming • Programmable Dimming Profile - Constant CCT Dimming - Black Body Line Dimming • 0% Minimum Dimming Level • Temperature Compensated LED Current • End-of-line Programming Using Power Line Calibration - Lower LED Binning Requirement • Programmable Series or Parallel Two-Channel Output - Interleaved Output Eliminates Additional Transformer • Programmable Quasi-resonant Second Stage with Constant-current Output - Flyback, Buck, and Tapped Buck • Register Lockout • Fast Startup • Tight LED Current Regulation: Better than ±5% • Primary-side Regulation (PSR) • >0.9 Power Factor • IEC-61000-3-2 Compliant • Soft Start • Protections: - Output Open/Short - Current-sense Resistor Open/Short - External Overtemperature Using NTC The CS1630 and CS1631 are high-performance offline AC /DC LED drivers for dimmable and high color rendering index (CRI) LED replacement lamps and luminaires. They feature Cirrus Logic’s proprietary digital dimmer compatibility control technology and digital correlated color temperature (CCT) control system that enables two-channel LED color mixing. The CS1630 is designed for 120VAC line voltage applications, and the CS1631 is optimized for 230VAC line voltage applications. L1 The CS1630/31 integrates a critical conduction mode boost converter, providing power factor correction and superior dimmer compatibility with a primary-side regulated quasi-resonant second stage, which is configurable for isolated and non-isolated topologies. The digital CCT control system provides the ability to program dimming profiles, such as constant CCT dimming and black body line dimming. The CS1630/31 optimizes LED color mixing by temperature compensating LED current with an external NTC. The IC controller is also equipped with power line calibration for remote system calibration and end-of-line programming. The CS1630/31 provides a register lockout feature for security against potential access to proprietary registers. Applications • • • • Dimmable Retrofit LED Lamps and LED Luminaries High CRI Lighting Offline LED Drivers Commercial Lighting Ordering Information See page 55. L2 Vrec t VB S T T1 D6 R8 C3 BR1 R2 BR1 R3 R5 R4 D3 C6 1 R7 D9 16 CS1630 /31 5 Q1 BR1 BR1 Z1 D5 GD FBAUX FBSENSE 14 C4 R12 VDD eOTP Q4 13 SGND 4 Q5 GND LED 1+ R16 C10 C12 D8 LED 115 IGND 11 10 R13 RS C7 Cirrus Logic, Inc. http://www.cirrus.com SOURCE LED2- D Q3 IAC Q2 Z3 D11 V CC _ Q C2 D1 C9 BSTOUT CLAMP 3 C1 LED2+ R15 D10 D4 2 D2 Z2 D7 R1 AC Mains C8 R9 BSTAUX C5 R10 C11 R6 GND 12 Copyright Cirrus Logic, Inc. 2012 (All Rights Reserved) CNTC NTC R11 R14 DEC’12 DS954F2 CS1630/31 TABLE OF CONTENTS 1.INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.CHARACTERISTICS AND SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.1 3.2 3.3 3.4 3.5 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 I2C Port Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Power Line Calibration Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 4.TYPICAL PERFORMANCE PLOTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.1 5.2 5.3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Startup Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Dimmer Switch Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 5.3.1 Dimmer Learn Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.3.2 Dimmer Validate Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.3.3 No-dimmer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.3.4 Leading-edge Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.3.5 Trailing-edge Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.4 Correlated Color Temperature Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 5.5 Dimming Signal Extraction and the Dim Mapping Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 5.6 Boost Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 5.6.1 Maximum Peak Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.6.2 Output BSTOUT Sense & Input IAC Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.6.3 Boost Auxiliary Winding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.6.4 Boost Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.7 Voltage Clamp Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 5.7.1 Clamp Overpower Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.8 Quasi-resonant Second Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 5.8.1 Series & Parallel Two-Channel Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.8.2 Primary-side Current Control for Two-Channel Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.8.3 Auxiliary Winding Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.8.4 Control Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.8.5 Frequency Dithering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.8.6 Output Open Circuit Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.8.7 Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.8.8 Open Loop Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.9 Overtemperature Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 5.9.1 Internal Overtemperature Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.9.2 External Overtemperature Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.10 Power Line Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 5.10.1 Power Line Calibration Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.10.2 PLC Program Mode Characters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.10.3 Calibration Mode Operation Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.10.4 Register Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.11 I2C™ Communication Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 5.11.1 I2C Control Port Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.11.2 Control Port Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.11.3 Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.11.4 Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.11.5 Customer I2C Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.12 OTP Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 5.12.1 Programming the OTP Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2 DS954F2 CS1630/31 6.ONE-TIME PROGRAMMABLE (OTP) REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 6.12 6.13 6.14 6.15 6.16 6.17 6.18 6.19 6.20 6.21 6.22 6.23 6.24 6.25 6.26 6.27 6.28 6.29 6.30 6.31 6.32 6.33 6.34 6.35 6.36 6.37 6.38 6.39 6.40 6.41 6.42 6.43 6.44 6.45 6.46 6.47 6.48 6.49 6.50 6.51 6.52 6.53 Registers Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Configuration 0 (Config0) – Address 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Lockout Key (LOCK0, LOCK1, LOCK2, LOCK3) – Address 1 - 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Color Polynomial Coefficient (P30, P20, P10, P03, P02, P01, P21, P12, P11, P00) – Address 5 - 24 . . . . . . . . . . . .29 Color Polynomial Coefficient (Q3, Q2, Q1, Q0) – Address 25 - 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Gate Drive Duration (GD_DUR) – Address 33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Configuration 2 (Config2) – Address 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Configuration 3 (Config3) – Address 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Configuration 4 (Config4) – Address 36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Second Stage Dim (S2DIM) – Address 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Maximum TT (TTMAX) – Address 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Configuration 7 (Config7) – Address 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Configuration 8 (Config8) – Address 40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Channel 1 Output Current (CH1CUR) – Address 41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Configuration 10 (Config10) – Address 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Channel 2 Output Current (CH2CUR) – Address 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Configuration 12 (Config12) – Address 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 PU Coefficient (PID) – Address 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Maximum Switching Frequency (TTFREQ) – Address 46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Configuration 15 (Config15) – Address 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Configuration 16 (Config16) – Address 48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Configuration 17 (Config17) – Address 49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Configuration 18 (Config18) – Address 50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Peak Current (PEAK_CUR) – Address 51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Configuration 38 (Config38) – Address 70 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Configuration 44 (Config44) – Address 76 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Configuration 45 (Config45) – Address 77 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Configuration 46 (Config46) – Address 78 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Configuration 47 (Config47) – Address 79 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Configuration 48 (Config48) – Address 80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Configuration 49 (Config49) – Address 81 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Configuration 50 (Config50) – Address 82 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Configuration 51 (Config51) – Address 83 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Configuration 52 (Config52) – Address 84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Configuration 53 (Config53) – Address 85 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Configuration 54 (Config54) – Address 86 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Configuration 55 (Config55) – Address 87 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 PLC Dim (PLC_DIM) – Address 89 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 Configuration 58 (Config58) – Address 90 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 Configuration 59 (Config59) – Address 91 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 Configuration 60 (Config60) – Address 92 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Configuration 61 (Config61) – Address 93 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Configuration 62 (Config62) – Address 94 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 CRC Tag (CRC_TAG) – Address 102 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Channel 1 Color Calibration 3A (CH1_CAL3A) – Address 119 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Channel 2 Color Calibration 3A (CH2_CAL3A) – Address 120 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 CRC Memory Tag 3A (CRC_MTAG3A) – Address 121 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Channel 1 Color Calibration 3B (CH1_CAL3B) – Address 122 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Channel 2 Color Calibration 3B (CH2_CAL3B) – Address 123 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 CRC Memory Tag 3B(CRC_MTAG3B) – Address 124 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Channel 1 Color Calibration 3C (CH1_CAL3C) – Address 125 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Channel 2 Color Calibration 3C (CH2_CAL3C) – Address 126 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 CRC Memory Tag 3C (CRC_MTAG3C) – Address 127 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 7.PACKAGE DRAWING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . 10.REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DS954F2 54 55 55 56 3 CS1630/31 1. INTRODUCTION BSTOUT 15k 16 Iref MUX IAC BSTAUX ADC POR 15k 2 1 VFB ZCD(th) 5 V S OURCE(th ) + + VDD 13 GD 12 GND 11 FBSENSE 15 FBAUX 3 CLAMP Boost ZCD - Blank 3 OLP + + - OCP + I S OURCE SGND 14 VZ V S T(th ) VS TP(th ) - t B S TZCD SOURCE Voltage Regulator Peak Control VOLP (th) VOCP (th ) + - 4 DAC SDA 6 SCL 7 SYNC 9 NC 8 eOTP 10 Output Open tFB ZCD Flyback ZCD VDD V P k_Max(th) + + - VOV P (th ) VFB ZCD(th) VDD ICONNE CT ICLA MP V CONNE CT(th) + Figure 1. CS1630/31 Block Diagram A typical schematic using the CS1630/31 IC is shown on the front page. Startup current is provided from a patent-pending, external high-voltage source-follower network. In addition to providing startup current, this unique topology is integral in providing compatibility with digital dimmers by ensuring VDD power is always available to the IC. During steady-state operation, an auxiliary winding on the boost inductor back-biases the source-follower circuit and provides steady-state operating current to the IC to improve system efficiency. The rectified input voltage is sensed as a current into pin IAC and is used to control the adaptive dimmer compatibility algorithm and extract the phase of the input voltage for output dimming control. During steady-state operation, the external high-voltage, source-follower circuit is source-switched in critical conduction mode (CRM) to boost the input voltage. This allows the boost stage to maintain good power factor, provide dimmer compatibility, reduce bulk capacitor ripple current, and provide a regulated input voltage to the second stage. The current into the boost output voltage sense pin (BSTOUT) senses the output voltage of the CRM boost front-end. 4 The quasi-resonant second stage is implemented with peakcurrent mode primary-side control, which eliminates the need for additional components to provide feedback from the secondary and reduces system cost and complexity. Voltage across an external user-selected resistor is sensed through pin FBSENSE to control the peak current through the second stage inductor. Leading-edge and trailing-edge blanking on pin FBSENSE prevents false triggering. Pin FBAUX is used to sense the second stage inductor demagnetization to ensure quasi-resonant switching of the output stage. An internal current source is adjusted by a feedback loop to regulate a constant reference voltage on pin eOTP for external negative temperature coefficient (NTC) thermistor measurements. An external NTC is connected to pin eOTP to provide thermal protection of the system and LED temperature compensation. The output current of the system is steadily reduced when the system temperature exceeds a programmable temperature set point. If the temperature reaches a designated high set point, the IC is shutdown and stops switching. DS954F2 CS1630/31 2. PIN DESCRIPTION 1 16 BSTOUT Boost Output Voltage Sense IAC 2 15 FBAUX Second Stage Zero-current Detect Voltage Clamp Current Source CLAMP 3 14 VDD IC Supply Voltage Source Ground SGND 4 13 GD Gate Driver Source Switch SOURCE 5 12 GND Ground Data SDA 6 11 FBSENSE Second Stage Current Sense I2C Clock SCL 7 10 eOTP External Overtemperature Protection SYNC Second Stage Synchronization Boost Zero-current Detect BSTAUX Rectifier Voltage Sense I2C No Connection NC 8 9 16-lead SOIC Figure 2. CS1630/31 Pin Assignments Pin Name Pin # I/O BSTAUX 1 IN Boost Zero-current Detect — Boost Inductor demagnetization sensing input for zero-current detection (ZCD) information. The pin is connected to the PFC boost inductor auxiliary winding through an external resistor divider. IAC 2 IN Rectifier Voltage Sense — A current proportional to the rectified line voltage is fed into this pin. The current is measured with an A/D converter. CLAMP 3 OUT SGND 4 PWR SOURCE 5 IN Source Switch — Connected to the source of the boost stage external high-voltage FET. SDA 6 I/O I2C™ Data — I2C data. SCL 7 IN I2C™ Clock — I2C clock. NC 8 - SYNC 9 OUT eOTP 10 IN FBSENSE 11 IN GND 12 PWR GD 13 OUT VDD 14 PWR FBAUX 15 IN BSTOUT 16 IN DS954F2 Description Voltage Clamp Current Source — Connect to a voltage clamp circuit on the output of the boost stage. Source Ground — Common reference current return for the SOURCE pin. No Connection — Leave pin unconnected. Second Stage Synchronization — A digital synchronization signal that indicates which channel the controller is signaling for each gate switching period. External Overtemperature Protection — Connect an external NTC thermistor to this pin, allowing the internal A/D converter to sample the change to NTC resistance. Second Stage Current Sense — The current flowing in the second stage FET is sensed across a resistor. The resulting voltage is applied to this pin and digitized for use by the second stage computational logic to determine the FET's duty cycle. Ground — Common reference. Current return for both the input signal portion of the IC and the gate driver. Gate Driver — Gate drive for the second stage power FET. IC Supply Voltage — Connect a storage capacitor to this pin to serve as a reservoir for operating current for the device, including the gate drive current to the power transistor. Second Stage Zero-current Detect — Second stage inductor sensing input. The pin is connected to the second stage inductor’s auxiliary winding through an external resistor divider. Boost Output Voltage Sense — A current proportional to the boost output is fed into this pin. The current is measured with an A/D converter. 5 CS1630/31 3. CHARACTERISTICS AND SPECIFICATIONS 3.1 Electrical Characteristics Typical characteristics conditions: • TA = 25ºC, VDD = 12V, GND = 0V • All voltages are measured with respect to GND. • Unless otherwise specified, all currents are positive when flowing into the IC. Parameter Minimum/Maximum characteristics conditions: • TJ = -40°C to +125°C, VDD = 11V to 17V, GND = 0V Condition Symbol Min Typ Max Unit VDD Supply Voltage After Turn-on VDD 11 - 17 V Turn-on Threshold Voltage VDD Increasing VST(th) - 8.5 - V Turn-off Threshold Voltage (UVLO) VDD Decreasing VSTP(th) - 7.5 - V IDD = 20mA VZ 18.5 - 19.8 V VDD <VST(th) IST - - 200 A - 5.8 - mA Iref - 133 133 - A A fBST(Max) - - 200 kHz ICLAMP - -3.8 - mA - 590 508 - mA mA VBSTZCD(th) - 200 - mV IBSTZCD -2 - - mA IBSTZCD = 1mA - VDD +0.6 - V 108 Vline 132 207 Vline 253 - 146.7 141.7 - A A VFBZCD(th) - 200 - mV IFBZCD -2 - - mA - VDD +0.6 - V - 1.4 - V - - 100 ns Operating Range Zener Voltage (Note 1) VDD Supply Current Startup Supply Current Operating Supply Current (Note 5) CL = 0.25nF, Fsw 60 kHz Reference Reference Current CS1630 CS1631 VBST = 200 V VBST = 400 V Boost Maximum Switching Frequency Clamp Current Dimmer Attach Peak Current CS1630 CS1631 108 Vline 132 207 Vline 253 Boost Zero-current Detect BSTZCD Threshold ZCD Sink Current (Note 2) BSTAUX Upper Voltage Boost Protection Clamp Turn-on CS1630 CS1631 Second Stage Zero-current Detect FBZCD Threshold ZCD Sink Current FBAUX Upper Voltage (Note 2) IFBZCD = 1mA Second Stage Current Sense Peak Control Threshold Delay to Output 6 VPk_Max(th) DS954F2 CS1630/31 Parameter Condition Symbol Min Typ Max Unit Minimum Switching Frequency tFB(Min) - 625 - Hz Maximum Switching Frequency tFB(Max) - 200 - kHz Second Stage Pulse Width Modulator Second Stage Gate Driver Output Source Resistance VDD = 12V - 24 - Output Sink Resistance VDD = 12V - 11 - Rise Time (Note 5) CL = 0.25nF - - 30 ns Fall Time (Note 5) CL = 0.25nF - - 20 ns Second Stage Protection Overcurrent Protection (OCP) VOCP(th) - 1.69 - V Overvoltage Protection (OVP) VOVP(th) - 1.25 - V Open Loop Protection (OLP) VOLP(th) - 200 - mV ICONNECT - 80 - A - - ±5 External Overtemperature Protection (eOTP) Pull-up Current Source – Maximum Conductance Accuracy (Note 3) Conductance Offset (Note 3) Current Source Voltage Threshold - ±250 - nS VCONNECT(th) - 1.25 - V Internal Overtemperature Protection (iOTP) Thermal Shutdown Threshold (Note 4) TSD - 135 - ºC Thermal Shutdown Hysteresis (Note 4) TSD(Hy) - 14 - ºC Notes: 1. 2. 3. 4. 5. The CS1630/31 has an internal shunt regulator that limits the voltage on the VDD pin. VZ, the shunt regulation voltage, is defined in the VDD Supply Voltage section on page 6. External circuitry should be designed to ensure that the ZCD current drawn from the internal clamp diode when it is forward biased does not exceed specification. Conductance is the inverse of resistance (1/) and is expressed in siemens (S). A decrease in conductance is equivalent to an increase in resistance. Specifications are guaranteed by design and are characterized and correlated using statistical process methods. For test purposes, load capacitance (CL) is 0.25nF and is connected as shown in the following diagram. VDD +15V VDD GD GND DS954F2 TP Buffer S1 R1 CL 0.25nF R3 R2 GD OUT S2 -15V 7 CS1630/31 3.2 I2C Port Switching Characteristics Test conditions (unless otherwise specified): • Inputs: Logic 0 = GND = 0V, Logic 1 = 3.3V. • The CS1630/31 control port only supports I2C slave functionality. • It is recommended that a 2.2k pull-up resistor be placed from the SDA pin to VDD. Parameter SCL Clock Frequency Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low time Clock High Time Setup Time for Repeated Start Condition SDA Input Hold Time from SCL Falling SDA Setup time to SCL Rising Setup Time for Stop Condition SDA Input Voltage Low SDA Input Voltage High SDA Output Voltage Low Symbol Min Typ Max Unit fscl tbuf thdst tlow thigh tsust thddi 1.3 0.6 1.3 0.6 0.6 0 - 400 0.9 kHz µs µs µs µs µs µs tsud tsusp Vil Vih Vol 100 0.6 - 1.5 1.85 0.25 - ns µs V V V Re pe ate d S ta rt Stop Stop Sta rt SD A tbuf t hdst t high tf t hdst tsusp SCL t low 8 thddi tsud thddo tsust tr DS954F2 CS1630/31 3.3 Power Line Calibration Characteristics Typical characteristics conditions: • TA = 25ºC, VDD = 12V, GND = 0V • All voltages are measured with respect to GND. • Unless otherwise specified, all current is positive when flowing into the IC. Parameter Input Line Frequency Input Voltage CS1630 CS1631 Dual-bit 00 (“00”) Dual-bit 01 (“01”) Dual-bit 10 (“10”) Dual-bit 11 (“11”) Special Character (SC) Notes: 6. 7. DS954F2 Minimum/Maximum characteristics conditions: TJ = 25ºC, VDD = 11V to 17V, GND = 0V (Note 6) (Note 7) (Note 7) Min 47 Typ 50/60 Max 63 Units Hz 114 218 24 52 108 136 80 120 230 34 62 118 146 90 126 242 44 72 128 156 100 V V Degrees Degrees Degrees Degrees Degrees The CS1630/31 supports leading-edge phase-cut waveforms only for power line calibration. Range is recommended for power line calibration operation only. 9 CS1630/31 3.4 Thermal Resistance Symbol Parameter Value Unit JA Junction-to-ambient Thermal Impedance 2 Layer PCB 4 Layer PCB 84 47 °C/W °C/W JC Junction-to-case Thermal Impedance 2 Layer PCB 4 Layer PCB 39 31 °C/W °C/W 3.5 Absolute Maximum Ratings Characteristics conditions: All voltages are measured with respect to GND. Pin Symbol 14 VDD Parameter IC Supply Voltage Value Unit 18.5 V 1, 2, 5, 6, 7, 9, 10, 11, 15, 16 Analog Input Maximum Voltage -0.5 to (VDD+0.5) V 1, 2, 6, 7, 9, 10, 11,15,16 Analog Input Maximum Current 5 mA Note: 13 VGD Gate Drive Output Voltage -0.3 to (VDD+0.3) V 13 IGD Gate Drive Output Current -1.0 / +0.5 A 5 ISOURCE 1.1 A 3 ICLAMP Clamp Output Current 5 mA - PD Total Power Dissipation 400 mW - TJ Junction Temperature Operating Range -40 to +125 ºC - TStg -65 to +150 ºC All Pins ESD 2000 500 V V 8. Current into Pin (Note 8) Storage Temperature Range Electrostatic Discharge Capability Human Body Model Charged Device Model Long-term operation at the maximum junction temperature will result in reduced product life. Derate internal power dissipation at the rate of 50mW/ºC for variation over temperature. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. 10 DS954F2 CS1630/31 4. TYPICAL PERFORMANCE PLOTS 3 12 10 8 IDD (mA) UVLO Hysteresis 2 6 4 1 2 0 0 -50 0 50 100 -2 150 0 2 4 6 Temperature (°C) 8 10 12 14 16 18 20 VDD (V) Figure 4. Supply Current vs. Voltage Figure 3. UVLO Characteristics 10 20 19.5 VZ (V) VDD (V) 9 Turn On 19 8 18.5 Turn Off 7 -50 0 50 100 18 150 -50 0 50 100 150 Temperature (°C) Temperature (C°) Figure 6. Zener Voltage vs. Temperature Figure 5. Turn-on/off Threshold Voltage vs. Temperature 0.5 40 0 Drift (%) ZOUT (:) 30 Source 20 -0.5 -1 Sink 10 -1.5 0 -50 0 50 Temperature (ºC) 100 Figure 7. Gate Drive Resistance vs. Temperature DS954F2 150 -2 -50 0 50 100 150 Temperature (°C) Figure 8. Reference Current (Iref) Drift vs. Temperature 11 CS1630/31 5. GENERAL DESCRIPTION 5.1 Overview The CS1630 and CS1631 are high-performance offline AC/DC LED drivers for dimmable and high color rendering index (CRI) LED replacement lamps and luminaires. They feature Cirrus Logic’s proprietary digital dimmer compatibility control technology and digital correlated color temperature (CCT) control system that enables two-channel LED color mixing. The CS1630 is designed for 120VAC line voltage applications, and the CS1631 is optimized for 230VAC line voltage applications. The CS1630/31 integrates a critical conduction mode (CRM) boost converter, providing power factor correction and superior dimmer compatibility with a primary-side regulated quasiresonant second stage, which is configurable for isolated and non-isolated topologies. The digital CCT control system provides the ability to program dimming profiles, such as constant CCT dimming and black body line dimming. The CS1630/31 optimizes LED color mixing by temperature compensating LED current with an external negative temperature coefficient (NTC) thermistor. The IC controller is also equipped with power line calibration for remote system calibration and end-of-line programming. The CS1630/31 provides a register lockout feature for security against potential access to proprietary registers. 5.2 Startup Circuit An external, high-voltage source-follower circuit is used to deliver startup current to the IC. During steady-state operation, an auxiliary winding on the boost inductor biases this circuit to an off state to improve system efficiency, and all IC supply current is generated from the auxiliary winding. The patent pending technology of the external, high-voltage sourcefollower circuit enables system compatibility with digital dimmers (dimmers containing an internal power supply) by providing a continuous path for a dimmer’s power supply to recharge during its off state. During steady-state operation, high-voltage FET Q1 is source-switched by a variable internal current source on the SOURCE pin to create the boost circuit. A Schottky diode with a forward voltage less than 0.6V is recommended for D5. Schottky diode D5 will limit inrush current through the internal diode, preventing damage to the IC. 5.3 Dimmer Switch Detection The CS1630/31 dimmer switch detection algorithm determines if the solid-state lighting system is controlled by a regular switch, a leading-edge dimmer, or a trailing-edge dimmer. Dimmer 12 switch detection is implemented using two modes: Dimmer Learn Mode and Dimmer Validate Mode. These assist in limiting the system power losses. Once the IC reaches UVLO start threshold VST(th) and begins operating, the CS1630/31 is in Dimmer Learn Mode, allowing the dimmer switch detection circuit to set the operating state of the IC to one of three modes: No-dimmer Mode, Leading-edge Mode, or Trailing-edge Mode. 5.3.1 Dimmer Learn Mode In Dimmer Learn Mode, the dimmer detection circuit spends approximately two line-cycles learning whether there is a dimmer switch and, if present, whether it is a trailing-edge or leading-edge dimmer. A modified version of the leading-edge algorithm is used. The trailing-side slope of the input line voltage is sensed to decide whether the dimmer switch is a trailing-edge dimmer. The dimmer detection circuit transitions to Dimmer Validate Mode once the circuit detects that a dimmer is present. 5.3.2 Dimmer Validate Mode During normal operation, CS1630/31 is in Dimmer Validate Mode. This instructs the dimmer detection circuit to periodically validate that the IC is executing the correct algorithm for the attached dimmer. The dimmer detection algorithm periodically verifies the IC operating state as a protection against incorrect detection. As additional protection, the output of the dimmer detection algorithm is low-pass filtered to prevent noise or transient events from changing the IC’s operating mode. The IC will return to Dimmer Learn Mode when it has determined that the wrong algorithm is being executed. 5.3.3 No-dimmer Mode Upon detection that the line is not phase cut with a dimmer, the CS1630/31 operates in No-dimmer Mode, where it provides a power factor that is in excess of 0.9. The CS1630/31 accomplishes this by boosting in CRM and DCM mode. The peak current is modulated to provide link regulation. The CS1630/31 alternates between two settings of peak current. To regulate the boost output voltage, the CS1630/31 uses a peak current set by register PEAK_CUR (see "Peak Current (PEAK_CUR) – Address 51" on page 39). The time that this current is used is determined by an internal compensation loop to regulate the boost output voltage. The internal algorithm will reduce the peak current of the boost stage to maintain output voltage regulation and obtain the desired power factor. DS954F2 CS1630/31 5.3.4 Leading-edge Mode In Leading-edge Mode, the CS1630/31 regulates boost output voltage VBST while maintaining the dimmer phase angle (see Figure 9). The device executes a CCM boost algorithm using dimmer attach current as the initial peak current for the initial firing event of the dimmer. Upon gaining control of the incoming current, the CS1630/31 transitions to a CRM boost algorithm to regulate VBST. The device periodically executes a probe event on the incoming waveform. The information from the probe event is used to maintain proper operation with the dimmer circuitry. 5.4 Correlated Color Temperature Control The CS1630/31 color control system can adjust and maintain the correlated color temperature (CCT) for the LED colormixing application by connecting an external negative temperature coefficient (NTC) thermistor to the eOTP pin. The LED temperature variation can be accurately detected by the internal eOTP feedback loops (see "External Overtemperature Protection" on page 19). Red and amber LEDs are necessary components in colormixing applications when providing warm white or other CCTs. When mixing colors, red and amber LEDs are the most temperature sensitive, so they cause a large variation in temperature. The CS1630/31 is capable of providing LED CCT and luminosity with temperature compensation using the NTC thermistor to resolve the significant change in the luminous output due to temperature variations. Since LED lumens are mainly a function of temperature and forward current, color temperature and luminosity can be maintained by independently adjusting each string's output current as the ambient temperature changes. This can be done by mapping the NTC reading to a required value of the current in each string using a digital mapping block. Figure 9. Leading-edge Mode Phase-cut Waveform 5.3.5 Trailing-edge Mode In Trailing-edge Mode, the CS1630/31 determines its operation based on the falling edge of the input voltage waveform (see Figure 10). To provide proper dimmer operation, the CS1630/31 executes the boost algorithm on the falling edge of the input line voltage that maintains a charge in the dimmer capacitor. To ensure maximum compatibility with dimmer components, the device boosts during this falling edge event using a peak current that must meet a minimum value. In Trailing-edge Mode, only the CRM boost algorithm is used. In the CS1630/31, only one of the LED string currents is compensated for due to temperature variations. The current in the other string is kept constant over temperature, which may result in the luminosity decreasing slightly as temperature increases. In order for the ADC to resolve the entire range of possible temperature variation in the LEDs, it is recommended to select series resistor RS and NTC resistor RNTC with the appropriate Beta value, which retains the total resistance (RS +RNTC) at all possible operating temperatures within the tracking range of the ADC. The final temperature-to-digital code mapping depends on these variables. The CS1630/31 color control system also has the ability to maintain a constant CCT or change CCT as the light dims. OTP configurations allow the selection of the dimming profile. A specific CCT profile can be programmed to the digital mapping device. In this case, the mapping is two-dimensional: one current versus temperature profile is generated for each dim level. The CS1630/31 provides two-dimensional mapping for the color LED’s current only, and one-dimensional mapping (current versus dim level) for the other string. A simplified block diagram of the color control system is shown in Figure 11. Figure 10. Trailing-edge Mode Phase-cut Waveform DS954F2 13 CS1630/31 Iref White X Cirrus Logic, Inc. and its affiliates and subsidiaries generally make no representations or warranties that the combination of Cirrus Logic’s products with light-emitting diodes (“LEDs”), converter materials, and/or other components will not infringe any third-party patents, including any patents related to color mixing in LED lighting applications, such as, for example, U.S. Patent No. 7,213,940 and related patents of Cree, Inc. For more information, please see Cirrus Logic’s Terms and Conditions of Sale, or contact a Cirrus Logic sales representative. IWhite X Gain White dim Iref Color 5.5 X ADC Gain Color X Dimming Signal Extraction and the Dim Mapping Algorithm When operating with a dimmer, the dimming signal is extracted in the time domain and is proportional to the conduction angle of the dimmer. A control variable is passed to the quasi-resonant second stage to achieve 0% to 100% output currents. IColor NTC Figure 11. Block Diagram of Color Control System The reference currents are the required values at TA = 25ºC and dim = 100%. They are multiplied by the appropriate gains, and these values are passed to the final power stage. The CS1630/31 uses polynomial approximations in one and two dimensions to generate the color gains. These polynomials can be up to third-order. GAINDTR approximations create a custom temperature compensation profile and dimming profile of the temperaturesensitive LEDs (see Equation 1). Profiles are programmed through the Color Polynomial Coefficient registers (see "Color Polynomial Coefficient (P30, P20, P10, P03, P02, P01, P21, P12, P11, P00) – Address 5 - 24" on page 29). GAINDR approximation allows custom dimming profile of the white LEDs (see Equation 2). The profile is programmed through the Color Polynomial Coefficient registers (see "Color Polynomial Coefficient (Q3, Q2, Q1, Q0) – Address 25 - 32" on page 30). 5.6 Boost Stage The high-voltage FET in the source-follower startup circuit is source-switched by a variable current source on the SOURCE pin to operate a boost circuit. Peak FET switching current is set by the PEAK_CUR register (see "Peak Current (PEAK_CUR) – Address 51" on page 39). In No-dimmer Mode, the boost stage begins operating when the start threshold is reached during each rectified half line-cycle and is disabled at the nominal boost output voltage. The peak FET switching current determines the percentage of the rectified input voltage conduction angle over which the boost stage will operate. The control algorithm adjusts the peak FET switching current to maximize the operating time of the boost stage, thus improving the input power factor. When operating in Leading-edge Mode, the boost stage ensures the hold current requirement of the dimmer is met from the initiation of each half-line dimmer conduction cycle until the peak of the rectified input voltage. Trailing-edge Mode boost stage ensures that the trailing-edge is exposed at the correct time with the correct current. 3 2 3 2 2 2 GAIN DTR= P30 T + P20 T + P10 T + P03 D + P02 D + P01 D + P21 T D + P12 T D + P11 T D + P00 [Eq.1] where, T = the measured normalized temperature and is 0 T 1.0 D = the normalized dim value and is 0 D 1.0 GAINDTR = gain of the channel based on the temperature measurement and the dim value: 3 2 GAIN DR = Q3 D + Q2 D + Q1 D + Q0 [Eq.2] where, D = the normalized dim value and is 0 D 1.0 GAINDR = gain of the channel based on the dim value 14 DS954F2 CS1630/31 5.6.1 Maximum Peak Current The maximum boost inductor peak current is configured by adjusting the peak switching current with IPK(code). The PEAK_CUR register (see "Peak Current (PEAK_CUR) – Address 51" on page 39) is used to store IPK(code). Maximum power output is proportional to IPK(code), as shown in Equation 3: IPK V RMS typ Output BSTOUT Sense & Input IAC Sense A current proportional to boost output voltage VBST is supplied to the IC on pin BSTOUT and is used as a feedback control signal. The ADC is used to measure the magnitude of the I BSTOUT current through resistor R BST. The magnitude of the I BSTOUT current is then compared to an internal reference current (I ref) of 133A. R8 RB S T Iref BSTOUT 15k ADC Figure 12. BSTOUT Input Pin Model Resistor RBST sets the feedback current at the nominal boost output voltage. For 230VAC line voltage applications, RBST is calculated as shown in Equation 4: V BST 400V R BST = -------------- = ------------------ 3M [Eq.4] I ref 133A where, VBST = Nominal boost output voltage Iref = Internal reference current For 120VAC line voltage applications (CS1630), nominal boost output voltage VBST is 200V, and resistor RBST is 1.5M. By using digital loop compensation, the voltage feedback signal does not require an external compensation network. DS954F2 R4 CS1630 /31 Iref IAC 15k ADC 12 Figure 13. IAC Input Pin Model Resistor RIAC sets the IAC current and is derived from Equation 5: R IAC = R BST [Eq.5] For optimal performance, resistors RIAC and RBST should use 1% tolerance or better resistors for best VBST voltage accuracy. 5.6.3 5.6.4 CS1630 /31 16 R IA C Boost Auxiliary Winding The boost auxiliary winding is used for zero-current detection (ZCD). The voltage on the auxiliary winding is sensed through the BSTAUX pin of the IC. It is also used to deliver startup current during startup time (see "Startup Circuit" on page 12). VB S T R9 R3 IA C 2 where, = correction term = 0.55 VRMS(typ) = nominal operating input RMS voltage IPK = IPK(code) 4.1mA IB S TOUT V rec t [Eq.3] P IN max = -----------------------------------------------2 5.6.2 A current proportional to the AC input voltage is supplied to the IC on pin IAC and is used by the boost control algorithm. Boost Overvoltage Protection The CS1630/31 supports boost overvoltage protection (BOP) to protect the bulk capacitor C8 (see Figure 14). If the boost output voltage exceeds the overvoltage protection thresholds programmed in the OTP registers a BOP fault signal is generated. The voltage level, VBOP(th), can be set within 227V to 257V for a CS1630 and 432V to 462V for a CS1631 (see "Configuration 53 (Config53) – Address 85" on page 45). The control logic continuously averages the BOP fault signal using a leaky integrator. When the output of the leaky integrator exceeds a certain threshold, which can be set using bits BOP_INTEG[3:0] in register Config53 (see "Configuration 53 (Config53) – Address 85" on page 45), a boost overvoltage fault is declared and the system stops boosting. More information on the leaky integrator size and sample rate is provided in section 6.23 "Configuration 18 (Config18) – Address 50" on page 38. During a boost overvoltage protection event, the second stage is kept enabled only if the MAX_CUR bit in register Config45 (see "Configuration 45 (Config45) – Address 77" on page 40) is set to ‘1’ (enabled), and its dim input is railed to full scale. This allows the second stage to quickly dissipate the stored energy on the bulk capacitor C8, bringing down the boost output voltage to a safe value. A visible flash on the LED might appear, indicating that an overvoltage event has occurred. When the boost output voltage drops to 195V (for a 120V application), or 392V (for a 230V application), the boost stage is enabled if bit BOP_RSTART in register Config54 (see 15 CS1630/31 "Configuration 54 (Config54) – Address 86" on page 46) is set to ‘1’, and the system returns to normal operation. If bit BOP_RSTART is set to ‘0’, a boost overvoltage fault is latched and the system stays in the fault mode until the input power is recycled. 5.7 Voltage Clamp Circuit To keep dimmers conducting and prevent them from misfiring, a minimum power needs to be delivered from the dimmer to the load. This power is nominally around 2W for 230V and 120V TRIAC dimmers. At low dim angles ( 90°), this excess power cannot be converted into light by the second stage due to the dim mapping at light loads. The output voltage of the boost stage (VBST) can rise above the safe operating voltage of the primary-side bulk capacitor C8. The CS1630/31 provides active clamp circuitry on the CLAMP pin, as shown in Figure 14. second stage can operate in quasi-resonant mode and provides constant output current with minimum line-frequency ripple. Primary-side control is used to simplify system design and reduce system cost and complexity. The digital algorithm ensures monotonic dimming from 0% to 100% of the dimming range with a linear relationship between the dimming signal and the LED current. Figure 15 illustrates a quasi-resonant flyback stage configured for two-channel parallel output. C11 C9 D7 D9 LED 115 IGND 11 R13 R11 R14 C8 VB E CS1630 /31 Figure 14. CLAMP Pin Model A PWM control loop ensures that the voltage on VBST does not exceed 227V for 120VAC applications or 424V for 230VAC applications. This control turns on the BJT of the voltage clamp circuit, allowing the clamp circuit to sink current through the load resistor, preventing VBST from exceeding the maximum safe voltage. Figure 15. Flyback Parallel Output Model The flyback stage is controlled by measuring current in the transformer primary and voltage on the auxiliary winding. Quasi-resonant operation is achieved by detecting transformer flyback using an auxiliary winding. A quasi-resonant buck stage configured for two-channel parallel output is illustrated in Figure 16. VB S T LED 2+ R15 D10 C11 C9 Clamp Overpower Protection The CS1630/31 clamp overpower protection (COP) control logic continuously monitors the ‘ON’ time of the clamp circuit. If the cumulative 'ON' time exceeds 84.48ms during the internally generated 1 second window time, a COP event is actuated, disabling the boost and second stages. The clamp circuitry is turned off during the fault event. 5.8 Quasi-resonant Second Stage The second stage is a quasi-resonant current-regulated DCDC converter capable of flyback, buck, or tapped buck operation. The second stage output configuration is set by bit S2CONFIG in register Config12 (see "Configuration 12 (Config12) – Address 44" on page 36) and bits BUCK[3:0] in register Config10 (see "Configuration 10 (Config10) – Address 42" on page 35). To deliver the highest possible efficiency, the 16 C12 D8 Q4 13 12 5.7.1 LED 1+ R16 GND C10 GND S1 Q5 D R12 CS1630 /31 R10 Q3 LED2D11 FBAUX ICLA MP CLAMP 3 Z3 V CC _ Q FBSENSE VDD LED2+ R15 D10 Z2 GD VB S T T1 VBST D9 D8 Z3 LED 2D11 V CC _ Q Q5 D R12 GND LED1+ R16 C10 CS1630 /31 GD FBAUX FBSENSE GND 12 C12 LED 1- L3 13 IGND Q4 15 R13 11 R11 R14 Figure 16. Buck Parallel Output Model DS954F2 CS1630/31 The buck stage is controlled by measuring current in the buck inductor and voltage on the auxiliary winding. Quasi-resonant operation is achieved by detecting buck inductor demagnetization using an auxiliary winding. The digital control algorithm rejects line-frequency ripple created on the second stage input by the front-end boost stage, resulting in the highest possible LED efficiency and long LED life. The tapped buck stage operates similar to a buck stage. The tapped buck topology provides minimum turn-on time and improves conversion efficiency when large input-to-output voltage ratio is present. The tapped buck inductor behaves as a transformer for voltage conversion and is controlled by measuring current in the tapped inductor and voltage on the auxiliary winding. Quasi-resonant operation is achieved by detecting tapped inductor demagnetization using an auxiliary winding. configuration, and a PMOS switch is used in buck/tapped buck configuration (see Figures 15, 16, and 17). LED 1+ T1 VBST C12 R15 D10 Z2 LED 1C9 D7 Z3 D9 V CC _ Q CS1630 /31 D11 Q5 D R12 LED 2+ R16 GND C10 GD FBAUX FBSENSE Q4 13 C11 D8 LED215 IGND 11 R13 R11 GND 12 R14 VBST LED2+ R15 D10 C11 C9 D9 D8 Z3 LED 2D11 V CC _ Q Q5 D R12 GND R16 C10 LED1+ C12 CS1630 /31 FBAUX FBSENSE 13 IGND Q4 Similarly, a series connection in a flyback stage and buck stage use an NMOS switch and a PMOS switch, respectively, as shown in Figures 18 and 19. LED1- L3 GD Figure 18. Flyback Series Output Model LED1+ VBST R15 15 C12 D10 LED1- R13 C9 11 D8 V CC _ Q GND R11 R12 12 Series & Parallel Two-Channel Output The CS1630/31 is designed to be programmed to support series or parallel two-channel output configurations using one set of power magnetics. Series or parallel configuration is set by bit STRING and bit LED_ARG in the Config3 register (see "Configuration 3 (Config3) – Address 35" on page 32). A parallel connection for a flyback stage and buck stage are connected differently: an NMOS switch is used in flyback DS954F2 GND GD FBAUX FBSENSE GND C11 LED 2- L3 13 IGND Q4 15 D11 LED2+ R16 C10 CS1630 /31 5.8.1 Q5 D R14 Figure 17. Tapped Buck Parallel Output Model Z3 D9 R13 11 R11 R14 12 Figure 19. Buck Series Output Model 17 CS1630/31 Figure 20 illustrates the tapped buck stage configured for series output mode. LED1+ VBST R15 C12 D10 LED 1C9 D8 V CC _ Q Q5 D GND R16 C10 D11 LED 2+ C11 CS1630 /31 L3 GD FBAUX FBSENSE GND 12 13 15 LED 2IGND Q4 R13 11 R11 R14 Figure 20. Tapped Buck Series Output Model To maintain constant output current with minimum linefrequency ripple, the following are required: • For parallel configurations, a minimum voltage potential difference between two strings • For series configurations, a minimum current amplitude difference between two strings 5.8.2 Primary-side Current Control for Two-Channel Output The CS1630/31 regulates two-channel output current independently using primary-side control, which eliminates the need for opto-coupler feedback. The control loop operates in peak current control mode, with the peak current set cycleby-cycle by the two independent current regulation loops. Demagnetization time of the second stage inductor is sensed by the FBAUX pin using an auxiliary winding on the second stage inductor. The FBAUX pin supplies an input to the digital control loop. The power conversion for two-channel output is carried out by interleaving the PWM. The two-channel control system consists of two components: • A toggle device (phase synchronizer circuit) on the secondary side that alternatively activates each output channel for each switching event • A digital sequencer on the primary side determines which output channel is active for any given switching event As the output is toggled between each channel, a sequencer on the primary side identifies the current control phase and regulates the current in each output channel. To ensure proper operation for a parallel configuration, the two output channels should target a voltage differential that is greater than 20%. For a series configuration, the two output channels should target a current differential that is greater than 20%. 18 Auxiliary Winding Configuration The second-stage inductor auxiliary winding is used for zerocurrent detection (ZCD) and overvoltage protection (OVP). The auxiliary winding is sensed through the FBAUX pin of the IC. 5.8.4 Z3 D9 R12 5.8.3 Control Parameters The second-stage control parameters are set to assure: • Line Regulation — The LED current remains constant despite a ±10% AC line voltage variation. • Effect of Variation in Transformer Magnetizing Inductance — The LED current remains constant over a ±20% variation in magnetizing inductance. The FBSENSE input is used to sense the current in the second stage inductor. When this current reaches a certain threshold, the gate drive turns ‘OFF’ (output on pin GD). Two OTP values are required to set the second-stage output currents, CH1CUR for channel 1 and CH2CUR for channel 2 (see "Channel 1 Output Current (CH1CUR) – Address 41" on page 35 and "Channel 2 Output Current (CH2CUR) – Address 43" on page 35). Equations 6 and 7 are used to calculate the values to be programmed into registers CH1CUR and CH2CUR. 511 2 R Sense I CH1 CH1CUR = ---------------------------------------------------------N V Sense [Eq.6] 511 2 R Sense I CH2 CH2CUR = ---------------------------------------------------------N V Sense [Eq.7] where, RSense = Resistance of current sense resistor VSense = Full scale voltage across sense resistor (~1.4V) ICH1 = Target current in channel 1 LED string ICH2 = Target current in channel 2 LED string RSense is determined by the input voltage, switching frequency, auxiliary transformer turns ratio, target output current and output voltage for each channel. The zero-current detect input on pin FBAUX is used to determine the demagnetization cycle T2. The controller then uses these inputs to control the gate drive output, GD. 5.8.5 Frequency Dithering The peak amplitude of switching harmonics can be reduced by spreading the energy into wider spectrums. The frequency dithering level can be managed using bits DITLEVEL[1:0] in register Config61 (see "Configuration 61 (Config61) – Address 93" on page 49). Additionally, the CS1630/31 has an option to enable dithering only in No-dimmer Mode by setting bit DITNODIM to ‘1’. If output currents differ, the CS1630/31 also has an option to allow for less dither on one of the two channels by selecting the channel using bit DITCHAN. The channel selected for less dither attenuates the dither level by the percentage configured by bits DITATT[1:0]. DS954F2 CS1630/31 5.8.6 Output Open Circuit Protection Output open circuit protection and output overvoltage protection (OVP) are implemented by monitoring the output voltage through the second-stage inductor auxiliary winding. Overvoltage protection is enabled by setting bit OVP to ‘0’ in register Config47 (see "Configuration 47 (Config47) – Address 79" on page 41). If the voltage on the FBAUX pin exceeds a threshold (VOVP(th)) of 1.25V during the time the second stage gate drive is turned ‘OFF’ and outside of the blanking window configured by bit OVP_TYPE and bits OVP_BLANK[2:0] in register Config50 (see "Configuration 50 (Config50) – Address 82" on page 43), then the OVP event accumulator is incremented by 1 before the start of the next switching cycle. If the OVP comparator threshold is not exceeded during the switching cycle, the event accumulator is decremented by 1. If the event accumulator count exceeds or equals the count set by bits OVP_CNT[2:0] in register Config50 then an OVP fault is declared and enters a fault state. The fault state is latched if bit OVP_LAT in register Config50 is set high. The OVP fault state is not cleared until the power to the IC is recycled. Otherwise, if bit OVP_LAT is set low, the system is restarted after a specified amount of time configured by using the bit FAULT_SLOW and bits RESTART[5:0] in register Config51 (see "Configuration 51 (Config51) – Address 83" on page 43). The fault behavior during the fault state initiated by this protection depends on the setting for bit FAULT_SHDN in register Config51. 5.8.7 Overcurrent Protection Overcurrent protection (OCP) is implemented by monitoring the voltage across the second-stage sense resistor. Overcurrent protection is enabled by setting bit OCP to ‘0’ in register Config47 (see "Configuration 47 (Config47) – Address 79" on page 41). If this voltage exceeds a threshold (VOCP(th)) of 1.69V during the time the second stage gate drive is turned ‘ON’ and outside of the blanking window configured by bits OCP_BLANK[2:0] in register Config48 (see "Configuration 48 (Config48) – Address 80" on page 42), then the OCP event accumulator is incremented by 1 after the gate drive turns ‘OFF’. If the OCP comparator threshold is not exceeded during this time, the event accumulator is decremented by 1. If the event accumulator count exceeds or equals the count set by bits OCP_CNT[2:0] in register Config49 (see "Configuration 49 (Config49) – Address 81" on page 42) then an OCP fault is declared and enters a fault state. The fault state is latched if bit OCP_LAT in register Config49 is set high. The OCP fault state is not cleared until the power to the IC is recycled. Otherwise, if bit OCP_LAT is set low, the system is restarted after a specified amount of time configured by using the bit FAULT_SLOW and bits RESTART[5:0] in register Config51 (see "Configuration 51 (Config51) – Address 83" on page 43). The fault behavior during the fault state DS954F2 initiated by this protection depends on the setting for bit FAULT_SHDN in register Config51. 5.8.8 Open Loop Protection Open loop protection (OLP) and sense resistor short protection are implemented by monitoring the voltage across the sense resistor. Open loop protection is enabled by setting bit OLP to ‘0’ in register Config47 (see "Configuration 47 (Config47) – Address 79" on page 41). If the voltage on pin FBSENSE does not reach the protection threshold (VOLP(th)) of 200mV during a 250ns scan period after the second stage gate drive is turned ‘ON’ and the blanking window configured by bits OLP_BLANK[2:0] in register Config48 (see "Configuration 48 (Config48) – Address 80" on page 42) has elapsed, then the OLP event accumulator is incremented by 1. If the OLP comparator threshold is exceeded during this time, the event accumulator is decremented by 1. If the event accumulator count exceeds or equals the count set by bits OLP_CNT[2:0] in register Config49 (see "Configuration 49 (Config49) – Address 81" on page 42) then an OLP fault is declared and enters a fault state. The fault state is latched if bit OCP_LAT in register Config49 is set high. The OLP fault state is not cleared until the power to the IC is recycled. Otherwise, if bit OLP_LAT is set low, the system is restarted after a specified amount of time configured by using the bit FAULT_SLOW and bits RESTART[5:0] in register Config51 (see "Configuration 51 (Config51) – Address 83" on page 43). The fault behavior during the fault state initiated by this protection depends on the setting for bit FAULT_SHDN in register Config51. 5.9 Overtemperature Protection The CS1630/31 incorporates an internal overtemperature protection (iOTP) circuit for IC protection and the circuitry required to connect an external overtemperature protection (eOTP) device. Typically, an NTC thermistor is used. 5.9.1 Internal Overtemperature Protection Internal overtemperature protection (iOTP) is activated and power switching devices are disabled when the die temperature of the CS1630/31 exceeds 135°C. A hysteresis of about 7°C occurs before resuming normal operation. 5.9.2 External Overtemperature Protection The external overtemperature protection (eOTP) pin is used to implement overtemperature protection using an external negative temperature coefficient (NTC) thermistor, RNTC. The total resistance on the eOTP pin is converted to an 8-bit digital ‘CODE’ (which gives an indication of the temperature) using a digital feedback loop that adjusts the current (ICONNECT) into the NTC and series resistor, RS, to maintain a constant reference voltage of 1.25V (VCONNECT(th)). Figure 21 19 CS1630/31 illustrates the functional block diagram when connecting an optional external NTC temperature sensor to the eOTP circuit. CS1630/31 eOTP Control VDD ICONNECT Comp_Out eOTP + - 10 VCONNECT (th) RS C NTC NTC Figure 21. eOTP Functional Diagram Current ICONNECT is generated from an 8-bit controlled current source with a full-scale current of 80A. See Equation 8: V CONNECT th I CONNECT = ------------------------------------R [Eq.8] When the loop is in equilibrium, the voltage on the eOTP pin fluctuates around VCONNECT(th). The digital ‘CODE’ output by the ADC is used to generate ICONNECT. In normal operating mode, the ICONNECT current is updated once every seventh half line-cycle by a single ± LSB step. See Equation 9. I CONNECT V CONNECT th - = ------------------------------------CODE -------------------------N R NTC + R S 2 [Eq.9] Solving Equation 9 for CODE: N 2 V CONNECT th CODE = ----------------------------------------------------------------I CONNECT R NTC + R S 256 1.25 V = --------------------------------------------------------- 80A R NTC + R S [Eq.10] 4M = -------------------------------- R NTC + R S The tracking range of this ADC is approximately 15.5k to 4M. The series resistor RS is used to adjust the resistance of the NTC to fall within this ADC tracking range so that the entire 8-bit dynamic range of the ADC is well used. A 14k (±1% tolerance) series resistor is required to allow measurements of up to 130°C to be within the eOTP tracking range when a 100k NTC with a Beta of 4334 is used. The eOTP tracking circuit is designed to function accurately with an external capacitance of a maximum of 470 pF. A higher 8bit code output reflects a lower resistance and hence a higher external temperature. The ADC output code is filtered to suppress noise. This filter is the faster low-pass filter with a programmable time constant configured using bits EOTP_FLP[2:0] in register Config55 20 (see "Configuration 55 (Config55) – Address 87" on page 47) and compared against a programmable code value that corresponds to the desired shutoff temperature set point. Shutoff temperature TempShutdown is set using bits SHUTDWN[3:0] in register Config58 (see "Configuration 58 (Config58) – Address 90" on page 48). If the temperature exceeds this threshold, the chip enters an external overtemperature state and shuts down. The external overtemperature state is not a latched protection state, and the ADC keeps tracking the temperature in this state in order to clear the fault state once the temperature drops below a temperature code corresponding to TempWakeup programmed using bits WAKEUP[3:0] in register Config46 (see "Configuration 46 (Config46) – Address 78" on page 40). If an external overtemperature protection thermistor is not used, connect the eOTP pin to GND using a 50k to 500k resistor to disable the eOTP feature so that the programmed TempWakeup and TempShutdown codes are greater than the measured 8-bit code corresponding to the total resistance on the pin. When exiting reset, the chip enters startup and the ADC quickly (<5ms) tracks the external temperature to check if it is below the TempWakeup reference code (CODEWakeup) before the boost and second stages are powered up. If this check fails, the chip will wait until this condition becomes true before initializing the rest of the system. For external overtemperature protection, a second low-pass filter with a programmable time constant of 2 minutes is configured using bits EOTP_SLP[2:0] in register Config55 (see "Configuration 55 (Config55) – Address 87" on page 47). The filter is applied to the ADC output and uses it to scale down the internal dim level of the system (and hence ILED) if the temperature exceeds a programmable 8-bit threshold that corresponds to TempeOTP (see Figure 22). The large time constant for this filter ensures that the dim scaling does not happen spontaneously and is not noticeable (suppress spurious glitches). Temperature threshold must be set such Register that TempeOTP <TempWakeup <TempShutdown. Config59 sets TempeOTP (see "Configuration 59 (Config59) – Address 91" on page 48). Register Config46 sets TempWakeup (see "Configuration 46 (Config46) – Address 78" on page 40). Register Config58 sets TempShutdown (see "Configuration 58 (Config58) – Address 90" on page 48). For example, the system can be set up such that ILED starts reducing when RNTC ~6.3k (assuming a 14k 1% tolerance, series resistor RS), which corresponds to a temperature of 95°C (TempeOTP code is 196) for a 100k NTC with a Beta of 4334 (100 kW at 25°C). The ILED current is scaled based on the programmed slope using bits RATE[1:0] in register Config44 (see "Configuration 44 (Config44) – Address 76" on page 39) until it reaches TempShutdown. The CS1630/31 uses this calculated value to DS954F2 CS1630/31 scale output LED current ILED, as shown in Figure 22. 5.10 Power Line Calibration 5.10.1 Power Line Calibration Specification The CS1630/31 integrates power line calibration technology within the controller to enable calibration and end-of-line programming without the need for an additional electrical connection, as shown in Figure 23. To ensure the success of phase detection, the angle for each bit is specified as shown in "Power Line Calibration Characteristics" on page 9. The CS1630/31 power line calibration system operates under universal line voltage and frequency with a leading-edge, phase-cut waveform. Current (ILED, Nom.) Beyond this temperature, the IC shuts down using the mechanism discussed above. If the external overtemperature protection and the temperature compensation for CCT control features are not required, connect the eOTP pin to GND using a 50k to 500k resistor to disable the eOTP feature. The power line calibration uses a phase-cut mechanism for data generation and return-to-zero data encoding to eliminate the need for clock synchronization. A code /command can be created by using the combination of input phase angles, as detailed in "Power Line Calibration Characteristics" on page 9. When an initial program mode command has been detected, the controller will begin to enter calibration mode. After key parameters of the lighting system have been characterized and programmed, a burn-in code plus an end-program mode command is transmitted, instructing the controller to exit the calibration mode. Power line calibration and end-of-line programming requires no human intervention. The CS1630/31 provides registers that allow up to three attempts for LED output current trimming over power line calibration. Six registers store the three optional color control system calibration values for channel 1 color calibration and channel 2 color calibration. For more detail regarding color calibration, see "Channel 1 Color Calibration 3A (CH1_CAL3A) – Address 119" on page 51 through "Channel 2 Color Calibration 3C (CH2_CAL3C) – Address 126" on page 53. 100% 50% eOTP Trips and Shuts Off Lamp 0 25 95 Temperature (°C) 125 Figure 22. eOTP Temperature vs. Impedance Line Power Supply Neutral LED Lamp with CS1630/31 Photodetector Light Measurement Light Calibrator Figure 23. Power Line Calibration Block Diagram DS954F2 21 CS1630/31 PLC Start Char Special Char 90° 90° 34° ‘01’ 34° 62° ‘10’ ‘11’ 118° 146° 90° PLC Stop Char 90° ‘00’ 146° 90° Figure 24. Power Line Calibration Mode Character Waveforms 5.10.2 PLC Program Mode Characters In order to program the CS1630/31, a set of encoded characters is built from specific phase-cut waveform patterns. Figure 24 illustrates the phase-cut waveform encoding recognized by the CS1630/31 power line calibration system. As shown in Table 1, six characters are formed using the special character and two-bit encoded data. Character Start Char Code Notes (SC)00(SC) Stop Char (SC)11(SC) (1) PLC Program Start Character PLC Program Stop Character(1) Name OPCODE Description NOP 0000 No Operation INIT_PROG_MODE 0001 Initialize program mode(1) I2C_WRITE 0010 Perform a generic I2C write 0011 Reserved BURN_OTP 0100 Initiate an OTP write cycle(3) STR1_OFFSET 0101 Write String 1 offset(2) STR2_OFFSET 0110 Write String 2 offset(2) WRITE_CRC 0111 Write CRC value Duo-bit ‘00’ 00 2-bit Data [00] END_PROG_MODE 1000 Disable programming mode Duo-bit ‘01’ 01 2-bit Data [01] WRITE_DIM 1001 Sets PLC dim value Duo-bit ‘10’ 10 2-bit Data [10] Duo bit ‘11’ 11 2-bit Data [11] Notes: (1) Allows other commands to program the device under test. (2) Range of Offset tolerance is ±15%. (3) The light is flashed to indicate pass or fail. Note: (1) A Special Character (SC) must precede and follow the Duo-bit. Table 2. Power Line Calibration Operation Code Table 1. Power Line Calibration Characters 5.10.3 Calibration Mode Operation Code The CS1630/31 power line calibration system requires a start and stop operation code to activate and deactivate power line calibration mode. Once in the power line calibration mode, operation codes (OPCODE) will be used to program specific addresses using the OPCODE listed in Table 2. The LED light flashes seven times to indicate a command error. The LED flashes two times when OTP registers are programmed successfully and four times when programming is unsuccessful. Figure 25 illustrates an example of a power line calibration mode command sequence and the cutwaveform pattern. Calibration Command Sequence Start Char [(SC)00(SC)] PLC Start Character Before Transmit 135° 135° Addr Bcast & Simple Code [1 Duo-bit] 90° 34° Addr Bcast & Simple Code 00 90° 34° OPCODE [2 Duo-bits] PLC Operation Code (4-bit) 0000 34° 34° Stop Char [(SC)11(SC)] Odd Parity & Don’t Care [1 Duo-bit] PLC Stop Character Odd Parity & Don’t Care 10 118° 90° 146° After Transmit 90° 135° 135° Figure 25. Power Line Calibration Mode Example 22 DS954F2 CS1630/31 5.10.4 Register Lockout The CS1630/31 provides register lockout for security against unauthorized access to proprietary registers using the I2C or PLC communication port. A 32-bit long-word is used for password protection when accessing the OTP registers. The register lockout password can be set by programming the Lockout Key registers (see "Lockout Key (LOCK0, LOCK1, LOCK2, LOCK3) – Address 1 - 4" on page 29). Register lockout is enabled by setting bit LOCKOUT in register Config0 (see "Configuration 0 (Config0) – Address 0" on page 29). 5.11 I2C™ Communication Interface The purpose of the communication system is to provide a mechanism to allow the transfer of data and accessibility to the device. Pins SDA and SCL are an I2C communication port used to provide access to control registers inside the EXL core. In applications that do not use I2C communication, pins SDA and SCL should be connected to VDD. When SDA and SCL are connected to VDD, read/write register values are controlled internally by the EXL core. A one-time programmable (OTP) memory is implemented as part of the communication system to store trim and key parameters. After power-on reset (POR), the OTP memory is uploaded into shadow registers as part of startup, and a cyclic redundancy check (CRC) is calculated and checked on the data read from the OTP memory. If the computed CRC does not match the CRC value saved in the OTP memory, default values are used for some of the parameters. Shadow registers can be written using the I2C interface. In order to write to or read from the I2C port, a defined messaging protocol must be implemented. The OTP memory is organized as 128 addressable bytes (8 bits). The contents of the OTP memory are read at reset and are addressable by the I2C interface. The shadow register values are used to control the internal operational parameters of the IC and can be modified. However, in the event of a POR or any kind of reset, the shadow registers will be rewritten with the OTP memory content. In the event that a CRC verification fails during normal operation, the registers will be rewritten with OTP memory content, negating any changes that have been made to the shadow registers. The CRC is verified after the OTP memory has been uploaded at POR, periodically during the operation of the IC, and at the exit of Control Port mode. The CRC can be disabled by writing to the CRC disable register, or by enabling the Control Port mode (see "Control Port Enable" on page 24). The shadow registers will be restored from OTP memory on a POR event, or any reset type event. The CRC is calculated using Equation 11. 8 Device Address (7-bit) Start Condition R/ W [Eq.11] The CRC calculation is implemented in hardware using a linear feedback shift register starting with address 0 and ending with address 57 (see Figure 26). The current CRC is stored in address 63. 8 3 2 1 0 Figure 26. CRC Hardware Representation To perform a successful write to the OTP memory, the CRC must be calculated and stored in the CRC registers prior to issuing the OTP write command. OTP memory can only be written once. OTP shadow registers accessible to the user are described in "One-Time Programmable (OTP) Registers" on page 27. 5.11.1 I2C Control Port Protocol The communication port is designed to allow a master device to read and write the OTP shadow registers of the CS1630/31 and the capability of programming the OTP memory using the data in the shadow registers. The OTP shadow registers provide a mechanism for configuring the device and calibrating the system prior to programming the device. The CS1630/31 communication port physical layer adheres to the I2C bus specification by Philips Semiconductor version 2.1, January 2000 (see "I2C Port Switching Characteristics" on page 8). The CS1630/31 control port only supports I2C slave functionality. The CS1630/31 I2C interface is intended for use with a single master and no other slaves on the bus. Figure 27 illustrates the frame format used for I2C data transfers. The first bit is a Start condition (bit S) followed by an 8-bit slave address that is comprised of a 7-bit device address plus a Read/Write (R/W) bit. The R/W bit is the least significant bit of the slave address byte, which indicates Slave Address (1 byte and acknowledge) S 2 CRC = CRC x + x + x + 1 Data Transferred (n bytes and acknowledge) A/A ‘1’ = Read ‘0’ = Write BLK/SGL ‘1’ = Block ‘0’ = Single Register Address (7-Bit) A/A A Data ‘A’ = Acknowledge (SDA Low) ‘ A’ = Not Acknowledge (SDA High) A/A A … ... Data A/A A P Stop Condition From Slave to Master From Master to Slave Figure 27. I2C Frame Format DS954F2 23 CS1630/31 whether data transfer is a read or write operation. This bit should be set to '0' to perform a write operation and '1' to perform a read operation. The 7-bit device address is the 7 most significant bit of the slave address. For data transfers, the CS1630/31 acknowledges a binary device address of ‘0010000’, which is reserved for accessing OTP shadow registers (see "One-Time Programmable (OTP) Registers" on page 27). After the 7-bit device address is received, the Control Port performs a compare to determine if it matches the CS1630/31 device address. If the compare is true, the Control Port will respond with an Acknowledge (bit A) and prepares the device for a read or write operation. Since the CS1630/31 is always in slave mode, the device sends an Acknowledge at the end of each byte. The final bit is the Stop condition (bit P), which is sent by the master to finish a data transfer. The communication port supports single and block data transfers. The block read or write capability is available by setting the MSB of the register address to ‘1’. Device address 0x10 provides access to the OTP shadow registers in the address range of 0x00 to 0x7F. 5.11.2 Control Port Enable Control Port mode is enabled and initiated by transmitting a two-byte hardware pass code using an I2C block write. To enable the control port, the master needs to write a Start condition followed by a slave address of 0x22 (7 MSB device address = ‘0010001’ and the LSB R/W = ‘0’ for a write operation). Then a 0x81 (MSB BLK/SGL = ‘1’ and 7 LSB register address = ‘0000001’) followed by two bytes of data 0xF4 and 0x4F, ending the transmission with a Stop condition. Once in Control Port mode, the CS1630/31 can be configured to perform color calibration functions and program the OTP memory. Several other system configuration tasks can be performed by writing and reading the shadow registers using the I2C port. Slave Address (1 Byte and Acknowledge) S Device Address (7-bit) Start Condition Device Address (7-Bit) 1 A ‘1’ = Read Start Condition 1 To perform a single shadow register read, a write to the Control Port must be used to set up the shadow register address and the BLK/SGL configuration bit (indicating a single read operation). To initiate a single read operation, a Start condition followed by a slave address of 0x21 (7 MSB device address = ‘0010000’ and the LSB R/W = ‘1’ for a read operation) is sent at the start of the message. The MSB of the second byte is cleared to ‘0’ to indicate a single byte read. The remaining 7 bits of the second byte represent the shadow register address of the read operation. After receiving the Acknowledge from the Control Port, the master should terminate the message by sending a Stop condition. The protocol for a single read operation is illustrated by the top frame in Figure 28. To initiate a block read operation, a Start condition followed by a slave address of 0x21 (7 MSB device address = ‘0010000’ and the LSB R/W = ‘1’ for a read operation) is sent at the start of the message. The MSB of the second byte is set to ‘1’ to indicate a block read. The remaining 7 bits of the second byte represent the starting shadow register address of the read operation. The slave continues to send data bytes until the master sends a Stop condition after receiving the Acknowledge, signifying the end of the block read message. The protocol for a block read operation is illustrated by the bottom frame in Figure 28. 5.11.4 Write Operation To perform a write operation, the master must write the 7-bit device address, the R/W bit, the BLK/SGL bit, and the 7-bit shadow register address. The master can then write the required bytes to the shadow registers. Figure 29 illustrates protocol for a single and block write operation. Register Address (7-bit) 0 ‘0’ = Single A Data A P Stop Condition ‘A’ = Acknowledge (SDA Low) Data Transferred (n Bytes and Acknowledge) A ‘1’ = Read To perform a read operation, the master must write the 7-bit device address, the R/W bit, the Block/Single (BLK/SGL) bit, and the 7-bit shadow register address. The master can then read the required bytes from the shadow registers. Figure 28 illustrates protocol for a single and block read operation. Data Transferred (2 Bytes and Acknowledge) Slave Address (1 Byte and Acknowledge) S 5.11.3 Read Operation 1 ‘1’ = Block Register Address (7-Bit) A Data Data A … ... ‘A’ = Acknowledge (SDA Low) Data A P Stop Condition From Slave to Master From Master to Slave Figure 28. Frame Formats for Read Operation 24 DS954F2 CS1630/31 Data Transferred (2 Bytes and Acknowledge) Slave Address (1 Byte and Acknowledge) S Device Address (7-bit) Start Condition 0 A ‘0’ = Write Register Address (7-bit) 0 ‘0’ = Single Device Address (7-Bit) Start Condition 0 A ‘0’ = Write Data A P Stop Condition ‘A’ = Acknowledge (SDA Low) Data Transferred (n Bytes and Acknowledge) Slave Address (1 Byte and Acknowledge) S A 1 ‘1’ = Block Register Address (7-Bit) A Data A … ... ‘A’ = Acknowledge (SDA Low) Data A P Stop Condition From Slave to Master From Master to Slave Figure 29. Frame Formats for Write Operation To perform a single shadow register write, a write to the Control Port must be used to set up the shadow register address and the BLK/SGL configuration bit (indicating a single write operation). To initiate a single write operation, a Start condition followed by a slave address of 0x20 (7 MSB device address = ‘0010000’ and the LSB R/W = ‘0’ for a write operation) is sent at the start of the message. The most significant bit of the second byte is cleared to ‘0’ to indicate a single byte write. The remaining 7 bits of the second byte represent the shadow register address of the write operation. After receiving the Acknowledge from the Control Port, the master should terminate the message by sending a Stop condition. The protocol for a single write operation is shown as the top frame in Figure 29. To initiate a block write operation, a Start condition followed by a slave address of 0x20 (7 MSB device address = ‘0010000’and the LSB R/W = ‘0’ for a write operation) is sent at the start of the message. The MSB of the second byte is set to ‘1’ to indicate a block write. The remaining 7 bits of the second byte represent the starting shadow register address of the write operation. The slave continues to send data bytes until the master sends a Stop condition after receiving the Acknowledge, signifying the end of the block write message. The protocol for a block write operation is illustrated by the bottom frame in Figure 29. Block writes will wrap around from shadow register address 127 to 0 if a Stop condition is not received. 2 5.11.5 Customer I C Lockout The CS1630/31 provides a mechanism that locks or disables the I2C control port. This feature provides security against potential access to proprietary register settings and OTP memory (color compensation) through the I2C control port. To enable the lockout feature, the LOCKOUT bit is set to ‘1’ in the Config0 register (see "Configuration 0 (Config0) – Address 0" on page 29) and setting a 32-bit Lockout Key in registers LOCK3, LOCK2, LOCK1, and LOCK0 (at register address DS954F2 0x01 to 0x04). The value of the Lockout Key is user programmable and stored in OTP memory (see "Lockout Key (LOCK0, LOCK1, LOCK2, LOCK3) – Address 1 - 4" on page 29). To unlock the Control Port, the proper programmed Lockout Key is written to the 32-bit Lockout Key shadow registers LOCK3, LOCK2, LOCK1, and LOCK0. The Lockout Key must be written in ascending address order for the lockout to be disabled. The MODE bit in register Config0 is set to ‘1’, the Color Polynomial Coefficient registers P10_MSB, P10_LSB, P01_MSB, and P01_LSB (at register address 0x09, 0x0A, 0x0F, and 0x10) are appended to the Lockout Key to increase security. If the wrong Lockout Key is written to the shadow resisters when attempting to disable the lockout feature, the part cannot be unlocked until a reset cycle occurs. In lockout mode, the Control Port disables the following operations through the I2C communication port: • I2C read operations from OTP shadow registers (value of 0x0 will be read through control port) • I2C write operations to lockout enabled or key shadow registers (including read operations through PLC) • Direct OTP memory read or write (including reads/writes through PLC) Write operations to either OTP or test space (except OTP Lockout Key) are allowed in lockout mode. 5.12 OTP Memory At startup, the contents of the OTP memory are read into shadow registers that make up a register file. Access to the OTP memory values is accomplished by reading and writing to the OTP corresponding address locations in that register file. To program the part, each unprogrammed address location must be filled with an appropriate value. Next, a CRC is calculated corresponding to the OTP space that is being programmed. Lastly, two special registers are written to initiate a burn/program cycle. 25 CS1630/31 5.12.1 Programming the OTP Memory When the CS1630/31 is shipped, some of the OTP memory will already be programmed. Do not clear any bits to ‘0’ that are programmed to '1', and do not modify any registers or bits that are reserved. Changing bits from '1' to '0' before attempting programming is likely to result in an unrecoverable CRC error, and changes to reserved bits may have detrimental effects on behavior. Step 1 Write Register and Bit Values Write the desired values to the OTP shadow register address locations. All reads and writes are performed with I2C communication using device address 0x10. Step 2 Enable Programming Set the CRC bit to ‘1’ in register Config38 (see "Configuration 38 (Config38) – Address 70" on page 39). Setting CRC = ‘1’ activates the use of the CRC_TAG register at address 0x66 (see "CRC Tag (CRC_TAG) – Address 102" on page 50). Step 3 Compute the CRC Compute the CRC value of registers located at address 0x0 to 0x5F, including all factory-programmed registers and bits. Write this calculated CRC value to the CRC_TAG register at address 0x66. Step 4 Initiate a Program Cycle To enable OTP memory programming, the master needs to write a Start condition followed by a slave address of 0x22 (7 MSB device address = ‘0010001’ and the LSB R/W = ‘0’ for a write operation). Then a 0x79 (MSB BLK/SGL = ‘0’ and 7 LSB register address = ‘1111001’) followed by one byte of data 0x73, ending the transmission with a Stop condition. To initiate the program cycle, the master needs to write a Start condition followed by a slave address of 0x22 (7 MSB device address = ‘0010001’ and the LSB R/W = ‘0’ for a write operation). Then a 0x72 (MSB BLK/SGL = ‘0’ and 7 LSB register address = ‘1110010’) followed by one byte of data 0x90, ending the transmission with a Stop condition. The program cycle takes approximately 35ms. 26 Step 5 Check OTP Program Status To check if the program cycle completed successfully, the master needs to write a Start condition followed by a slave address of 0x23 (7 MSB device address = ‘0010001’ and the LSB R/W = ‘1’ for a read operation). Then write a 0x59 (MSB BLK/SGL = ‘0’ and 7 LSB register address = ‘1011001’). After the acknowledge is received, the master needs to read the 8bit OTP Program Status register, ending the transmission with a Stop condition. If bit 4 of the Program Status register is set to ‘1’ then the OTP write has finished. If bit 4 of the Program Status register is not set to ‘1’, after the 35ms program cycle is complete, then a CRC error likely occurred, or the program cycle was not started properly. Step 6 OTP Verification Check Cycle the power to the CS1630/31. The OTP memory is uploaded to the shadow registers. To check if the program cycle was successful, the master needs to write a Start condition followed by a slave address of 0x23 (7 MSB device address = ‘0010001’ and the LSB R/W = ‘1’ for a read operation). Then write a 0x7C (MSB BLK/SGL = ‘0’ and 7 LSB register address = ‘1111100’). After the acknowledge is received, the master needs to read the 8-bit OTP Verification register, ending the transmission with a Stop condition bit (P). If the value in the 8-bit OTP Verification register is 0x01, then the program process failed to execute properly. If the 8-bit value is 0x00 then use a read operation to verify that the values in the shadow registers match what was written to the shadow registers in Step 1. If the values do not match, then it is likely the OTP program process was not performed due to an error when calculating the CRC or the CRC bit in the Config38 register was not set to ‘1’. Verify that all bits read from the shadow register match the bits prior to starting the program process and start at Step 1 to perform the OTP program process. DS954F2 CS1630/31 6. ONE-TIME PROGRAMMABLE (OTP) REGISTERS 6.1 Registers Map Address 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 DS954F2 RA[7:0] 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 Name Config0 LOCK3 LOCK2 LOCK1 LOCK0 P30_MSB P30_LSB P20_MSB P20_LSB P10_MSB P10_LSB P03_MSB P03_LSB P02_MSB P02_LSB P01_MSB P01_LSB P21_MSB P21_LSB P12_MSB P12_LSB P11_MSB P11_LSB P00_MSB P00_LSB Q3_MSB Q3_LSB Q2_MSB Q2_LSB Q1_MSB Q1_LSB Q0_MSB Q0_LSB GD_DUR Config2 Config3 Config4 S2DIM TTMAX Config7 Config8 CH1CUR Config10 CH2CUR Config12 PID TTFREQ Config15 Config16 Description1 Configuration 0 Lockout Key[31:24] Lockout Key[23:16] Lockout Key[15:8] Lockout Key[7:0] Color Polynomial Coefficient P30[15:8] Color Polynomial Coefficient P30[7:0] Color Polynomial Coefficient P20[15:8] Color Polynomial Coefficient P20[7:0] Color Polynomial Coefficient P10[15:8] Color Polynomial Coefficient P10[7:0] Color Polynomial Coefficient P03[15:8 Color Polynomial Coefficient P03[7:0] Color Polynomial Coefficient P02[15:8] Color Polynomial Coefficient P02[7:0] Color Polynomial Coefficient P01[15:8] Color Polynomial Coefficient P01[7:0] Color Polynomial Coefficient P21[15:8] Color Polynomial Coefficient P21[7:0] Color Polynomial Coefficient P12[15:8] Color Polynomial Coefficient P12[7:0] Color Polynomial Coefficient P11[15:8] Color Polynomial Coefficient P11[7:0] Color Polynomial Coefficient P00[15:8] Color Polynomial Coefficient P00[7:0] Color Polynomial Coefficient Q3[15:8] Color Polynomial Coefficient Q3[7:0] Color Polynomial Coefficient Q2[15:8] Color Polynomial Coefficient Q2[7:0] Color Polynomial Coefficient Q1[15:8] Color Polynomial Coefficient Q1[7:0] Color Polynomial Coefficient Q0[15:8] Color Polynomial Coefficient Q0[7:0] Gate Drive Duration Configuration 2 Configuration 3 Configuration 4 Second Stage Dim Maximum TT Configuration 7 Configuration 8 Channel 1 Output Current Configuration 10 Channel 2 Output Current Configuration 12 PU Coefficient Maximum Switching Frequency Configuration 15 Configuration 16 27 CS1630/31 49 50 51 0x31 0x32 0x33 Config17 Config18 PEAK_CUR Configuration 17 Configuration 18 Peak Current .... ............. - Reserved 70 0x46 Config38 Configuration 38 .... ............. - Reserved 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 0x4C 0x4D 0x4E 0x4F 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x51 0x52 0x53 0x54 Config44 Config45 Config46 Config47 Config48 Config49 Config50 Config51 Config52 Config53 Config54 Config55 PLC_DIM Config58 Config59 Config60 Config61 Config62 Configuration 44 Configuration 45 Configuration 46 Configuration 47 Configuration 48 Configuration 49 Configuration 50 Configuration 51 Configuration 52 Configuration 53 Configuration 54 Configuration 55 PLC Dim Configuration 58 Configuration 59 Configuration 60 Configuration 61 Configuration 62 .... ............. - Reserved 102 0x66 CRC_TAG CRC Tag .... .............. - Reserved 119 120 121 122 123 124 125 126 127 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F CH1_CAL3A CH2_CAL3A CRC_MTAG3A CH1_CAL3B CH2_CAL3B CRC_MTAG3B CH1_CAL3C CH2_CAL3C CRC_MTAG3C Channel 1 Color Calibration 3A Channel 2 Color Calibration 3A CRC Tag 3A Channel 1 Color Calibration 3B Channel 2 Color Calibration 3B CRC Tag 3B Channel 1 Color Calibration 3C Channel 2 Color Calibration 3C CRC Tag 3C Note: 28 (1) Warning: Do not write to unpublished or reserved register locations. DS954F2 CS1630/31 6.2 Configuration 0 (Config0) – Address 0 7 - 6 - 5 - Number Name [7:2] - [1] MODE [0] LOCKOUT 4 - 3 - 2 - 1 MODE 0 LOCKOUT Description Reserved Appends two of the color system coefficients (P01 followed by P10) to the 32bit lockout key to make it a 64-bit key from a 32-bit key to increase security. 0 = 32-bit key 1 = 64-bit key Configures the IC lockout security mechanism by using Lockout Key. 0 = Disable 1 = Enable 6.3 Lockout Key (LOCK0, LOCK1, LOCK2, LOCK3) – Address 1 - 4 MSB 30 29 28 27 26 25 24 231 230 229 228 227 226 225 224 ..... ..... 6 5 4 3 2 1 LSB 26 25 24 23 22 21 20 Lockout Key is a 32-bit long-word used for password protection when accessing the OTP registers. Register LOCK0 is the least significant byte of the Lockout Key, and register LOCK3 is the most significant byte of Lockout Key. Register LOCK2 is the byte to the right of LOCK3, and register LOCK1 is the byte to the left of LOCK0. To access the OTP registers on an IC with a lockout mechanism that has been enabled, see “Customer I2C Lockout” on page 25. 6.4 Color Polynomial Coefficient (P30, P20, P10, P03, P02, P01, P21, P12, P11, P00) – Address 5 - 24 MSB 14 13 12 11 10 9 8 7 6 5 4 3 2 1 LSB -(23) 22 21 20 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 Color polynomial coefficients used to calculate the gain (GAINDTR) that controls the current in the color LED channel based on temperature drift and current dim level. The value is a two's complement number in the range of -8.0value<8.0, with the binary point to the right of bit 12. The gain polynomial is: 3 2 3 2 2 2 GAIN DTR = P30 T + P20 T + P10 T + P03 D + P02 D + P01 D + P21 T D + P12 T D + P11 T D + P00 where, T = the measured normalized temperature and is 0 T<1.0 D = the normalized dim value and is 0 D<1.0 GAINDTR = gain of the channel based on the temperature measurement and the dim value. The polynomial coefficients should be selected such that the computed GAINDTR is always a positive number in the range of 0<GAINDTR <4. Color Polynomial Coefficients, Pxx, are 16 bits in length where Pxx - MSB is the most significant byte and PxxLSB is the least significant byte. DS954F2 29 CS1630/31 6.5 Color Polynomial Coefficient (Q3, Q2, Q1, Q0) – Address 25 - 32 MSB 3 -(2 ) 14 13 12 11 10 2 1 0 -1 -2 2 2 2 2 2 9 8 7 6 5 4 3 2 1 LSB -3 -4 -5 -6 -7 -8 -9 -10 -11 2-12 2 2 2 2 2 2 2 2 2 Coefficients of the color polynomial used to calculate the gain (GAINDR) that controls the current in the white LED channel based on the current dim level. The value is a two's complement number in the range of -8.0value<8.0, with the binary point to the right of bit 12. Coefficients Q3, Q2, Q1, and Q0 are distributed in the gain polynomial: 3 2 GAIN DR = Q 3 D + Q2 D + Q1 D + Q0 where, D = the normalized dim value and is 0<D<1.0 GAINDR = gain of the channel based on the dim value. The polynomial coefficients should be selected such that the computed GAINDR is always a positive number such that 0<GAINDR <4. Color Polynomial Coefficients, Qxx, are 16-bits in length where Qxx - MSB is the most significant byte and Qxx-LSB is the least significant byte. 6.6 Gate Drive Duration (GD_DUR) – Address 33 7 6 5 4 3 2 1 0 27 26 25 24 23 22 21 20 GD_DUR sets the maximum gate drive duration for the second stage (flyback, buck, or tapped buck). The register value is an unsigned integer in the range of 0value255. The maximum gate drive duration is determined by: GD_DUR 8 + 7 50 ns The maximum gate drive duration can be configured from 350ns to 102.35s. 30 DS954F2 CS1630/31 6.7 Configuration 2 (Config2) – Address 34 7 CLAMP1 Number [7:6] 6 CLAMP0 5 T2COMP Name CLAMP[1:0] 4 - 3 - 2 - 1 VALLEYSW 0 - Description Configures the offset adjustment for the minimum measurable peak current level on the second stage sense resistor when the gate drive is turned on. CLAMP[1:0] is an unsigned integer in the range of 0value3. The voltage on the FBSENSE pin that corresponds to the minimum peak current is calculated using the following formula: IPEAK[2:0] + 1 16 + 15 – CLAMP[1:0] 8 + 8 1.4 --------------------------------------------------------------------------------------------------------------------------------------------------- 512 [5] T2COMP [4:2] - [1] VALLEYSW [0] - DS954F2 Configures T2 measurement compensation for second stage flyback designs with a large delay between the fall of the primary current and the rise of the secondary current during the switching cycle. When using this feature, the measured T2 time (measured from the falling edge of the gate drive) is adjusted to obtain the actual T2 time, allowing the control loop to tightly regulate the output currents and reduce errors. 0 = Disable T2 measurement compensation 1 = Enable T2 measurement compensation Reserved Configures quasi-resonant switching (valley switching) on the second stage. 0 = Disables valley switching on the second stage 1 = Enables valley switching on the second stage Reserved 31 CS1630/31 6.8 Configuration 3 (Config3) – Address 35 7 STRING 6 TT_MAX1 Number Name [7] STRING [6:5] [4] [3:1] 5 TT_MAX0 4 LED_ARG 3 IPEAK2 2 IPEAK1 1 IPEAK0 0 - Description Configures second stage series/parallel output channel configuration. 0 = Second stage configured as parallel strings 1 = Second stage configured with strings in series Configures the maximum measurable second stage switching cycle period. 00 = 51.15s TT_MAX[1:0] 01 = 102.35s 10 = 153.55s 11 = 204.75s LED_ARG IPEAK[2:0] Configures which channel is connected to the color LED string (the string with a gain that is dependent on dim and temperature). 0 = Color LED string connected to channel 1 1 = Color LED string connected to channel 2 Configures the minimum measurable peak current level on the second stage sense resistor when the gate drive is turned on along with the CLAMP[1:0] setting. IPEAK[2:0] is an unsigned integer in the range of 0value7. The voltage on the FBSENSE pin that corresponds to the minimum peak current is calculated using the following formula: IPEAK[2:0] + 1 16 + 15 – CLAMP[1:0] 8 + 8 1.4 --------------------------------------------------------------------------------------------------------------------------------------------------- 512 [0] 32 - Reserved DS954F2 CS1630/31 6.9 Configuration 4 (Config4) – Address 36 7 6 5 4 3 2 T2CH1GAIN5 T2CH1GAIN4 T2CH1GAIN3 T2CH1GAIN2 T2CH1GAIN1 T2CH1GAIN0 Number [7:2] Name T2CH1GAIN[5:0] 1 SYNC 0 POL_ZCD Description Sets T2 compensation gain T2CH1CompGain for channel 1, which is required when T2 measurement compensation is enabled for flyback designs. The value is an unsigned integer in the range of 0T2CH1GAIN[5:0]<63. Compensated T2 time T2Compensated used in the second stage charge regulation loop is given by: T2 Compensated = T2 Measured – T ZCD Ri sin gEdge T2 CH1CompGain where, T2CH1CompGain is a decimal number in the range of 0.0T2CH1CompGain <4.0: T2 CH1CompGain = T2CH1GAIN[5:0] 0.0625 SYNC Enables the digital synchronization signal that indicates which channel the controller is signaling for each gate switching period on the IC’s SYNC pin. The SYNC bit should be enabled for non-isolated second stage designs where the synchronizer circuit is directly driven from the IC's SYNC pin. 0 = Disables SYNC onto pin 1 = Enables SYNC onto pin POL_ZCD Sets polarity of zero-current detection comparator output. Recommended to set bit POL_ZCD to active-low polarity. 0 = Active-low polarity 1 = Positive polarity [1] [0] 6.10 Second Stage Dim (S2DIM) – Address 37 7 6 5 4 3 2 1 0 27 26 25 24 23 22 21 20 S2DIM sets the minimum dim for second stage (flyback, buck, or tapped buck). The register value is an unsigned integer in the range of 0value255. Enforced minimum dim percentage dimmin is determined by the following equation: S2DIM[7:0] 16 + 15 dim min = -------------------------------------------------------- 100 4095 6.11 Maximum TT (TTMAX) – Address 38 7 6 5 4 3 2 1 0 27 26 25 24 23 22 21 20 TTMAX sets the maximum allowable target period for the second stage TT. The register value is an unsigned integer in the range of 0value255. The maximum TT period is determined by: TTMAX[7:0] 128 + 127 50ns The maximum period for TT can be configured from 6.35s to 1.63835ms. DS954F2 33 CS1630/31 6.12 Configuration 7 (Config7) – Address 39 7 PROBE Number [7] 6 PRCNT3 5 PRCNT2 4 PRCNT1 Name 3 PRCNT0 2 - 1 - 0 - Description Configures the automated TRES probe operation that measures the resonant frequency on the drain of the second stage FET using the reflected voltage applied to the FBAUX pin for improved valley switching performance. 0 = Disables TRES probe 1 = Enables TRES probe PROBE When PROBE=‘1’, sets the number of switching cycles TTCycles between TRES probe measurements. TT Cycles = 16 P RCNT[3:0] + 15 [6:3] PRCNT[3:0] When PROBE=‘0’, sets the time for a quarter period of the resonant period TRES. T RES ------------- = 2 PRCNT[3:0] 50ns 4 [2:0] - Reserved 6.13 Configuration 8 (Config8) – Address 40 7 RSHIFT3 Number [7:4] [3:1] 6 RSHIFT2 5 RSHIFT1 4 RSHIFT0 3 CH1_ZCD2 2 CH1_ZCD1 1 CH1_ZCD0 0 CH1CURMSB Name Description RSHIFT[3:0] Sets the number of right shifts performed on the second stage PID integrator value to generate a 10-bit threshold value for the peak control comparator. For peak rectify mode, the threshold is calculated by a right shift of the integrator value. If RSHIFT[3:0] is set to 12, the 24-bit integrator is shifted right 12 times and the remaining bits represent the threshold value provided to the peak control comparator. Sets fixed time delay TCH1ZCD(Delay) to account for the delay of the second stage zero-current detection (ZCD) comparator during channel 1 switching cycles when the voltage applied to the FBAUX pin falls below the 250mV ZCD CH1_ZCD[2:0] comparator threshold. Configuring TCH1ZCD(Delay) is essential for good quasiresonant (valley switching) performance. The value is an unsigned integer in the range of 0value7. The delay is defined by: T CH1ZCD Delay = CH1_ZCD [2:0] 50ns [0] 34 CH1CURMSB Most significant bit for the CH1CUR register (see "Channel 1 Output Current (CH1CUR) – Address 41" on page 35). DS954F2 CS1630/31 6.14 Channel 1 Output Current (CH1CUR) – Address 41 7 2 6 7 2 5 6 2 5 4 2 3 4 2 2 3 2 2 1 2 1 0 20 CH1CUR sets the target output current for channel 1. The register value plus bit CH1CURMSB forms an unsigned integer in the range of 0value511. 6.15 Configuration 10 (Config10) – Address 42 7 BUCK3 6 BUCK2 Number [7:4] [3:1] 5 BUCK1 4 BUCK0 3 RE1_ZCD2 Name BUCK[3:0] 2 RE1_ZCD1 1 RE1_ZCD0 0 CH2CURMSB Description Configures buck topology. The value is an unsigned integer in the range of 0value15. 0 = Normal buck configuration 1 = Tapped buck ratio of one which is equivalent to a normal buck configuration 2-15 = Tapped buck configuration where the ratio is equal to N. Configures fixed time delay TRE1ZCD(delay) for zero-current detection (ZCD) comparator to account for the delay on the rising edge of ZCD for channel 1. The value is an unsigned integer in the range of 0value7. The delay is RE1_ZCD[2:0] defined by: T RE1ZCD delay = RE1_ZCD [2:0] 50ns [0] CH2CURMSB Most significant bit for the CH2CUR register (see "Channel 2 Output Current (CH2CUR) – Address 43" on page 35). 6.16 Channel 2 Output Current (CH2CUR) – Address 43 7 6 5 4 3 2 1 0 27 26 25 24 23 22 21 20 CH2CUR sets the target output current for channel 2. The register value plus bit CH2CURMSB forms an unsigned integer in the range of 0value511. DS954F2 35 CS1630/31 6.17 Configuration 12 (Config12) – Address 44 7 TIMEOUT1 Number [7:6] 6 TIMEOUT0 5 S2CONFIG 4 DITATT1 3 DITATT0 Name 2 - 1 - 0 - Description Sets the T2 time-out limit to ensure a minimum switching frequency for each channel. 00 = 45ms TIMEOUT[1:0] 01 = 70.6ms 10 = 96.2ms 11 = 121.8ms S2CONFIG Configures second stage for flyback or buck/tapped buck. 0 = Enables second stage for buck/tapped buck topology 1 = Enables second stage for flyback topology [4:3] DITATT[1:0] Configures the dither attenuation by right shifting the dither value on a selected channel for dithering reduction. The nominal dither level (set using bits DITLEVEL[1:0]) is attenuated by the amount configured by bits DITATT[1:0] on the channel set using bit DITCHAN. 00 = No attenuation 01 = 50% attenuation 10 = 25% attenuation 11 = 12.5% attenuation [2:0] - [5] Reserved 6.18 PU Coefficient (PID) – Address 45 7 6 5 4 3 2 1 0 27 26 25 24 23 22 21 20 PID sets the maximum coefficient for the second stage PU integrator. The register value is an unsigned integer in the range of 0value255. 6.19 Maximum Switching Frequency (TTFREQ) – Address 46 7 2 7 6 5 4 3 2 1 0 26 25 24 23 22 21 20 TTFREQ sets the minimum switching period (maximum switching frequency) for the second stage TT (see "Maximum TT (TTMAX) – Address 38" on page 33). The register value is an unsigned integer in the range of 0value255. The minimum TTFREQ switching period is determined by: TTFREQ[7:0] 4 50ns The switching period for TT can be configured from 0ns to 51s. 36 DS954F2 CS1630/31 6.20 Configuration 15 (Config15) – Address 47 7 EXIT_PH3 Number 6 EXIT_PH2 5 EXIT_PH1 4 EXIT_PH0 3 DECL_PH3 2 DECL_PH2 1 DECL_PH1 0 DECL_PH0 Name Description [7:4] EXIT_PH[3:0] Configures the number of channel 1 switching periods between phase synchronization conditions on the second stage. EXIT_PH[3:0] provides a hysteresis to prevent consecutive resynchronizations by the controller. The value is an unsigned integer in the range of 0value15. EXIT_PH[3:0] needs to be configured only for designs that use a dual channel synchronization circuit and is not directly driven from the SYNC pin. The RESYNC bit must be enabled (see “Configuration 17 (Config17) – Address 49” on page 38). [3:0] Configures the number of second stage switching periods with improper output identification until the controller resynchronizes. There is a counter that increments by 1 on improper output identification and decrements by 2 if proper output identification is measured. If this counter exceeds the threshold set by bits DECL_PH[3:0] and the controller has not seen a phase resynchroDECL_PH[3:0] nization in EXIT_PH[3:0] cycles, the controller resynchronizes. The value is an unsigned integer in the range of 0value15. DECL_PH[3:0] needs to be configured only for designs that use a dual channel synchronization circuit and is not directly driven from the SYNC pin. The RESYNC bit must be enabled (see “Configuration 17 (Config17) – Address 49” on page 38). 6.21 Configuration 16 (Config16) – Address 48 7 RE2_ZCD2 Number [7:5] 6 RE2_ZCD1 5 RE2_ZCD0 Name RE2_ZCD[2:0] 4 CH2_ZCD2 3 CH2_ZCD1 2 CH2_ZCD0 1 SCP 0 VDIFF Description Sets the fixed time delay TRE2ZCD(delay) for zero-current detection (ZCD) comparator to account for the delay on the rising edge of ZCD for channel 2. The value is an unsigned integer in the range of 0value7. The delay is defined by: TRE2ZCD delay = RE2_ZCD [2:0] 50ns [4:2] Sets fixed time delay TCH2ZCD(delay) to account for the delay of the second stage zero-current detection (ZCD) comparator during channel 2 switching cycles when the voltage applied to the FBAUX pin falls below the 200mV ZCD CH2_ZCD[2:0] comparator threshold. Configuring TCH2ZCD(delay) is essential to achieve good quasi-resonant (valley switching) performance. The value is an unsigned integer in the range of 0value7. The delay is defined by: T CH2ZCD delay = CH2_ZCD [2:0] 50ns [1] [0] DS954F2 SCP VDIFF Configures the second stage short circuit protection. 0 = Enable short circuit protection 1 = Disable short circuit protection Configures the VDiff fault mechanism for use by the protection module. 0 = Enable VDiff fault 1 = Disable VDiff fault 37 CS1630/31 6.22 Configuration 17 (Config17) – Address 49 7 DITHER 6 RESYNC 5 4 3 2 1 0 T2CH2GAIN5 T2CH2GAIN4 T2CH2GAIN3 T2CH2GAIN2 T2CH2GAIN1 T2CH2GAIN0 Number Name [7] DITHER Configures dither on the second stage primary side peak current threshold. 0 = Disable dither 1 = Enable dither RESYNC Configures resynchronization of a dual channel second stage design where the channel synchronization circuit is not directly driven from the SYNC pin. Bit RESYNC controls the behavior of bits EXIT_PH[3:0] and DECL_PH[3:0] (see "Configuration 15 (Config15) – Address 47" on page 37). 0 = Disable phase resynchronization 1 = Enable phase resynchronization [6] [3:0] Description T2CH2GAIN[5:0] Sets T2 compensation gain T2CH2CompGain for channel 2 which is required when T2 measurement compensation is enabled for flyback designs. The value is an unsigned integer in the range of 0T2CH2CompGain <63. Compensated T2 time T2Compensated used in the second stage charge regulation loop is given by: T2 Compensated = T2 Measured – T ZCD Ri sin gEdge T2 CH2CompGain where, T2CH2CompGain is a decimal number the range of 0.0T2CH2CompGain <4.0. T2 CH2CompGain = T2CH2GAIN[5:0] 0.0625 6.23 Configuration 18 (Config18) – Address 50 7 LEB3 Number [7:4] 6 LEB2 Name LEB[3:0] 5 LEB1 4 LEB0 3 TEB3 2 TEB2 1 TEB1 0 TEB0 Description Configures the leading-edge blanking time TLEB for the second stage peak current measurement. The output of the current sense comparator which controls the primary side peak current is ignored for time TLEB from the rising edge of the gate drive signal. T LEB = LEB[3:0] 2 50ns [3:0] TEB[3:0] Configures the trailing-edge blanking time TTEB for zero-current detection. The ZCD comparator output signal used to detect the secondary side inductor demagnetization is blanked for time TTEB after the falling edge of the second stage gate drive signal. T TEB = TEB[3:0] 2 50ns 38 DS954F2 CS1630/31 6.24 Peak Current (PEAK_CUR) – Address 51 7 2 6 7 2 5 6 2 5 4 2 4 3 2 3 2 2 2 1 2 1 0 20 PEAK_CUR sets the boost stage peak current, which assists in configuring the boost output power. The register value is an unsigned integer in the range of 0value255 where the LSB = 4.1mA.The peak current can be configured from 0mA to 1.0455A. 6.25 Configuration 38 (Config38) – Address 70 7 - 6 - 5 - Number Name [7:1] - [0] CRC 4 - 3 - 2 - 1 - 0 CRC Description Reserved Configures the communication system to use the CRC value in the CRC_TAG register (see "CRC Tag (CRC_TAG) – Address 102" on page 50). Enabling this bit is required when programming the OTP registers of the CS1630/31. 0 = Disables the use of the CRC register 1 = Enables the use of the CRC register 6.26 Configuration 44 (Config44) – Address 76 7 - 6 - 5 - Number Name [7:2] - [1:0] DS954F2 RATE[1:0] 4 - 3 - 2 - 1 RATE1 0 RATE0 Description Reserved Configures the dimming rate for the external overtemperature protection (eOTP) feature which decreases the second stage dim level once the measured 8-bit temperature value corresponding to the external NTC resistance connected to pin eOTP exceeds the temperature value configured using bits eOTP[4:0] (Config59[7:3] of Address 91). The rate at which the 12-bit dim level is decreased is set to any one of the following: 00 = 4 dims per temperature code above CODETEMPeOTP 01 = 8 dims per temperature code above CODETEMPeOTP 10 = 16 dims per temperature code above CODETEMPeOTP 11 = 32 dims per temperature code above CODETEMPeOTP 39 CS1630/31 6.27 Configuration 45 (Config45) – Address 77 7 - 6 - 5 - 4 - 3 - 2 - 1 VDIFF_LAT 0 MAX_CUR Number Name [7:2] - [1] VDIFF_LAT Selects if the VDiff fault is to be a latched type fault. 0 = Unlatched fault 1 = Latched fault MAX_CUR Configures the second stage to draw maximum power when the boost output voltage exceeds boost overvoltage protection threshold VBST > VBOP(th), triggering a boost overvoltage fault. 0 = Disable 1 = Enable [0] Description Reserved 6.28 Configuration 46 (Config46) – Address 78 7 - 6 - 5 - Number Name [7:4] - [3:0] WAKEUP[3:0] 4 - 3 WAKEUP3 2 WAKEUP2 1 WAKEUP1 0 WAKEUP0 Description Reserved Configures the 8-bit code value corresponding to temperature threshold TempWakeup. Upon power-up the system will enter an external overtemperature fault disabling the power train, unless the external temperature measured at the external NTC is below TempWakeup. If the temperature drops below this threshold, the device will clear all overtemperature faults. The setting is an offset to TempeOTP (see “Configuration 59 (Config59) – Address 91” on page 48 for configuring TempeOTP). CODE TEMPWakeup = CODE TEMPeOTP + WAKEUP [3:0] 4 The equation above is setting 8-bit code, CODETEMPWakeup, corresponding to temperature TempWakeup, which is in degrees Celsius. The wakeup temperature code is configured as an offset from the eOTP temperature code and the shutdown temperature code is configured as an offset from the wakeup temperature code; TempeOTP < TempWakeup < TempShutdown. 40 DS954F2 CS1630/31 6.29 Configuration 47 (Config47) – Address 79 7 OCP 6 OLP 5 OVP 4 BOP 3 COP 2 LLP 1 EEOTP 0 IOTP Number Name [7] OCP Configures second stage primary side overcurrent protection. 0 = Enable 1 = Disable OLP Configures second stage primary side open loop protection (RSense Short Protection). 0 = Enable 1 = Disable [5] OVP Configures second stage secondary side overvoltage protection (Output Open Circuit Protection). 0 = Enable 1 = Disable [4] BOP Configures boost overvoltage protection. 0 = Enable 1 = Disable [3] COP Configures clamp overpower protection. 0 = Enable 1 = Disable [2] LLP Configures line link protection. 0 = Enable 1 = Disable [1] EEOTP Configures external overtemperature protection. 0 = Enable 1 = Disable [0] IOTP Configures internal overtemperature protection. 0 = Enable 1 = Disable [6] DS954F2 Description 41 CS1630/31 6.30 Configuration 48 (Config48) – Address 80 7 6 5 4 3 2 1 0 OCP_BLANK3 OCP_BLANK2 OCP_BLANK1 OCP_BLANK0 OLP_BLANK2 OLP_BLANK1 OLP_BLANK0 IOTP_SAMP Number [7:4] Name Description Configures fixed time-blanking interval tOCP for overcurrent protection OCP_BLANK[3:0] (OCP). The value is an unsigned integer in the range of 0value15. t OCP = 150ns + OCP_BLANK [3:0] 50ns [3:1] Configures fixed time blanking interval tOLP for open loop protection (OLP) and sense resistor protection. The value is an unsigned integer in the range OLP_BLANK[2:0] of 0value7. t OLP = 1s + OLP_BLANK [2:0] 0.5s [0] IOTP_SAMP Sample internal temperature sensor at a slower rate when not in internal overtemperature state (iOTP fault state). Recommended to set bit IOTP_SAMP to sample slow. 0 = Sample fast 1 = Sample slow 6.31 Configuration 49 (Config49) – Address 81 7 OCP_CNT2 Number [7:5] [4] [3:1] [0] 42 6 OCP_CNT1 5 OCP_CNT0 4 OCP_LAT 3 OLP_CNT2 Name 2 OLP_CNT1 1 OLP_CNT0 0 OLP_LAT Description Sets the second stage OCP fault counter threshold used when declaring a fault. OCP_CNT[2:0] 0 = Force OCP fault (debug only) 1-7= Number of times an OCP fault has to occur consecutively. OCP_LAT Configures OCP fault type. 0 = Unlatched fault 1 = Latched fault Sets the second stage OLP fault counter threshold used when declaring a fault. OLP_CNT[2:0] 0 = Force OLP fault (debug only) 1-7= Number of times an OLP fault has to occur consecutively before the IC will enter a fault state. OLP_LAT Configures OLP fault type. 0 = Unlatched fault 1 = Latched fault DS954F2 CS1630/31 6.32 Configuration 50 (Config50) – Address 82 7 OVP_CNT2 Number 6 OVP_CNT1 5 OVP_CNT0 4 OVP_LAT 3 OVP_TYPE 2 1 0 OVP_BLANK2 OVP_BLANK1 OVP_BLANK0 Name Description [7:5] OVP_CNT[2:0] Sets the second stage OVP fault counter threshold used when declaring a fault. 0 = Force OVP fault (debug only) 1-7 = Number of times an OVP fault has to occur consecutively before the IC will enter a fault state. [4] OVP_LAT [3] [2:0] OVP_TYPE Configures second stage OVP fault type. 0 = Unlatched fault 1 = Latched fault Selects the type of blanking for the second stage OVP. When bit OVP_TYPE is set to T2 offset, the blanking time is always equal to the corresponding channel’s previous T2 switching cycle time minus an offset of 500ns. 0 = Fixed time blanking mode 1 = T2 offset blanking mode. Configures fixed time blanking interval tOVP for output open protection, OVP_BLANK[2:0] OVP. The value is an unsigned integer in the range of 0value7. t OVP = 1s + OVP_BLANK [2:0] 0.5s 6.33 Configuration 51 (Config51) – Address 83 7 RESTART5 Number 6 RESTART4 5 RESTART3 Name 4 RESTART2 3 RESTART1 2 RESTART0 1 0 FAULT_SLOW FAULT_SHDN Description Set fault restart time TRestart for second stage faults that are set as unlatched type. If slow restart bit FAULT_SLOW is enabled, then [7:2] RESTART[5:0] else T Restart = RESTART[5:0] 40.96ms T Restart = RESTART[5:0] 25.6s DS954F2 [1] FAULT_SLOW Configures slow restart for second stage faults that are set at unlatched type. 0 = Disable slow restart; use 25.6s timer for restart time countdown 1 = Enable slow restart; use 40.96ms timer for restart time countdown [0] FAULT_SHDN Selects which stages to disable when a fault event occurs in the second stage. 0 = Shutdown second stage only 1 = Shutdown boost stage and second stage 43 CS1630/31 6.34 Configuration 52 (Config52) – Address 84 7 6 5 4 3 2 1 COP_THRES6 COP_THRES5 COP_THRES4 COP_THRES3 COP_THRES2 COP_THRES1 COP_THRES0 Number [7:1] Name COP_THRES[6:0] 0 COP_INT Description Value used to determine the COP Filter Threshold. The clamp is sampled every 20s and over the selected interval is compared to COP time-on threshold, TON(th) to determine if an COP fault has occurred. For a 1 second interval: T ON th = COP_THRES [6:0] 5.12ms + 2.56ms For a 2 second interval: T ON th = COP_THRES [6:0] 10.24ms + 5.12ms [0] 44 COP_INT Configures the time interval to check for a boost stage COP fault. 0 = 1 second interval 1 = 2 second interval DS954F2 CS1630/31 6.35 Configuration 53 (Config53) – Address 85 7 6 5 4 3 2 1 0 BOP_INTEG2 BOP_INTEG1 BOP_INTEG0 BOP_THRES3 BOP_THRES2 BOP_THRES1 BOP_THRES0 BOOST_ON Number [7:5] Name Description Sets the leaky integrator output threshold for declaring a boost output protection (BOP) fault. The BOP fault signal is averaged continuously using a leaky integrator and if the averaged value exceeds the leaky integrator output threshold a BOP fault is declared. When VBST exceeds the set threshold BOP_THRES[3:0], the leaky integrator uses these parameters: feedback coefficient = 63/64; sample rate = 12.5kHz; input = 8. 000 = BOP fault trips immediately when VBST crosses threshold (no filter) BOP_INTEG[2:0] 001 = 1 010 = 2 011 = 3 100 = 4 101 = 5 110 = 6 111 = 7 Configures threshold VBOP(th) for the BOP to be 0 to 30V above the clamp turn-on voltage setting which is 227V for 120V IC (CS1630) and 432V for 230V IC (CS1631). The threshold value can be set from 0 to 30V in increments of 2V above the clamp turn-on voltage setting. For a 120V IC: [4:1] BOP_THRES[3:0] For a 230V IC: V BOP th = BOP_THRES [3:0] 2 + 227V V BOP th = BOP_THRES [3:0] 2 + 432V This value is limited internally to 254V for 120V IC and 508V for 230V IC. The boost overvoltage protection does not trip immediately when the boost output voltage crosses this threshold, unless BOP_INTEG[2:0] = 0. [0] DS954F2 BOOST_ON Selects when to enable boost stage on chip power-up. 0 = Boost after eOTP measurement check for TempNTC >TempWakeup 1 = Boost after ADC lock without waiting for eOTP measurement to finish 45 CS1630/31 6.36 Configuration 54 (Config54) – Address 86 7 LLP_TIME2 Number 5 LLP_TIME0 4 BOP_RSTART Name 3 - 2 - 1 - 0 - Description [7:5] Sets the time that the condition VBST < (VLine - VLLPMin(th)) is true to trigger a boost LLP fault. See “Configuration 62 (Config62) – Address 94” on page 50 for configuring VLLPMin(th) using bits BST_LLP[1:0]. 000 = 0ms 001 = 1ms LLP_TIME[2:0] 010 = 2ms 011 = 2.5ms 100 = 3ms 101 = 3.5ms 110 = 4ms 111 = 5ms [4] Configures boost BOP fault behavior. When bit BOP_RSTART is set to ‘1’ the IC attempts to restart after VBST drops down to a nominal voltage level. It is recommended to enable bit MAX_CUR when BOP_RSTART = 1 so the second stage can deliver full output power when a boost BOP fault is detected. BOP_RSTART This helps quickly dissipate the energy stored in the boost output capacitor bringing down the voltage on the capacitor. 0 = Latched fault 1 = Attempts to restart if VBST equals 195V for 120V application or 392V for 230V application [3:0] 46 6 LLP_TIME1 - Reserved DS954F2 CS1630/31 6.37 Configuration 55 (Config55) – Address 87 7 - 6 - 5 EOTP_FLP2 Number Name [7:6] - 4 EOTP_FLP1 3 EOTP_FLP0 2 EOTP_SLP2 1 EOTP_SLP1 0 EOTP_SLP0 Description Reserved [5:3] Sets time constant of the faster low pass filter used for filtering the coarse 8-bit ADCR temperature measurements. This filter's output is used for external overtemperature fault detection by quickly detecting if the external NTC temperature has exceeded the temperature set point TempShutdown. Its output is also used by the Color Control System for controlling the color gain with temperature for the temperature-dependent channel. 000 = No filter EOTP_FLP[2:0] 001 = 233ms 010 = 466ms 011 = 933ms 100 = 1.866s 101 = 3.733s 110 = Reserved 111 = Reserved [2:0] Time constant of the slower low pass filter used for filtering the coarse ADCR temperature measurements. It's output is used for the external overtemperature protection (eOTP) dim with temperature feature which decreases the second stage dim level once the temperature measured using the external NTC connected to pin eOTP exceeds the temperature threshold set using eOTP, TempeOTP (see “Configuration 59 (Config59) – Address 91” on page 48). 000 = 3.75s EOTP_SLP[2:0] 001 = 7.5s 010 = 10s 011 = 15s 100 = 20s 101 = 30s 110 = 1min 111 = 2min 6.38 PLC Dim (PLC_DIM) – Address 89 7 6 5 4 3 2 1 0 27 26 25 24 23 22 21 20 PLC_DIM sets the second stage dim level while in PLC mode (see "Calibration Mode Operation Code" on page 22) and Leading-edge Mode. The register value is an unsigned integer in the range of 0value255. The dim value prevents flashing when a command is sent to the device. If PLC_DIM = 0x00 then 0x7F is used which is equivalent to a 50% dim value. The 12-bit PLC dim value is given by: PLC_DIM 16 + 15 DS954F2 47 CS1630/31 6.39 Configuration 58 (Config58) – Address 90 7 SHUTDWN3 6 SHUTDWN2 Number 5 SHUTDWN1 4 SHUTDWN0 3 LOW_SAT2 Name 2 LOW_SAT1 1 LOW_SAT0 0 DIM_TEMP Description Configures the 8-bit code value corresponding to temperature threshold TempShutdown. If the temperature exceeds this threshold, the device enters an external overtemperature state and shuts down. [7:4] SHUTDWN[3:0] CODE TEMPShutdown = CODE TEMPWakeup + SHUTDWN [3:0] 4 The wakeup temperature code is configured as an offset from the eOTP temperature code and the shutdown temperature code is configured as an offset from the wakeup temperature code; TempeOTP < TempWakeup < TempShutdown [3:1] Sets the lower saturation limit for the 8-bit temperature code provided to the color system from the fast low pass filter before it is used for polynomial comLOW_SAT[2:0] putations.The lower saturation limit is given by: LOW_SAT[2:0] + 1 5 [0] DIM_TEMP Configures the external overtemperature protection (eOTP) dim with temperature feature, which decreases the second stage dim level once the temperature measured using the external NTC connected to pin eOTP exceeds the temperature threshold set using eOTP[4:0], TempeOTP (see “Configuration 59 (Config59) – Address 91” on page 48). 0 = Disable 1 = Enable 6.40 Configuration 59 (Config59) – Address 91 7 eOTP4 Number [7:3] 6 eOTP3 Name eOTP[4:0] 5 eOTP2 4 eOTP1 3 eOTP0 2 HI_SAT2 1 HI_SAT1 0 HI_SAT0 Description Configures 8-bit code value CODETEMPeOTP corresponding to the temperature TempeOTP set point at which the eOTP dim with temperature feature is enabled. CODE TEMPeOTP = 80 + eOTP [4:0] 4 [2:0] 48 HI_SAT[2:0] Sets the higher saturation limit for the 8-bit temperature code provided to the color system before it is used for polynomial computations. 000 = CODETEMPShutdown 001 = 100 010 = 120 011 = 140 100 = 160 101 = 180 110 = 200 111 = 220 DS954F2 CS1630/31 6.41 Configuration 60 (Config60) – Address 92 7 - 6 PLC 5 - Number Name [7] - [6] PLC [5] - [4:2] 4 CS_DELAY2 3 CS_DELAY1 2 CS_DELAY0 1 - 0 - Description Reserved Configures the power line calibration (PLC) mode. 0 = Enable 1 = Disable Reserved Configures the ISense comparator delay and board delays incurred through FET switching T1comp. Switching time T1comp can be set from 0ns to 350ns in CS_DELAY[2:0] steps of 50ns. T1 comp = CS_DELAY[2:0] 50ns [1:0] - Reserved 6.42 Configuration 61 (Config61) – Address 93 7 DITNODIM 6 DITLEVEL1 5 DITLEVEL0 Number Name [7] DITNODIM [6:5] 3 - 2 - 1 - 0 - Description Configures dithering, if enabled, to work in No-dimmer mode only. 0 = Dithering works in all modes 1 = Dithering works in No-dimmer mode only Configures the second stage dithering level based on the percentage of variation on the ISense DAC reference setting. 00 = 1.3% DITLEVEL[1:0] 01 = 2.9% 10 = 6% 11 = 12.3% [4] DITCHAN [3:0] - DS954F2 4 DITCHAN Selects the channel for less dithering for which the nominal dither level, set using bits DITLEVEL[1:0], is attenuated by the amount set by bits DITATT[1:0]. 0 = Channel 1 1 = Channel 2 Reserved 49 CS1630/31 6.43 Configuration 62 (Config62) – Address 94 7 CH2_OFF2 Number [7:5] 6 CH2_OFF1 5 CH2_OFF0 4 CH1_OFF2 3 CH1_OFF1 Name 2 CH1_OFF0 1 BST_LLP1 0 BST_LLP0 Description Sets fixed offset delay for ZCD comparator and other path delays in order to get correct T2 measurements for channel 2. Adjusting CH2_OFF[2:0] correctly CH2_OFF[2:0] is necessary to achieve accurate and predictable output currents across the entire dimming range.The offset delay is given by: CH2_OFF[2:0] 50ns [4:2] Sets fixed offset delay for ZCD comparator and other path delays in order to get correct T2 measurements for channel 1. Adjusting CH1_OFF[2:0] correctly is necessary to achieve accurate and predictable output currents across the CH1_OFF[2:0] entire dimming range. The offset delay is given by: CH1_OFF[2:0] 50ns [1:0] Sets the minimum value VLLPMin(th) by which the boost output voltage needs to be below the AC line voltage to trigger an LLP fault. 00 = 80V for 120V applications; 160V for 230V applications BST_LLP[1:0] 01 = 40V for 120V applications; 80V for 230V applications 10 = 20V for 120V applications; 40V for 230V applications 11 = 10V for 120V applications; 20V for 230V applications 6.44 CRC Tag (CRC_TAG) – Address 102 7 6 5 4 3 2 1 0 27 26 25 24 23 22 21 20 CRC Tag register used by the communication system. To activate the use of this register the CRC bit must be programmed to ‘1’ (see "Configuration 38 (Config38) – Address 70" on page 39). The correct CRC value is obtained by computing the CRC for all the registers from address 0 through 95. This includes all the reserved settings which have been factory programmed. 50 DS954F2 CS1630/31 6.45 Channel 1 Color Calibration 3A (CH1_CAL3A) – Address 119 7 SET_3A 6 - Number 5 4 3 2 1 0 CH1_CAL3A5 CH1_CAL3A4 CH1_CAL3A3 CH1_CAL3A2 CH1_CAL3A1 CH1_CAL3A0 Name Description [7] SET_3A [6] - [5:0] Configures the color control system to use the color calibration values in memory tag 3A. 0 = Disables the use of memory tag 3A 1 = Enables the use of memory tag 3A Reserved Channel 1 color control system calibration value that scales the current of channel 1 within ±15%. The value is a two’s complement integer in the range CH1_CAL3A[5:0] of -32CH1_CAL3A[5:0]31. The calibration current gain is given by: 1 + CH1_CAL3A[5:0] 0.00488 6.46 Channel 2 Color Calibration 3A (CH2_CAL3A) – Address 120 7 - 6 - 5 4 3 2 1 0 CH2_CAL3A5 CH2_CAL3A4 CH2_CAL3A3 CH2_CAL3A2 CH2_CAL3A1 CH2_CAL3A0 Number Name [7:6] - [5:0] Description Reserved Channel 2 color control system calibration value that scales the current of channel 2 within ±15%. The value is a two’s complement integer in the range CH2_CAL3A[5:0] of -32CH2_CAL3A[5:0]31. The calibration current gain is given by: 1 + CH2_CAL3A[5:0] 0.00488 6.47 CRC Memory Tag 3A (CRC_MTAG3A) – Address 121 7 6 5 4 3 2 1 0 27 26 25 24 23 22 21 20 CRC Memory Tag 3A register used by the color control system. To activate the use of this register the SET_3A bit must be programmed to ‘1’ (see "Channel 1 Color Calibration 3A (CH1_CAL3A) – Address 119" on page 51). The CRC value is obtained by computing the CRC value for the registers at address 119 and 120. DS954F2 51 CS1630/31 6.48 Channel 1 Color Calibration 3B (CH1_CAL3B) – Address 122 7 SET_3B 6 - Number 5 4 3 2 1 0 CH1_CAL3B5 CH1_CAL3B4 CH1_CAL3B3 CH1_CAL3B2 CH1_CAL3B1 CH1_CAL3B0 Name Description [7] SET_3B [6] - [5:0] Configures the color control system to use the color calibration values in memory tag 3B. 0 = Disables the use of memory tag 3B 1 = Enables the use of memory tag 3B (Takes priority over SET_3A=1) Reserved Channel 1 color control system calibration value that scales the current of channel 1 within ±15%. The value is a two’s complement integer in the range CH1_CAL3B[5:0] of -32CH1_CAL3B[5:0]31. The calibration current gain is given by: 1 + CH1_CAL3B[5:0] 0.00488 6.49 Channel 2 Color Calibration 3B (CH2_CAL3B) – Address 123 7 - 6 - 5 4 3 2 1 0 CH2_CAL3B5 CH2_CAL3B4 CH2_CAL3B3 CH2_CAL3B2 CH2_CAL3B1 CH2_CAL3B0 Number Name [7:6] - [5:0] Description Reserved Channel 2 color control system calibration value that scales the current of channel 2 within ±15%. The value is a two’s complement integer in the range of -32CH2_CAL3B[5:0]31. The calibration current gain is given by: CH2_CAL3B[5:0] 1 + CH2_CAL3B[5:0] 0.00488 6.50 CRC Memory Tag 3B(CRC_MTAG3B) – Address 124 7 27 6 2 6 5 2 5 4 2 4 3 2 3 2 2 2 1 2 1 0 20 CRC Memory Tag 3B register used by the color control system. To activate the use of this register the SET_3B bit must be programmed to ‘1’ (see "Channel 1 Color Calibration 3B (CH1_CAL3B) – Address 122" on page 52). The CRC value is obtained by computing the CRC value for the registers at address 122 and 123. 52 DS954F2 CS1630/31 6.51 Channel 1 Color Calibration 3C (CH1_CAL3C) – Address 125 7 SET_3C 6 - 5 4 3 2 1 0 CH1_CAL3C5 CH1_CAL3C4 CH1_CAL3C3 CH1_CAL3C2 CH1_CAL3C1 CH1_CAL3C0 Number Name [7] SET_3C [6] - [5:0] Description Configures the color control system to use the color calibration values in memory tag 3C. 0 = Disables the use of memory tag 3C 1 = Enables the use of memory tag 3C (Takes priority over SET_3B=1) Reserved Channel 1 color control system calibration value that scales the current of channel 1 within ±15%. The value is a two’s complement integer in the range CH1_CAL3C[5:0] of -32CH1_CAL3C[5:0]31. The calibration current gain is given by: 1 + CH1_CAL3C[5:0] 0.00488 6.52 Channel 2 Color Calibration 3C (CH2_CAL3C) – Address 126 7 - 6 - 5 4 3 2 1 0 CH2_CAL3C5 CH2_CAL3C4 CH2_CAL3C3 CH2_CAL3C2 CH2_CAL3C1 CH2_CAL3C0 Number Name [7:6] - [5:0] Description Reserved Channel 2 color control system calibration value that scales the current of channel 2 within ±15%. The value is a two’s complement integer in the range CH2_CAL3C[5:0] of -32CH2_CAL3C[5:0]31. The calibration current gain is given by: 1 + CH2_CAL3C[5:0] 0.00488 6.53 CRC Memory Tag 3C (CRC_MTAG3C) – Address 127 7 6 5 4 3 2 1 0 27 26 25 24 23 22 21 20 CRC Memory Tag 3C register used by the color control system. To activate the use of this register, the SET_3C bit must be programmed to ‘1’ (see "Channel 1 Color Calibration 3C (CH1_CAL3C) – Address 125" on page 53). The CRC value is obtained by computing the CRC value for the registers at address 125 and 126. DS954F2 53 CS1630/31 7. PACKAGE DRAWING 16 SOICN (150 MIL BODY WITH EXPOSED PAD) mm MIN NOM MAX MIN NOM MAX A -- -- 1.75 -- -- 0.069 A1 0.10 -- 0.25 0.004 -- 0.010 b 0.31 -- 0.51 0.012 -- 0.020 c 0.10 -- 0.25 0.004 -- 0.010 D D1 9.90BSC 4.95 5.25 0.195 0.201 E 6.00BSC 0.236BSC 3.90BSC 0.154BSC 2.35 e 54 5.10 0.390BSC E1 E2 1. 2. 3. 4. inch Dimension 2.50 2.65 0.093 1.27BSC 0.098 0.207 0.104 0.05BSC L 0.40 -- 1.27 0.016 -- 0.050 Θ 0° -- 8° 0° -- 8° aaa 0.10 0.004 bbb 0.25 0.010 ddd 0.25 0.010 Controlling dimensions are in millimeters. Dimensions and tolerances per ASME Y14.5M. This drawing conforms to JEDEC outline MS-012, variation AC for standard 16 SOICN narrow body. Recommended reflow profile is per JEDEC/IPC J-STD-020. DS954F2 CS1630/31 8. ORDERING INFORMATION Ordering Number Container CS1630-FSZ Bulk CS1630-FSZR Tape & Reel CS1631-FSZ Bulk CS1631-FSZ Tape & Reel AC Line Voltage Temperature Package Description 120VAC -40°C to +125°C 16-lead SOICN, Lead (Pb) Free 230VAC -40°C to +125°C 16-lead SOICN, Lead (Pb) Free 9. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION Model Number Peak Reflow Temp MSL Ratinga Max Floor Lifeb CS1630-FSZ 260°C 3 7 Days CS1631-FSZ 260°C 3 7 Days a. MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. b. Stored at 30°C, 60% relative humidity. DS954F2 55 CS1630/31 10.REVISION HISTORY Revision Date Changes PP1 OCT 2011 Edited for content PP2 JAN 2012 Edited for clarity and corrected typographical errors PP3 MAY 2012 Edited for content PP4 MAY 2012 Corrected typographical errors F1 MAY 2012 Corrected typographical errors F2 DEC 2012 Edited context for clarity Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find one nearest you go to http://www.cirrus.com IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. 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Use of the formulas, equations, calculations, graphs, and/or other design guide information is at your sole discretion and does not guarantee any specific results or performance. The formulas, equations, graphs, and/or other design guide information are provided as a reference guide only and are intended to assist but not to be solely relied upon for design work, design calculations, or other purposes. Cirrus Logic makes no representations or warranties concerning the formulas, equations, graphs, and/or other design guide information. Cirrus Logic, Cirrus, the Cirrus Logic logo designs, EXL Core, the EXL Core logo design, TruDim, and the TruDim logo design are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. I2C is a trademark of Philips Semiconductor. 56 DS954F2