ETC DM4M32SJ-15L

Enhanced
Memory Systems Inc.
Features
DM4M32SJ
4Mb x 32 Enhanced DRAM SIMM
Product Specification
Architecture
The DM4M32SJ achieves
4Mb x 32 density by mounting
32 4M x 1 EDRAMs, packaged
in 28-pin plastic SOJ packages
on both sides of the multilayer substrate. Four buffers
have been added to reduce the
loading on the address and
control lines. The buffers have
balanced output current levels
and current limiting resistors.
These offer low ground
Description
bounce, minimal undershoot,
and controlled fall times.
The Enhanced Memory Systems 16MB EDRAM SIMM module
The EDRAM memory
provides a single memory module solution for the main memory or
module
architecture is very
local memory of fast PCs, workstations, servers, and other high
similar
to
a
standard
16MB
DRAM
module
with
the addition of an
performance systems. Due to its fast 12ns cache row register, the
integrated
cache
and
on-chip
control
which
allows
it to operate much
EDRAM memory module supports zero-wait-state burst read
like
a
page
mode
or
static
column
DRAM.
operations at up to 66MHz bus rates in a non-interleave configuration
The EDRAM's SRAM cache is integrated into the DRAM array as
and >100MHz bus rates with a two-way interleave configuration.
tightly coupled row registers. Memory reads always occur from the
On-chip write posting and fast page mode operation supports
cache row register. When the on-chip comparator detects a page hit,
12ns write and burst write operations. On a cache miss, the fast
DRAM array reloads the entire 8Kbyte cache over an 8Kbyte-wide bus only the SRAM is accessed and data is available in 12ns from column
in 18ns for an effective bandwidth of 454 Gbytes/sec. This means very address. When a page read miss is detected, the entire new DRAM row
is updated into the cache and data is available at the output all within
low latency and fewer wait states on a cache miss than a nona single 30ns access. Subsequent reads within the page (burst reads,
integrated cache/DRAM solution. The JEDEC compatible SIMM
local instructions, or data) will continue at 12ns cycle time. Since reads
configuration allows a single memory controller to be designed to
support either JEDEC slow DRAMs or high speed EDRAMs to provide occur from the SRAM cache, DRAM precharge can occur simultaneously
without degrading performance. The on-chip refresh counter with
a simple upgrade path to higher system performance.
independent refresh bus allows the EDRAM to
be refreshed during cache reads.
DM4M32SJ Functional Diagram
Memory writes are internally posted in
12ns
and directed to the DRAM array. During
A
0-10
Column
CAL 0-3
Add
Column Decoder
a
write
hit, the on-chip address comparator
Latch
activates a parallel write path to the SRAM
2048 X 32 Cache (Row Register)
11-Bit
cache to maintain coherency. The EDRAM
Comp
Sense Amps
delivers 12ns cycle page mode memory writes.
G
& Column Write Select
I/O
Last
Memory writes do not affect the contents of
Control
Row
DQ 0-31
and
Read
A 0-10
the cache row register except during a cache
Data
Add
Latches
Latch
hit.
S
By integrating the SRAM cache as row
Memory
Row
Array
WE
Add
registers in the DRAM array and keeping the
16Mbyte
Latch
on-chip control simple, the EDRAM is able to
provide superior performance over standard
V
slow DRAMs.
A 0-9
C
Integrated 2,048 x 32 SRAM Cache Row Register Allows 12ns
Access Random Reads Within the Page
■ Interleaved SRAM Cache for 8ns Burst Reads
■ 30ns DRAM Array for Fast Random Access to Any Page
■ Ultra-Fast Integrated 8Kbyte-Wide DRAM to Cache Bus
for 454-Gbyte/sec Cache Fill Bandwidth
■ On-Chip Write Posting and Fast Page Mode Operation Allows
12ns Writes and Burst Writes
■ On-Board Address and Control Buffering
■ Low Power Self Refresh Mode Option
Row Decoder
■
CC
F
W/R
RE 0,2
Row Add
and
Refresh
Control
1-36
Refresh
Counter
VSS
PD
PD16M
The information contained herein is subject to change without notice. Enhanced reserves the right
to change or discontinue this product without notice.
© 1996 Enhanced Memory Systems Inc., 1850 Ramtron Drive, Colorado Springs, CO 80921
Telephone (800) 545-DRAM; Fax (719) 488-9095; http://www.csn.net/ramtron/enhanced
38-2110-002
Functional Description
DRAM Read Miss
If a DRAM read request is initiated by clocking /RE with W/R
The EDRAM is designed to provide optimum memory
low and /F and /CAL high, the EDRAM will compare the new row
performance with high speed microprocessors. As a result, it is
address to the LRR address latch (an 11-bit latch loaded on each
possible to perform simultaneous operations to the DRAM and
SRAM cache sections of the EDRAM. This feature allows the EDRAM /RE active read cycle). If the row address does not match the LRR,
to hide precharge and refresh operation during SRAM cache reads the requested data is not in SRAM cache and a new row must be
fetched from the DRAM. The EDRAM will load the new row data
and maximize SRAM cache hit rate by maintaining valid cache
contents during write operations even if data is written to another
into the SRAM cache and update the LRR latch. The data at the
memory page. These new functions, in conjunction with the faster specified column address is available at the output pins at the
basic DRAM and cache speeds of the EDRAM, minimize processor greater of times tRAC, tAC, and tGQV. It is possible to bring /RE high
wait states.
after time tRE since the new row data is safely latched into SRAM
cache. This allows the EDRAM to precharge the DRAM array while
EDRAM Basic Operating Modes
data is accessed from SRAM cache. It is possible to access
The EDRAM operating modes are specified in the table below. additional SRAM cache locations by providing new column
addresses to the multiplex address inputs. New data is available at
Hit and Miss Terminology
the output at time tAC after each column address change in static
In this datasheet, “hit” and “miss” always refer to a hit or miss column mode. During read cycles, it is possible to operate in either
to the page of data contained in the SRAM cache row register. This static column mode with /CAL=high or page mode with /CAL
is always equal to the contents of the last row that was read from
clocked to latch the column address. In page mode, data valid
(as modified by any write hit data). Writing to a new page does not time is determined by either tAC or tCQV.
cause the cache to be modified.
DRAM Write Hit
DRAM Read Hit
If a DRAM write request is initiated by clocking /RE while W/R
If a DRAM read request is initiated by clocking /RE with W/R
and /F are high, the EDRAM will compare the new row address to
low and /F and /CAL high, the EDRAM will compare the new row
the LRR address latch (an 11-bit address latch loaded on each /RE
address to the last row read address latch (LRR; an 11-bit latch
active read). If the row address matches, the EDRAM will write data
loaded on each /RE active read cycle). If the row address matches to both the DRAM array and selected SRAM cache simultaneously
the LRR, the requested data is already in the SRAM cache and no
to maintain coherency. The write address and data are posted to
DRAM memory reference is initiated. The data specified by the
the DRAM as soon as the column address is latched by bringing
column address is available at the output pins at the greater of
/CAL low and the write data is latched by bringing /WE low (both
times tAC or tGQV. Since no DRAM activity is initiated, /RE can be
/CAL and /WE must be high when initiating the write cycle with the
brought high after time tRE1, and a shorter precharge time, tRP1, is falling edge of /RE). The write address and data can be latched very
required. It is possible to access additional SRAM cache locations
quickly after the fall of /RE (tRAH + tASC for the column address and
by providing new column addresses to the multiplex address
tDS for the data). During a write burst sequence, the second write
inputs. New data is available at the output at time tAC after each
data can be posted at time tRSW after /RE. Subsequent writes within
column address change in static column mode. During read cycles, a page can occur with write cycle time t . With /G enabled and
PC
it is possible to operate in either static column mode with
/WE disabled, it is possible to perform cache read operations while
/CAL=high or page mode with /CAL clocked to latch the column
the /RE is activated in write hit mode. This allows read-modifyaddress. In page mode, data valid time is determined by either tAC write, write-verify, or random read-write sequences within the page
or tCQV.
with 12ns cycle times (the first read cannot complete until after
time tRAC2). At the end of a write sequence (after /CAL and /WE are
brought high and tRE is satisfied), /RE can be brought high to
EDRAM Basic Operating Modes
Function
/S
/RE
W/R
/F
/CAL
/WE
A0-10
Read Hit
L
↓
L
H
H
X
Row = LRR
No DRAM Reference, Data in Cache
Read Miss
L
↓
L
H
H
X
Row ≠ LRR
DRAM Row to Cache
Write Hit
L
↓
H
H
H
H
Row = LRR
Write to DRAM and Cache, Reads Enabled
Write Miss
L
↓
H
H
H
H
Row ≠ LRR
Write to DRAM, Cache Not Updated, Reads Disabled
Internal Refresh
X
↓
X
L
X
X
X
Cache Reads Enabled
Low Power Standby
H
H
X
X
H
H
X
Standby Current
Unallowed Mode
H
L
X
H
X
X
X
Unallowed Mode (Except -L Option)
Low Power Self
Refresh Option
H
↓
X
H
L
H
X
Standby Current, Internal Refresh Clock
H = High; L = Low; X = Don’t Care; ↓ = High-to-Low Transition; LRR = Last Row Read
1-106
Comment
On-Chip SRAM Interleave
The DM4M32 has an on-chip interleave of its SRAM cache
which allows 8ns random accesses (tAC1) for up to three data
words (burst reads) following an initial read access (hit or miss).
The SRAM cache is integrated into the DRAM arrays in a 512 x 128
organization. It is converted into a 2K x 32 page organization by
using an on-chip address multiplexer to select one of four 32-bit
words to the output pins DQ0-31 (as shown below). The specific
DRAM Write Miss
If a DRAM write request is initiated by clocking /RE while W/R word selected to the output is determined by column addresses Ao
and A1. System operation is consistent with the standard
and /F are high, the EDRAM will compare the new row address to
“Functional Description” and timing diagrams shown in this
the LRR address latch (an 11-bit latch loaded on each /RE active
specification. See the note in the read timing diagrams and
read cycle). If the row address does not match, the EDRAM will
“Switching Characteristics” chart for the faster access and data
write data to the DRAM array only and contents of the current
cache is not modified. The write address and data are posted to the hold times.
DM4M32 Datapath Architecture
DRAM as soon as the column address is latched by bringing /CAL
low and the write data is latched by bringing /WE low (both /CAL
and /WE must be high when initiating the write cycle with the
32
Row Address
falling edge of /RE). The write address and data can be latched very
4M DRAM Arrays
A0-10
quickly after the fall of /RE (tRAH + tASC for the column address and
65,538 Bits
tDS for the data). During a write burst sequence, the second write
data can be posted at time tRSW after /RE. Subsequent writes within
32
a page can occur with write cycle time tPC. During a write miss
Column Address
2K SRAM Caches
A2-10
sequence, cache reads are inhibited and the output buffers are
disabled (independently of /G) until time tWRR after /RE goes high.
128 Bits
At the end of a write sequence (after /CAL and /WE are brought
high and tRE is satisfied), /RE can be brought high to precharge the
Column Address
4 to 1
memory. It is possible to perform cache reads concurrently with
A0,A1
Output Selector
the precharge. During write sequences, a write operation is not
32 Bits
performed unless both /CAL and /WE are low. As a result, /CAL can
be used as a byte write select in multi-chip systems. If /CAL is not
clocked on a write sequence, the memory will perform a /RE only
Q
refresh to the selected row and data will remain unmodified.
/RE Inactive Operation
Internal Refresh
It is possible to read data from the SRAM cache without
If /F is active (low) on the assertion of /RE, an internal refresh
clocking /RE. This option is desirable when the external control
cycle is executed. This cycle refreshes the row address supplied by
logic is capable of fast hit/miss comparison. In this case, the
an internal refresh counter. This counter is incremented at the end
controller can avoid the time required to perform row/column
of the cycle in preparation for the next /F refresh cycle. At least
multiplexing on hit cycles. This capability also allows the EDRAM to 1,024 /F cycles must be executed every 64ms. /F refresh cycles can
perform cache read operations during precharge and refresh
be hidden because cache memory can be read under column
cycles to minimize wait states. It is only necessary to select /S and
address control throughout the entire /F cycle. /F cycles are the
/G and provide the appropriate column address to read data as
only active cycles during which /S can be disabled.
shown in the table below. The row address of the SRAM cache
accessed without clocking /RE will be specified by the LRR address /CAL Before /RE Refresh (“/CAS Before /RAS”)
latch loaded during the last /RE active read cycle. To perform a
/CAL before /RE refresh, a special case of internal refresh, is
cache read in static column mode, /CAL is held high, and the cache discussed in the “Reduced Pin Count Operation” section below.
contents at the specified column address will be valid at time tAC
/RE Only Refresh Operation
after address is stable. To perform a cache read in page mode,
/CAL is clocked to latch the column address. The cache data is
Although /F refresh using the internal refresh counter is the
valid at time tAC after the column address is setup to /CAL.
recommended method of EDRAM refresh, it is possible to perform
an /RE only refresh using an externally supplied row address. /RE
refresh is performed by executing a write cycle (W/R and /F are
Function
/S
/G
/CAL
A0-10
high) where /CAL is not clocked. This is necessary so that the current
cache contents and LRR are not modified by the refresh operation.
Cache Read (Static Column)
L
L
H
Column Address
All combinations of addresses A0, A2 - A10 must be sequenced every
Cache Read (Page Mode)
L
L
↕
Column Address
64ms refresh period. A1 does not need to be cycled. Read refresh
cycles are not allowed because a DRAM refresh cycle does not occur
H = High; L = Low; X = Don’t Care; ↕ = Transitioning
when a read refresh address matches the LRR address latch.
precharge the memory. It is possible to perform cache reads
concurrently with precharge. During write sequences, a write
operation is not performed unless both /CAL and /WE are low. As a
result, the /CAL input can be used as a byte write select in multichip systems. If /CAL is not clocked on a write sequence, the
memory will perform a /RE only refresh to the selected row and
data will remain unmodified.
1-107
Low Power Self Refresh
When the low power, self-refresh option is specified when
ordering the EDRAM, the EDRAM enters this mode when /RE is
clocked while /S, W/R, /F, and /WE are high; and /CAL is low. In
this mode, the power is turned off to all I/O pins except /RE to
minimize chip power and an on-board refresh clock is enabled to
perform self-refresh cycles using the on-board refresh counter.
The EDRAM remains in this low power mode until /RE is brought
high again to terminate the mode. The EDRAM /RE input must
remain high for tRP2 following exit from self-refresh mode to allow
any on-going internal refresh to terminate prior to the next
memory operation.
Low Power Mode
The EDRAM enters its low power mode when /S is high. In this
mode, the internal DRAM circuitry is powered down to reduce
standby current to 34mA.
Initialization Cycles
A minimum of 10 initialization (start-up) cycles are required
before normal operation is guaranteed. A combination of eight /F
refresh cycles and two read cycles to different row addresses are
necessary to complete initialization. /RE must be high for 300ns
prior to initialization.
Unallowed Mode
Read, write, or /RE only refresh operations must not be
initiated to unselected memory banks by clocking /RE when /S is
high.
Reduced Pin Count Operation
It is possible to simplify the interface to the 16 MByte SIMM to
reduce the number of control lines. /REO and /RE2 could be tied
together externally to provide a single row enable. W/R and /G can
be tied together if reads are not performed during write hit cycles.
This external wiring simplifies the interface without any
performance impact.
Pin Descriptions
/F — Refresh
This input will initiate a DRAM refresh operation using the
internal refresh counter as an address source when it is low on the
low going edge of /RE.
/WE — Write Enable
This input controls the latching of write data on the input data
pins. A write operation is initiated when both /CAL and /WE are low.
/G — Output Enable
This input controls the gating of read data to the output data
pins during read operations.
/S — Chip Select
This input is used to power up the I/O and clock circuitry.
When /S is high, the EDRAM remains in its low power mode. /S
must remain active throughout any read or write operation. With
the exception of /F refresh cycles, /RE0,2 should never be clocked
when /S is inactive.
DQ0 -31 — Data Input/Output
These bidirectional pins are used to read and write data to the
EDRAM.
PD — Presence Detect
This signal is grounded to indicate the presence of SIMM
module in the socket.
PD16M — 16M Presence Detect
This signal is grounded to indicate the presence of a 16M
SIMM. A 4 or 8 MB SIMM has this pin open.
A0-10 — Multiplex Address
These inputs are used to specify the row and column
addresses of the EDRAM data. The 11-bit row address is latched on
the falling edge of /RE. The 11-bit column address can be specified
at any other time to select read data from the SRAM cache or to
specify the write column address during write cycles. A0,1 are used
to select one of four interleaved data words during read
operations.
/RE0, 2 — Row Enable
VCC Power Supply
These inputs are used to initiate DRAM read and write
These inputs are connected to the +5 volt power supply.
operations and latch a row address as well as the states of W/R and
/F. It is not necessary to clock /RE0, 1 to read data from the EDRAM VSS Ground
SRAM row registers. On read operations, /RE0, 1 can be brought
These inputs are connected to the power supply ground
high as soon as data is loaded into cache to allow early precharge. connection.
/REO controls Bytes 1 and 2. /RE2 controls Bytes 3 and 4.
/CAL0 -3 — Column Address Latch
These inputs are used to latch the column address and in
combination with /WE to trigger write operations. When /CAL is
high, the column address latch is transparent. When /CAL is low,
the column address is closed and the output of the latch contains
the address present while /CAL was high. /CAL can be toggled when
/RE is low or high. However, /CAL must be high during the high-tolow transition of /RE except for /F refresh cycles. /CAL 0-3 controls
Bytes 1-4 respectively.
W/R — Write/Read
This input along with /F specifies the type of DRAM operation
initiated on the low going edge of /RE. When /F is high, W/R
specifies either a write (logic high) or read operation (logic low).
1-108
Pinout
Pin No. Function
Organization
Pin No. Function
Organization
1
GND
Ground
37
+5 Volts
VCC
2
DQ0
Byte 1 I/O 1
38
GND
Ground
3
DQ18
Byte 3 I/O 1
39
GND
Ground
4
DQ1
Byte 1 I/O 2
40
CAL 0
Byte 1 Column Address Latch
5
DQ19
Byte 3 I/O 2
41
CAL 2
Byte 3 Column Address Latch
6
DQ2
Byte 1 I/O 3
42
CAL 3
Byte 4 Column Address Latch
7
DQ20
Byte 3 I/O 3
43
CAL 1
Byte 2 Column Address Latch
8
DQ3
Byte 1 I/O 4
44
RE0
Row Enable (Bytes 1, 2)
9
DQ21
Byte 3 I/O 4
45
NC
Not Connected
10
+5 Volts
VCC
46
PD16M
11
+5 Volts
VCC
47
WE
Write Enable
12
A0
Address
48
W/R
W/R Mode Control
13
A1
Address
49
DQ9
Byte 2 I/O 1
14
A2
Address
50
DQ27
Byte 4 I/O 1
15
A3
Address
51
DQ10
Byte 2 I/O 2
16
A4
Address
52
DQ28
Byte 4 I/O 2
17
A5
Address
53
DQ11
Byte 2 I/O 3
18
A6
Address
54
DQ29
Byte 4 I/O 3
19
A 10
Address
55
DQ12
Byte 2 I/O 4
20
DQ4
Byte 1 I/O 5
56
DQ30
Byte 4 I/O 4
21
DQ22
Byte 3 I/O 5
57
DQ13
Byte 2 I/O 5
22
DQ5
Byte 1 I/O 6
58
DQ31
Byte 4 I/O 5
23
DQ23
Byte 3 I/O 6
59
+5 Volts
VCC
24
DQ6
Byte 1 I/O 7
60
DQ32
Byte 4 I/O 6
25
DQ24
Byte 3 I/O 7
61
DQ14
Byte 2 I/O 6
26
DQ7
Byte 1 I/O 8
62
DQ33
Byte 4 I/O 7
27
DQ25
Byte 3 I/O 8
63
DQ15
Byte 2 I/O 7
28
A7
Address
64
DQ34
Byte 4 I/O 8
29
GND
Ground
65
DQ16
Byte 2 I/O 8
30
+5 Volts
VCC
66
+5 Volts
VCC
31
A8
Address
67
G
Output Enable
32
A9
Address
68
F
Refresh Mode Control
33
NC
Not Connected
69
S
Chip Select
34
RE2
Row Enable (Bytes 3, 4)
70
PD
35
GND
Ground
71
GND
Ground
36
GND
Ground
72
GND
Ground
1-109
Signal GND
Signal GND
Ground
Presence Detect
Buffer Diagram
Edge
Connecter
12
13
A0
A1
30
U32A4
19 A9B1
29
20 A9B2
27
22 A9B3
26
15
A2
A3
48
17
A4
A5
18
11 W/RB3
47
U33A1
2 A10B1
36
U33A3
13 /WEB1
46
3 A10B2
35
14 /WEB2
44
5 A10B3
43
6 A10B4
47
31
32
19
A8
A9
A10
/WE
33
16 /WEB3
32
17 /WEB4
30
U33A4
19 /FB1
36
U14A2
11 A2B1
U14A2
12 A2B2
U14A3
13 A2B3
U14A3
14 A3B1
26
23 /FB4
35
33
16 A3B2
47
U15A1
2 /SB1
32
17 A3B3
46
3 /SB2
37
30
U14A4
19 A4B1
29
20 A4B2
27
22 A4B3
47
U32A1
2 A5B1
46
3 A5B2
44
5 A5B3
41
68
36
35
U32A3
14 A8B1
33
16 A8B2
32
17 A8B3
47
U14A1
2 A0B1
37
44
U32A1
6 A6B1
U32A2
8 A6B2
U32A2
9 A6B3
U32A2
11 A7B1
U32A2
12 A7B2
U32A3
13 A7B3
38
28
9 W/RB2
12 W/RB4
40
A7
40
37
43
A6
U33A2
8 W/RB1
23 A9B4
69
16
W/R
41
38
38
14
Edge
Connecter
46
3 A0B2
44
5 A0B3
43
U14A1
6 A1B1
41
8 A1B2
40
9 A1B3
34
67
29
20 /FB2
27
22 /FB3
/F
/S
44
5 /SB3
43
6 /SB4
41
U15A2
8 /RE0B1
40
9 /RE0B2
38
11 /RE0B3
37
12 /RE0B4
36
U15A3
13 /RE2B1
/RE0
35
14 /RE2B2
33
16 /RE2B3
32
17 /RE2B4
/RE2
U14A4
/G
26
/GB
23
U15A4
40
43
41
42
/CAL0
/CAL0B
30
/CAL1
19
U15A4
/CAL1B
20
29
U15A4
/CAL2
27
U15A4
/CAL3
26
/CAL2B
22
/CAL3B
23
U14, 15, 32, 33 Pins 1, 4, 10, 21, 24, 25, 28, 34, 39, 45, 48 - Gnd.
U14, 15, 32, 33, Pins 7, 18, 31, 42, - Vcc
Note: Address and control buffers add minimum
of 1.7ns to maximum of 4.5ns to each signal path.
1-110
Interconnect Diagram — Byte 1
Edge
Connecter
J1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ7
2
4
6
8
20
22
24
26
DQ5
DQ6
+5V
DQ4
27
DQ3
DQ2
DQ1
Q
/CAL0B
/RE0B1
/RE0B2
+5V
VCC
VCC
VCC
VCC
VCC
VCC
1
29
39
35
36
38
71
72
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
70
46
PD
PD16M
C1
C2
C3
C4
C5
C6
C7
C8
1-111
C9
/RE
6
/CAL
16
6
/RE
/CAL
16
/RE
6
/CAL
16
6
/CAL
6
16
/RE
/CAL
16
/RE
EDRAM
EDRAM
EDRAM
/RE
/CAL
EDRAM
6
/RE
DM2200J
4Mb x 1
DM2200J
4Mb x 1
EDRAM
6
W/R
/WE
/F
/S
/G
DM2200J
4Mb x 1
EDRAM
/CAL
17
20
18
19
23
EDRAM
DM2200J
4Mb x 1
Q
EDRAM
/RE
W/RB1
/WEB1
/FB1
/SB1
/GB
DM2200J
4Mb x 1
6
U1
DM2200J
4Mb x 1
/CAL
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
16
Q
1
2
12
3
4
5
9
10
11
13
15
16
Q
DM2200J
4Mb x 1
U2
A0B1
A1B1
A2B1
A3B1
A4B1
A5B1
A6B1
A7B1
A8B1
A9B1
A10B1
10
11
30
37
59
66
Q
DM2200J
4Mb x 1
U3
27
D
26
U4
Q
D
27
27
D
26
VSS
VSS
VSS
U5
16
DQ0
26
U6
27
D
26
VCC
VCC
VCC
U7
27
D
26
U8
27
D
26
Q
D
26
Q
27
D
26
7
14
22
8
21
28
Interconnect Diagram — Byte 2
DQ14
DQ15
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
16
/CAL1B
/RE0B3
/RE0B4
+5V
10
11
30
37
59
66
VCC
VCC
VCC
VCC
VCC
VCC
1
29
39
35
36
38
71
72
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
70
46
PD
PD16M
C10
C11
C12
C13
C14
C15
C16
C17
1-112
C18
6
/RE
6
/CAL1
EDRAM
16
/RE
/CAL1
EDRAM
6
/RE
/CAL1
EDRAM
6
/CAL1
16
/RE
/CAL1
6
/RE
6
/CAL1
EDRAM
/RE
EDRAM
EDRAM
16
DM2200J
4Mb x 1
EDRAM
16
DM2200J
4Mb x 1
/RE
EDRAM
DM2200J
4Mb x 1
DM2200J
4Mb x 1
Q
D
Q
DM2200J
4Mb x 1
16
Q
DM2200J
4Mb x 1
16
Q
DM2200J
4Mb x 1
6
W/R
/WE
/F
/S
/G
DM2200J
4Mb x 1
U11
/CAL1
17
20
18
19
23
Q
D
27
U10
16
W/RB2
/WEB2
/FB2
/SB2
/GB
VSS
VSS
VSS
U9
/RE
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
VCC
VCC
VCC
6
1
2
12
3
4
5
9
10
11
13
15
/CAL1
A0B1
A1B1
A2B1
A3B1
A4B1
A5B1
A6B1
A7B1
A8B1
A9B2
A10B2
U26
U25
27
D
26
U27
27
D
26
+5V
U28
Q
D
DQ10
DQ9
26
A0
A1
A2
A3
A4
A5
A6
A7
A8
U29
27
Q
27
D
1
2
12
3
4
5
9
10
11
DQ11
A0B2
A1B2
A2B2
A3B2
A4B2
A5B2
A6B2
A7B2
A8B2
27
27
D
26
Q
DQ13
26
26
27
D
26
26
DQ12
49
51
53
55
57
61
63
65
DQ16
Edge
Connecter
J1
7
14
22
8
21
28
Interconnect Diagram — Byte 3
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ24
27
DQ23
DQ22
D
DQ20
Q
D
DM2200J
4Mb x 1
/CAL2B
/RE2B1
/RE2B2
+5V
1
29
39
35
36
38
71
72
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
70
46
PD
PD16M
C19
C20
C21
C22
C23
C24
C25
C26
1-113
C27
/RE
6
/CAL2
16
6
/RE
/CAL2
16
/RE
6
/CAL2
16
/RE
6
/CAL2
16
/RE
6
16
/CAL2
EDRAM
EDRAM
EDRAM
/RE
EDRAM
6
/RE
/CAL2
16
DM2200J
4Mb x 1
DM2200J
4Mb x 1
EDRAM
/RE
W/R
/WE
/F
/S
/G
DM2200J
4Mb x 1
6
17
20
18
19
23
EDRAM
DM2200J
4Mb x 1
EDRAM
/CAL2
W/RB3
/WEB3
/FB3
/SB3
/GB
DM2200J
4Mb x 1
DM2200J
4Mb x 1
EDRAM
/CAL2
DM2200J
4Mb x 1
16
U19
VSS
VSS
VSS
16
D
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
VCC
VCC
VCC
VCC
VCC
VCC
U24
U22
Q
D
Q
1
2
12
3
4
5
9
10
11
13
15
VCC
VCC
VCC
U23
U20
A0B2
A1B2
A2B2
A3B2
A4B2
A5B2
A6B2
A7B2
A8B2
A9B3
A10B3
27
U21
Q
D
27
27
D
26
27
27
+5V
27
Q
DQ19
DQ18
26
U16
U34
A1
A2
A3
A4
A5
A6
A7
A8
Q
DQ21
26
26
26
26
10
11
30
37
59
66
1
2
12
3
4
5
9
10
11
Q
D
26
A0B3
A1B3
A2B3
A3B3
A4B3
A5B3
A6B3
A7B3
A8B3
27
Q
D
26
6
3
5
7
9
21
23
24
25
DQ25
Edge
Connecter
J1
7
14
22
8
21
28
Interconnect Diagram — Byte 4
Edge
Connecter
J1
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ34
50
52
54
56
58
60
62
64
DQ32
DQ33
+5V
/CAL3B
/RE2B3
/RE2B4
+5V
1
29
39
35
36
38
71
72
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
70
46
PD
PD16M
C28
C29
C30
C31
C32
C33
C34
C35
1-114
C36
/RE
6
/CAL3
16
6
/RE
/CAL3
16
/CAL3
/RE
6
/RE
6
/CAL3
16
/RE
EDRAM
6
16
/CAL3
EDRAM
EDRAM
16
DM2200J
4Mb x 1
/CAL3
/RE
6
/RE
6
DM2200J
4Mb x 1
EDRAM
DM2200J
4Mb x 1
EDRAM
/CAL3
W/R
/WE
/F
/S
/G
EDRAM
DM2200J
4Mb x 1
EDRAM
/RE
17
20
18
19
23
DM2200J
4Mb x 1
6
W/RB4
/WEB4
/FB4
/SB4
/GB
DM2200J
4Mb x 1
EDRAM
16
DM2200J
4Mb x 1
16
Q
U36
/CAL3
U35
Q
DM2200J
4Mb x 1
16
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
VCC
VCC
VCC
VCC
VCC
VCC
Q
D
Q
Q
D
U18
Q
D
Q
1
2
12
3
4
5
9
10
11
13
15
10
11
30
37
59
66
VSS
VSS
VSS
U30
U17
A0B3
A1B3
A2B3
A3B3
A4B3
A5B3
A6B3
A7B3
A8B3
A9B4
A10B4
VCC
VCC
VCC
U12
27
D
26
U13
U31
27
27
D
26
27
27
D
DQ28
DQ27
26
27
D
DQ30
DQ29
26
27
Q
DQ31
26
26
26
27
D
26
7
14
22
8
21
28
AC Test Load and Waveforms
Load Circuit
Input Waveforms
5.0V
VIH
R1 = 828Ω
VIH
Output
R 2 = 295 Ω
C L = 50pf
GND
VIL
VIL
≤ 5ns
Absolute Maximum Ratings
≤ 5ns
Capacitance
(Beyond Which Permanent Damage Could Result)
Description
Ratings
Description
Max
Input Voltage (VIN )
- 1 ~ 7v
Input Capacitance
29pf
A 0-10
Output Voltage (VOUT )
- 1 ~ 7v
Input Capacitance
39pf
/RE 0, /RE 2, W/R, /WE, /F, /S
Power Supply Voltage (VCC )
- 1 ~ 7v
Input Capacitance
19pf
Ambient Operating Temperature (TA )
0 ~ 70°C
/G, /CAL 0-3
Input/Output Capacitance
18pf
DQ
-55 ~ 150°C
Storage Temperature (TS )
Static Discharge Voltage
(Per MIL-STD-883 Method 3015)
Class 1
Short Circuit O/P Current (I OUT )
50mA*
Pins
0-31
Electrical Characteristics
Symbol
Parameters
Min
Max
VCC
Supply Voltage
4.75V
5.25V
VIH
Input High Voltage
2.4V
6.5V
V IL
Input Low Voltage
-1.0V
0.8V
VOH
Output High Level
2.4V
VOL
Output Low Level
I i(L)
Input Leakage Current
I O(L)
Output Leakage Current
Symbol
Operating Current
Test Conditions
All Voltages Referenced to VSS
IOUT = - 5mA
0.4V
IOUT = 4.2mA
40µA
40µA
OV ≤ V IN ≤ 6.5V, All Other Pins Not Under Test = 0V
20µA
20µA
OV ≤ V IN , OV ≤ VOUT ≤ 5.5V
33MHz Typ (1) -12 Max
-15 Max
Test Condition
Notes
ICC1
Random Read
3840mA
7520mA
7520mA
/RE, /CAL, /G and Addresses Cycling: tC = tC Minimum
2, 3
ICC2
Fast Page Mode Read
2400mA
4960mA
4960mA
/CAL, /G and Addresses Cycling: tPC = tPC Minimum
2, 4
ICC3
Static Column Read
2080mA
3840mA
3840mA
/G and Addresses Cycling: t SC = t SC Minimum
2, 4
ICC4
Random Write
4640mA
6400mA
6400mA
/RE, /CAL, /WE and Addresses Cycling: t C = t C Minimum
2, 3
ICC5
Fast Page Mode Write
1920mA
4640mA
4640mA
/CAL, /WE and Addresses Cycling: tPC = tPC Minimum
2, 4
ICC6
Standby
36mA
36mA
36mA
ICC7
Self-Refresh (-L Option)
6.4mA
6.4mA
6.4mA
All Control Inputs Stable ≥ VCC - 0.2V, Outputs Driven
/S, /F, W/R, /WE and A 0-10 at ≥ VCC - 0.2V,
/RE and /CAL at < V SS + 0.2V, I/O Option
ICCT
Average Typical
Operating Current
1280mA
1280mA
1280mA
See “Estimating EDRAM Operating Power” Application Note
1
(1) “33MHz Typ” refers to worst case ICC expected in a system operating with a 33MHz memory bus. In this typical example, page mode and random reads refers to page burst hits and
misses. Writes are two clock cycle random and page mode writes. See power applications note for further details. This parameter is not 100% tested or guaranteed.
(2) ICC is dependent on cycle rates and is measured with CMOS levels and the outputs open.
(3) ICC is measured with a maximum of one address change while /RE = VIL.
(4) ICC is measured with a maximum of one address change while /CAL = VIH.
1-115
Switching Characteristics
Vcc = 5V + 5%, TA = 0 - 70oC, CL = 50pf
Note: These parameters do not include address and control buffer delays. See page 1-110 for derating factor.
-12
Symbol
tAC(1)
Description
Min
Column Address Access Time for Addresses A2-10
(1)
tAC1
Column Address Access Time for Addresses A0 and A1
tACH
Column Address Valid to /CAL Inactive (Write Cycle)
tAQX
-15
Max
Min
Max
Units
12
15
ns
8
8
ns
12
15
ns
Column Address Change to Output Data Invalid for Addresses A0-8
5
5
ns
tAQX1
Column Address Change to Output Data Invalid for Addresses A9 and A10
1
1
ns
tASC
Column Address Setup Time
5
5
ns
tASR
Row Address Setup Time
5
5
ns
tC
Row Enable Cycle Time
55
65
ns
tC1
Row Enable Cycle Time, Cache Hit (Row=LRR), Read Cycle Only
20
25
ns
tCA
Address Cycle Time (Cache Hits)
12
15
ns
tCAE
Column Address Latch Active Time
5
6
ns
tCAH
Column Address Hold Time
0
0
ns
tCH
Column Address Latch High Time (Latch Transparent)
5
5
ns
tCHR
/CAL Inactive Lead Time to /RE Inactive (Write Cycles Only)
-2
-2
ns
tCHW
Column Address Latch High to Write Enable Low (Multiple Writes)
0
0
ns
tCQV
Column Address Latch High to Data Valid
tCQX
Column Address Latch Inactive to Data Invalid for Addresses A0-8
5
5
ns
tCQX1
Column Address Latch Inactive to Data Invalid for Addresses A9 and A10
1
1
ns
tCRP
Column Address Latch Setup Time to Row Enable
5
5
ns
tCWL
/WE Low to /CAL Inactive
5
5
ns
tDH
Data Input Hold Time
0
0
ns
tDS
Data Input Setup Time
5
5
ns
tGQV(1)
(2,3)
15
Output Enable Access Time
17
5
ns
5
ns
tGQX
Output Enable to Output Drive Time
0
5
0
5
ns
tGQZ(4,5)
Output Turn-Off Delay From Output Disabled (/G↑)
0
5
0
5
ns
tMH
/F and W/R Mode Select Hold Time
0
0
ns
tMSU
/F and W/R Mode Select Setup Time
5
5
ns
tNRH
/CAL, /G, and /WE Hold Time For /RE-Only Refresh
0
0
ns
tNRS
/CAL, /G, and /WE Setup Time For /RE-Only Refresh
5
5
ns
tPC
Column Address Latch Cycle Time
12
15
ns
(1)
tRAC
Row Enable Access Time, On a Cache Miss
30
35
ns
tRAC1
Row Enable Access Time, On a Cache Hit (Limit Becomes tAC)
15
17
ns
tRAC2(1,6)
Row Enable Access Time for a Cache Write Hit
30
35
ns
tRAH
Row Address Hold Time
(1)
1
1-116
1.5
ns
Switching Characteristics (continued)
Vcc = 5V + 5%, TA = 0 - 70oC, CL = 50pf
Note: These parameters do not include address and control buffer delays. See page 1-110 for derating factor.
-12
Symbol
Description
tRE
Row Enable Active Time
tRE1
Row Enable Active Time, Cache Hit (Row=LRR) Read Cycle
tREF
Refresh Period
tRGX
Output Enable Don't Care From Row Enable (Write, Cache Miss), O/P Hi Z
tRQX1
Row Enable High to Output Turn-On After Write Miss
(7)
-15
Min
Max
Min
Max
30
100000
35
100000
8
10
64
64
tRP
Row Precharge Time
tRP1
Row Precharge Time, Cache Hit (Row=LRR) Read Cycle
tRP2
Row Precharge Time, Self-Refresh Mode
tRRH
Read Hold Time From Row Enable (Write Only)
tRSH
ms
ns
15
12
ns
ns
10
9
Units
ns
20
25
ns
8
10
ns
100
100
ns
0
0
ns
Last Write Address Latch to End of Write
12
15
ns
Row Enable to Column Address Latch Low For Second Write
35
40
ns
tRWL
Last Write Enable to End of Write
12
15
ns
tSC
Column Address Cycle Time
12
15
ns
tSHR
Select Hold From Row Enable
0
0
ns
RSW
tSQV
(1)
Chip Select Access Time
tSQX
(2,3)
Output Turn-On From Select Low
0
12
tSQZ
(4,5)
Output Turn-Off From Chip Select
0
8
tSSR
Select Setup Time to Row Enable
5
tT
Transition Time (Rise and Fall)
1
tWC
Write Enable Cycle Time
tWCH
12
15
ns
0
15
ns
0
10
ns
5
10
1
ns
10
ns
12
15
ns
Column Address Latch Low to Write Enable Inactive Time
5
5
ns
tWHR
Write Enable Hold After /RE
0
0
ns
tWI
Write Enable Inactive Time
5
5
ns
tWP
Write Enable Active Time
5
5
ns
(1)
Data Valid From Write Enable High
(2,5)
Data Output Turn-On From Write Enable High
0
12
(3,4)
tWQZ
Data Turn-Off From Write Enable Low
0
12
tWRP
Write Enable Setup Time to Row Enable
5
tWRR
Write to Read Recovery (Cache Miss)
tWQV
tWQX
12
1-117
ns
0
15
ns
0
15
ns
5
16
(1) VOUT Timing Reference Point at 1.5V
(2) Parameter Defines Time When Output is Enabled (Sourcing or Sinking Current) and is Not Referenced to VOH or VOL
(3) Minimum Specification is Referenced from VIH and Maximum Specification is Referenced from VIL on Input Control Signal
(4) Parameter Defines Time When Output Achieves Open-Circuit Condition and is Not Referenced to VOH or VOL
(5) Minimum Specification is Referenced from VIL and Maximum Specification is Referenced from VIH on Input Control Signal
(6) Access Parameter Applies When /CAL Has Not Been Asserted Prior to tRAC2
(7) For Back-to-Back /F Refreshes, tRP = 40ns. For Non-Consecutive /F Refreshes, tRP = 25ns and 32ns respectively.
15
ns
18
ns
/RE Inactive Cache Read Hit (Static Column Mode)
/RE0, 2
/F
W/R
A0-10
Column 1
Column 2
Column 3
t SC
t SC
t SC
Column 4
/CAL0-3
/WE
t AC
t AC
t AQX
t AQX
DQ0-31
Open
Data 1
t AC
t AC
t AQX
Data 2
Data 3
Data 4
t GQZ
t GQX
t GQV
/G
t SQX
t SQV
t SQZ
/S
Don’t Care or Indeterminate
NOTES: 1. Data accessed during /RE inactive read is from the row address specified during the last /RE active read cycle.
2. If column address 2, 3, or 4 modifies only address pin A0 or A1, then tAC becomes tAC1 for data 2, 3, and 4, and tAQX becomes
tAQX1 for data 1, 2, and 3.
1-118
/RE Inactive Cache Read Hit (Page Mode)
/RE0, 2
/F
W/R
t CAH
A0-10
Column 1
Column 2
t ASC
t CAH
t CAE
/CAL0-3
Row
t ASC
t CH
t PC
t CQV
/WE
t AC
t CQX
DQ0-31
Open
Data 1
Data 2
t AC
t GQX
t GQZ
t GQV
/G
t SQX
t SQV
t SQZ
/S
Don’t Care or Indeterminate
NOTES: 1. Data accessed during /RE inactive read is from the row address specified during the last /RE active read cycle.
2. If column address 2 modifies only address pin A0 or A1, then tAC becomes tAC1 for data 2 and tCQX becomes
tCQX1 for data 1.
1-119
/RE Active Cache Read Hit (Static Column Mode)
t C1
t RE1
/RE0, 2
t RP1
t MSU
t MH
/F
t MSU
t MH
W/R
t ASR
t RAH
A0-10
Row
Column 1
Column 2
Column 3
t SC
t SC
t SC
Column 4
t CRP
/CAL0-3
/WE
t AC
t RAC1
DQ0-31
t AC
t AQX
t AQX
Open
Data 1
t GQX
t AC
t AC
t AQX
Data 2
Data 3
Data 4
t GQZ
t GQV
/G
t SHR
t SSR
t SQZ
/S
Don’t Care or Indeterminate
NOTES: 1. If column address 2, 3, or 4 modifies only address pin A0 or A1, then tAC becomes tAC1 for data 2, 3, and 4, and tAQX becomes
tAQX1 for data 1, 2, and 3.
1-120
/RE Active Cache Read Hit (Page Mode)
t C1
t RE1
/RE0, 2
t RP1
t MSU
t MH
/F
t MSU
t MH
W/R
t ASR
t RAH
A0-10
Row
t CAH
Column 1
Column 2
t ASC
t CRP
t CAH
t CAE
/CAL0-3
Row
t ASC
t CH
t PC
t CQV
/WE
t AC
t CQX
t RAC1
DQ0-31
Open
Data 1
Data 2
t AC
t GQX
t GQZ
t GQV
/G
t SHR
t SSR
t SQZ
/S
Don’t Care or Indeterminate
NOTES: 1. If column address 2 modifies only address pin A0 or A1, then tAC becomes tAC1 for data 2 and tCQX becomes tCQX1 for data 1.
1-121
/RE Active Cache Read Miss (Static Column Mode)
/RE
tC
t RE
t RP
0, 2
t MSU
t MH
/F
t MSU
t MH
W/R
t ASR
t RAH
A 0-10
t SC
Row
Column 1
Column 2
Row
t CRP
/CAL0-3
t AQX
/WE
t AC
t AC
t RAC
DQ0-31
t AQX
Open
Data 1
Data 2
t GQX
t GQV
t GQZ
/G
t SHR
t SSR
t SQZ
/S
Don’t Care or Indeterminate
NOTES: 1. If column address 2 modifies only address pin A0 or A1, then tAC becomes tAC1 for data 2, and tAQX becomes tAQX1 for data 1.
1-122
/RE Active Cache Read Miss (Page Mode)
t C1
t RE1
/RE0, 2
t RP1
t MSU
t MH
/F
t MSU
t MH
W/R
t ASR
t RAH
A0-10
Row
t CAH
Column 1
Column 2
t ASC
t CRP
t CAH
t CAE
/CAL0-3
Row
t ASC
t CH
t PC
t CQV
/WE
t AC
t CQX
t RAC1
DQ0-31
Open
Data 1
Data 2
t AC
t GQX
t GQZ
t GQV
/G
t SHR
t SSR
t SQZ
/S
Don’t Care or Indeterminate
NOTES: 1. If column address 2 modifies only address pin A0 or A1, then tAC becomes tAC1 for data 2 and tCQX becomes tCQX1 for data 1.
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Burst Write (Hit or Miss) Followed By /RE Inactive Cache Reads
t RE
/RE0, 2
t MSU
t RP
t MH
t CHR
/F
t MSU
t MH
t MH
W/R
t ASR
t RAH
A 0-10
Row
t CAH
t RSW
Column 1
Column 2
t ACH
t ACH
A 0 - A 10
t ASC
t CAH
t CAE
t CRP
/CAL0-3
t WCH
t WRP
t RSH
t CWL
t CHW
DQ0-31
Open
t CWL
t WCH
t RRH
t WP
/WE
t DS
t CAE
t CH
t PC
t WP
t WHR
Column n
t WC
t DH
t WI
t RWL
t DH
t DS
Data 1
Data 2
t RQX1
tGQX
Cache (Column n)
t WRR
t AC
t GQV
/G
t SSR
/S
Don’t Care or Indeterminate
NOTES: 1. /G becomes a don’t care after tRGX during a write miss.
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Page Read/Write During Write Hit Cycle (Can Include Read-Modify-Write)
tC
t RE
/RE0, 2
t RP
t MSU
t CHR
t MH
/F
t MSU
t MH
W/R
t ASR
t RAH
A0-10
Row
Column 1
t CRP
t AC
t CAH
Column 2
t ACH
t ASC
Column 3
t RSH
t CAE
/CAL0-3
t WCH
t CQV
t CWL
t WRP
/WE
t WHR
t RAC2
t AQX
t RWL
t AC
t CQX
DQ0-31
t RRH
t WP
t WQV
Read Data
Write Data
Read Data
t DH
t WQX
t DS
t GQX
t GQZ
t GQZ
/G
t GQV
t GQV
t SSR
/S
Don’t Care or Indeterminate
NOTES: 1. If column address 2 modifies only address pin A0 or A1, then tAQX becomes tAQX1.
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/F Refresh Cycle
t RE
/RE0, 2
t MSU
t RP
t MH
/F
Don’t Care or Indeterminate
NOTES: 1. During /F refresh cycles, the status of W/R, /WE, A0-10, /CAL, /S, and /G is a don’t care.
2. /RE inactive cache reads may be performed in parallel with /F refresh cycles.
/RE-Only Refresh
t RE
/RE0, 2
tC
t RP
t ASR
t RAH
A 0-10
Row
t NRS
/CAL
0-3
t NRH
, /WE, /G
t MSU
t MH
W/R, /F
t SSR
t SHR
/S
Don’t Care or Indeterminate
NOTES: 1. All binary combinations of A0, A2-10 must be refreshed every 64ms interval. A1does not have to be cycled, but must remain valid
during row address setup and hold times.
2. /RE refresh is write cycle with no /CAL active cycle.
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Low Power Self-Refresh Mode Option
/RE0,2
t RP2
A 0-10
t MSU
t MH
/CAL
t MSU
/F, W/R,
/WE, /S
t MH
Don’t Care or Indeterminate
NOTES: 1. EDRAM self refreshes as long as /RE remains low. (Low Power Self Refresh part only).
2. When using the Low Power Self Refresh mode the following operations must be performed:
If row addresses are being refreshed in an evenly distributed manner over the refresh interval using /F refresh cycles,
then at least one /F refresh cycle must be performed immediately after exit from the Low Power Self Refesh Mode.
If row addresses are being refreshed in any other manner (/F burst or /RE distributed or burst), then all rows must
be refreshed immediately befor entry to and immediately after exit from the Low Power Self Refresh.
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Mechanical Data
DM4M32SJ 72 Pin Simm Module Configuration
4.595 (116.70)
Inches (mm)
Double
Side
Mounting
3.984 (101.19)
C
C
C
C
C
C
C
C
C
C
C
C
C
1.40
(35.56)
0.125
(3.17)
C
C
C
C
0.125
(3.18)
C
0.350
(8.89)
0.400
(10.16)
1
0.050 (1.27)
0.041 (1.04)
0.080 (2.03)
0.250 (6.35)
0.062 (1.57) RAD.
0.250 (6.35)
0.100
(2.54)
0.185
(4.70)
0.250 (6.35)
1.750 (44.45)
0.062 (1.57) RAD.
0.225
(5.71)
72
0.050
(1.27)
3.750 (95.25)
2.125 (53.98)
U1-13, U16-31, U34-36 — Enhanced DM2200J-XX, 4M x 1 EDRAMs, 300 Mil SOJ
U14-15, U32-33 — IDT 74 FCT 162244CT PA 16-bit Buffer/Line Driver or Equivalent
C1-13, C16-31, C34-36 — 0.22µF Chip Capacitor
C14-15, C32-33 — 4.7µF Chip Capacitor
Socket — Amp 822030-3 or Equivalent
Part Numbering System
DM4M32SJ -12L
Lower Power, Self Refresh Option
No Designator = 0 to 70oC (Commercial)
L= 0 to 70oC, Low Power Self Refresh Option
Access Time from Cache in Nanoseconds
12ns
15ns
Packaging System
J = 300 Mil, Plastic SOJ
Memory Module Configuration
S = SIMM
I/O Width (Including Parity)
32 = 32 Bits
Memory Depth (Megabits)
4M
Dynamic Memory
The information contained herein is subject to change without notice. Enhanced Memory Systems Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in
an Enhanced product, nor does it convey or imply any license under patent or other rights.
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