NSC DP83864AUT

September 2003
DP83864 Quad GigPHYTER™
10/100/1000 Ethernet Physical Layer
General Description
Features
The DP83864 is an extremely efficient full featured Quad ■ IEEE compliant 10BASE-T,100BASE-TX, 1000BASE-T
Physical Layer transceiver with integrated PMD sublayers ■ Adaptive equalization and Baseline Wander comp.
to support 10BASE-T, 100BASE-TX and 1000BASE-T
■ IEEE 802.3u Auto-Negotiation and Parallel Detection
Ethernet protocols.
– Fully auto-negotiates between 1000 Mb/s, 100 Mb/s,
The DP83864 contains four integrated ultra low power
and 10 Mb/s full duplex and half duplex devices
Gigabit Physical layers. It uses advanced 0.18 µm, 1.8 V
■
2.5
V/3.3 V MAC interfaces:
CMOS technology, fabricated at National’s South Portland,
Maine facilities.
– IEEE 802.3u MII with programmable bus ordering
– IEEE 802.3z GMII with programmable bus ordering
The DP83864 is designed for easy implementation of
10/100/1000 Mb/s Ethernet LANs. Each port interfaces
– Reduced GMII (RGMII) ver. 1.3
directly to Twisted Pair media via an external transformer.
– Serial GMII (SGMII)
This device interfaces directly to the MAC layer through the
■
LED support (Link10, Link100, Link1000, Activity and
IEEE 802.3u Standard Media Independent Interface (MII)
Duplex indicators); Direct drive LED’s thru management
or the IEEE 802.3z Gigabit Media Independent Interface
(GMII). It also supports the reduced pin count RGMII (12 ■ User Programmable Interrupt
pins per port) and serial GMII (8 pins per port).
■ A 25Mhz or 125Mhz oscillator as reference clock input
The DP83864 is a fourth generation of Gigabit Physical ■ PHY level CRC checking on received packets and PHY
layer product with field proven architecture and perforlevel CRC generation for test mode transmit packets
mance. Its robust performance ensures drop in replace■
292 BGA package
ment of existing 10/100M equipment with 10/100/1000M
■ Power dissipation approximately 1 W / port
Networking infrastructure.
■ 1.8 V CMOS (core & analog); 2.5 V (analog & I/O); 3.3 V
Applications
is optional for 3.3 V I/O voltage
The DP83864 fits applications in:
■ One management port per chip
■ Switches with 10/100/1000 Mb/s capable ports
■ Supports Auto-MDIX/polarity at all speeds
■ High speed uplink ports with redundancies (backbone)
■ One JTAG interface per chip
■ Servers with Quad Ethernet ports
ETHERNET
PHYSICAL LAYER
25 MHz or
125 MHz
Oscillator
GigPHYTER
™
Status
LED’s
Per Port
RJ-45
RJ-45
RJ-45
MAC
10BASE-T,
100BASE-TX,
or
1000BASE-T
RJ-45
ETHERNET
DP83864
10/100/1000 Mb/s
MAGNETICS
10/100/1000 Mb/s
MAGNETICS
Quad Port
MII
GMII
RGMII
SGMII
MAGNETICS
MAGNETICS
System Diagram
is a trademark of National Semiconductor Corporation.
© 2003 National Semiconductor Corporation
www.national.com
DP83864 Quad GigPHYTER™ 10/100/1000 Ethernet Physical Layer
ADVANCED INFORMATION
(Showing One Port)
COMBINED GMII, RGMII, SGMII, and MII INTERFACE
GTX_CLK
TX_ER
TX_EN
TXD[7:0]
TX_CLK
RX_CLK
COL
CRS
RX_ER
RX_DV
RXD[7:0]
MGMT INTERFACE
MDIO
MDC
DP83864
Block Diagram
µC MGMT
& PHY CNTRL
MUX/DMUX
MII
100BASE-TX Block
10BASE-T Block
MII
MII
100BASE-TX
PCS
10BASE-T
PLS
100BASE-TX
PMA
10BASE-T
PMA
100BASE-TX
PMD
GMII, RGMII, SGMII
1000BASE-T Block
GMII
1000BASE-T
PCS
1000BASE-T
PMA
Manchester
10 Mb/s
PAM-5
PR Shaped
125 Msymbols/s
MLT-3
100 Mb/s
DAC/ADC
SUBSYSTEM
DAC/ADC
TIMING BLOCK
TIMING
DRIVERS/
RECEIVERS
Block Diagram for One Port
MAGNETICS
4-pair CAT-5 Cable
2
www.national.com
DP83864
Notes:
3
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DP83864 Quad GigPHYTER™ 10/100/1000 Ethernet Physical Layer
Physical Dimensions
inches (millimeters) unless otherwise noted
NS Package BGA-292
Order Number DP83864AUT
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