DS3650 Quad Differential Line Receivers General Description Features The DS3650 is TTL compatible quad high speed circuits intended primarily for line receiver applications. Switching speeds have been enhanced over conventional line receivers by the use of Schottky technology, and TRI-STATE ® strobing is incorporated offering a high impedance output state for bussed organizations. n n n n n n The DS3650 has active pull-up outputs and offers a TRI-STATE strobe. Connection Diagram High speed TTL compatible Input sensitivity: ± 25 mV TRI-STATE outputs for high speed busses Standard supply voltages: ± 5V Pin and function compatible with MC3450 Wired “OR” Data Selecting Using TRI-STATE Logic Dual-In-Line Package DS005782-1 Top View Order Number DS3650M or DS3650N See NS Package Number M16A or N16A For Complete Military 883 Specifications, see RETS Data Sheet. Input Strobe DS005782-3 Output DS3650 VD ≥ 25 mV −25 mV ≤ VID ≤ 25 mV VID ≤ −25 mV L H H Open L X H Open L L H Open L = Low Logic State Open = TRI-STATE H = High Logic State X = Indeterminate State TRI-STATE ® is a registered trademark of National Semiconductor Corporation. © 1999 National Semiconductor Corporation DS005782 www.national.com DS3650 Quad Differential Line Receivers June 1999 Absolute Maximum Ratings (Note 2) SO Package If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Power Supply Voltages VCC VEE Differential-Mode Input Signal Voltage Range, VIDR Common-Mode Input Voltage Range, VICR Strobe Input Voltage, VI(S) Storage Temperature Range Lead Temperature (Soldering, 4 seconds) Maximum Power Dissipation (Note 1) at 25˚C Cavity Package Molded DIP Package 1051 mW Operating Conditions Supply Voltage, VCC Supply Voltage, VEE Operating Temperature, TA Output Load Current, IOL Differential-Mode Input Voltage Range, VIDR Common-Mode Input Voltage Range, VICR Input Voltage Range Input to GND, VIR +7.0 VDC −7.0 VDC ± 6.0 VDC ± 5.0 VDC 5.5 VDC −65˚C to +150˚C 260˚C Min 4.75 −4.75 0 Max 5.25 −5.25 +70 16 Units VDC VDC ˚C mA −5.0 +5.0 VDC −3.0 +3.0 VDC −5.0 +3.0 VDC Note 1: Derate cavity package 10.1 mW/˚C above 25˚C; derate molded DIP package 11.8 mW/˚C above 25˚C; derate SO package 8.41 mW/˚C above 25˚C. 1509 mW 1476 mW Electrical Characteristics (Notes 3, 4) (VCC = 5.0 VDC, VEE = −5.0 VDC, Min ≤ TA ≤ Max, unless otherwise noted) Symbol VIS IIH(I) Parameter Conditions Min Typ Max Units ± 25.0 mV (Figure 5 ) 75 µA (Figure 6 ) −10 µA Input Sensitivity, (Note 6) (Common-Mode Voltage Range = Min ≤ VCC ≤ Max −3V ≤ VIN ≤ 3V) Min ≥ VEE ≥ Max High Level Input Current to Receiver Input IIL(I) Low Level Input Current to Receiver Input IIH(S) High Level Input Current to Strobe Input (Figure 3 ) VIH(S) = 2.4V VIH(S) = VCC VIH(S) = 0.4V 40 µA 1 mA −1.6 mA IIL(S) Low Level Input Current to Strobe Input VOH High Level Output Voltage (Figure 1 ) VOL Low Level Output Voltage (Figure 1 ) IOS Short-Circuit Output Current (Note 5) (Figure 4 ) IOFF Output Disable Leakage Current (Figure 7 ) 40 µA ICCH High Logic Level Supply Current (Figure 2 ) 45 60 mA (Figure 2 ) −17 −30 mA 2.4 V −18 0.45 V −70 mA from VCC IEEH High Logic Level Supply Current from VEE Note 2: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Except for “Operating Temperature Range” they are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation. Note 3: Unless otherwise specified, min/max limits apply across the 0˚C to +70˚C range for the DS3650. All typical values are for TA = 25˚C, VCC = 5V and VEE = −5V. Note 4: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shown as max or min on absolute value basis. Note 5: Only one output at a time should be shorted. Note 6: A parameter which is of primary concern when designing with line receivers is, what is the minimum differential input voltage required as the receiver input terminals to guarantee a given output logic state. This parameter is commonly referred to as threshold voltage. It is well known that design considerations of threshold voltage are plagued by input offset currents, bias currents, network source resistances, and voltage gain. As a design convenience, the DS3650 is specified to a parameter called input sensitivity (VIS). This parameter takes into consideration input offset currents and bias currents and guarantees a minimum input differential voltage to cause a given output logic state with respect to a maximum source impedance of 200Ω at each input. www.national.com 2 Switching Characteristics (VCC = 5 VDC, VEE = −5 VDC, TA = 25˚C unless otherwise noted) Symbol tPHL(D) Parameter Delay Time (Differential Inputs) tPLH(D) Conditions High-to-Low Logic Level Propagation (Figure 8 ) Low-to-High Logic Level Propagation Delay Time (Differential Inputs) tPOH(S) TRI-STATE to High Logic Level Min Typ Max Units 21 25 ns 20 25 ns 16 21 ns 7 18 ns 19 27 ns 14 29 ns Propagation Delay Time (Strobe) tPHO(S) High Logic Level to TRI-STATE Propagation Delay Time (Strobe) tPOL(S) (Figure 9 ) TRI-STATE to Low Logic Level Propagation Delay Time (Strobe) tPLO(S) Low Logic Level to TRI-STATE Propagation Delay Time (Strobe) 3 www.national.com Electrical Characteristic Test Circuits DS005782-4 V1 V2 V3 V4 I1 VOH +2.975V +3.0V +3.0V GND −0.4 mA −3.0V −2.975V GND −3.0V −0.4 mA VOL +3.0V +2.975V GND +3.0V +16 mA −2.975V −3.0V −3.0V GND +16 mA Channel A shown under test. Other channels are tested similarly. FIGURE 1. VOH and VOL DS005782-5 DS005782-6 FIGURE 2. ICCH and IEEH FIGURE 3. IIH(S) and IIL(S) www.national.com 4 (Continued) DS005782-8 Note: Channel A(−) shown under test, other channels are tested similarly. Devices are tested with V1 from 3V to −3V. DS005782-7 FIGURE 5. IIH Note: Channel A shown under test, other channels are tested similiarly. Only one output shorted at a time. FIGURE 4. IOS DS005782-9 Note: Channel A(−) shown under test, other channels are tested similarly. Devices are tested with V1 from 3V to −3V. FIGURE 6. IIL DS005782-10 Note: Output of Channel A shown under test, other outputs are testedsimilarly for V1 = 0.4V and 2.4V. FIGURE 7. IOFF 5 www.national.com AC Test Circuits and Switching Time Waveforms DS005782-12 Note. EIN waveform characteristics: tTLH and tTHL ≤ 10 ns measured 10% to 90% PRR = 1 MHz Duty Cycle = 50% DS005782-11 Note. Output of Channel B shown under test, other channels are tested similarly. S1 at “B” for DS1650/DS3650 CL = 50 pF total for DS3650 FIGURE 8. Receiver Propagation Delay tPLH(D) and tPHL(D) www.national.com 6 (Continued) DS005782-13 Note. Output of Channel B shown under test, other channels are tested similiarly. V1 V2 S1 S2 CL tPLO(S) 100 mV GND Closed Closed 15 pF tPOL(S) 100 mV GND Closed Open 50 pF tPHO(S) GND 100 mV Closed Closed 15 pF tPOH(S) GND 100 mV Open Closed 50 pF CL includes jig and probe capacitance. EIN waveform characteristics: tTLH and tTHL ≤ 10 ns measured 10% to 90% PRR = 1 MHz Duty Cycle = 50% DS005782-15 DS005782-14 DS005782-17 DS005782-16 FIGURE 9. Strobe Propagation Delay tPLO(S), tPOL(S), tPHO(S) and tPOH(S) 7 www.national.com Schematic Diagrams DS3650 DS005782-20 1/4 of circuit shown www.national.com 8 Physical Dimensions inches (millimeters) unless otherwise noted SO Package (M) Order Number DS3650M NS Package Number M16A Molded Dual-In-Line Package (N) Order Number DS3650N NS Package Number N16A 9 www.national.com DS3650 Quad Differential Line Receivers Notes LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: [email protected] www.national.com National Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: [email protected] Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 Français Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 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