19-1306; Rev 0; 10/97 EVALUATION KIT AVAILABLE Serial-to-Parallel/Parallel-to-Serial Converters and Load-Switch Controllers with SMBus Interface ____________________________Features The MAX1661/MAX1662/MAX1663 serial-to-parallel/ parallel-to-serial converters are intended to control external power MOSFETs in power-plane switching applications. These small, low-cost devices can be used on a system motherboard to control point-of-load switching from a 2wire SMBus™ serial interface. Each device has three highvoltage open-drain outputs that double as TTL-level logic inputs, giving them bidirectional capabilities. The I/O pins can withstand +28V, so they can control battery voltagedistribution switches in notebook computers. The MAX1661 is intended for driving N-channel MOSFETs and its outputs are low upon power-up. The MAX1662/ MAX1663 are intended for P-channel MOSFETs, and their outputs are high-impedance upon power-up. This ensures that the MOSFETs are off at power-up, so the system can enforce power-plane sequencing. The SMBSUS control input selects control data between two separate data registers. This feature allows the system to select between two different power-plane configurations asynchronously, eliminating latencies introduced by the serial bus. Other features include thermal-overload and overcurrent protection, ultra-low supply current, and both hardware and software interrupt capabilities. These devices are available in the space-saving 10-pin µMAX package. ♦ Performs Serial-to-Parallel and Parallel-to-Serial Conversions ♦ Three General-Purpose Digital Input/Output Pins (withstand +28V) ♦ SMBus 2-Wire Serial Interface ♦ Supports SMBSUS Asynchronous Suspend Mode ♦ 3µA Supply Current ♦ +2.7V to +5.5V Supply Range ♦ Space-Saving, Low-Cost 10-Pin µMAX Package ______________Ordering Information PART TEMP. RANGE PIN-PACKAGE MAX1661EUB -40°C to +85°C 10 µMAX MAX1662EUB MAX1663EUB -40°C to +85°C -40°C to +85°C 10 µMAX 10 µMAX __________________Pin Configuration TOP VIEW VCC 1 ________________________Applications Power-Plane Switching Point-of-Load Power-Bus Switching I/O1 2 I/O2 3 I/O3 4 GND 5 Notebook and Subnotebook Computers 10 ALERT MAX1661 MAX1662 MAX1663 9 SMBCLK 8 SMBDATA 7 SMBSUS 6 ADD µMAX Desktop Computers Smart Batteries Typical Operating Circuits appear at end of data sheet. ______________________________________________________________Selector Guide PART x POWER-ONRESET STATE INTENDED APPLICATION SMBus ADDRESS ADDRESS PIN ADDRESS 0100000 0111100 1001000 MAX1661 Outputs Low N-Channel MOSFETs GND High-Z VCC MAX1662 Outputs High (high-Z state) P-Channel MOSFETs GND High-Z VCC 0100001 0111101 1001001 MAX1663 Outputs High (high-Z state) P-Channel MOSFETs GND High-Z VCC 0100010 0111110 1001010 SMBus is a trademark of Intel Corp. ________________________________________________________________ Maxim Integrated Products 1 For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 408-737-7600 ext. 3468. MAX1661/MAX1662/MAX1663 ________________General Description MAX1661/MAX1662/MAX1663 Serial-to-Parallel/Parallel-to-Serial Converters and Load-Switch Controllers with SMBus Interface ABSOLUTE MAXIMUM RATINGS VCC to GND ..............................................................-0.3V to +6V I/O to GND (I/O1, I/O2, I/O3) ..................................-0.3V to +30V I/O Sink Current (I/O1, I/O2, I/O3), Internally Limited.............................................-1mA to +50mA Digital Inputs to GND (SMBCLK, SMBDATA, SMBSUS, ALERT).................................................-0.3V to +6V ADD to GND ...............................................-0.3V to (VCC + 0.3V) SMBDATA Current, ALERT Current ....................-1mA to +50mA Continuous Power Dissipation (TA = +70°C) 10-pin µMAX (derate 5.6mW/°C above +70°C) ...........444mW Operating Temperature Range MAX166_EUB ..................................................-40°C to +85°C Storage Temperature Range .............................-65°C to +160°C Lead Temperature (soldering, 10sec) .............................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VCC = +2.7V to +5.5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are for TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS Input Voltage Range TYP MAX UNITS 5.5 V 3 10 µA 1.6 2.5 V 2.7 Supply Current Static condition; SMBDATA, SMBCLK, ADD, ALERT = VCC or GND (Note 2) Undervoltage Lockout/ Power-On Reset Threshold VCC falling 1.2 VI/O_ = 0.4V, VCC = 2.7V or 5.5V 2 VI/O_ = 1.0V, VCC = 4.5V 8 I/O Current Limit I/O1, I/O2, or I/O3; VCC = 4.5V 15 Thermal Shutdown Typical hysteresis of 10°C 140 VI/O_ = 28V, high-impedance state 0.5 5 0.5 1 I/O Sink Current I/O Leakage Current 2 MIN mA 13 20 50 mA °C µA VI/O_ = 0V, VCC; high-impedance state -1 Digital Input Current VSMBDATA, VSMBCLK, V SMBSUS, VADD = 0V, VCC -1 1 µA SMBus Logic Input Voltage Range VCC = 2.7V to 5.5V; SMBDATA, SMBCLK, SMBSUS 0 5.5 V Logic Input High Voltage I/O_, SMBSUS, SMBCLK, SMBDATA Logic Input Low Voltage I/O_, SMBSUS, SMBCLK, SMBDATA SMBDATA Output Low Sink Current VSMBDATA = 0.6V 6 ALERT Output Low Sink Current V ALERT = 0.4V 1 ALERT Output Leakage Current V ALERT = 5.5V, high-Z state SMBus Input Capacitance SMBCLK, SMBDATA SMBus Clock Frequency (Notes 3, 4) 2.4 V 0.8 V mA mA 1 µA 100 kHz 5 pF SMBCLK High Time tHIGH Measured between the 90% level of the rising edge and the 90% level of the falling edge 4 µs SMBCLK Low Time tLOW Measured between the 10% level of the falling edge and the 10% level of the rising edge 4.7 µs _______________________________________________________________________________________ Serial-to-Parallel/Parallel-to-Serial Converters and Load-Switch Controllers with SMBus Interface (VCC = +2.7V to +5.5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are for TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Start-Condition Setup Time tSU:STA Measured from 90% of the SMBCLK rising edge to 90% of the SMBDATA falling edge Start-Condition Hold Time tHD:STA Measured from 10% of the falling edge of SMBDATA to 90% of the falling edge of SMBCLK 4 µs SMBus Stop-Condition Setup Time tSU:STO Measured from 90% of the rising edge of SMBCLK to 10% of the rising edge of SMBDATA 4 µs SMBDATA Valid to SMBCLK Rising Edge Time, Slave Clocking in Data tSU:DAT 10% or 90% of SMBDATA to 10% of the rising edge of SMBCLK SMBCLK Falling Edge to SMBDATA Transition Hold Time tHD:DAT 4.7 µs VCC = 4.5V to 5.5V 500 VCC = 2.7V to 4.5V 1000 ns (Notes 4, 5) 0 µs SMBCLK Falling Edge to SMBus Data Valid Time tDV Tested with a 10kΩ pull-up resistor on SMBDATA (Note 6) SMBus Bus-Free Time tBUF Between stop and start conditions (Note 7) SMBus Write to I/O_ Propagation Delay tP:I/O Measured from SMBCLK rising edge to 10% or 90% of I/O (Note 4) I/O Data Valid to SMBCLK Rising-Edge Setup Time tSU:I/O Measured from 10% or 90% of VI/O to 10% of the rising edge of SMBCLK (Note 8) 15 µs I/O Data Hold Time tHD:I/O (Note 8) 0 µs START-STOP Software-Interrupt Pulse Width tLOW:SS Measured from the 10% point of the falling edge of SMBDATA to the 10% point of the rising edge of SMBDATA (Note 7) 10 1 4.7 µs µs 100 15 ns 30 µs Note 1: Specifications from 0°C to -40°C are guaranteed by design, not production tested. Note 2: Supply current is specified for static state only. Note 3: The SMBus logic block is a static design that works with clock frequencies down to DC. While slow operation is possible, it violates the 10kHz minimum clock frequency of the SMBus specifications, and may monopolize the bus. Note 4: Refer to Figures 2a and 2b for SMBus timing parameter definitions (write and read diagrams). Note 5: A transition must internally provide a hold time of 300ns to accommodate for the undefined region of the falling edge. Note 6: Refer to Figure 3 for the acknowledge timing diagram and tDV parameter definition. Note 7: Refer to Figure 5 for START-STOP interrupt timing diagrams and parameter definitions. Note 8: Refer to Figure 4 for I/O setup and hold timing parameter definitions. _______________________________________________________________________________________ 3 MAX1661/MAX1662/MAX1663 ELECTRICAL CHARACTERISTICS (continued) __________________________________________Typical Operating Characteristics (VCC = +5.0V, TA = +25°C, unless otherwise noted.) VCC = 2.7V 2.0 1.5 3.0 2.5 2.0 1.5 1.0 1.0 ALL I/Os OFF -20 0 20 40 60 80 2.5 3.0 I/O_ CURRENT LIMIT vs. TEMPERATURE 4.0 4.5 5.0 5.5 0 0.6 1.2 1.8 2.4 3.0 3.6 4.2 4.8 5.4 6.0 SUPPLY VOLTAGE (V) MAX1661toc04 22 22.5 20 18 16 VCC = 5.5V 20.0 CURRENT LIMIT (mA) POR DELAY vs. TEMPERATURE 40 35 30 17.5 15.0 VCC = 2.7V 12.5 10.0 7.5 25 20 15 10 5.0 12 5 2.5 0 10 -20 0 20 40 60 80 0 0 100 3 6 9 -20 0 20 40 60 TEMPERATURE (°C) VI/O_ (V) TEMPERATURE (°C) POR DELAY vs. SUPPLY VOLTAGE I/O_ INPUT BIAS CURRENT vs. TEMPERATURE I/O_INPUT BIAS CURRENT vs. OUTPUT VOLTAGE INPUT BIAS CURRENT (µA) 30 0.9 25 20 15 10 5 VCC = 5.5V VI/O_ = 15V 0.8 0.7 0.6 0.5 0.4 0.3 3.5 4.0 4.5 SUPPLY VOLTAGE (V) 5.0 5.5 0.9 0.8 100 0.7 0.6 0.5 0.4 0.3 0.2 0.2 0.1 0.1 0 0 0 1.0 80 MAX1661toc09 1.0 MAX1661toc07 35 3.0 -40 12 15 18 21 24 27 30 INPUT BIAS CURRENT (µA) -40 MAX1661toc08 CURRENT LIMIT (mA) 3.5 25.0 14 4 4.5 I/O_ CURRENT LIMIT vs. I/O_ VOLTAGE VI/O_ FORCED TO 15V VCC = 5.5V 24 VI/O_ = 0.4V 6.0 SUPPLY VOLTAGE (V) TEMPERATURE (°C) 26 7.5 0 2.0 100 POR DELAY (µs) -40 9.0 1.5 0 MAX1661toc05 0 10.5 3.0 0.5 0.5 VI/O_ = 1.0V 12.0 3.5 MAX1661toc06 2.5 13.5 SINK CURRENT (mA) 3.0 4.0 SUPPLY CURRENT (µA) 3.5 15.0 MAX1661toc02 VCC = 5.5V 4.0 SUPPLY CURRENT (µA) 4.5 MAX1661toc03 5.0 4.5 I/O_ SINK CURRENT vs. SUPPLY VOLTAGE SUPPLY CURRENT vs. SUPPLY VOLTAGE MAX1661toc01 SUPPLY CURRENT vs. TEMPERATURE POR DELAY (µs) MAX1661/MAX1662/MAX1663 Serial-to-Parallel/Parallel-to-Serial Converters and Load-Switch Controllers with SMBus Interface -40 -20 0 20 40 60 TEMPERATURE (°C) 80 100 0 3 6 9 12 15 18 21 24 27 30 OUTPUT VOLTAGE (V) _______________________________________________________________________________________ ? ?W2@@@@@@@@@h?W2@@@@@@@@@ ?W2@@@@@@@f@@@@@@@@@6X?g?W2@@@@@@@@@f@@@@@@@@ ?W2@@@@@@@@@h?W2@@@@@@@@@? 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This pin can tolerate up to 28V. 5 GND Ground 6 ADD SMBus Address Select Pin (see Table 1 for details). 7 SMBSUS 8 SMBDATA 9 SMBCLK 10 ALERT SMBus Suspend-Mode Control Input. Drive low to select the suspend-mode register. Drive high to select the normal-mode register. (See Detailed Description.) SMBus Serial-Data Input/Output (open drain) SMBus Serial Clock Input Interrupt Output, active low, open drain TRANSITION DETECTORS I/01 SMBCLK SMBDATA 8 SMB INPUT REGISTER I/02 MAX1661/ MAX1662/ MAX1663 ADD I/03 ADDRESS DECODER NORMAL NORMAL DATA REGISTER 7 MUX O1 SUSPEND CONTROL NORMAL ALERT RESPONSE REGISTER MUX O2 SUSPEND CONTROL ALERT SUSPENDMODE DATA REGISTER R FAULT LATCH S THERMAL SHUTDOWN NORMAL MUX O3 SUSPEND CONTROL SMBSUS Figure 1. Functional Diagram _______________________________________________________________________________________ 5 MAX1661/MAX1662/MAX1663 ______________________________________________________________Pin Description MAX1661/MAX1662/MAX1663 Serial-to-Parallel/Parallel-to-Serial Converters and Load-Switch Controllers with SMBus Interface _______________Detailed Description The MAX1661/MAX1662/MAX1663 convert 2-wire SMBus serial data into three latched parallel outputs (I/O1, I/O2, I/O3). These devices are intended to drive Nchannel and P-channel, high-side MOSFET switches in load power-management systems. Readback capabilities allow them to function as parallel-to-serial devices. The MAX1661/MAX1662/MAX1663 operate from a single supply with a typical quiescent current of 3µA, making them ideal for portable applications (Figure 1). SMBus Interface Operation The SMBus serial interface is a 2-wire interface with multi-mastering capability. From a software perspective, the MAX1661/MAX1662/MAX1663 appears as a set of byte-wide registers that contain information controlling the I/O_ pins, masking capabilities, and a control bit that determines which register is being addressed. The 2-wire slave interface employs standard SMBus send-byte and receive-byte protocols. SMBDATA and SMBCLK are Schmitt-triggered inputs that can accommodate slower edges; however, the rising and falling edges should still be faster than 1µs and 300ns, respectively. Except for the stop and start conditions, the SMBDATA input never transitions while SMBCLK is high. A third interface line (SMBSUS) is used to execute commands asynchronously from previously stored registers (see the section SMBSUS (Suspend-Mode) Input) . This reduces the inherent delay in a standard 2-wire serial interface. In the receive-byte operation, the SMBus interface reads back I/O states and thermal-shutdown status. SMBus Addressing Each slave device only responds to two addresses: its own unique address and the alert response address. The device’s unique address is determined at power-up (Table 1). The three-level state of the address-select pin (ADD) is only sampled upon power-on reset (POR) causing momentary input bias current of 100µA. The address will not change until the part is power cycled. Stray capacitance in excess of 50pF on the ADD pin when floating may cause address recognition problems. The normal start condition consists of a high-to-low transition on SMBDATA while SMBCLK is high. After the start condition, the master transmits a 7-bit address followed by a single bit to determine whether the device is sending or receiving (high = READ, low = WRITE). If the address is correct, the MAX1661/MAX1662/ MAX1663 sends an acknowledgment pulse by pulling SMBDATA low. Otherwise, the address is not recognized and the device stays off the bus and waits until another start condition occurs. 6 Table 1. SMBus Addresses MAX1661 MAX1662 MAX1663 GND ADD 0100000 0100001 0100010 High-Z (floating) 0111100 0111101 0111110 VCC 1001000 1001001 1001010 SMBus Send-Byte Commands If the MAX1661/MAX1662/MAX1663 receives its correct slave address (Table 1) followed by R/W low, it expects to receive a byte of information. If the device detects a start or stop condition prior to clocking in the byte of data, it considers this an error condition and disregards all of the data. The MAX1661/MAX1662/MAX1663 generates a first acknowledge after the write bit and another acknowledge after the data. It executes the data byte at the rising edge of SMBCLK following the second acknowledge, just prior to the stop condition (Figure 2a). See Table 2 for sendbyte operations. SMBSUS (Suspend-Mode) Input The SMBus can write to either of the normal-data and suspend-mode registers via the MSB (bit 7) of the send-byte word (Table 2). The state of the SMBSUS input selects which register contents (normal data or suspend mode) are applied to the I/O_ pins. Driving SMBSUS low selects the suspend-mode register, while driving SMBSUS high selects the normal-data register. This feature allows the system to select between two different power-plane configurations asynchronously, eliminating latencies introduced by the serial bus. SMBSUS typically connects to the SUSTAT# signal in a notebook computer. SMBus Receive-Byte Operation If the MAX1661/MAX1662/MAX1663 receives its correct slave address, followed by R/W high, the device becomes a slave transmitter (Figure 2b). After receiving the address data, the device generates an acknowledge during the acknowledge clock pulse and drives SMBDATA in sync with SMBCLK. The SMB protocol requires that the master terminate the read transmission by not acknowledging during the acknowledge bit of SMBCLK. See Table 3 for receive-byte data format. Figure 4 shows the complete receive-byte operation timing diagram. The logic states of the three I/O pins can be read over the serial interface (Table 3). The state of the I/O pins is sampled at the falling edge of the SMBCLK pulse that follows the R/W bit and acknowledge bit (Figure 4). The states of the I/O bits in the status register reflect the _______________________________________________________________________________________ Serial-to-Parallel/Parallel-to-Serial Converters and Load-Switch Controllers with SMBus Interface MAX1661/MAX1662/MAX1663 tP: I/O I/O A tLOW B tHIGH C D E F G I H J K L M SMBCLK SMBDATA tSU:STA tHD:STA tSU:DAT A = START CONDITION B = MSB OF ADDRESS CLOCKED INTO SLAVE C = LSB OF ADDRESS CLOCKED INTO SLAVE D = R/W BIT CLOCKED INTO SLAVE E = SLAVE PULLS SMBDATA LINE LOW tHD:DAT tSU:STO tBUF F = ACKNOWLEDGE BIT CLOCKED INTO MASTER G = MSB OF DATA CLOCKED INTO SLAVE (OP/SUS BIT) H = LSB OF DATA CLOCKED INTO SLAVE I = SLAVE PULLS SMBDATA LINE LOW J = ACKNOWLEDGE CLOCKED INTO MASTER K = ACKNOWLEDGE CLOCK PULSE L = STOP CONDITION, DATA EXECUTED BY SLAVE M = NEW START CONDITION Send-Byte Format START CONDITION ADDRESS WRITE ACK DATA ACK 7 bits 1 bit (low) 1 bit (low) 8 bits 1 bit (low) STOP CONDITION Shaded = Slave Transmission Figure 2a. SMBus Send-Byte Timing Diagram and Format Table 2. Format for Send-Byte Data BIT NAME POR STATE* (MAX1661) POR STATE* (MAX1662/MAX1663) FUNCTION 7 (MSB) SELECT N/A N/A Writes data to normal register when high; writes data to suspend register when low. 6 Mask SS 1 1 Masks START-STOP software interrupts when high. 5 Mask 3 1 1 Masks I/O3 interrupts when high. 4 Mask 2 1 1 Masks I/O2 interrupts when high. 3 Mask 1 1 1 Masks I/O1 interrupts when high. 2 I/O3 0 1 I/O output enable bit. I/O3 is on when this bit is low (low state). 1 I/O2 0 1 I/O output enable bit. I/O2 is on when this bit is low (low state). 0 I/O1 0 1 I/O output enable bit. I/O1 is on when this bit is low (low state). *Note: POR states apply to both suspend- and normal-mode registers. current I/O pin states (i.e., they are not latched). There is a 15µs data-setup time requirement, due to the slow level translators needed for high-voltage (28V) operation. Data-hold time is zero. Interrupts The MAX1661/MAX1662/MAX1663 generate interrupts (hardware and software) whenever the logic states of the I/O pins change or when thermal shutdown occurs. Interrupts are signaled with the hardware ALERT pin _______________________________________________________________________________________ 7 MAX1661/MAX1662/MAX1663 Serial-to-Parallel/Parallel-to-Serial Converters and Load-Switch Controllers with SMBus Interface A B tLOW C D E F G H J I tHIGH K SMBCLK SMBDATA tSU:STA tHD:STA tSU:STO tSU:DAT A = START CONDITION B = MSB OF ADDRESS CLOCKED INTO SLAVE C = LSB OF ADDRESS CLOCKED INTO SLAVE D = R/W BIT CLOCKED INTO SLAVE E = SLAVE PULLS SMBDATA LINE LOW F = ACKNOWLEDGE BIT CLOCKED INTO MASTER G = MSB OF DATA CLOCKED INTO MASTER H = LSB OF DATA CLOCKED INTO MASTER tBUF I = ACKNOWLEDGE CLOCK PULSE J = STOP CONDITION K = NEW START CONDITION Receive-Byte Format ADDRESS READ ACK DATA ACK 7 bits 1 bit (high) 1 bit (low) 8 bits 1 bit (high-Z) START CONDITION STOP CONDITION ACK = SMBDATA High Shaded = Slave Transmission Figure 2b. SMBus Receive-Byte Timing Diagram and Format Table 3. Format for Receive-Byte Data BIT NAME POR STATE FUNCTION 7 (MSB) — 0 Not used — 6 — 0 Not used — 5 — 0 Not used — Not used 4 — 0 3 THSD N/A This bit indicates a thermal shutdown. Yes 2 Data 3 N/A This bit indicates the state of I/O3 (high or low). No 1 Data 2 N/A This bit indicates the state of I/O2 (high or low). No 0 Data 1 N/A This bit indicates the state of I/O1 (high or low). No and with the software START-STOP method (software interrupts are discussed in the START-STOP Software Interrupt section). The I/O interrupts can be masked individually. In addition, the software START-STOP interrupt can be masked independently. The power-onreset state masks the START-STOP interrupt, as well as the individual I/O interrupts to the ALERT pin (Table 1). The thermal-shutdown interrupt cannot be masked. Note that excessive noise on the supply can cause false interrupts (see Applications Information). 8 LATCHED — The MAX1661/MAX1662/MAX1663 are slave-only devices that never initiate communications, except when asserting an interrupt by forcing ALERT low, or via the software START-STOP interrupt. Alert Response Address (0001100) The Alert Response (interrupt pointer) address provides quick fault identification for simple slave devices that lack the complex, expensive logic needed to be a bus master. When a slave device generates an inter- _______________________________________________________________________________________ Serial-to-Parallel/Parallel-to-Serial Converters and Load-Switch Controllers with SMBus Interface SMBCLK MAX1661/MAX1662/MAX1663 ACKNOWLEDGE BIT CLOCKED INTO MASTER R/W BIT CLOCKED INTO SLAVE MOST SIGNIFICANT BIT OF DATA CLOCKED INTO MASTER • • • SLAVE PULLING SMBDATA LOW SMBDATA • • • tDV tDV Figure 3. SMB Serial-Interface Timing—Acknowledge and Data Valid ADDRESS LSB ADDRESS MSB SLAVE ACKNOWLEDGE R/W BIT START SLAVE ACKNOWLEDGE (ACK) I/O LATCHED DATA MSB DATA LSB SMBCLK tSU:I/O tHD:I/O (NOTE 1) (NOTE 1) THSD SMBDATA NOTE 1: THE SETUP AND HOLD TIMING LIMITS ARE ABSOLUTE LIMITS (15µs MIN AND 0µs MIN, RESPECTIVELY) AND DO NOT NECESSARILY CORRESPOND TO A PARTICULAR CLOCK EDGE. SLAVE PULLS SMBDATA LOW DATA3 DATA2 DATA1 4 ZEROS (NOT USED) Figure 4. I/O Read Timing Diagram rupt, the host (Bus Master) interrogates the bus slave devices via a special receive-byte operation that includes the alert response address. The data returned by this receive-byte operation is the address of the offending slave device. The interrupt pointer address can activate several different slave devices simultaneously. If more than one slave attempts to respond, bus arbitration rules apply, with the lowest address code going first. The other device(s) will not generate an acknowledge and will continue to hold the ALERT line low or repeat the START-STOP interrupt until serviced. Clearing Interrupts via Alert Response When a fault occurs, ALERT asserts and latches low. If the fault is momentary and disappears before the device is serviced, ALERT remains asserted. Normally, the master sends out the Alert Response address followed by a read bit (00011001). ALERT clears when the device responds by successfully putting its address on the bus. Reading the Alert Response address is the only method for clearing hardware and software interrupt latches. Clearing the interrupt has no effect on the state of the status registers. _______________________________________________________________________________________ 9 MAX1661/MAX1662/MAX1663 Serial-to-Parallel/Parallel-to-Serial Converters and Load-Switch Controllers with SMBus Interface SLAVE ACKNOWLEDGE (ACK) START STOP SMBCLK tLOW:SS SMBDATA tBUF DATA LINE HELD LOW BY SLAVE ALERT START-STOP INTERRUPT ALERT RESPONSE ADDRESS (0001100) DUMMY BIT (1) ACTUAL SLAVE ADDRESS (0100000 IN THIS EXAMPLE) Figure 5. START-STOP Software Interrupt Timing Diagram and Alert Response START-STOP Software Interrupt The START-STOP interrupt is a method for the slave device to initiate a signal over the 2-wire interface without the need for a third (interrupt) wire. A START-STOP interrupt is a start condition followed by a stop condition; in other words, SMBDATA goes low and then high with SMBCLK high (Figure 5 shows the START-STOP interrupt and a subsequent Alert Response transmission used to clear the interrupt). The START-STOP function can be disabled (masked) by setting the data register mask SS (bit 6) high. In order to avoid bus collisions, the START-STOP interrupt will not occur when the bus is busy. If the device begins a start condition simultaneously with another transmitter on the bus, it recognizes the falling SMBCLK as a collision and re-transmits the interrupt when the bus becomes available. Upon thermal shutdown or a transition on an I/O line, the device issues only one START-STOP interrupt, and won’t repeat it unless there has been a collision. However, thermal-shutdown faults, not being edge triggered, may result in a continuous stream of START-STOP bits. Input/Output Pins Each input/output (I/O) is protected by an internal 20mA (typical) current-limit circuit. The I/O current limit depends on the supply voltage and the voltage applied to the I/O pins (see Typical Operating Characteristics). The typical I/O bias current is 0.5µA to VI/O_ = 28V. The ability of the I/Os to sink current depends on VCC as well as the voltage on the I/O. Typical pull-down onresistance at VCC = 2.7V and 5.5V is 106Ω and 66Ω, respectively. I/O source and sink capability can affect the rise and fall times of external power MOSFETs com- 10 monly used in power-switching applications. Other factors include the VGS, the input capacitance of the MOSFET, and the pull-up resistor value used in the circuit. Typical MOSFET gate capacitance ranges from 150pF to 2000pF. Increasing the RC time constant slows down the MOSFET’s response, but provides for a smoother transition. Power-On Reset The power-on reset circuit keeps the external MOSFETs off during a power-up sequence. When the supply voltage falls below the power-on reset threshold voltage, the MAX1662/MAX1663’s outputs reset to a highimpedance state, and the MAX1661’s outputs reset to a low state. During the initial power-up sequence, as VCC increases, the ALERT pin goes low and then high, which indicates the device is powered on. The time between the low and high state on ALERT is the poweron delay time. Below VCC = 0.8V (typical) the POR states can’t be enforced, and the I/O pins of all versions exhibit increasingly weak pull-down current capability, eventually becoming high impedance. Thermal Shutdown These devices have internal thermal-shutdown circuitry that turns off all output stages (I/O pins) when the junction temperature exceeds +140°C typical. Thermal shutdown only occurs during an overload condition on the I/O pins. The device cycles between thermal shutdown and the overcurrent condition until the overload condition is removed. This could cause a sustained START-STOP interrupt and, in the extreme case, tie up the master controller. However, the device asserts ALERT low, indicating this fault status. ______________________________________________________________________________________ Serial-to-Parallel/Parallel-to-Serial Converters and Load-Switch Controllers with SMBus Interface Bypassing and Grounding Considerations Voltage transients exceeding 500mV at 25V/µs may trigger a false interrupt and thermal-shutdown indication. If large VCC transients are expected, add a 100Ω resistor in series with VCC. Retain the 0.1µF capacitor from VCC to GND to act as a filter. P-Channel/N-Channel Load Switch with Controlled Turn-On For a more controlled voltage-switching application, add a series resistor to slow the switch turn-on time. The external MOSFET gate has typical capacitance of 150pF to 2000pF, but an optional external capacitance can be added to further slow the switching time (Figure 6). +5V 100Ω* 10k 10k 10k 10k VCC 10k 0.01µF* 0.01µF* 0.1µF MAX1662 MAX1663 TO/FROM HOST 10k 0.01µF* 200k ALERT I/O1 SMBDATA I/O2 SMBCLK I/O3 200k 200k IRF7406 IRF7406 IRF7406 SMBSUS ADD GND LOAD1 LOAD2 LOAD3 +12V +5V 100Ω* 10k 10k 10k 0.1µF TO/FROM HOST 10k VCC 10k 10k IRF7413 MAX1661 200k ALERT I/O1 SMBDATA I/O2 SMBCLK I/O3 IRF7413 200k 0.01µF* IRF7413 200k 0.01µF* 0.01µF* SMBSUS ADD GND LOAD1 LOAD2 LOAD3 *OPTIONAL Figure 6. Load Switch with Controlled Turn-On ______________________________________________________________________________________ 11 MAX1661/MAX1662/MAX1663 __________Applications Information MAX1661/MAX1662/MAX1663 Serial-to-Parallel/Parallel-to-Serial Converters and Load-Switch Controllers with SMBus Interface Battery Switch with Back-to-Back MOSFETs LED Drivers A MAX1661/MAX1662/MAX1663 can be used as a programmable LED driver (Figure 8). With their low quiescent current, these devices are ideal for use as indicator light drivers on the front panel of a notebook computer. For battery-operated applications, use back-to-back MOSFETs to keep reverse currents from flowing from the load to the supply (Figure 7). This protects the battery from potential damage, and isolates the load from the power source. +5V +3.3V TO +28V 100Ω* 100k 10k 10k 10k VCC 0.1µF IRF7406 MAX1662 MAX1663 TO/FROM HOST 75k** ALERT I/O1 SMBDATA I/O2 SMBCLK I/O3 P 1M IRF7406 P SMBSUS ADD GND LOAD NOTE: I/O2 AND I/O3 CAN BE CONFIGURED SIMILARLY. *OPTIONAL **75kΩ RESISTOR FOR VOLTAGES GREATER THAN +12V. Figure 7. Battery Switch with Back-to-Back MOSFETs +5V 100Ω* 1k 10k TO/FROM HOST 10k VCC 1k 1k 0.1µF MAX1661 MAX1662 ALERT MAX1663 I/O1 SMBDATA I/O2 SMBCLK I/O3 SMBSUS ADD GND *OPTIONAL Figure 8. LED Drivers 12 ______________________________________________________________________________________ Serial-to-Parallel/Parallel-to-Serial Converters and Load-Switch Controllers with SMBus Interface Simple High-Voltage Switch For applications requiring a higher voltage, use a simple resistive divider to protect the gate from breakdown yet allow the MOSFETs to handle higher-voltage applications (Figure 10). +5V 100Ω* 10k 10k 10k 0.1µF 100k VCC 100k 100k MAX1661 MAX1662 ALERT MAX1663 I/O1 TO/FROM HOST SMBDATA I/O2 SMBCLK I/O3 SMBSUS ADD GND *OPTIONAL Figure 9. Open-Lid Detect or Chassis Intrusion Detector +5V VIN = 10V TO 28V 100Ω* 200k 10k 10k 10k TO/FROM HOST VCC 0.1µF MAX1662 MAX1663 200k 0.01µF* ALERT I/O1 SMBCLK I/O2 SMBDATA I/O3 IRF7406 SMBSUS ADD GND LOAD *OPTIONAL I/O2 AND I/O3 CAN BE CONFIGURED SIMILIARLY. Figure 10. Simple High-Voltage Switch ______________________________________________________________________________________ 13 MAX1661/MAX1662/MAX1663 Mechanical Switch Monitor The ability of the MAX1661/MAX1662/MAX1663 to read back the logic state of the I/Os makes them suitable for checking system status. They can be used as an “open-lid indicator”, sensing a change in the I/O and sending an interrupt to the master to indicate a change in status (Figure 9). The same can be done to detect a chassis intrusion. MAX1661/MAX1662/MAX1663 Serial-to-Parallel/Parallel-to-Serial Converters and Load-Switch Controllers with SMBus Interface ___________________________________________________Typical Operating Circuit +2.7V TO +5.5V 100k VCC 100k 0.1µF MAX1662 MAX1663 SMBUS TO/ FROM HOST 100k ALERT I/O1 SMBDATA I/O2 SMBCLK I/O3 P-CH SMBSUS ADD GND LOAD1 LOAD2 LOAD3 +12V +2.7V TO +5.5V 100k VCC 100k 0.1µF MAX1661 SMBUS TO/ FROM HOST 100k ALERT I/O1 SMBDATA I/O2 SMBCLK I/O3 N-CH SMBSUS ADD GND LOAD1 LOAD2 LOAD3 ___________________Chip Information TRANSISTOR COUNT: 3334 SUBSTRATE CONNECTED TO GND 14 ______________________________________________________________________________________ Serial-to-Parallel/Parallel-to-Serial Converters and Load-Switch Controllers with SMBus Interface 10LUMAXB.EPS ______________________________________________________________________________________ 15 MAX1661/MAX1662/MAX1663 ________________________________________________________Package Information Serial-to-Parallel/Parallel-to-Serial Converters and Load-Switch Controllers with SMBus Interface MAX1661/MAX1662/MAX1663 NOTES Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 1997 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.