SP8853 1.3 GHz Professional Synthesiser Data Sheet VEE3 IC Cd LOCK DETECT 2 1 28 27 26 NC PD1 OUTPUT 3 5 25 PD2 OUTPUT POWER DOWN 6 24 RPD VEE4 7 VCC4 8 VCC1 SP8853 23 VCC3 22 GROUND RF INPUT 11 19 VEE2 13 14 15 16 17 18 VCC2 12 NC XTAL2 CLOCK XTAL 1 20 ENABLE 21 10 DATA 9 RF INPUT VEE1 FEATURES ■ Improved Digital Phase Detector Eliminates ‘Dead Band’ Effects ■ Low Operating Power, Typically 175mW ■ 1·3GHz Operating Frequency ■ Complete Phase Locked Loop ■ High Input Sensitivity ■ Programmed throughThree-Wire Bus ■ Wide Range of Reference Division Ratios ■ Local Storage for Two Frequency Words, giving Rapid Frequency Toggling ■ Programmable Phase Detector Gain ■ Power Down Mode 4 FREF* F1/F2 The SP8853 is a low power single chip synthesiser intended for professional radio applications, containing all the elements (apart from the loop amplifier) required to build a PLL frequency synthesis loop The device is serially programmable by a three-wire data highway and contains three independent buffers to store one reference divider word and two local oscillator divider words. A digital phase detector with two charge pumps, programmable in phase and gain, are provided to improve lock-up performance. The preset operation of the charge pumps can be overwritten or the comparison frequencies switched to output ports under control of the divider word. The dual modulus ratio and so operating range is also programmable through the same word. A power down mode is incorporated as a battery economy feature. The SP8853 is specified at 1.3GHz at -55°C to +125°C (mil temp) and -40°C to +85°C (ind. temp). FPD* June 2003 HC28 *FPD and FREF outputs are reversed by the phase detector sense bit in the F1/F2 programming word. The above diagram is correct when the sense bit is low. See Table 2 and Fig. 7. VCC1, VEE1 – preamplifier and prescaler supplies VCC2, VEE2 – oscillator supplies VCC3, VEE3 – charge pump 2 supplies VCC4, VEE4 – ECL supplies Fig. 1 Pin identification diagram (top view) ABSOLUTE MAXIMUM RATINGS Supply voltage Storage temperature Prescaler input voltage 20·3V to 17V 255°C to 1150°C 2·5V p-p ORDERING INFORMATION SP8853/A/DG, SP8853/A/HC Industrial temperature versions SP8853/AC/DG, SP8853/AC/HC Military temperature versions SP8853 RF INPUT RF INPUT Data Sheet 10 16/17 OR 8/9 CONTROL 11 LOGIC F1/F2 DATA CLOCK ENABLE A COUNT 1LOGIC M COUNT 1LOGIC 4 BIT 15 BIT fPD PHASE DETECTOR 2 BIT 13 DUAL F1/F2 DATA BUFFER 1 BIT CHARGE PUMP 1 3 14 N0 15 DATA INPUT N3 N4 2-BIT SR N18 N19 N20 N21 22 BIT SHIFT REGISTER 24 16 28 N0 POWER 6 DOWN N12 N13 13 BIT N14 1 BIT N15 CHARGE PUMP 2 SINGLE REFERENCE BUFFER 2 BIT R COUNT 4 *FREF and FPD outputs are reversed by the phase detector sense bit in the F1/F2 programming word. The pin allocations shown are correct when the sense bit is low (see Table 2 and Fig. 7). 20 21 CRYSTAL Fig. 2 SP8853 block diagram VCC PD1 3 CHARGE PUMP 1 DISABLE (SEE TABLE 4) CHARGE PUMP 1 45k 31 + CHARGE PUMP 2 Output current at pin 27 is proportional to voltage difference between pins 25 and 28, IMAX = 625µA − − 10k + 31 TRANSCONDUCTANCE AMPLIFIER fPD fREF 31 BUFFER − 27 LOCK DETECT + PHASE DETECTOR 45k 24 RPD 25 PD2 DUAL VOLTAGE COMPARATOR 28 Cd Fig. 3 Detailed block diagram of lock detect circuit Cd PD2 27 LOCK DETECT fREF REFERENCE DIVIDER RPD 25 5 OUTPUT INTERFACE LOGIC 2 PD1 FREF* FPD* SP8853 Data Sheet 400 TYPICAL OVERLOAD INPUT VOLTAGE (mV RMS) 350 300 250 200 GUARANTEED OPERATING WINDOW 48/9 MODE 150 GUARANTEED OPERATING WINDOW 416/17 MODE 100 TYPICAL SENSITIVITY 50 25 0 80 150 0 650 500 750 1000 1300 1500 FREQUENCY (MHz) Fig. 4 Typical input characteristics and input drive requirements for SP8853 A and B tS1tCH DATA 2V tS FIRST DATA BIT tCH LAST DATA BIT tCL tREP CLOCK ENABLE 2V 2V tE tREP = 1µs min., tS = 50ns min., tCH = 50ns min., tCL = 100ns min., tE = 50ns min. Fig. 5 Data and clock timing requirements 3 SP8853 Data Sheet ELECTRICAL CHARACTERISTICS These characteristics are guaranteed over the following range of operating conditions unless otherwise stated: Supply voltage VCC = 14·75V to 15·25V. TAMB = 255°C to 1125°C (A Grade), 240°C to 185°C (B Grade) Value Characteristic Supply current Supply current in power down mode Units Typ. Max. 8,9,18,23 33 40 mA 8 4·5 7·5 mA Min. Conditions Input sensitivity 10,11 See Fig. 4 Input overload 10,11 See Fig. 4 RF input division ratio Comparison frequency Reference oscillator input frequency External reference input voltage Reference division ratio Data clock repetition rate, tREP 10,11,4 256 524287 With 416/17 selected 56 262143 With 48/9 selected 4,5 5 MHz 20,21 4 20 MHz 20 10 500 mVrms 20,5 1 8191 1 15 µs See Fig. 5 ns See Fig. 5 14,15 50 DATA input high 14 0·6VCC VCC V DATA input low 14 VEE 0·3VCC V CLOCK input high 15 0·6VCC VCC V CLOCK input low 15 VEE 0·3VCC V Data ENABLE high 16 0·6VCC VCC V Data ENABLE low 16 VEE 0·3VCC V F1/F2 input high 13 0·6VCC VCC V F1 buffer selected F1/F2 input low 13 VEE 0·3VCC V F2 buffer selected POWER DOWN input high 6 0·6VCC 0·9VCC V POWER DOWN input low 6 VEE 0·3VCC V F1/F2 input current 13 5 µA V pin 13 = 5·0V POWER DOWN input current 6 5 µA V pin 6 = 4·5V RDP external resistance 24 330 kΩ LOCK DETECT output voltage when in lock 27 1 V I pin 27 = 1mA LOCKDETECT switching voltage high 25 V VCC = 5V LOCK DETECT switching voltage low 25 V VCC = 5V V VCC = 5V, external pulldown may be required Minimum setup time, tS FPD and FREF output voltage swing 4 Pin 68 2·7 2·3 0·9 SP8853 Data Sheet DESCRIPTION Prescaler and AM Counter The programmable divider chain is of AM counter design and therefore contains a dual modulus front end prescaler, an A counter which controls the dual modulus ratio and an M counter which controls the bulk multi-modulus division. A programmable divider of this type has a division ratio of MN1A and a minimum integer steppable division ratio of N(N21). In the SP8853, the dual modulus front end prescaler is a dual N ratio device, capable of being statically switched between 416/17 and 48/9 ratios. The controlling A counter is of four-bit design, allowing a maximum count sequence of 15 (2421), which begins with the start of the M counter sequence and stops when it has counted by the pre-loaded number of cycles. While the A counter is counting, the dual modulus prescaler is held in the N11 mode then reverts to the N mode at the completion of the sequence. The M counter is a 15-bit asynchronous divider which counts with a ratio set by a control word. In both A and M counters the controlling data from the F1/F2 buffer is loaded in sequence with every M count cycle. The N ratio of the dual modulus prescaler is selected by a one-bit word in the reference divider buffer and, when when a ratio of 48/9 is selected, the A counter requires only three programming bits, having an impact on the frequency bit allocation as described in the data entry section. Reference Source and Divider The reference source in the SP8853 is obtained from an on-chip oscillator which is frequency controlled by an external crystal. The oscillator can also function as a buffer amplifier to allow the use of an external reference source. In this mode, the source is simply AC-coupled into the oscillator transistor base on pin 20. The oscillator output is coupled to a programmable reference counter (R) whose output is the reference for the phase detector. The reference divider is a fully programmable 13-bit asynchronous design and can be set to any division ratio between 1 and 8191. The actual division ratio is controlled by a data word stored in the internal reference buffer. Phase Detector The SP8853 contains a digital phase detector which feeds two charge pump circuits. Charge pump 1 has preset currents which are programmble as shown in Table 1. Charge pump 2 has a current level set by an external resistor RPD; the current is multiplied by a factor which is determined by bits G1 and G2 of the F1 or F2 word (see Table 1). Note that charge pump 2 current is pin 24 current 3 muliplication factor, where I pin 24 = VCC21·5V RPD A lock detect circuit is connected to the output of charge pump 2. when the voltage level at pin 25 is between approximately 2·25V and 2·75V, LOCK DETECT (pin 27) will be low and charge pump 1 disabled, depending on the PD1 and PD2 programming bits as shown in Table 4. The output signals from the R and M counters are available on pins 4 and 5 (FPD and FREF) when programmed by the reference programming word; the various options are shown in Table 4. An external phase detector may be connected to pins 4 and 5 and may be used independently or in conjunction with the on-chip phase detector. To allow for control direction changes introduced by the design of the control loop, a control bit in the F1/F2 programming word interchanges the inputs to the on-chip phase detector and reverses the functions on pins 4 and 5 (see Table 2). F1 or F2 word G2 G1 Charge pump 1 current (µA) Charge pump 2 multiplier 0 1 0 1 0 0 1 1 50 75 125 200 1 1·5 2·5 4 Table 1 Charge pump currents Output for RF phase lag F1/F2 sense bit Pins 3 and 25 Pin 4 Pin 5 0 1 Current source Current sink FPD FREF FREF FPD Table 2 Data Entry and Storage The data section of the SP8853 consists of a data input interface, a data shift register and three data buffers. Data is entered to the data input interface via a three-wire highway, with DATA (pin 24), CLOCK (pin 15) and ENABLE (pin16) inputs. The input interface routes the data into a 24bit shift register with bus connections to three data buffers. Data entered via the serial bus is transferred to the appropriate data buffer on the negative transition of the data enable input according to the two final data bits C1 and C2 as shown in Table 3. The MSB of the data is entered first. 2-bit SR contents Buffer loaded C2 C1 0 1 0 0 0 1 F1 F2 Transfer A counter bits (N0:N3) into 4-bit buffer (see Figs. 2 and 7) 1 1 Reference Table 3 The dual F1/F2 buffer can receive two 22-bit words and controls the programmable divider A and M counters using 19 bits, the phase detector gain with two bits and the phase detector sense with one bit. A fourth input from the synthesiser control system selects the active buffer. The third buffer contains only 16 bits, 13 being used to set the reference divider division ratio and 2 to control the phase detector enable logic. The remaining bit sets the dual modulus prescaler N ratio. The data words may be entered in any individual multiple sequence and the shift register can be updated whils the data buffers retain control of the synthesiser with the previously loaded data. This enables four unique data words to be stored in the device, with three in the data buffers and a fourth in the shift register, while the chip is enabled. The F1 word may also be updated while F2 is controlling the programmable divider and vice-versa. The dual F1/F2 buffer enables allows the device to be toggled between two frequencies using the F1/F2 select input at a rate determined by the comparison frequency and also permits random frequency hopping at a rate determined by a btye load period; this is possible because the loop can be locked to F1 while F2 is updated by entering new data via the shift register. The F1/F2 input is high to select F1. 5 SP8853 Data Sheet unused bit in the 22-bit F1/F2 buffer. This bit must always be set to zero when the 48/9 mode is required. Various programming sequences are shown in Fig. 7. The data entry and storage registers are always powered up, making it possible to enter data when the device is in the powered down state. An F1 or F2 update cycle will consist of a byte containing 24 bits whereas the reference byte will contain 18 bits. The device requires 3 bytes, each with a chip select sequence, totalling 66 bits to fully program. When the dual modulus A counter is set to 48/9, the data required to set the counter is reduced by one bit, leaving an PD2 PD2 Result 0 0 FREF and FPD outputs off, charge pumps 1 and 2 on 1 0 FREF and FPD outputs on, charge pump 1 off, charge pump 2 on 0 1 FREF and FPD outputs off, charge pump 1 disabled by lock detect, charge pump 2 on 1 1 FREF and FPD outputs on, charge pump 1 disabled by lock detect, charge pump 2 on Table 4 LOOP FILTER FREF 15V 15V FPD 15V C2 C1 Rx 2·2k R2 SL562 15V − + Rb 4 Rx VCC 2 3 2 1 28 27 5 25 6 24 7 23 SP8853 8 RPD Rb > 26 0·25 PD2 current 15V 22 9 21 10 20 11 19 33p 1n VOLTAGE CONTROLLED OSCILLATOR 12 0·1µ 13 14 15 16 CONTROL MICRO VCC FROM CHARGE PUMP 19 10k Ra EXTERNAL REFERENCE SOURCE 3 2 1 28 SP8853 27 TO VCO 26 25 24 VARICAP SUPPLY 15V Cd NC 1n VCC TO LOOP AMPLIFIER 20 18 1n Fig. 6a Typical application 21 17 39p LOOP FILTER 470 Ra 22k Fig. 6b Connection of external reference 0·25 Ra > 23 PD2 current Fig. 6c Use of lock detect circuit with PD1 Fig. 6 Application diagrams 6 Fig. 6d Simple discrete amplifier SP8853 Data Sheet PHASE DETECTOR GAIN CONTROL (SEE TABLE 1) MSB 217 216 215 214 213 212 211 210 29 28 27 26 25 24 23 22 21 20 C2 C1 G2 G1 LSB 218 15-BIT PROGRAMMABLE COUNTER (M COUNTER) PHASE DETECTOR SENSE BIT (SEE TABLE 2) 4-BIT PROGRAMMABLE COUNTER (A COUNTER) Fig. 7a F1 or F2 word, bit allocation with 416/17 selected PHASE DETECTOR GAIN CONTROL (SEE TABLE 1) MUST BE ZERO 215 214 213 212 211 210 29 28 27 26 25 24 23 0 15-BIT PROGRAMMABLE COUNTER (M COUNTER) PHASE DETECTOR SENSE BIT (SEE TABLE 2) 22 21 20 C2 C1 216 G2 G1 LSB 217 MSB CONTROL LOGIC (SEE TABLE 3) 3-BIT CONTROL PROGRAMMABLE LOGIC COUNTER (SEE (A COUNTER) TABLE 3) Fig. 7b F1 or F2 word, bit allocation with 48/9 selected DUAL MODULUS N RATIO SELECT 0 = 416/17 1 = 48/9 MSB LSB 212 211 210 29 28 27 26 25 24 23 22 21 20 C2 C1 PD1 PD2 13-BIT PROGRAMMABLE COUNTER (R COUNTER) PHASE DETECTOR BISTABLE CONTROL (SEE TABLE 4) CONTROL LOGIC (SEE TABLE 3) Fig. 7c Reference word bit allocation F1 WORD 22 BITS F2 WORD 0 0 22 BITS REF WORD 1 0 22 BITS 1 1 DATA 22 CLOCKS 22 CLOCKS 22 CLOCKS DATA CLOCK CHIP SELECT DATA LOADS ON FALLING EDGES Fig. 7d Data load sequence Fig. 7 Data format diagrams 7 SP8853 Data Sheet VCC1 13·25k 500 1250 VCC4 6k 1250 6k VCC4 62·5k 12k 12k 500 10 3, 14, 6 77·5k RF INPUT 15, 16 11 24k RF INPUT 10k 50µA 0·8mA 176k 37·5k 50µA VEE1 27·5µA VEE4 Fig. 8a RF preamplifer inputs Fig. 8b F1/F2 data and power down inputs VEE4 Fig. 8c Hysteresis inputs, data clock and enable VCC4 (CP1) / VCC3 (CP2) VCC2 VCC3 24k 20 f UP 21 80k f UP 3, 25 VEE VCC 27 100µA f DOWN f DOWN 35k VEE3 50µA VEE2 VEE4 (CP1) / VEE3 (CP2) Fig. 8d Oscillator pins Fig. 8e Lock detect output Fig. 8f Phase detector charge pumps VCC4 10k VCC3 EXTERNAL RESISTOR RPD (See Table 1) FROM M OR R COUNTERS 24 4, 5 OUTPUT ENABLE VEE3 100µA 50µA VEE4 Fig. 8g Charge pump 2 current programming Fig. 8h FPD and FREF outputs Fig. 8 Input and output interface diagrams 8 SP8853 Data Sheet DESCRIPTION A basic application using a single phase detector is shown in Fig. 6a. The SP8853 is a 1·3GHz part so good RF design techniques should be employed, including the use of a ground plane and suitable high frequency capacitors at the RF input and for power supply decoupling. The RF input should be coupled to either pin 10 or pin 11, with the other pin decoupled to ground. The reference oscillator is of conventional Colpitts type, with two capacitors required to provide a low impedance tap for the feedback signal to the transistor emitter. Typical values are shown in Fig. 6a, although these may be varied to suit the loading requirements of particular crystals. Where a suitable reference signal already exists or where a very stable source is required, it is possible to apply an external reference as shown in Fig. 6b. The amplitude should be kept below 0·5Vrms to avoid forward biasing the transistor’s collector-base junction. Lock Detect and Charge Pump Operation In some systems, it is useful to have an indication of phase lock. This function is provided on pin 27 (LOCK DETECT), which goes low when the output of charge pump 2 (PD2) is between 2·25V and 2·75V and can be used to drive an LED to give visual indication of phase lock. Alternatively, a pullup resistor may be connected from pin 27 to VCC and the output used to signal to the control microprocessor that the loop is locked, thus speeding up system operation. The output current available from pin 27 is limited to 1·5mA; if this is exceeded, the logic low level will be uncertain. The circuit diagram of Fig. 6a is a basic application with minimum component count but which is neverthless perfectly adequate for many applications. Charge pump 1 output (pin3) is used to drive the loop amplifier which provides the control voltage for the VCO. When charge pump 1 is used in this mode, the PD1 and PD2 bits in the reference programming word must be set to enable charge pump 1 continuously (see Table 4). This application could also use charge pump 2 output (pin 25) or, if a higher phase detectot gain is required, pins 3 and 25 could be connected in parallel to use the combined output current from both charge pumps. The lock detect circuit can be programmed to automatically disable charge pump 1 as shown in Table 4. This feature can be used to reduce the system lock up time by connecting the charge pump outputs in parallel to the loop amplifier with resistor Rb connected in series with charge pump 2 output. This connection allows a relatively high current to be used from charge pump 1 to give a short lock up time, and a low charge pump 2 current to be set to give low reference frequency sidebands. The degree of lock up time improvement depends on the ratio of charge pump 1 and charge pump 2 currents. When the loop is out of lock, both charge pumps will be enabled and will feed current to the loop amplifier to bring the VCO to phase lock. The current from charge 2 will produce a voltage drop across Rb, allowing operation of the lock detect circuit and enabling charge pump 1. The value of Rb must be chosen to give a voltage drop greater than 0·25V at the current level programmed for charge pump 2. When phase lock is achieved, there will be no charge pump current and therefore the voltage at pin 25 will be equal to that on the virtual earth point of the loop amplifier (2·5V), disabling charge pump 1. Charge pump 1 should not be left open circuit when enabled as this would prevent correct operation of the phase detector. The output on pin 3 should be biased to half supply with a pair of 4·7kΩ resistors connected across supplies. When charge pump 2 is used to drive the loop amplifier, the lock detect circuit will only give an out of lock indication when large frequency changes are made or when a frequency outside the range of the VCO is programmed. at other times the loop amplifier is maintained at 2·5V by the action of the loop filter components. Again, a resistor connected between pin 25 and the loop amplifier, producing a voltage drop greater than 0·25V at the charge current programmed will allow sensitive out of lock detection. When phase lock detection is required using charge pump 1 only, charge pump 2 output should be biased to 2·5V, using two equal value resistors, Ra, across the supply as shown in Fig. 6c. A small capacitor, Cd, connected frompin 28 to ground may be used to reduce chatter at the lock detect output. A detailed block diagram of the lock detect circuit is shown in Fig. 3. Choice of Loop Amplifier The loop amplifier converts the charge pump current pulses into a voltage of a magnitude suitable for driving the chosen VCO. The choice of amplifier is determined by the voltage swing required at the VCO to achieve the necessary range. In most cases, an operational amplifier will be used to provide the essential characteristcs of high input impedance, high gain and low output impedance required in this application. A simple discrete design could also be used as shown in Fig. 6d. This arrangement can be particularly useful where the minimum VCO control voltage must be close to ground and where negative supplies are inconvenient. This form of amplifier is not suitable for use with charge pump 2 when the lock detect circuit is required. When an operational amplifier is used in the inverting configuration shown in Fig. 6a, the charge pump output is connected directly to the virtual earth point and will therefore operate a a voltage close to that set on the non-inverting input. Normally, this operating point should be set at half supply using a potential divider of two equal value resistors, Rx, but if necessary the voltage can be set up to 1V higher or lower without detrimental effect. When the lock detect function is required on charge pump 2 however, the non-inverting input must be at half supply. The digital phase detector and charge pump in the SP8853 produces bi-directional current pulses in order to correct errors between the reference and the VCO divider outputs. Once synchronisation is achieved, in theory no further output from the charge pump should be required. In practice, due to leakage currents and particularly the input current of the amplifier, the capacitors in the loop filter will gradually discharge, modifying the VCO control voltage and requiring further outputs from the charge pump to restore the charge. The effect of this continuous correction is to frequency modulate the VCO frequency and thus produce sidebands at the reference frequency. In order to reduce this effect to a minimum, an amplifier with low input bias is essential. 9 SP8853 Data Sheet C1 FROM PHASE DETECTOR R1 C1 R2 − + TO VCO + C2 Fig. 9 Standard form of second order loop filter Fig. 10 Modified form of second order loop filter LOOP CALCULATIONS Many frequency synthesiser designs use a second order loop with a loop filter of the form shown in Fig. 9. In practice, an additional RC time constant (shown dashed in Fig. 9) is often added to reduce noise from the amplifier. In addition, any feedthrough capacitor or local decoupling at the VCO will be added to the value of C2. These additional components in fact form a third order loop and, if the values are chosen correctly, the additional filtering provided can considerably reduce the level of reference frequency sidebands and noise without adversely affecting the loop settling time. The calculations of values for both types of loop are shown below. Example Calculate values for a second order loop with the following parameters: Frequency to be synthesised = 800MHz Reference frequency =100kHz 800MHz Division ration N = 100kHz = 8000 6 t1 = 0·079632p310 2 From equation (1), (2p3500) 383103 ∴t1 = 6·334µs t2 = 230·7071 From equation (2), 2p3500 Second Order Loop ∴t2 = 450µs For this filter, two equations are required to determine the time constants t1 (= C1R1) and t2 (= C1R2); the equations are: KK t1 = u2 0 vn N t2 = 2z vn …(1) …(2) where Ku is the phase detector gain factor in V/radian K0 is the VCO gain factor = 2p310MHz/V N is the division ratio from VCO to reference frequency vn is the natural loop frequency = 500Hz z is the damping factor = 0·7071 The SP8853 phase detector is a current source rather than a conventional voltage source and has a gain factor specified in µA/radian. Since the equations deal with a filter where R1 is feeding the virtual earth point of an operational amplifier from a voltage source, R1 sets the input current to the filter – similar to the circuit shown in Fig. 10 – where a current source phase detector is connected directly to the virtual earth point of the operational amplifier. The equivalent voltage gain of the phase detector can be calculated by assuming a value for R1 and calculating a gain in V/radian which would produce the set current. The digital phase detector used in the SP8853 is linear over a range of 2p radians and therefore the phase detector gain is given by: Phase detector current setting µA/radian 2p For R1 = 1kΩ and assuming a value of phase detector current of 50µA, the phase detector gain is therefore: 50µA Ku = 3103 2p Ku = Now, since t1 = C1R1 , and, since t2 = C1R2 , This value can now be inserted in equation 1 to obtain a value for C1 and equation 2 used to determine a value for R2. C1 = 6·334310 103 ∴C1 = 6·33nF 26 24 R2 = 4·5310 29 6·33310 ∴R2 = 71kΩ Third Order Loop The third order loop is normally as shown in Fig. 11. Fig. 12 shows the circuit redrawn to use an RC time constant after the amplifier, allowing any feedthrough capacitance on the VCO line to be included in the loop calculations. Where the modified form in Fig. 12 is used, it is advantageous to connect a small capacitor CX of typically 100pF (shown dashed) across R2 to reduce sidebands caused by the amplifier being forced into non-linear operation by the phase comparator pulses Three equations are required to determine the time constants t1, t2, and t3, where for Fig. 11 t1 = C1R1 t2 = R2 (C11C2) t3 = C2R2 and for Fig. 12 t1 = C1R1 t2 = C1R2 t3 = C2R3 The equations are: 1 t1 = t2 = = 0·00796V/radian 10 − PHASE DETECTOR R3 R2 t3 = KuK0 11vn2 t22 2 vn2N 11vn2 t32 1 …(3) …(4) vn2t32 1 2tan F0 1 cos F0 vn …(5) SP8853 Data Sheet Cx C2 C1 C1 R2 R1 FROM CHARGE PUMP FROM CHARGE PUMP − TO VCO + Fig. 11 Standard form of third order loop filter − R3 TO VCO + C3 Fig. 12 Modified form of third order loop filter where Ku, K0, N and vn are as defined for the second order loop and F0 is the phase margin, normally set to 45°. These values can now be substituted in equation (3) to obtain a value for C1 and in equations (4) and (5) to determine values for C2 and R2. For Fig. 11, t2 = R2 (C11C2) For Fig. 12, t3 = C2R2 Substituting for C2: t2 = R2 C11t3 = R2 C11t3 Example Calculate values for a third order loop with parameters as for the second order loop and F0 = 45°. From equation (5): 1 2tan 45°1 cos 45° t3 = 500Hz32 p = R2 R1 or, R2= R2 t22t3 C1 7·6873102421·31831024 0·015331026 ∴R2 = 41·627kΩ = 0·4142 3161·6 t3 = C2R2 = t3 ∴t3 = 131·8µs R2 From equation (4): 1·31831024 41627 ∴C2 = 3·17nF = t2 = 1 (500323p)231·31831024 ∴t2 = 768·7µs For Fig. 12, Using these values in equation (3): t1 = where A = 23 7·96310 32p310MHz/V 80003(50032p)2 1 2 3[A] 11vn2 t22 11vn2 t32 t1 = C1R1 1·5331025 103 ∴C1 = 0·0153nF or, C1 = t2 = C1R2 11(50032p)23(7·68731024)2 = 11(50032p)23(1·31831024)2 1 2 t1 = 500141·6 10 6·832 7·896110 1·1714 = 6·3343102632·415 ∴t1 = 15·3µs 1·5331025 Now, since t1 = C1R1 and R1 =1kΩ, C1 = 103 ∴C1 = 0·0153µF 7·68731024 1·5331028 ∴R2 = 50·242kΩ or, R2 = t3 = C2R3 Since the values of C2 and R3 are independent of the other components, either can be chosen and the other determined. Assuming that R3 = 1kΩ, then 1·31831024 103 ∴C2 = 0·01318µF C2 = 11 For more information about all Zarlink products visit our Web Site at www.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. 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