MM54C175/MM74C175 Quad D Flip-Flop General Description All inputs are protected from static discharge by diode clamps to VCC and GND. The MM54C175/MM74C175 consists of four positive-edge triggered D type flip-flops implemented with monolithic CMOS technology. Both are true and complemented outputs from each flip-flop are externally available. All four flipflops are controlled by a common clock and a common clear. Information at the D inputs meeting the set-up time requirements is transferred to the Q outputs on the positivegoing edge of the clock pulse. The clearing operation, enabled by a negative pulse at Clear input, clears all four Q outputs to logical ‘‘0’’ and Q’s to logical ‘‘1’’. Features Y Y Y Y Wide supply voltage range Guaranteed noise margin High noise immunity Low power TTL compatibility 3V to 15V 1.0V 0.45 VCC (typ.) Fan out of 2 driving 74L Connection Diagram & Truth Table Dual-In-Line Package TL/F/5900 – 1 Top View Order Number MM54C175 or MM74C175 Each Flip-Flop Inputs Outputs Clear Clock D Q Q L H H H H X X H L X X L H L NC NC H L H NC NC u u H L H e High level L e Low level X e Irrelevant e Transition from low to high level NC e No change u C1995 National Semiconductor Corporation TL/F/5900 RRD-B30M105/Printed in U. S. A. MM54C175/MM74C175 Quad D Flip-Flop February 1988 Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Voltage at Any Pin Storage Temperature Range b 0.3V to VCC a 0.3V Operating Temperature Range MM54C175 MM74C175 b 65§ C to a 150§ C Power Dissipation (PD) Dual-In-Line Small Outline Operating VCC Range b 55§ C to a 125§ C b 40§ C to a 85§ C 700 mW 500 mW 3V to 15V 18V Absolute Maximum VCC Lead Temperature (Soldering, 10 seconds) 260§ C DC Electrical Characteristics Min/Max limits apply across temperature range unless otherwise specified Symbol Parameter Conditions Min Typ Max Units CMOS TO CMOS VIN(1) Logical ‘‘1’’ Input Voltage VCC e 5V VCC e 10V 3.5 8.0 VIN(0) Logical ‘‘0’’ Input Voltage VCC e 5V VCC e 10V VOUT(1) Logical ‘‘1’’ Output Voltage VCC e 5V, IO e b10 mA VCC e 10V, IO e b10 mA VOUT(0) Logical ‘‘0’’ Output Voltage VCC e 5V, IO e 10 mA VCC e 10V, IO e 10 mA IIN(1) Logical ‘‘1’’ Input Current VCC e 15V, VIN e 15V IIN(0) Logical ‘‘0’’ Input Current VCC e 15V, VIN e 0V ICC Supply Current VCC e 15V V V 1.5 2.0 4.5 9.0 V V 0.5 1.0 0.005 b 1.0 V V 1.0 b 0.005 0.05 V V mA mA 300 mA CMOS/LPTTL INTERFACE VIN(1) Logical ‘‘1’’ Input Voltage 54C, VCC e 4.5V 74C, VCC e 4.75V VIN(0) Logical ‘‘0’’ Input Voltage 54C, VCC e 4.5V 74C, VCC e 4.75V VOUT(1) Logical ‘‘1’’ Output Voltage 54C, VCC e 4.5V, IO e b360 mA 74C, VCC e 4.75V, IO e b360 mA VOUT(0) Logical ‘‘0’’ Output Voltage 54C, VCC e 4.5V, IO e 360 mA 74C, VCC e 4.75V, IO e 360 mA VCC b 1.5 VCC b 1.5 V V 0.8 0.8 2.4 2.4 V V V V 0.4 0.4 V V OUTPUT DRIVE (See 54C/74C Family Characteristics Data Sheet) (Short Circuit Current) ISOURCE Output Source Current (P-Channel) VCC e 5V, TA e 25§ C, VOUT e 0V ISOURCE Output Source Current (P-Channel) ISINK ISINK b 1.75 b 3.3 mA VCC e 10V, TA e 25§ C, VOUT e 0V b 8.0 b 15 mA Output Sink Current (N-Channel) VCC e 5V, TA e 25§ C, VOUT e VCC 1.75 3.6 mA Output Sink Current (N-Channel) VCC e 10V, TA e 25§ C, VOUT e VCC 8.0 16 mA Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’ they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device operation. 2 AC Electrical Characteristics* TA e 25§ C, CL e 50 pF, unless otherwise noted Typ Max Units tpd Symbol Propagation Delay Time to a Logical ‘‘0’’ or Logical ‘‘1’’ from Clock to Q or Q Parameter VCC e 5V VCC e 10V Conditions Min 190 75 300 110 ns ns tpd Propagation Delay Time to a Logical ‘‘0’’ from Clear to Q VCC e 5V VCC e 10V 180 70 300 110 ns ns tpd Propagation Delay Time to a Logical ‘‘1’’ from Clear to Q VCC e 5V VCC e 10V 230 90 400 150 ns ns tS Time Prior to Clock Pulse that Data Must be Present VCC e 5V VCC e 10V 100 40 45 16 ns ns tH Time After Clock Pulse that Data Must be Held VCC e 5V VCC e 10V 0 0 b 11 b4 ns ns tW Minimum Clock Pulse Width VCC e 5.0V VCC e 10V 130 45 250 100 ns ns tW Minimum Clear Pulse Width VCC e 5.0V VCC e 10V 120 45 250 100 ns ns tr Maximum Clock Rise Time VCC e 5V VCC e 10V 15 5.0 450 125 ms ms tf Maximum Clock Fall Time VCC e 5V VCC e 10V 15 5.0 50 50 ms ms fMAX Maximum Clock Frequency VCC e 5V VCC e 10V 2.0 5.0 3.5 10 MHz MHz CIN Input Capacitance Clear Input (Note 2) Any Other Input 10 5.0 pF pF CPD Power Dissipation Capacitance Per Package (Note 3) 130 pF *AC Parameters are guaranteed by DC correlated testing. Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’ they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device operation. Note 2: Capacitance is guaranteed by periodic testing. Note 3: CPD determines the no load AC power consumption of any CMOS device. For complete explanation see 54C/74C Family Characteristics Application Note AN-90. Switching Time Waveforms CMOS to CMOS TL/F/5900 – 6 3 Logic Diagram Typical One of Four TL/F/5900 – 4 TL/F/5900 – 5 TL/F/5900 – 2 TL/F/5900–3 4 Physical Dimensions inches (millimeters) Ceramic Dual-In-Line Package (J) Order Number MM54C175J or MM74C175J NS Package Number J16A 5 MM54C175/MM74C175 Quad D Flip-Flop Physical Dimensions inches (millimeters) (Continued) Molded Dual-In-Line Package (N) Order Number MM54C175N or MM74C175N NS Package Number N16E LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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