Revised January 1999 MM74C174 Hex D-Type Flip-Flop General Description Features The MM74C174 hex D-type flip-flop is a monolithic complementary MOS (CMOS) integrated circuit constructed with N- and P-channel enhancement transistors. All have a direct clear input. Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clear is independent of clock and accomplished by a low level at the clear input. All inputs are protected by diodes to VCC and GND. ■ Wide supply voltage range: 3.0V to 15V ■ Guaranteed noise margin: ■ High noise immunity: 1.0V 0.45 VCC (typ.) ■ Low power TTL compatibility: Fan out of 2 driving 74L Ordering Code: Order Number Package Number Package Description MM74C174M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow MM74C174N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagram Truth Table Pin Assignments for DIP and SOIC Inputs Output Clear Clock D L X X Q L H ↑ H H H ↑ L L H L X Q Top View © 1999 Fairchild Semiconductor Corporation DS005899.prf www.fairchildsemi.com MM74C174 Hex D-Type Flip-Flop October 1987 MM74C174 Logic Diagrams www.fairchildsemi.com 2 Absolute Maximum VCC −0.3V to VCC +0.3V Voltage at Any Pin Operating Temperature Range Storage Temperature Range (Soldering, 10 seconds) −40°C to +85°C −65°C to +150°C 700 mW Small Outline 500 mW Operating VCC Range 260°C Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Except for “Operating Temperature Range” they are not meant to imply that the devices should be operated at these limits. The Electrical Characteristics table provides conditions for actual device operation. Power Dissipation (PD) Dual-In-Line 18V Lead Temperature 3.0V to 15V DC Electrical Characteristics Min/Max limits apply across temperature range unless otherwise specified Symbol Parameter Conditions Min Typ Max Units CMOS TO CMOS VIN(1) VIN(0) VOUT(1) VOUT(0) Logical “1” Input Voltage Logical “0” Input Voltage Logical “1” Output Voltage Logical “0” Output Voltage VCC = 5V 3.5 V VCC = 10V 8.0 V VCC = 5V 1.5 V VCC = 10V 2.0 V VCC = 5V, IO = −10 µA 4.5 V VCC = 10V, IO = −10 µA 9.0 V VCC = 5V, IO = 10 µA 0.5 V VCC = 10V, IO = 10 µA 1.0 V 1.0 µA IIN(1) Logical “1” Input Current VCC = 15V, VIN = 15V IIN(0) Logical “0” Input Current VCC = 15V, VIN = 0V ICC Supply Current VCC = 15V 0.005 −1.0 −0.005 0.05 µA 300 µA 0.8 V CMOS/LPTTL INTERFACE VIN(1) Logical “1” Input Voltage VCC = 4.75V VIN(0) Logical “0” Input Voltage VCC = 4.75V VCC−1.5 VOUT(1) Logical “1” Output Voltage VCC = 4.75V, IO = −360 µA VOUT(0) Logical “0” Output Voltage VCC = 4.75V, IO = 360 µA V 2.4 V 0.4 V OUTPUT DRIVE (See Family Characteristics Data Sheet) (short circuit current) ISOURCE ISOURCE ISINK ISINK Output Source Current VCC = 5V (P-Channel) TA = 25°C, VOUT = 0V Output Source Current VCC = 10V (P-Channel) TA = 25°C, VOUT = 0V Output Sink Current VCC = 5V (N-Channel) TA = 25°C, VOUT = 0V Output Sink Current VCC = 5V (N-Channel) TA = 25°C, VOUT = 0V 3 −1.75 −3.3 mA −8.0 −15 mA 1.75 3.6 mA 8.0 16 mA www.fairchildsemi.com MM74C174 Absolute Maximum Ratings(Note 1) MM74C174 AC Electrical Characteristics (Note 2) TA = 25°C, CL = 50 pF, unless otherwise noted Symbol tpd tpd tS1, tS0 tH1, tH0 tW tW Typ Max Propagation Delay Time to a Logical Parameter VCC = 5V Conditions Min 150 300 Units ns “0” or Logical “1” from Clock to Q VCC = 10V 70 110 ns Propagation Delay Time to VCC = 5V 110 300 ns a Logical “0” from Clear VCC = 10V 50 110 ns Time Prior to Clock Pulse that VCC = 5V 75 ns Data Must be Present VCC = 10V 25 ns Time after Clock Pulse VCC = 5V 0 −10 ns that Data Must be Held VCC = 10V 0 −5.0 ns Minimum Clock Pulse Width VCC = 5V 50 250 ns VCC = 10V 35 100 ns VCC = 5V 65 140 ns VCC = 10V 35 70 ns Minimum Clear Pulse Width Maximum Clock Rise and VCC = 5V 15 >1200 Fall Time VCC = 10V 5.0 >1200 µs fMAX Maximum Clock Frequency VCC = 5V 2.0 6.5 MHz VCC = 10V 5.0 CIN Input Capacitance tr, tf CPD Power Dissipation Capacitance µs 12 MHz Clear Input (Note 3) 11 pF Any Other Input 5.0 pF Per Package (Note 4) 95 pF Note 2: AC Parameters are guaranteed by DC correlated testing. Note 3: Capacitance is guaranteed by periodic testing. Note 4: CPD determines the no load AC power consumption of any CMOS device. For complete explanation see Family Characteristics Application Note AN-90. AC Test Circuit Switching Time Waveforms CMOS to CMOS tr = tf = 20 ns www.fairchildsemi.com 4 MM74C174 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Package Number M16A 5 www.fairchildsemi.com MM74C174 Hex D-Type Flip-Flop Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N16E LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.