DINTEK DTU2N60

DT81
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Power MOSFET
FEATURES
PRODUCT SUMMARY
• Halogen-free According to IEC 61249-2-21
Definition
• Dynamic dV/dt Rating
• Repetitive Avalanche Rated
• Surface Mount (IRFRC20, SiHFRC20)
• Straight Lead (IRFUC20, SiHFUC20)
• Available in Tape and Reel
• Fast Switching
• Ease of Paralleling
• Compliant to RoHS Directive 2002/95/EC
600
VDS (V)
RDS(on) (Ω)
VGS = 10 V
Qg (Max.) (nC)
4.4
18
Qgs (nC)
3.0
Qgd (nC)
8.9
Single
Configuration
D
DPAK
(TO-252)
IPAK
(TO-251)
D
D
G
G
S
G
D S
S
N-Channel MOSFET
ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted
PARAMETER
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current
SYMBOL
VDS
VGS
VGS at 10 V
TC = 25 °C
TC = 100 °C
Currenta
ID
Pulsed Drain
IDM
Linear Derating Factor
Linear Derating Factor (PCB Mount)e
EAS
Single Pulse Avalanche Energyb
Repetitive Avalanche Currenta
IAR
Repetitive Avalanche Energya
EAR
Maximum Power Dissipation
TC = 25 °C
PD
Maximum Power Dissipation (PCB Mount)e
TA = 25 °C
Peak Diode Recovery dV/dtc
dV/dt
Operating Junction and Storage Temperature Range
TJ, Tstg
Soldering Recommendations (Peak Temperature)
for 10 s
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. VDD = 50 V, starting TJ = 25 °C, L = 37 mH, Rg = 25 Ω, IAS = 2.0 A (see fig. 12).
c. ISD ≤ 2.0 A, dI/dt ≤ 40 A/μs, VDD ≤ VDS, TJ ≤ 150 °C.
d. 1.6 mm from case.
e. When mounted on 1" square PCB (FR-4 or G-10 material).
LIMIT
600
± 20
2.0
1.3
8.0
0.33
0.020
74
2.0
4.2
42
2.5
3.0
- 55 to + 150
260d
UNIT
V
A
W/°C
mJ
A
mJ
W
V/ns
°C
* Pb containing terminations are not RoHS compliant, exemptions may apply
1
DT81
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THERMAL RESISTANCE RATINGS
SYMBOL
MIN.
TYP.
MAX.
Maximum Junction-to-Ambient
PARAMETER
RthJA
-
-
110
Maximum Junction-to-Ambient
(PCB Mount)a
RthJA
-
-
50
Maximum Junction-to-Case (Drain)
RthJC
-
-
3.0
UNIT
°C/W
Note
a. When mounted on 1" square PCB (FR-4 or G-10 material).
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-Source Breakdown Voltage
VDS Temperature Coefficient
Gate-Source Threshold Voltage
VDS
VGS = 0 V, ID = 250 μA
600
-
-
V
ΔVDS/TJ
Reference to 25 °C, ID = 1 mA
-
0.88
-
V/°C
VGS(th)
VDS = VGS, ID = 250 μA
2.0
-
4.0
V
Gate-Source Leakage
IGSS
VGS = ± 20 V
-
-
± 100
nA
Zero Gate Voltage Drain Current
IDSS
VDS = 600 V, VGS = 0 V
-
-
100
VDS = 480 V, VGS = 0 V, TJ = 125 °C
-
-
500
Drain-Source On-State Resistance
Forward Transconductance
RDS(on)
gfs
ID = 1.2 Ab
VGS = 10 V
VDS = 50 V, ID = 1.2 A
μA
-
-
4.4
Ω
1.4
-
-
S
-
350
-
-
48
-
-
8.6
-
-
-
18
Dynamic
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
Total Gate Charge
Qg
Gate-Source Charge
Qgs
-
-
3.0
Gate-Drain Charge
Qgd
-
-
8.9
Turn-On Delay Time
td(on)
-
10
-
tr
-
23
-
-
30
-
-
25
-
-
4.5
-
-
7.5
-
-
-
2.0
-
-
8.0
-
-
1.6
-
290
580
ns
-
0.67
1.3
μC
Rise Time
Turn-Off Delay Time
Fall Time
td(off)
VGS = 0 V,
VDS = - 25 V,
f = 1.0 MHz, see fig. 5
VGS = 10 V
ID = 2.0 A, VDS = 360 V,
see fig. 6 and 13b
VDD = 300 V, ID = 2.0 A,
Rg = 18 Ω, RD = 135 Ω, see fig. 10b
tf
Internal Drain Inductance
LD
Internal Source Inductance
LS
Between lead,
6 mm (0.25") from
package and center of
die contact
pF
nC
ns
D
nH
G
S
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
IS
Pulsed Diode Forward Currenta
ISM
Body Diode Voltage
VSD
Body Diode Reverse Recovery Time
trr
Body Diode Reverse Recovery Charge
Qrr
Forward Turn-On Time
ton
MOSFET symbol
showing the
integral reverse
p - n junction diode
A
G
S
TJ = 25 °C, IS = 2.0 A, VGS = 0 Vb
TJ = 25 °C, IF = 2.0 A, dI/dt = 100 A/μsb
V
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width ≤ 300 μs; duty cycle ≤ 2 %.
2
D
DT81
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TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
Fig. 1 - Typical Output Characteristics, TC = 25 °C
Fig. 2 - Typical Output Characteristics, TC = 150 °C
Fig. 3 - Typical Transfer Characteristics
Fig. 4 - Normalized On-Resistance vs. Temperature
3
DT81
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4
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
Fig. 7 - Typical Source-Drain Diode Forward Voltage
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
Fig. 8 - Maximum Safe Operating Area
DT81
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RD
VDS
VGS
D.U.T.
Rg
+
- VDD
10 V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
Fig. 10a - Switching Time Test Circuit
VDS
90 %
10 %
VGS
td(on)
tr
td(off) tf
Fig. 9 - Maximum Drain Current vs. Case Temperature
Fig. 10b - Switching Time Waveforms
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
5
DT81
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L
Vary tp to obtain
required IAS
VDS
VDS
tp
VDD
D.U.T
Rg
+
-
I AS
V DD
VDS
10 V
0.01 Ω
tp
Fig. 12a - Unclamped Inductive Test Circuit
IAS
Fig. 12b - Unclamped Inductive Waveforms
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
Current regulator
Same type as D.U.T.
50 kΩ
QG
VGS
12 V
0.2 µF
0.3 µF
QGS
QGD
+
D.U.T.
VG
-
VDS
VGS
3 mA
Charge
IG
ID
Current sampling resistors
Fig. 13a - Basic Gate Charge Waveform
6
Fig. 13b - Gate Charge Test Circuit
DT81
www.din-tek.jp
Peak Diode Recovery dV/dt Test Circuit
+
D.U.T.
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
-
-
Rg
•
•
•
•
+
dV/dt controlled by Rg
Driver same type as D.U.T.
ISD controlled by duty factor “D”
D.U.T. - device under test
+
-
VDD
Driver gate drive
P.W.
Period
D=
P.W.
Period
VGS = 10 Va
D.U.T. lSD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
Inductor current
VDD
Body diode forward drop
Ripple ≤ 5 %
ISD
Note
a. VGS = 5 V for logic level devices
Fig. 14 - For N-Channel
7
Package Information
www.din-tek.jp
TO-252AA (HIGH VOLTAGE)
E
b3
E1
L3
D1
D
H
L4
b2
b
A
c2
e
A1
L1
L
c
θ
L2
MILLIMETERS
INCHES
DIM.
MIN.
MAX.
MIN.
MAX.
E
6.40
6.73
0.252
0.265
L
1.40
1.77
0.055
L1
2.743 REF
L2
0.070
0.108 REF
0.508 BSC
0.020 BSC
L3
0.89
1.27
0.035
0.050
L4
0.64
1.01
0.025
0.040
D
6.00
6.22
0.236
0.245
H
9.40
10.40
0.370
0.409
b
0.64
0.88
0.025
0.035
b2
0.77
1.14
0.030
0.045
b3
5.21
5.46
0.205
e
2.286 BSC
0.215
0.090 BSC
A
2.20
2.38
0.087
0.094
A1
0.00
0.13
0.000
0.005
c
0.45
0.60
0.018
0.024
c2
0.45
0.58
0.018
0.023
D1
5.30
-
0.209
-
E1
4.40
-
0.173
-
θ
0'
10'
0'
10'
ECN: S-81965-Rev. A, 15-Sep-08
DWG: 5973
Notes
1. Package body sizes exclude mold flash, protrusion or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 0.10 mm per side.
2. Package body sizes determined at the outermost extremes of the plastic body exclusive of mold flash, gate burrs and interlead flash, but
including any mismatch between the top and bottom of the plastic body.
3. The package top may be smaller than the package bottom.
4. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.10 mm total in excess of "b" dimension at maximum
material condition. The dambar cannot be located on the lower radius of the foot.
1
Package Information
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TO-251AA (HIGH VOLTAGE)
4
3
E1
E
Thermal PAD
4
b4
θ2
4
A
0.010 0.25 M C A B
L2 4
c2
A
θ1
B
D
D1
A
C
3
Seating
plane
5
C
L1 L3
(Datum A)
C
L
B
B
A
A1
3 x b2
View A - A
2xe
c
3xb
0.010 0.25 M C A B
Plating
5
b1, b3
Base
metal
Lead tip
c1
(c)
5
(b, b2)
Section B - B and C - C
MILLIMETERS
DIM.
MIN.
MILLIMETERS
INCHES
MAX.
MIN.
MAX.
DIM.
MIN.
INCHES
MAX.
MIN.
MAX.
A
2.18
2.39
0.086
0.094
D1
5.21
-
0.205
-
A1
0.89
1.14
0.035
0.045
E
6.35
6.73
0.250
0.265
4.32
-
0.170
-
b
0.64
0.89
0.025
0.035
E1
b1
0.65
0.79
0.026
0.031
e
b2
0.76
1.14
0.030
0.045
L
8.89
9.65
0.350
0.380
b3
0.76
1.04
0.030
0.041
L1
1.91
2.29
0.075
0.090
b4
4.95
5.46
0.195
0.215
L2
0.89
1.27
0.035
0.050
2.29 BSC
2.29 BSC
c
0.46
0.61
0.018
0.024
L3
1.14
1.52
0.045
0.060
c1
0.41
0.56
0.016
0.022
θ1
0'
15'
0'
15'
c2
0.46
0.86
0.018
0.034
θ2
25'
35'
25'
35'
D
5.97
6.22
0.235
0.245
ECN: S-82111-Rev. A, 15-Sep-08
DWG: 5968
Notes
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Dimension are shown in inches and millimeters.
3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.13 mm (0.005") per side. These dimensions are measured at the
outermost extremes of the plastic body.
4. Thermal pad contour optional with dimensions b4, L2, E1 and D1.
5. Lead dimension uncontrolled in L3.
6. Dimension b1, b3 and c1 apply to base metal only.
7. Outline conforms to JEDEC outline TO-251AA.
1
Application Note
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RECOMMENDED MINIMUM PADS FOR DPAK (TO-252)
0.224
0.243
0.087
(2.202)
0.090
(2.286)
(10.668)
0.420
(6.180)
(5.690)
0.180
0.055
(4.572)
(1.397)
Recommended Minimum Pads
Dimensions in Inches/(mm)
Return to Index
APPLICATION NOTE
3
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Material Category Policy
Din-Tek Intertechnology, Inc. hereby certifies that all its products that are identified as RoHS-Compliant fulfill the
definitions and restrictions defined under Directive 2011/65/EU of The European Parliament and of the Council
of June 8, 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment
(EEE) - recast, unless otherwise specified as non-compliant.
Please note that some Din-Tek documentation may still make reference to RoHS Directive 2002/95/EC. We confirm that
all the products identified as being compliant to Directive 2002/95/EC conform to Directive 2011/65/EU.
Din-Tek Intertechnology, Inc. hereby certifies that all its products that are identified as Halogen-Free follow Halogen-Free
requirements as per JEDEC JS709A standards. Please note that some Din-Tek documentation may still make reference
to the IEC 61249-2-21 definition. We confirm that all the products identified as being compliant to IEC 61249-2-21
conform to JEDEC JS709A standards.
1