EON EN25QH32

EN25QH32
EN25QH32
32 Megabit Serial Flash Memory with 4Kbyte Uniform Sector
FEATURES
• Single power supply operation
- Full voltage range: 2.7-3.6 volt
• Serial Interface Architecture
- SPI Compatible: Mode 0 and Mode 3
• 32 M-bit Serial Flash
- 32 M-bit/4,096 K-byte/16,384 pages
- 256 bytes per programmable page
•
-
Standard, Dual or Quad SPI
Standard SPI: CLK, CS#, DI, DO, WP#, HOLD#
Dual SPI: CLK, CS#, DQ0, DQ1, WP#, HOLD#
Quad SPI: CLK, CS#, DQ0, DQ1, DQ2, DQ3
•
-
High performance
104MHz clock rate for Standard SPI
80MHz clock rate for two data bits
50MHz clock rate for four data bits
• Low power consumption
- 12 mA typical active current
- 1 μA typical power down current
•
-
Uniform Sector Architecture:
1024 sectors of 4-Kbyte
64 blocks of 64-Kbyte
Any sector or block can be erased individually
• Software and Hardware Write Protection:
- Write Protect all or portion of memory via
software
- Enable/Disable protection with WP# pin
•
-
High performance program/erase speed
Page program time: 1.3ms typical
Sector erase time: 90ms typical
Block erase time 500ms typical
Chip erase time: 25 seconds typical
• Lockable 512 byte OTP security sector
• Support Serial Flash Discoverable
Parameters (SFDP) signature
• Read Unique ID Number
• Minimum 100K endurance cycle
• Package Options
- 8 pins SOP 200mil body width
- 8 contact VDFN
- 8 pins PDIP
- 16 pins SOP 300mil body width
- 24 balls TFBGA (6x8mm)
- All Pb-free packages are RoHS compliant
• Industrial temperature Range
GENERAL DESCRIPTION
The EN25QH32 is a 32 Megabit (4,096 K-byte) Serial Flash memory, with enhanced write protection
mechanisms. The EN25QH32 supports the standard Serial Peripheral Interface (SPI), and a high
performance Dual/Quad output as well as Dual/Quad I/O using SPI pins: Serial Clock, Chip Select,
Serial DQ0(DI), DQ1(DO), DQ2(WP#) and DQ3(HOLD#). SPI clock frequencies of up to 80MHz are
supported allowing equivalent clock rates of 160MHz (80MHz x 2) for Dual Output when using the Dual
Output Fast Read instructions, and SPI clock frequencies of up to 50MHz are supported allowing
equivalent clock rates of 200MHz (50MHz x 4) for Quad Output when using the Quad Output Fast
Read instructions. The memory can be programmed 1 to 256 bytes at a time, using the Page Program
instruction.
The EN25QH32 is designed to allow either single Sector/Block at a time or full chip erase operation.
The EN25QH32 can be configured to protect part of the memory as the software protected mode. The
device can sustain a minimum of 100K program/erase cycles on each sector or block.
This Data Sheet may be revised by subsequent versions
©2004 Eon Silicon Solution, Inc.,
1
or modifications due to changes in technical specifications.
Rev. E, Issue Date: 2012/01/30
www.eonssi.com
EN25QH32
Figure.1 CONNECTION DIAGRAMS
CS#
1
8
VCC
DO (DQ1)
2
7
HOLD# (DQ3)
WP# (DQ2)
3
6
CLK
4
5
DI (DQ0)
VSS
8 - LEAD SOP / PDIP
CS#
1
8
VCC
DO (DQ1)
2
7
HOLD# (DQ3)
WP# (DQ2)
3
6
CLK
4
5
DI (DQ0)
VSS
8 - LEAD VDFN
16 - LEAD SOP
This Data Sheet may be revised by subsequent versions
©2004 Eon Silicon Solution, Inc.,
2
or modifications due to changes in technical specifications.
Rev. E, Issue Date: 2012/01/30
www.eonssi.com
EN25QH32
Top View, Balls Facing Down
24 - Ball TFBGA
This Data Sheet may be revised by subsequent versions
©2004 Eon Silicon Solution, Inc.,
3
or modifications due to changes in technical specifications.
Rev. E, Issue Date: 2012/01/30
www.eonssi.com
EN25QH32
Figure 2. BLOCK DIAGRAM
Note:
1. DQ0 and DQ1 are used for Dual and Quad instructions.
2. DQ0 ~ DQ3 are used for Quad instructions.
This Data Sheet may be revised by subsequent versions
©2004 Eon Silicon Solution, Inc.,
4
or modifications due to changes in technical specifications.
Rev. E, Issue Date: 2012/01/30
www.eonssi.com
EN25QH32
Table 1. Pin Names
Symbol
Pin Name
CLK
Serial Clock Input
DI (DQ0)
Serial Data Input (Data Input Output 0)
DO (DQ1)
Serial Data Output (Data Input Output 1)
CS#
Chip Select
WP# (DQ2)
Write Protect (Data Input Output 2)
HOLD# (DQ3)
HOLD# pin (Data Input Output 3)
Vcc
Supply Voltage (2.7-3.6V)
Vss
Ground
NC
No Connect
*1
*1
*2
*2
Note:
1. DQ0 and DQ1 are used for Dual and Quad instructions.
2. DQ2 ~ DQ3 are used for Quad instructions.
SIGNAL DESCRIPTION
Serial Data Input, Output and IOs (DI, DO and DQ0, DQ1, DQ2, DQ3)
The EN25QH32 support standard SPI, Dual SPI and Quad SPI operation. Standard SPI instructions
use the unidirectional DI (input) pin to serially write instructions, addresses or data to the device on the
rising edge of the Serial Clock (CLK) input pin. Standard SPI also uses the unidirectional DO (output) to
read data or status from the device on the falling edge CLK.
Dual and Quad SPI instruction use the bidirectional IO pins to serially write instruction, addresses or
data to the device on the rising edge of CLK and read data or status from the device on the falling edge
of CLK.
Serial Clock (CLK)
The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See
SPI Mode")
Chip Select (CS#)
The SPI Chip Select (CS#) pin enables and disables device operation. When CS# is high the device is
deselected and the Serial Data Output (DO, or DQ0, DQ1, DQ2 and DQ3) pins are at high impedance.
When deselected, the devices power consumption will be at standby levels unless an internal erase,
program or status register cycle is in progress. When CS# is brought low the device will be selected,
power consumption will increase to active levels and instructions can be written to and data read from
the device. After power-up, CS# must transition from high to low before a new instruction will be
accepted.
Hold (HOLD#)
The HOLD# pin allows the device to be paused while it is actively selected. When HOLD# is brought
low, while CS# is low, the DO pin will be at high impedance and signals on the DI and CLK pins will be
ignored (don’t care). The hold function can be useful when multiple devices are sharing the same SPI
signals. The HOLD# function is only available for standard SPI and Dual SPI operation, when during
Quad SPI, this pin is the Serial Data IO (DQ3) for Quad I/O operation.
Write Protect (WP#)
The Write Protect (WP#) pin can be used to prevent the Status Register from being written. Used in
conjunction with the Status Register’s Block Protect (BP0, BP1, BP2 and BP3) bits and Status Register
Protect (SRP) bits, a portion or the entire memory array can be hardware protected. The WP# function
is only available for standard SPI and Dual SPI operation, when during Quad SPI, this pin is the Serial
Data IO (DQ2) for Quad I/O operation.
This Data Sheet may be revised by subsequent versions
©2004 Eon Silicon Solution, Inc.,
5
or modifications due to changes in technical specifications.
Rev. E, Issue Date: 2012/01/30
www.eonssi.com
EN25QH32
MEMORY ORGANIZATION
The memory is organized as:
z
4,194,304 bytes
z
Uniform Sector Architecture
64 blocks of 64-Kbyte
1,024 sectors of 4-Kbyte
16,384 pages (256 bytes each)
Each page can be individually programmed (bits are programmed from 1 to 0). The device is Sector,
Block or Chip Erasable but not Page Erasable.
This Data Sheet may be revised by subsequent versions
©2004 Eon Silicon Solution, Inc.,
6
or modifications due to changes in technical specifications.
Rev. E, Issue Date: 2012/01/30
www.eonssi.com
EN25QH32
Table 2. Uniform Block Sector Architecture ( 1/2 )
320000h
31F000h
320FFFh
31FFFFh
784
783
310000h
30F000h
310FFFh
30FFFFh
768
300000h
300FFFh
34
33
32
….
2B0FFFh
2AFFFFh
2A0FFFh
29FFFFh
290FFFh
28FFFFh
280FFFh
27FFFFh
270FFFh
26FFFFh
260000h
25F000h
260FFFh
25FFFFh
592
591
250000h
24F000h
250FFFh
24FFFFh
….
….
608
607
….
….
270000h
26F000h
….
624
623
….
….
280000h
27F000h
….
640
639
….
….
290000h
28F000h
….
656
655
….
….
2A0000h
29F000h
….
672
671
….
….
….
….
….
….
….
2B0000h
2AF000h
….
….
….
….
….
….
….
….
….
688
687
….
….
2C0FFFh
2BFFFFh
576
575
240000h
23F000h
240FFFh
23FFFFh
….
35
2C0000h
2BF000h
….
36
704
703
560
559
230000h
22F000h
230FFFh
22FFFFh
….
800
799
37
2D0FFFh
2CFFFFh
544
543
220000h
21F000h
220FFFh
21FFFFh
….
330FFFh
32FFFFh
38
2D0000h
2CF000h
528
527
210000h
20F000h
210FFFh
20FFFFh
….
330000h
32F000h
….
816
815
39
720
719
….
340FFFh
33FFFFh
40
2E0FFFh
2DFFFFh
….
340000h
33F000h
….
832
831
41
2E0000h
2DF000h
….
350FFFh
34FFFFh
….
350000h
34F000h
….
848
847
42
736
735
….
360FFFh
35FFFFh
….
360000h
35F000h
….
864
863
43
2F0FFFh
2EFFFFh
….
370FFFh
36FFFFh
….
370000h
36F000h
….
880
879
44
2F0000h
2EF000h
….
380FFFh
37FFFFh
….
380000h
37F000h
….
896
895
45
752
751
….
390FFFh
38FFFFh
….
390000h
38F000h
….
912
911
46
Address range
2FF000h
2FFFFFh
….
….
3A0FFFh
39FFFFh
….
….
….
….
….
….
….
3A0000h
39F000h
….
….
….
….
….
….
….
….
….
….
….
928
927
….
….
3B0FFFh
3AFFFFh
47
Sector
767
….
48
3B0000h
3AF000h
Block
….
49
944
943
….
50
3C0FFFh
3BFFFFh
….
51
3C0000h
3BF000h
….
52
960
959
….
53
3D0FFFh
3CFFFFh
….
54
3D0000h
3CF000h
….
55
976
975
….
56
3E0FFFh
3DFFFFh
….
57
3E0000h
3DF000h
….
58
992
991
….
59
3F0FFFh
3EFFFFh
….
60
3F0000h
3EF000h
….
61
1008
1007
….
62
Address range
3FF000h
3FFFFFh
….
63
Sector
1023
….
Block
512
200000h
200FFFh
This Data Sheet may be revised by subsequent versions
©2004 Eon Silicon Solution, Inc.,
7
or modifications due to changes in technical specifications.
Rev. E, Issue Date: 2012/01/30
www.eonssi.com
EN25QH32
Table 2. Uniform Block Sector Architecture ( 2/2 )
120000h
11F000h
120FFFh
11FFFFh
272
271
110000h
10F000h
110FFFh
10FFFFh
256
100000h
100FFFh
2
1
0
….
0B0FFFh
0AFFFFh
0A0FFFh
09FFFFh
090FFFh
08FFFFh
080FFFh
07FFFFh
070FFFh
06FFFFh
060000h
05F000h
060FFFh
05FFFFh
80
79
050000h
04F000h
050FFFh
04FFFFh
….
….
96
95
….
….
070000h
06F000h
….
112
111
….
….
080000h
07F000h
….
128
127
….
….
090000h
08F000h
….
144
143
….
….
0A0000h
09F000h
….
160
159
….
….
….
….
….
….
….
0B0000h
0AF000h
….
….
….
….
….
….
….
….
….
176
175
….
….
0C0FFFh
0BFFFFh
64
63
040000h
03F000h
040FFFh
03FFFFh
….
3
0C0000h
0BF000h
….
4
192
191
48
47
030000h
02F000h
030FFFh
02FFFFh
….
288
287
5
0D0FFFh
0CFFFFh
32
31
020000h
01F000h
020FFFh
01FFFFh
….
130FFFh
12FFFFh
6
0D0000h
0CF000h
16
15
010000h
00F000h
010FFFh
00FFFFh
….
130000h
12F000h
….
304
303
7
208
207
….
140FFFh
13FFFFh
8
0E0FFFh
0DFFFFh
….
140000h
13F000h
….
320
319
9
0E0000h
0DF000h
….
150FFFh
14FFFFh
….
150000h
14F000h
….
336
335
10
224
223
….
160FFFh
15FFFFh
….
160000
15F000
….
352
351
11
0F0FFFh
0EFFFFh
….
170FFFh
16FFFFh
….
170000h
16F000h
….
368
367
12
0F0000h
0EF000h
….
180FFFh
17FFFFh
….
180000h
17F000h
….
384
383
13
240
239
….
190FFFh
18FFFFh
….
190000h
18F000h
….
400
399
14
Address range
0FF000h
0FFFFFh
….
….
1A0FFFh
19FFFF
….
….
….
….
….
….
….
1A0000h
19F000h
….
….
….
….
….
….
….
….
….
….
….
416
415
….
….
1B0FFFh
1AFFFFh
15
Sector
255
….
16
1B0000h
1AF000h
Block
….
17
432
431
….
18
1C0FFFh
1BFFFFh
….
19
1C0000h
1BF000h
….
20
448
447
….
21
1D0FFFh
1CFFFFh
….
22
1D0000h
1CF000h
….
23
464
463
….
24
1E0FFFh
1DFFFFh
….
25
1E0000h
1DF000h
….
26
480
479
….
27
1F0FFFh
1EFFFFh
….
28
1F0000h
1EF000h
….
29
496
495
….
30
Address range
1FF000h
1FFFFFh
….
31
Sector
511
….
Block
4
3
2
1
0
004000h
003000h
002000h
001000h
000000h
004FFFh
003FFFh
002FFFh
001FFFh
000FFFh
This Data Sheet may be revised by subsequent versions
©2004 Eon Silicon Solution, Inc.,
8
or modifications due to changes in technical specifications.
Rev. E, Issue Date: 2012/01/30
www.eonssi.com
EN25QH32
OPERATING FEATURES
Standard SPI Modes
The EN25QH32 is accessed through a SPI compatible bus consisting of four signals: Serial Clock
(CLK), Chip Select (CS#), Serial Data Input (DI) and Serial Data Output (DO). Both SPI bus operation
Modes 0 (0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and Mode 3, as
shown in Figure 3, concerns the normal state of the CLK signal when the SPI bus master is in standby
and data is not being transferred to the Serial Flash. For Mode 0 the CLK signal is normally low. For
Mode 3 the CLK signal is normally high. In either case data input on the DI pin is sampled on the rising
edge of the CLK. Data output on the DO pin is clocked out on the falling edge of CLK.
Figure 3. SPI Modes
Dual SPI Instruction
The EN25QH32 supports Dual SPI operation when using the “Dual Output Fast Read and Dual I/O
Fast Read “ (3Bh and BBh) instructions. These instructions allow data to be transferred to or from the
Serial Flash memory at two to three times the rate possible with the standard SPI. The Dual Read
instructions are ideal for quickly downloading code from Flash to RAM upon power-up (code-shadowing)
or for application that cache code-segments to RAM for execution. The Dual output feature simply
allows the SPI input pin to also serve as an output during this instruction. When using Dual SPI
instructions the DI and DO pins become bidirectional I/O pins; DQ0 and DQ1. All other operations use
the standard SPI interface with single output signal.
Quad SPI Instruction
The EN25QH32 supports Quad output operation when using the Quad I/O Fast Read (EBh).This
instruction allows data to be transferred to or from the Serial Flash memory at four to six times the rate
possible with the standard SPI. The Quad Read instruction offer a significant improvement in
continuous and random access transfer rates allowing fast code-shadowing to RAM or for application
that cache code-segments to RAM for execution. The EN25QH32 also supports full Quad Mode
function while using the Enable Quad Peripheral Interface mode (EQPI) (38h). When using Quad SPI
instruction the DI and DO pins become bidirectional I/O pins; DQ0 and DQ1, and the WP# and HOLD#
pins become DQ2 and DQ3 respectively.
This Data Sheet may be revised by subsequent versions
©2004 Eon Silicon Solution, Inc.,
9
or modifications due to changes in technical specifications.
Rev. E, Issue Date: 2012/01/30
www.eonssi.com
EN25QH32
Figure 4. Quad SPI Modes
Page Programming
To program one data byte, two instructions are required: Write Enable (WREN), which is one byte, and
a Page Program (PP) sequence, which consists of four bytes plus data. This is followed by the internal
Program cycle (of duration tPP).
To spread this overhead, the Page Program (PP) instruction allows up to 256 bytes to be programmed
at a time (changing bits from 1 to 0) provided that they lie in consecutive addresses on the same page
of memory.
Sector Erase, Block Erase and Chip Erase
The Page Program (PP) instruction allows bits to be reset from 1 to 0. Before this can be applied, the
bytes of memory need to have been erased to all 1s (FFh). This can be achieved a sector at a time,
using the Sector Erase (SE) instruction, a block at a time using the Block Erase (BE) instruction or
throughout the entire memory, using the Chip Erase (CE) instruction. This starts an internal Erase cycle
(of duration tSE tBE or tCE). The Erase instruction must be preceded by a Write Enable (WREN)
instruction.
Polling During a Write, Program or Erase Cycle
A further improvement in the time to Write Status Register (WRSR), Program (PP) or Erase (SE, BE or
CE) can be achieved by not waiting for the worst case delay (tW, tPP, tSE, tBE or tCE). The Write In
Progress (WIP) bit is provided in the Status Register so that the application program can monitor its
value, polling it to establish when the previous Write cycle, Program cycle or Erase cycle is complete.
Active Power, Stand-by Power and Deep Power-Down Modes
When Chip Select (CS#) is Low, the device is enabled, and in the Active Power mode. When Chip
Select (CS#) is High, the device is disabled, but could remain in the Active Power mode until all internal
cycles have completed (Program, Erase, and Write Status Register). The device then goes into the
Stand-by Power mode. The device consumption drops to ICC1.
The Deep Power-down mode is entered when the specific instruction (the Enter Deep Power-down
Mode (DP) instruction) is executed. The device consumption drops further to ICC2. The device remains
in this mode until another specific instruction (the Release from Deep Power-down Mode and Read
Device ID (RDI) instruction) is executed.
This Data Sheet may be revised by subsequent versions
©2004 Eon Silicon Solution, Inc.,
10
or modifications due to changes in technical specifications.
Rev. E, Issue Date: 2012/01/30
www.eonssi.com
EN25QH32
All other instructions are ignored while the device is in the Deep Power-down mode. This can be used
as an extra software protection mechanism, when the device is not in active use, to protect the device
from inadvertent Write, Program or Erase instructions.
Status Register
The Status Register contains a number of status and control bits that can be read or set (as appropriate)
by specific instructions.
WIP bit. The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status
Register, Program or Erase cycle.
WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits are non-volatile. They define
the size of the area to be software protected against Program and Erase instructions.
QE bit. The Quad Enable (QE) bit, non-volatile bit, enable bit only for Quad Input/Output FAST_READ
(EBh) in SPI command. When it is “0” (factory default), it disables Quad Input/Output FAST_READ
(EBh) in SPI command and WP#, HOLD# are enabled. While QE is “1”, it enables Quad Input/Output
FAST_READ (EBh) in SPI command and WP#, HOLD# are disabled. In other words, in SPI mode, the
QE bit needs to be assigned through WRSR to enable or disable SPI command Quad Input/Output
FAST_READ (EBh). If the system goes into Full Quad I/O (EQPI), this QE bit becomes no affection
since WP# and HOLD# function will be disabled by EQPI mode and Quad Input/Output FAST_READ
(EBh) will be always available in EQPI mode.
SRP bit / OTP_LOCK bit The Status Register Protect (SRP) bit operates in conjunction with the Write
Protect (WP#) signal. The Status Register Protect (SRP) bit and Write Protect (WP#) signal allow the
device to be put in the Hardware Protected mode. In this mode, the non-volatile bits of the Status
Register (SRP, BP3, BP2, BP1, BP0) become read-only bits.
In OTP mode, this bit serves as OTP_LOCK bit, user can read/program/erase OTP sector as normal
sector while OTP_LOCK bit value is equal 0, after OTP_LOCK bit is programmed with 1 by WRSR
command, the OTP sector is protected from program and erase operation. The OTP_LOCK bit can only
be programmed once.
Note : In OTP mode, the WRSR command will ignore any input data and program OTP_LOCK bit to 1,
user must clear the protect bits before entering OTP mode and program the OTP code, then execute
WRSR command to lock the OTP sector before leaving OTP mode.
Write Protection
Applications that use non-volatile memory must take into consideration the possibility of noise and other
adverse system conditions that may compromise data integrity. To address this concern the
EN25QH32 provides the following data protection mechanisms:
z
Power-On Reset and an internal timer (tPUW) can provide protection against inadvertent changes
while the power supply is outside the operating specification.
z
Program, Erase and Write Status Register instructions are checked that they consist of a number
of clock pulses that is a multiple of eight, before they are accepted for execution.
z
All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set
the Write Enable Latch (WEL) bit. This bit is returned to its reset state by the following events:
– Power-up
– Write Disable (WRDI) instruction completion or Write Status Register (WRSR) instruction
completion or Page Program (PP) instruction completion or Sector Erase (SE) instruction
completion or Block Erase (BE) instruction completion or Chip Erase (CE) instruction
completion
z
The Block Protect (BP3, BP2, BP1, BP0) bits allow part of the memory to be configured as readonly. This is the Software Protected Mode (SPM).
z
The Write Protect (WP#) signal allows the Block Protect (BP3, BP2, BP1, BP0) bits and Status
Register Protect (SRP) bit to be protected. This is the Hardware Protected Mode (HPM).
z
In addition to the low power consumption feature, the Deep Power-down mode offers extra
software protection from inadvertent Write, Program and Erase instructions, as all instructions are
ignored except one particular instruction (the Release from Deep Power-down instruction).
This Data Sheet may be revised by subsequent versions
©2004 Eon Silicon Solution, Inc.,
11
or modifications due to changes in technical specifications.
Rev. E, Issue Date: 2012/01/30
www.eonssi.com
EN25QH32
Table 3. Protected Area Sizes Sector Organization
Status Register Content
BP3
Bit
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
BP2
Bit
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
BP1
Bit
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
BP0
Bit
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Memory Content
Protect Areas
None
Block 63
Block 62 to 63
Block 60 to 63
Block 56 to 63
Block 48 to 63
Block 32 to 63
All
None
Block 0
Block 0 to 1
Block 0 to 3
Block 0 to 7
Block 0 to 15
Block 0 to 31
All
Addresses
None
3F0000h-3FFFFFh
3E0000h-3FFFFFh
3C0000h-3FFFFFh
380000h-3FFFFFh
300000h-3FFFFFh
200000h-3FFFFFh
000000h-3FFFFFh
None
000000h-00FFFFh
000000h-01FFFFh
000000h-03FFFFh
000000h-07FFFFh
000000h-0FFFFFh
000000h-1FFFFFh
000000h-3FFFFFh
Density(KB)
None
64KB
128KB
256KB
512KB
1024KB
2048KB
4096KB
None
64KB
128KB
256KB
512KB
1024KB
2048KB
4096KB
Portion
None
Upper 1/64
Upper 2/64
Upper 4/64
Upper 8/64
Upper 16/64
Upper 32/64
All
None
Lower 1/64
Lower 2/64
Lower 4/64
Lower 8/64
Lower 16/64
Lower 32/64
All
INSTRUCTIONS
All instructions, addresses and data are shifted in and out of the device, most significant bit first. Serial
Data Input (DI) is sampled on the first rising edge of Serial Clock (CLK) after Chip Select (CS#) is
driven Low. Then, the one-byte instruction code must be shifted in to the device, most significant bit first,
on Serial Data Input (DI), each bit being latched on the rising edges of Serial Clock (CLK).
The instruction set is listed in Table 4. Every instruction sequence starts with a one-byte instruction
code. Depending on the instruction, this might be followed by address bytes, or by data bytes, or by
both or none. Chip Select (CS#) must be driven High after the last bit of the instruction sequence has
been shifted in. In the case of a Read Data Bytes (READ), Read Data Bytes at Higher Speed
(Fast_Read), Dual Output Fast Read (3Bh), Dual I/O Fast Read (BBh), Quad Input/Output
FAST_READ (EBh), Read Status Register (RDSR), Read Information Register (RDIFR) or Release
from Deep Power-down, and Read Device ID (RDI) instruction, the shifted-in instruction sequence is
followed by a data-out sequence. Chip Select (CS#) can be driven High after any bit of the data-out
sequence is being shifted out.
In the case of a Page Program (PP), Sector Erase (SE), Block Erase (BE), Chip Erase (CE), Write
Status Register (WRSR), Write Enable (WREN), Write Disable (WRDI) or Deep Power-down (DP)
instruction, Chip Select (CS#) must be driven High exactly at a byte boundary, otherwise the instruction
is rejected, and is not executed. That is, Chip Select (CS#) must driven High when the number of clock
pulses after Chip Select (CS#) being driven Low is an exact multiple of eight. For Page Program, if at
any time the input byte is not a full byte, nothing will happen and WEL will not be reset.
In the case of multi-byte commands of Page Program (PP), and Release from Deep Power Down
(RES ) minimum number of bytes specified has to be given, without which, the command will be
ignored.
In the case of Page Program, if the number of byte after the command is less than 4 (at least 1
data byte), it will be ignored too. In the case of SE and BE, exact 24-bit address is a must, any
less or more will cause the command to be ignored.
All attempts to access the memory array during a Write Status Register cycle, Program cycle or Erase
cycle are ignored, and the internal Write Status Register cycle, Program cycle or Erase cycle continues
unaffected.
This Data Sheet may be revised by subsequent versions
©2004 Eon Silicon Solution, Inc.,
12
or modifications due to changes in technical specifications.
Rev. E, Issue Date: 2012/01/30
www.eonssi.com
EN25QH32
Table 4A. Instruction Set
Instruction Name
Byte 1
Code
EQPI
38h
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
n-Bytes
RSTQIO(2)
Release Quad I/O or
Fast Read Enhanced
Mode
FFh
RSTEN
66h
RST(1)
99h
Write Enable
Write Disable / Exit
OTP mode
Read Status
Register
Write Status
Register
Page Program
06h
04h
05h
(S7-S0)(3)
01h
S7-S0
02h
A23-A16
A15-A8
A7-A0
Sector Erase
20h
A23-A16
A15-A8
A7-A0
Block Erase
D8h
A23-A16
A15-A8
A7-A0
Chip Erase
C7h/ 60h
Deep Power-down
Release from Deep
Power-down, and
read Device ID
Release from Deep
Power-down
Manufacturer/
Device ID
B9h
continuous(4)
D7-D0
Next byte
continuous
(5)
dummy
dummy
dummy
(ID7-ID0)
90h
dummy
dummy
00h
01h
Read Identification
9Fh
(M7-M0)
(ID15-ID8)
(ID7-ID0)
(7)
Enter OTP mode
Read SFDP mode
and Unique ID
Number
3Ah
A23-A16
A15-A8
A7-A0
dummy
ABh
5Ah
(M7-M0)
(ID7-ID0)
(ID7-ID0)
(M7-M0)
(D7-D0)
(6)
(Next Byte)
continuous
Notes:
1. RST command only executed if RSTEN command is executed first. Any intervening command will disable Reset.
2. Device accepts eight-clocks command in Standard SPI mode, or two-clocks command in Quad SPI mode
3. Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis “( )” indicate data being read from the
device on the DO pin
4. The Status Register contents will repeat continuously until CS# terminate the instruction
5. The Device ID will repeat continuously until CS# terminates the instruction
6. The Manufacturer ID and Device ID bytes will repeat continuously until CS# terminates the instruction.
00h on Byte 4 starts with MID and alternate with DID, 01h on Byte 4 starts with DID and alternate with MID
7. (M7-M0) : Manufacturer, (ID15-ID8) : Memory Type, (ID7-ID0) : Memory Capacity
This Data Sheet may be revised by subsequent versions
©2004 Eon Silicon Solution, Inc.,
13
or modifications due to changes in technical specifications.
Rev. E, Issue Date: 2012/01/30
www.eonssi.com
EN25QH32
Table 4B. Instruction Set (Read Instruction)
Instruction Name
Byte 1
Code
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Read Data
03h
A23-A16
A15-A8
A7-A0
(D7-D0)
(Next byte)
Fast Read
0Bh
A23-A16
A15-A8
A7-A0
dummy
(D7-D0)
Dual Output Fast
Read
3Bh
A23-A16
A15-A8
A7-A0
dummy
(D7-D0, …) (1)
Dual I/O Fast Read
BBh
A23-A8(2)
A7-A0,
dummy (2)
(D7-D0, …) (1)
Quad I/O Fast Read
EBh
A23-A0,
dummy (4)
(dummy,
D7-D0 ) (5)
(D7-D0, …) (3)
n-Bytes
continuous
(Next Byte)
continuous
(one byte
per 4 clocks,
continuous)
(one byte
per 4 clocks,
continuous)
(one byte
per 2 clocks,
continuous)
Notes:
1. Dual Output data
DQ0 = (D6, D4, D2, D0)
DQ1 = (D7, D5, D3, D1)
2. Dual Input Address
DQ0 = A22, A20, A18, A16, A14, A12, A10, A8 ; A6, A4, A2, A0, dummy 6, dummy 4, dummy 2, dummy 0
DQ1 = A23, A21, A19, A17, A15, A13, A11, A9 ; A7, A5, A3, A1, dummy 7, dummy 5, dummy 3, dummy 1
3. Quad Data
DQ0 = (D4, D0, …… )
DQ1 = (D5, D1, …… )
DQ2 = (D6, D2, …... )
DQ3 = (D7, D3, …... )
4. Quad Input Address
DQ0 = A20, A16, A12, A8, A4, A0, dummy 4, dummy 0
DQ1 = A21, A17, A13, A9, A5, A1, dummy 5, dummy 1
DQ2 = A22, A18, A14, A10, A6, A2, dummy 6, dummy 2
DQ3 = A23, A19, A15, A11, A7, A3, dummy 7, dummy 3
5. Quad I/O Fast Read Data
DQ0 = ( dummy 12, dummy 8, dummy 4, dummy 0, D4, D0 )
DQ1 = ( dummy 13, dummy 9, dummy 5, dummy 1, D5, D1 )
DQ2 = ( dummy 14, dummy 10, dummy 6, dummy 2, D6, D2 )
DQ3 = ( dummy 15, dummy 11, dummy 7, dummy 3, D7, D3 )
This Data Sheet may be revised by subsequent versions
©2004 Eon Silicon Solution, Inc.,
14
or modifications due to changes in technical specifications.
Rev. E, Issue Date: 2012/01/30
www.eonssi.com
EN25QH32
Table 5. Manufacturer and Device Identification
OP Code
(M7-M0)
(ID15-ID0)
ABh
(ID7-ID0)
15h
90h
1Ch
9Fh
1Ch
15h
7016h
Enable Quad Peripheral Interface mode (EQPI) (38h)
The Enable Quad Peripheral Interface mode (EQPI) instruction will enable the flash device for Quad
SPI bus operation. Upon completion of the instruction, all instructions thereafter will be 4-bit multiplexed
input/output until a power cycle or “ Reset Quad I/O instruction “ instruction, as shown in Figure 5. The
device did not support the Read Data Bytes (READ) (03h), Dual Output Fast Read (3Bh) and Dual
Input/Output FAST_READ (BBh) modes while the Enable Quad Peripheral Interface mode (EQPI) (38h)
turns on.
Figure 5. Enable Quad Peripheral Interface mode Sequence Diagram
Reset Quad I/O (RSTQIO) or Release Quad I/O Fast Read Enhancement Mode (FFh)
The Reset Quad I/O instruction resets the device to 1-bit Standard SPI operation. To execute a Reset
Quad I/O operation, the host drives CS# low, sends the Reset Quad I/O command cycle (FFh) then,
drives CS# high. This command can’t be used in Standard SPI mode.
User also can use the 0xFFh command to release the Quad I/O Fast Read Enhancement Mode. The detail
description, please see the Quad I/O Fast Read Enhancement Mode section.
Note:
If the system is in the Quad I/O Fast Read Enhance Mode under EQPI Mode, it is necessary to execute
0xFFh command by two times. The first 0xFFh command is to release Quad I/O Fast Read Enhance Mode,
and the second 0xFFh command is to release EQPI Mode.
This Data Sheet may be revised by subsequent versions
©2004 Eon Silicon Solution, Inc.,
15
or modifications due to changes in technical specifications.
Rev. E, Issue Date: 2012/01/30
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EN25QH32
Reset-Enable (RSTEN) (66h) and Reset (RST) (99h)
The Reset operation is used as a system (software) reset that puts the device in normal operating
Ready mode. This operation consists of two commands: Reset-Enable (RSTEN) and Reset (RST).
To reset the EN25QH32 the host drives CS# low, sends the Reset-Enable command (66h), and drives
CS# high. Next, the host drives CS# low again, sends the Reset command (99h), and drives CS# high.
The Reset operation requires the Reset-Enable command followed by the Reset command. Any
command other than the Reset command after the Reset-Enable command will disable the ResetEnable.
A successful command execution will reset the Status register and the Information register to data =
00h, see Figure 6 for SPI Mode and Figure 6.1 for EQPI Mode. A device reset during an active
Program or Erase operation aborts the operation, which can cause the data of the targeted address
range to be corrupted or lost. Depending on the prior operation, the reset timing may vary. Recovery
from a Write operation requires more software latency time (tSR) than recovery from other operations.
Figure 6. Reset-Enable and Reset Sequence Diagram
Figure 6.1 Reset-Enable and Reset Sequence Diagram under EQPI Mode
This Data Sheet may be revised by subsequent versions
©2004 Eon Silicon Solution, Inc.,
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or modifications due to changes in technical specifications.
Rev. E, Issue Date: 2012/01/30
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EN25QH32
Software Reset Flow
Initial
Command
= 66h ?
No
Yes
Reset enable
Command
= 99h ?
No
Yes
Reset start
No
WIP = 0 ?
Embedded
Reset Cycle
Yes
Reset done
Note:
1. Reset-Enable (RSTEN) (66h) and Reset (RST) (99h) commands need to match standard SPI or
EQPI (Quad) mode.
2. Continue (Enhance) EB mode need to use quad Reset-Enable (RSTEN) (66h) and quad Reset (RST)
(99h) commands.
3. If user is not sure it is in SPI or Quad mode, we suggest to execute sequence as follows:
Quad Reset-Enable (RSTEN) (66h) -> Quad Reset (RST) (99h) -> SPI Reset-Enable (RSTEN) (66h)
-> SPI Reset (RST) (99h) to reset.
4. The reset command could be executed during embedded program and erase process, EQPI mode
and Continue EB mode to back to SPI mode.
5. This flow cannot release the device from Deep power down mode.
6. The Status Register Bit and Information register Bit will reset to default value after reset done.
7. If user reset device during erase, the embedded reset cycle software reset latency will take about
28us in worst case.
This Data Sheet may be revised by subsequent versions
©2004 Eon Silicon Solution, Inc.,
17
or modifications due to changes in technical specifications.
Rev. E, Issue Date: 2012/01/30
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EN25QH32
Write Enable (WREN) (06h)
The Write Enable (WREN) instruction (Figure 7) sets the Write Enable Latch (WEL) bit. The Write
Enable Latch (WEL) bit must be set prior to every Page Program (PP), Sector Erase (SE), Block Erase
(BE), Chip Erase (CE) and Write Status Register (WRSR) instruction.
The Write Enable (WREN) instruction is entered by driving Chip Select (CS#) Low, sending the
instruction code, and then driving Chip Select (CS#) High.
The instruction sequence is shown in Figure 8.1 while using the Enable Quad Peripheral Interface mode
(EQPI) (38h) command.
Figure 7. Write Enable Instruction Sequence Diagram
Write Disable (WRDI) (04h)
The Write Disable instruction (Figure 8) resets the Write Enable Latch (WEL) bit in the Status Register
to a 0 or exit from OTP mode to normal mode. The Write Disable instruction is entered by driving Chip
Select (CS#) low, shifting the instruction code “04h” into the DI pin and then driving Chip Select (CS#)
high. Note that the WEL bit is automatically reset after Power-up and upon completion of the Write
Status Register, Page Program, Sector Erase, Block Erase (BE) and Chip Erase instructions.
The instruction sequence is shown in Figure 8.1 while using the Enable Quad Peripheral Interface mode
(EQPI) (38h) command.
Figure 8. Write Disable Instruction Sequence Diagram
This Data Sheet may be revised by subsequent versions
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or modifications due to changes in technical specifications.
Rev. E, Issue Date: 2012/01/30
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EN25QH32
Figure 8.1 Write Enable/Disable Instruction Sequence under EQPI Mode
Read Status Register (RDSR) (05h)
The Read Status Register (RDSR) instruction allows the Status Register to be read. The Status
Register may be read at any time, even while a Program, Erase or Write Status Register cycle is in
progress. When one of these cycles is in progress, it is recommended to check the Write In Progress
(WIP) bit before sending a new instruction to the device. It is also possible to read the Status Register
continuously, as shown in Figure 9.
The instruction sequence is shown in Figure 9.1 while using the Enable Quad Peripheral Interface mode
(EQPI) (38h) command.
Figure 9. Read Status Register Instruction Sequence Diagram
This Data Sheet may be revised by subsequent versions
©2004 Eon Silicon Solution, Inc.,
19
or modifications due to changes in technical specifications.
Rev. E, Issue Date: 2012/01/30
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EN25QH32
Figure 9.1 Read Status Register Instruction Sequence under EQPI Mode
Table 6. Status Register Bit Locations
S7
S6
S5
SRP
Status
Register
Protect
1 = status
register write
disable
OTP_LOCK
bit
(note 1)
1 = OTP
sector is
protected
Non-volatile bit
QE
(Quad
Enable)
1 = Quad
enable
0 = not Quad
enable
BP3
S4
S3
S2
S1
BP2
BP1
BP0
WEL
(Block
(Block
(Block
(Block
(Write Enable
Protected bits) Protected bits) Protected bits) Protected bits)
Latch)
(note 2)
(note 2)
(note 2)
(note 2)
S0
WIP
(Write In
Progress bit)
(Note 3)
1 = write
enable
0 = not write
enable
1 = write
operation
0 = not in write
operation
volatile bit
volatile bit
Non-volatile bit Non-volatile bit. Non-volatile bit Non-volatile bit Non-volatile bit
Note
1. In OTP mode, SRP bit is served as OTP_LOCK bit.
2. See the table “Protected Area Sizes Sector Organization”.
The status and control bits of the Status Register are as follows:
WIP bit. The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status
Register, Program or Erase cycle. When set to 1, such a cycle is in progress, when reset to 0 no such
cycle is in progress.
WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is
reset and no Write Status Register, Program or Erase instruction is accepted.
BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits are non-volatile. They define
the size of the area to be software protected against Program and Erase instructions. These bits are
written with the Write Status Register (WRSR) instruction. When one or both of the Block Protect (BP3,
BP2, BP1, BP0) bits is set to 1, the relevant memory area (as defined in Table 3.) becomes protected
against Page Program (PP) Sector Erase (SE) and , Block Erase (BE), instructions. The Block Protect
(BP3, BP2, BP1, BP0) bits can be written provided that the Hardware Protected mode has not been set.
The Chip Erase (CE) instruction is executed if, and only if, all Block Protect (BP3, BP2, BP1, BP0) bits
are 0.
This Data Sheet may be revised by subsequent versions
©2004 Eon Silicon Solution, Inc.,
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or modifications due to changes in technical specifications.
Rev. E, Issue Date: 2012/01/30
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EN25QH32
QE bit. The Quad Enable (QE) bit, non-volatile bit, enable bit only for Quad Input/Output FAST_READ
(EBh) in SPI command. When it is “0” (factory default), it disables Quad Input/Output FAST_READ
(EBh) in SPI command and WP#, HOLD# are enabled. While QE is “1”, it enables Quad Input/Output
FAST_READ (EBh) in SPI command and WP#, HOLD# are disabled. In other words, in SPI mode, the
QE bit needs to be assigned through WRSR to enable or disable SPI command Quad Input/Output
FAST_READ (EBh). If the system goes into Full Quad I/O (EQPI), this QE bit becomes no affection
since WP# and HOLD# function will be disabled by EQPI mode and Quad Input/Output FAST_READ
(EBh) will be always available in EQPI mode.
SRP bit / OTP_LOCK bit. The Status Register Protect (SRP) bit operates in conjunction with the Write
Protect (WP#) signal. The Status Register Write Protect (SRP) bit and Write Protect (WP#) signal allow
the device to be put in the Hardware Protected mode (when the Status Register Protect (SRP) bit is set
to 1, and Write Protect (WP#) is driven Low). In this mode, the non-volatile bits of the Status Register
(SRP, BP3, BP2, BP1, BP0) become read-only bits and the Write Status Register (WRSR) instruction is
no longer accepted for execution.
In OTP mode, this bit serves as OTP_LOCK bit, user can read/program/erase OTP sector as normal
sector while OTP_LOCK bit value is equal 0, after OTP_LOCK bit is programmed with 1 by WRSR
command, the OTP sector is protected from program and erase operation. The OTP_LOCK bit can only
be programmed once.
Note : In OTP mode, the WRSR command will ignore any input data and program OTP_LOCK bit to 1,
user must clear the protect bits before enter OTP mode and program the OTP code, then execute
WRSR command to lock the OTP sector before leaving OTP mode.
Write Status Register (WRSR) (01h)
The Write Status Register (WRSR) instruction allows new values to be written to the Status Register.
Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed.
After the Write Enable (WREN) instruction has been decoded and executed, the device sets the Write
Enable Latch (WEL).
The Write Status Register (WRSR) instruction is entered by driving Chip Select (CS#) Low, followed by
the instruction code and the data byte on Serial Data Input (DI).
The instruction sequence is shown in Figure 10. The Write Status Register (WRSR) instruction has no
effect on S1 and S0 of the Status Register. Chip Select (CS#) must be driven High after the eighth bit of
the data byte has been latched in. If not, the Write Status Register (WRSR) instruction is not executed.
As soon as Chip Select (CS#) is driven High, the self-timed Write Status Register cycle (whose
duration is tW) is initiated. While the Write Status Register cycle is in progress, the Status Register may
still be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1
during the self-timed Write Status Register cycle, and is 0 when it is completed. When the cycle is
completed, the Write Enable Latch (WEL) is reset.
The Write Status Register (WRSR) instruction allows the user to change the values of the Block Protect
(BP3, BP2, BP1, BP0) bits, to define the size of the area that is to be treated as read-only, as defined in
Table 3. The Write Status Register (WRSR) instruction also allows the user to set or reset the Status
Register Protect (SRP) bit in accordance with the Write Protect (WP#) signal. The Status Register
Protect (SRP) bit and Write Protect (WP#) signal allow the device to be put in the Hardware Protected
Mode (HPM). The Write Status Register (WRSR) instruction is not executed once the Hardware
Protected Mode (HPM) is entered.
The instruction sequence is shown in Figure 10.1 while using the Enable Quad Peripheral Interface mode
(EQPI) (38h) command.
NOTE : In the OTP mode, WRSR command will ignore input data and program OTP_LOCK bit to 1.
This Data Sheet may be revised by subsequent versions
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or modifications due to changes in technical specifications.
Rev. E, Issue Date: 2012/01/30
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EN25QH32
Figure 10. Write Status Register Instruction Sequence Diagram
Figure 10.1 Write Status Register Instruction Sequence under EQPI Mode
This Data Sheet may be revised by subsequent versions
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or modifications due to changes in technical specifications.
Rev. E, Issue Date: 2012/01/30
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EN25QH32
Read Data Bytes (READ) (03h)
The device is first selected by driving Chip Select (CS#) Low. The instruction code for the Read Data
Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being latched-in during the
rising edge of Serial Clock (CLK). Then the memory contents, at that address, is shifted out on Serial
Data Output (DO), each bit being shifted out, at a maximum frequency fR, during the falling edge of
Serial Clock (CLK).
The instruction sequence is shown in Figure 11. The first byte addresses can be at any location. The
address is automatically incremented to the next higher address after each byte of data is shifted out.
The whole memory can, therefore, be read with a single Read Data Bytes (READ) instruction. When
the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence
to be continued indefinitely.
The Read Data Bytes (READ) instruction is terminated by driving Chip Select (CS#) High. Chip Select
(CS#) can be driven High at any time during data output. Any Read Data Bytes (READ) instruction,
while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the
cycle that is in progress.
Figure 11. Read Data Instruction Sequence Diagram
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or modifications due to changes in technical specifications.
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EN25QH32
Read Data Bytes at Higher Speed (FAST_READ) (0Bh)
The device is first selected by driving Chip Select (CS#) Low. The instruction code for the Read Data
Bytes at Higher Speed (FAST_READ) instruction is followed by a 3-byte address (A23-A0) and a
dummy byte, each bit being latched-in during the rising edge of Serial Clock (CLK). Then the memory
contents, at that address, is shifted out on Serial Data Output (DO), each bit being shifted out, at a
maximum frequency FR, during the falling edge of Serial Clock (CLK).
The instruction sequence is shown in Figure 12. The first byte addressed can be at any location. The
address is automatically incremented to the next higher address after each byte of data is shifted out.
The whole memory can, therefore, be read with a single Read Data Bytes at Higher Speed
(FAST_READ) instruction. When the highest address is reached, the address counter rolls over to
000000h, allowing the read sequence to be continued indefinitely.
The Read Data Bytes at Higher Speed (FAST_READ) instruction is terminated by driving Chip Select
(CS#) High. Chip Select (CS#) can be driven High at any time during data output. Any Read Data Bytes
at Higher Speed (FAST_READ) instruction, while an Erase, Program or Write cycle is in progress, is
rejected without having any effects on the cycle that is in progress.
The instruction sequence is shown in Figure 12.1 while using the Enable Quad Peripheral Interface mode
(EQPI) (38h) command.
Figure 12. Fast Read Instruction Sequence Diagram
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or modifications due to changes in technical specifications.
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EN25QH32
Figure 12.1 Fast Read Instruction Sequence under EQPI Mode
Dual Output Fast Read (3Bh)
The Dual Output Fast Read (3Bh) is similar to the standard Fast Read (0Bh) instruction except that
data is output on two pins, DQ0 and DQ1, instead of just DQ0. This allows data to be transferred from
the EN25QH32 at twice the rate of standard SPI devices. The Dual Output Fast Read instruction is
ideal for quickly downloading code from to RAM upon power-up or for applications that cache codesegments to RAM for execution.
Similar to the Fast Read instruction, the Dual Output Fast Read instruction can operation at the highest
possible frequency of FR (see AC Electrical Characteristics). This is accomplished by adding eight
“dummy clocks after the 24-bit address as shown in Figure 13. The dummy clocks allow the device’s
internal circuits additional time for setting up the initial address. The input data during the dummy clock
is “don’t care”. However, the DI pin should be high-impedance prior to the falling edge of the first data
out clock.
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or modifications due to changes in technical specifications.
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EN25QH32
Figure 13. Dual Output Fast Read Instruction Sequence Diagram
Dual Input / Output FAST_READ (BBh)
The Dual I/O Fast Read (BBh) instruction allows for improved random access while maintaining two IO
pins, DQ0 and DQ1. It is similar to the Dual Output Fast Read (3Bh) instruction but with the capability to
input the Address bits (A23-A0) two bits per clock. This reduced instruction overhead may allow for
code execution (XIP) directly from the Dual SPI in some applications.
The Dual I/O Fast Read instruction enable double throughput of Serial Flash in read mode. The
address is latched on rising edge of CLK, and data of every two bits (interleave 2 I/O pins) shift out on
the falling edge of CLK at a maximum frequency. The first address can be at any location. The address
is automatically increased to the next higher address after each byte data is shifted out, so the whole
memory can be read out at a single Dual I/O Fast Read instruction. The address counter rolls over to 0
when the highest address has been reached. Once writing Dual I/O Fast Read instruction, the following
address/dummy/data out will perform as 2-bit instead of previous 1-bit, as shown in Figure 14.
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or modifications due to changes in technical specifications.
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EN25QH32
Figure 14. Dual Input / Output Fast Read Instruction Sequence Diagram
This Data Sheet may be revised by subsequent versions
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or modifications due to changes in technical specifications.
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EN25QH32
Quad Input / Output FAST_READ (EBh)
The Quad Input/Output FAST_READ (EBh) instruction is similar to the Dual I/O Fast Read (BBh)
instruction except that address and data bits are input and output through four pins, DQ0, DQ1, DQ2 and
DQ3 and six dummy clocks are required prior to the data output. The Quad I/O dramatically reduces
instruction overhead allowing faster random access for code execution (XIP) directly from the Quad SPI.
The Quad Input/Output FAST_READ (EBh) instruction enable quad throughput of Serial Flash in read
mode. In SPI mode, the QE bit needs to be assigned through WRSR to set to “1” before sending the
SPI instruction Quad Input/Output FAST_READ (EBh). If the system goes into Full Quad I/O (EQPI),
this QE bit becomes no affection since WP# and HOLD# function will be disabled by EQPI mode and
Quad Input/Output FAST_READ (EBh) will be always available in EQPI mode.
The address is latching on rising edge of CLK, and data of every four bits (interleave on 4 I/O pins) shift
out on the falling edge of CLK at a maximum frequency FR. The first address can be any location. The
address is automatically increased to the next higher address after each byte data is shifted out, so the
whole memory can be read out at a single Quad Input/Output FAST_READ instruction. The address
counter rolls over to 0 when the highest address has been reached. Once writing Quad Input/Output
FAST_READ instruction, the following address/dummy/data out will perform as 4-bit instead of previous
1-bit.
The sequence of issuing Quad Input/Output FAST_READ (EBh) instruction is: CS# goes low ->
sending Quad Input/Output FAST_READ (EBh) instruction -> 24-bit address interleave on DQ3, DQ2,
DQ1 and DQ0 -> 6 dummy cycles -> data out interleave on DQ3, DQ2, DQ1 and DQ0 -> to end Quad
Input/Output FAST_READ (EBh) operation can use CS# to high at any time during data out, as shown
in Figure 15.
The instruction sequence is shown in Figure 15.1 while using the Enable Quad Peripheral Interface mode (EQPI)
(38h) command.
Figure 15. Quad Input / Output Fast Read Instruction Sequence Diagram
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EN25QH32
Figure 15.1. Quad Input / Output Fast Read Instruction Sequence under EQPI Mode
Another sequence of issuing Quad Input/Output FAST_READ (EBh) instruction especially useful in
random access is : CS# goes low -> sending Quad Input/Output FAST_READ (EBh) instruction -> 24bit address interleave on DQ3, DQ2, DQ1 and DQ0 -> performance enhance toggling bit P[7:0] -> 4
dummy cycles -> data out interleave on DQ3, DQ2, DQ1 and DQ0 till CS# goes high -> CS# goes low
(reduce Quad Input/Output FAST_READ (EBh) instruction) -> 24-bit access address, as shown in
Figure 16.
In the performance – enhancing mode, P[7:4] must be toggling with P[3:0] ; likewise P[7:0] = A5h, 5Ah,
F0h or 0Fh can make this mode continue and reduce the next Quad Input/Output FAST_READ (EBh)
instruction. Once P[7:4] is no longer toggling with P[3:0] ; likewise P[7:0] = FFh, 00h, AAh or 55h. These
commands will reset the performance enhance mode. And afterwards CS# is raised or issuing FF
command (CS# goes high -> CS# goes low -> sending 0xFFh -> CS# goes high) instead of no toggling,
the system then will escape from performance enhance mode and return to normal operation.
While Program/ Erase/ Write Status Register is in progress, Quad Input/Output FAST_READ (EBh)
instruction is rejected without impact on the Program/ Erase/ Write Status Register current cycle.
The instruction sequence is shown in Figure 16.1 while using the Enable Quad Peripheral Interface mode (EQPI)
(38h) command.
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EN25QH32
Figure 16. Quad Input/Output Fast Read Enhance Performance Mode Sequence Diagram
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EN25QH32
Figure 16.1 Quad Input/Output Fast Read Enhance Performance Mode Sequence under EQPI Mode
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EN25QH32
Page Program (PP) (02h)
The Page Program (PP) instruction allows bytes to be programmed in the memory. Before it can be
accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write
Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL).
The Page Program (PP) instruction is entered by driving Chip Select (CS#) Low, followed by the instruction code, three address bytes and at least one data byte on Serial Data Input (DI). If the 8 least
significant address bits (A7-A0) are not all zero, all transmitted data that goes beyond the end of the
current page are programmed from the start address of the same page (from the address whose 8
least significant bits (A7-A0) are all zero). Chip Select (CS#) must be driven Low for the entire duration
of the sequence.
The instruction sequence is shown in Figure 17. If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If less than 256 Data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page.
Chip Select (CS#) must be driven High after the eighth bit of the last data byte has been latched in,
otherwise the Page Program (PP) instruction is not executed.
As soon as Chip Select (CS#) is driven High, the self-timed Page Program cycle (whose duration is tPP)
is initiated. While the Page Program cycle is in progress, the Status Register may be read to check the
value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Page
Program cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed,
the Write Enable Latch (WEL) bit is reset.
A Page Program (PP) instruction applied to a page which is protected by the Block Protect (BP3, BP2,
BP1, BP0) bits (see Table 3) is not executed.
The instruction sequence is shown in Figure 17.1 while using the Enable Quad Peripheral Interface mode
(EQPI) (38h) command.
Figure 17. Page Program Instruction Sequence Diagram
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EN25QH32
Figure 17.1 Program Instruction Sequence under EQPI Mode
Sector Erase (SE) (20h)
The Sector Erase (SE) instruction sets to 1 (FFh) all bits inside the chosen sector. Before it can be
accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write
Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL).
The Sector Erase (SE) instruction is entered by driving Chip Select (CS#) Low, followed by the instruction code, and three address bytes on Serial Data Input (DI). Any address inside the Sector (see
Table 2) is a valid address for the Sector Erase (SE) instruction. Chip Select (CS#) must be driven Low
for the entire duration of the sequence.
The instruction sequence is shown in Figure 18. Chip Select (CS#) must be driven High after the eighth
bit of the last address byte has been latched in, otherwise the Sector Erase (SE) instruction is not
executed. As soon as Chip Select (CS#) is driven High, the self-timed Sector Erase cycle (whose duration is tSE) is initiated. While the Sector Erase cycle is in progress, the Status Register may be read
to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the
self-timed Sector Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle
is completed, the Write Enable Latch (WEL) bit is reset.
A Sector Erase (SE) instruction applied to a sector which is protected by the Block Protect (BP3, BP2,
BP1, BP0) bits (see Table 3) is not executed.
The instruction sequence is shown in Figure 18.1 while using the Enable Quad Peripheral Interface mode
(EQPI) (38h) command.
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EN25QH32
Figure 18. Sector Erase Instruction Sequence Diagram
Block Erase (BE) (D8h)
The Block Erase (BE) instruction sets to 1 (FFh) all bits inside the chosen block. Before it can be
accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write
Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL).
The Block Erase (BE) instruction is entered by driving Chip Select (CS#) Low, followed by the instruction code, and three address bytes on Serial Data Input (DI). Any address inside the Block (see
Table 2) is a valid address for the Block Erase (BE) instruction. Chip Select (CS#) must be driven Low
for the entire duration of the sequence.
The instruction sequence is shown in Figure 19. Chip Select (CS#) must be driven High after the eighth
bit of the last address byte has been latched in, otherwise the Block Erase (BE) instruction is not
executed. As soon as Chip Select (CS#) is driven High, the self-timed Block Erase cycle (whose duration is tBE) is initiated. While the Block Erase cycle is in progress, the Status Register may be read to
check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the selftimed Block Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset.
A Block Erase (BE) instruction applied to a block which is protected by the Block Protect (BP3, BP2,
BP1, BP0) bits (see Table 3) is not executed.
The instruction sequence is shown in Figure 19.1 while using the Enable Quad Peripheral Interface mode
(EQPI) (38h) command.
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EN25QH32
Figure 19. Block Erase Instruction Sequence Diagram
Figure 19.1 Block/Sector Erase Instruction Sequence under EQPI Mode
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EN25QH32
Chip Erase (CE) (C7h/60h)
The Chip Erase (CE) instruction sets all bits to 1 (FFh). Before it can be accepted, a Write Enable
(WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction
has been decoded, the device sets the Write Enable Latch (WEL).
The Chip Erase (CE) instruction is entered by driving Chip Select (CS#) Low, followed by the instruction
code on Serial Data Input (DI). Chip Select (CS#) must be driven Low for the entire duration of the
sequence.
The instruction sequence is shown in Figure 20. Chip Select (CS#) must be driven High after the eighth
bit of the instruction code has been latched in, otherwise the Chip Erase instruction is not executed. As
soon as Chip Select (CS#) is driven High, the self-timed Chip Erase cycle (whose duration is tCE) is
initiated. While the Chip Erase cycle is in progress, the Status Register may be read to check the value
of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Chip Erase
cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write
Enable Latch (WEL) bit is reset.
The Chip Erase (CE) instruction is executed only if all Block Protect (BP3, BP2, BP1, BP0) bits are 0.
The Chip Erase (CE) instruction is ignored if one, or more blocks are protected.
The instruction sequence is shown in Figure 20.1 while using the Enable Quad Peripheral Interface mode
(EQPI) (38h) command.
Figure 20. Chip Erase Instruction Sequence Diagram
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EN25QH32
Figure 20.1 Chip Erase Sequence under EQPI Mode
Deep Power-down (DP) (B9h)
Executing the Deep Power-down (DP) instruction is the only way to put the device in the lowest consumption mode (the Deep Power-down mode). It can also be used as an extra software protection
mechanism, while the device is not in active use, since in this mode, the device ignores all Write,
Program and Erase instructions.
Driving Chip Select (CS#) High deselects the device, and puts the device in the Standby mode (if there
is no internal cycle currently in progress). But this mode is not the Deep Power-down mode. The Deep
Power-down mode can only be entered by executing the Deep Power-down (DP) instruction, to reduce
the standby current (from ICC1 to ICC2, as specified in Table 12.)
Once the device has entered the Deep Power-down mode, all instructions are ignored except the
Release from Deep Power-down and Read Device ID (RDI) instruction. This releases the device from
this mode. The Release from Deep Power-down and Read Device ID (RDI) instruction also allows the
Device ID of the device to be output on Serial Data Output (DO).
The Deep Power-down mode automatically stops at Power-down, and the device always Powers-up in
the Standby mode. The Deep Power-down (DP) instruction is entered by driving Chip Select (CS#) Low,
followed by the instruction code on Serial Data Input (DI). Chip Select (CS#) must be driven Low for the
entire duration of the sequence.
The instruction sequence is shown in Figure 21. Chip Select (CS#) must be driven High after the eighth
bit of the instruction code has been latched in, otherwise the Deep Power-down (DP) instruction is not
executed. As soon as Chip Select (CS#) is driven High, it requires a delay of tDP before the supply
current is reduced to ICC2 and the Deep Power-down mode is entered.
Any Deep Power-down (DP) instruction, while an Erase, Program or Write cycle is in progress, is
rejected without having any effects on the cycle that is in progress.
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EN25QH32
Figure 21. Deep Power-down Instruction Sequence Diagram
Release from Deep Power-down and Read Device ID (RDI)
Once the device has entered the Deep Power-down mode, all instructions are ignored except the
Release from Deep Power-down and Read Device ID (RDI) instruction. Executing this instruction takes
the device out of the Deep Power-down mode.
Please note that this is not the same as, or even a subset of, the JEDEC 16-bit Electronic Signature
that is read by the Read Identifier (RDID) instruction. The old-style Electronic Signature is supported for
reasons of backward compatibility, only, and should not be used for new designs. New designs should,
instead, make use of the JEDEC 16-bit Electronic Signature, and the Read Identifier (RDID) instruction.
When used only to release the device from the power-down state, the instruction is issued by driving
the CS# pin low, shifting the instruction code “ABh” and driving CS# high as shown in Figure 22. After
the time duration of tRES1 (See AC Characteristics) the device will resume normal operation and other
instructions will be accepted. The CS# pin must remain high during the tRES1 time duration.
When used only to obtain the Device ID while not in the power-down state, the instruction is initiated by
driving the CS# pin low and shifting the instruction code “ABh” followed by 3-dummy bytes. The Device
ID bits are then shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in
Figure 23. The Device ID value for the EN25QH32 are listed in Table 5. The Device ID can be read
continuously. The instruction is completed by driving CS# high.
When Chip Select (CS#) is driven High, the device is put in the Stand-by Power mode. If the device
was not previously in the Deep Power-down mode, the transition to the Stand-by Power mode is
immediate. If the device was previously in the Deep Power-down mode, though, the transition to the
Standby Power mode is delayed by tRES2, and Chip Select (CS#) must remain High for at least tRES2
(max), as specified in Table 14. Once in the Stand-by Power mode, the device waits to be selected, so
that it can receive, decode and execute instructions.
Except while an Erase, Program or Write Status Register cycle is in progress, the Release from Deep
Power-down and Read Device ID (RDI) instruction always provides access to the 8bit Device ID of the
device, and can be applied even if the Deep Power-down mode has not been entered.
Any Release from Deep Power-down and Read Device ID (RDI) instruction while an Erase, Program or
Write Status Register cycle is in progress, is not decoded, and has no effect on the cycle that is in
progress.
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EN25QH32
Figure 22. Release Power-down Instruction Sequence Diagram
Figure 23. Release Power-down / Device ID Instruction Sequence Diagram
Read Manufacturer / Device ID (90h)
The Read Manufacturer/Device ID instruction is an alternative to the Release from Power-down /
Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device
ID.
The Read Manufacturer/Device ID instruction is very similar to the Release from Power-down / Device
ID instruction. The instruction is initiated by driving the CS# pin low and shifting the instruction code
“90h” followed by a 24-bit address of 000000h. After which, the Manufacturer ID for Eon (1Ch) and the
Device ID are shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in
Figure 24. The Device ID values for the EN25QH32 are listed in Table 5. If the 24-bit address is initially
set to 000001h the Device ID will be read first
The instruction sequence is shown in Figure 24.1 while using the Enable Quad Peripheral Interface mode
(EQPI) (38h) command.
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EN25QH32
Figure 24. Read Manufacturer / Device ID Diagram
Figure 24.1. Read Manufacturer / Device ID Diagram under EQPI Mode
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EN25QH32
Read Identification (RDID) (9Fh)
The Read Identification (RDID) instruction allows the 8-bit manufacturer identification to be read,
followed by two bytes of device identification. The device identification indicates the memory type in the
first byte , and the memory capacity of the device in the second byte .
Any Read Identification (RDID) instruction while an Erase or Program cycle is in progress, is not
decoded, and has no effect on the cycle that is in progress. The Read Identification (RDID) instruction
should not be issued while the device is in Deep Power down mode.
The device is first selected by driving Chip Select Low. Then, the 8-bit instruction code for the
instruction is shifted in. This is followed by the 24-bit device identification, stored in the memory, being
shifted out on Serial Data Output, each bit being shifted out during the falling edge of Serial Clock. The
instruction sequence is shown in Figure 25. The Read Identification (RDID) instruction is terminated by
driving Chip Select High at any time during data output.
When Chip Select is driven High, the device is put in the Standby Power mode. Once in the Standby
Power mode, the device waits to be selected, so that it can receive, decode and execute instructions.
The instruction sequence is shown in Figure 25.1 while using the Enable Quad Peripheral Interface mode
(EQPI) (38h) command.
Figure 25. Read Identification (RDID)
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EN25QH32
Figure 25.1. Read Identification (RDID) under EQPI Mode
Enter OTP Mode (3Ah)
This Flash has an extra 512 bytes OTP sector, user must issue ENTER OTP MODE command to read,
program or erase OTP sector. After entering OTP mode, the OTP sector is mapping to sector 1023,
SRP bit becomes OTP_LOCK bit and can be read with RDSR command. Program / Erase command
will be disabled when OTP_LOCK bit is ‘1’
WRSR command will ignore the input data and program OTP_LOCK bit to 1. User must clear the
protect bits before enter OTP mode.
OTP sector can only be program and erase before OTP_LOCK bit is set to ‘1’ and BP [3:0] = ‘0000’. In
OTP mode, user can read other sectors, but program/erase other sectors only allowed when
OTP_LOCK bit equal to ‘0’.
User can use WRDI (04h) command to exit OTP mode.
While in OTP mode, user can use Sector Erase (20h) command only to erase OTP data.
The instruction sequence is shown in Figure 26.1 while using the Enable Quad Peripheral Interface mode
(EQPI) (38h) command.
Table 7. OTP Sector Address
Sector
Sector Size
Address Range
1023
512 byte
3FF000h – 3FF1FFh
Note: The OTP sector is mapping to sector 1023
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Figure 26. Enter OTP Mode Sequence
Figure 26.1 Enter OTP Mode Sequence under EQPI Mode
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EN25QH32
Read SFDP Mode and Unique ID Number (5Ah)
Read SFDP Mode
EN25QH32 features Serial Flash Discoverable Parameters (SFDP) mode. Host system can retrieve the
operating characteristics, structure and vendor specified information such as identifying information,
memory size, operating voltage and timing information of this device by SFDP mode.
The device is first selected by driving Chip Select (CS#) Low. The instruction code for the Read SFDP
Mode is followed by a 3-byte address (A23-A0) and a dummy byte, each bit being latched-in during the
rising edge of Serial Clock (CLK). Then the memory contents, at that address, is shifted out on Serial
Data Output (DO), each bit being shifted out, at a maximum frequency FR, during the falling edge of
Serial Clock (CLK).
The instruction sequence is shown in Figure 27. The first byte addressed can be at any location. The
address is automatically incremented to the next higher address after each byte of data is shifted out.
The whole memory can, therefore, be read with a single Serial Flash Discoverable Parameters (SFDP)
instruction. When the highest address is reached, the address counter rolls over to 0x00h, allowing the
read sequence to be continued indefinitely. The Serial Flash Discoverable Parameters (SFDP)
instruction is terminated by driving Chip Select (CS#) High. Chip Select (CS#) can be driven High at
any time during data output. Any Read Data Bytes at Serial Flash Discoverable Parameters (SFDP)
instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects
on the cycle that is in progress.
Figure 27. Read SFDP Mode and Unique ID Number Instruction Sequence Diagram
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EN25QH32
Table 8. Serial Flash Discoverable Parameters (SFDP) Signature and Parameter Identification
Data Value (Advanced Information)
Description
SFDP Signature
SFDP Minor Revision Number
SFDP Major Revision Number
Number of Parameter Headers (NPH)
Unused
ID Number
Parameter Table Minor Revision
Number
Parameter Table Major Revision
Number
Parameter Table Length (in DW)
Parameter Table Pointer (PTP)
Unused
Address (h)
Address (Bit)
(Byte Mode)
Data
Comment
00h
01h
02h
03h
04h
05h
06h
07h
08h
07 : 00
15 : 08
23 : 16
31 : 24
07 : 00
15 : 08
23 : 16
31 : 24
07 : 00
53h
46h
44h
50h
00h
01h
00h
FFh
00h
Star from 0x00
Star from 0x01
1 parameter header
Reserved
JEDEC ID
09h
15 : 08
00h
Star from 0x00
0Ah
23 : 16
01h
Star from 0x01
0Bh
0Ch
0Dh
0Eh
0Fh
31 : 24
07 : 00
15 : 08
23 : 16
31 : 24
09h
30h
00h
00h
FFh
9 DWORDs
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Signature [31:0]:
Hex: 50444653
000030h
Reserved
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EN25QH32
Table 9. Parameter ID (0) (Advanced Information) 1/9
Description
Address (h)
(Byte Mode)
Address
(Bit)
Block / Sector Erase sizes
Identifies the erase granularity for all Flash
Components
00
Write Granularity
Write Enable Instruction Required for
Writing to Volatile Status Register
Write Enable Opcode Select for Writing to
Volatile Status Register
02
30h
01b
1b
0 = No, 1 = Yes
00b
00 = N/A
01 = use 50h opcode
11 = use 06h opcode
03
04
31h
Supports (1-1-2) Fast Read
Device supports single input opcode & address
and quad output data Fast Read
05
06
07
08
09
10
11
12
13
14
15
111b
4 KB Erase Support
(FFh = not supported)
1b
0 = not supported
1 = supported
00b
00 = 3-Byte
01 = 3- or 4-Byte (e.g.
defaults to 3-Byte
mode; enters 4-Byte
mode on command)
10 = 4-Byte
11 = reserved
19
0b
0 = not supported
1 = supported
20
1b
0 = not supported
1 = supported
21
1b
0 = not supported
1 = supported
22
0b
0 = not supported
1 = supported
23
24
1b
Reserved
FFh
Reserved
17
Supports Double Transfer Rate (DTR)
Clocking
Indicates the device supports some type of
double transfer rate clocking.
Supports (1-2-2) Fast Read
Device supports single input opcode, dual input
address, and quad output data Fast Read
Supports (1-4-4) Fast Read
Device supports single input opcode, quad input
address, and quad output data Fast Read
Supports (1-1-4) Fast Read
Device supports single input opcode & address
and quad output data Fast Read
Unused
18
32h
Reserved
20h
16
Address Byte
Number of bytes used in addressing for flash arra
write and erase.
Comment
00 = reserved
01 = 4KB erase
10 = reserved
11 = 64KB erase
01
Unused
4 Kilo-Byte Erase Opcode
Data
25
26
Unused
33h
27
28
29
30
31
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EN25QH32
Table 9. Parameter ID (0) (Advanced Information) 2/9
Description
Flash Memory Density
Address (h)
(Byte Mode)
37h : 34h
Address
(Bit)
31 : 00
Data
Comment
01FFFFFFh
32 Mbits
Data
Comment
00100b
4 dummy clocks
010b
8 mode bits
Table 9. Parameter ID (0) (Advanced Information) 3/9
Description
(1-4-4) Fast Read Number of Wait states
(dummy clocks) needed before valid
output
Address (h)
(Byte Mode)
38h
Quad Input Address Quad Output (1-44) Fast Read Number of Mode Bits
(1-4-4) Fast Read Opcode
Opcode for single input opcode, quad input
address, and quad output data Fast Read.
(1-1-4) Fast Read Number of Wait states
(dummy clocks) needed before valid
output
39h
3Ah
(1-1-4) Fast Read Number of Mode Bits
(1-1-4) Fast Read Opcode
Opcode for single input opcode & address
and quad output data Fast Read.
3Bh
Address
(Bit)
00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
23
31 : 24
EBh
00000b
Not Supported
000b
Not Supported
FFh
Not Supported
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or modifications due to changes in technical specifications.
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EN25QH32
Table 9. Parameter ID (0) (Advanced Information) 4/9
Description
(1-1-2) Fast Read Number of Wait states
(dummy clocks) needed before valid
output
Address (h)
(Byte Mode)
3Ch
(1-1-2) Fast Read Number of Mode Bits
(1-1-2) Fast Read Opcode
Opcode for single input opcode & address
and dual output data Fast Read.
(1-2-2) Fast Read Number of Wait states
(dummy clocks) needed before valid
output
3Dh
15 : 08
3Eh
16
17
18
19
20
21
22
23
(1-2-2) Fast Read Number of Mode Bits
(1-2-2) Fast Read Opcode
Opcode for single input opcode, dual input
address, and dual output data Fast Read.
Address
(Bit)
00
01
02
03
04
05
06
07
3Fh
Data
Comment
01000b
8 dummy clocks
000b
Not Supported
3Bh
00100b
4 dummy clocks
000b
Not Supported
31 : 24
BBh
Address
(Bit)
Data
Supports (4-4-4) Fast Read
Device supports Quad input opcode &
address and quad output data Fast Read.
00
0b
Reserved. These bits default to all 1’s
01
02
03
111b
04
1b
Table 9. Parameter ID (0) (Advanced Information) 5/9
Description
Supports (2-2-2) Fast Read
Device supports dual input opcode &
address and dual output data Fast Read.
Address (h)
(Byte Mode)
40h
Reserved. These bits default to all 1’s
Reserved. These bits default to all 1’s
43h : 41h
05
06
07
31 : 08
Comment
0 = not supported
1 = supported
Reserved
0 = not supported
1 = supported
(EQPI Mode)
111b
Reserved
FFh
Reserved
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or modifications due to changes in technical specifications.
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EN25QH32
Table 9. Parameter ID (0) (Advanced Information) 6/9
Description
Reserved. These bits default to all 1’s
(2-2-2) Fast Read Number of Wait states
(dummy clocks) needed before valid
output
Address (h)
(Byte Mode)
45h : 44h
46h
(2-2-2) Fast Read Number of Mode Bits
(2-2-2) Fast Read Opcode
Opcode for dual input opcode & address
and dual output data Fast Read.
47h
Address
(Bit)
15 : 00
16
17
18
19
20
21
22
23
31 : 24
Data
Comment
FFh
Reserved
00000b
Not Supported
000b
Not Supported
FFh
Not Supported
Data
Comment
Table 9. Parameter ID (0) (Advanced Information) 7/9
Description
Reserved. These bits default to all 1’s
(4-4-4) Fast Read Number of Wait states
(dummy clocks) needed before valid
output
Address (h)
(Byte Mode)
49h : 48h
4Ah
(4-4-4) Fast Read Number of Mode Bits
(4-4-4) Fast Read Opcode
Opcode for quad input opcode/address,
quad output data Fast Read.
4Bh
Address
(Bit)
15 : 00
16
17
18
19
20
21
22
23
FFh
Reserved
00100b
4 dummy clocks
010b
8 mode bits
31 : 24
EBh
Must Enter EQPI
Mode Firstly
Table 9. Parameter ID (0) (Advanced Information) 8/9
Description
Sector Type 1 Size
Sector Type 1 Opcode
Sector Type 2 Size
Sector Type 2 Opcode
Address (h)
(Byte Mode)
4Ch
4Dh
4Eh
4Fh
Address
(Bit)
07 : 00
15 : 08
23 : 16
31 : 24
Data
Comment
0Ch
20h
00h
FFh
4 KB
Not Supported
Not Supported
Data
Comment
10h
D8h
00h
FFh
64 KB
Table 9. Parameter ID (0) (Advanced Information) 9/9
Description
Sector Type 3 Size
Sector Type 3 Opcode
Sector Type 4 Size
Sector Type 4 Opcode
Address (h)
(Byte Mode)
50h
51h
52h
53h
Address
(Bit)
07 : 00
15 : 08
23 : 16
31 : 24
This Data Sheet may be revised by subsequent versions
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or modifications due to changes in technical specifications.
Rev. E, Issue Date: 2012/01/30
Not Supported
Not Supported
www.eonssi.com
EN25QH32
Read Unique ID Number
The Read Unique ID Number instruction accesses a factory-set read-only 96-bit number that is unique
to each EN25QH32 device. The ID number can be used in conjunction with user software methods to
help prevent copying or cloning of a system. The Read Unique ID instruction is initiated by driving the
CS# pin low and shifting the instruction code “5Ah” followed by a three bytes of addresses, 0x80h, and
one byte of dummy clocks. After which, the 96-bit ID is shifted out on the falling edge of CLK as shown
in figure 27.
Table 10. Unique ID Number
Description
Address (h)
(Byte Mode)
Address
(Bit)
Data
Unique ID Number
80h : 8Bh
95 : 00
By die
Comment
Power-up Timing
Figure 28. Power-up Timing
Table 11. Power-Up Timing and Write Inhibit Threshold
Symbol
Parameter
Min.
Max.
Unit
tVSL(1)
VCC(min) to CS# low
10
tPUW(1)
Time delay to Write instruction
1
10
ms
Write Inhibit Voltage
1
2.5
V
VWI(1)
µs
Note:
1.The parameters are characterized only.
2. VCC (max.) is 3.6V and VCC (min.) is 2.7V
INITIAL DELIVERY STATE
The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh).
The Status Register contains 00h (all Status Register bits are 0).
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or modifications due to changes in technical specifications.
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EN25QH32
Table 12. DC Characteristics
(Ta = - 40°C to 85°C; VCC = 2.7-3.6V)
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
ILI
Input Leakage Current
-
±2
µA
ILO
Output Leakage Current
-
±2
µA
ICC1
Standby Current
CS# = VCC, VIN = VSS or VCC
-
20
µA
ICC2
Deep Power-down Current
-
20
µA
-
25
mA
ICC3
Operating Current (READ)
CS# = VCC, VIN = VSS or VCC
CLK = 0.1 VCC / 0.9 VCC at
104MHz, DQ = open
-
20
mA
ICC4
Operating Current (PP)
CLK = 0.1 VCC / 0.9 VCC at
80MHz, DQ = open
CS# = VCC
-
28
mA
-
18
mA
Operating Current (SE)
CS# = VCC
CS# = VCC
-
25
mA
ICC7
Operating Current (BE)
CS# = VCC
-
25
mA
VIL
Input Low Voltage
– 0.5
0.2 VCC
V
VIH
Input High Voltage
0.7VCC
VCC+0.4
V
VOL
Output Low Voltage
IOL = 1.6 mA
-
0.4
V
VOH
Output High Voltage
IOH = –100 µA
VCC-0.2
-
V
ICC5
Operating Current (WRSR)
ICC6
Table 13. AC Measurement Conditions
Symbol
CL
Parameter
Min.
Max.
Unit
Load Capacitance
20
pF
Input Rise and Fall Times
5
ns
Input Pulse Voltages
0.2VCC to 0.8VCC
V
Input Timing Reference Voltages
0.3VCC to 0.7VCC
V
VCC / 2
V
Output Timing Reference Voltages
Figure 29. AC Measurement I/O Waveform
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or modifications due to changes in technical specifications.
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EN25QH32
Table 14. AC Characteristics
(Ta = - 40°C to 85°C; VCC = 2.7-3.6V)
Symbol
FR
Alt
fC
Parameter
Serial Clock Frequency for:
FAST_READ, PP, SE, BE, DP, RES, WREN,
WRDI, WRSR
MHz
D.C.
-
80
MHz
D.C.
-
50
MHz
4
-
-
ns
4
-
-
ns
Serial Clock Rise Time (Slew Rate)
0.1
-
-
V / ns
Serial Clock Fall Time (Slew Rate)
0.1
-
-
V / ns
5
-
-
ns
Serial Clock Frequency for:
RDSR, RDID, Dual Output Fast Read
Serial Clock Low Time
tCHCL
2
tSLCH
tCSS
Unit
104
tCL1
tCLCH
Max
-
tCH 1
2
Typ
D.C.
Serial Clock Frequency for READ, Quad I/O Fast
Read
Serial Clock High Time
fR
Min
CS# Active Setup Time (Relative to CLK)
tCHSH
CS# Active Hold Time (Relative to CLK)
5
-
-
ns
tSHCH
CS# Not Active Setup Time (Relative to CLK)
5
-
-
ns
tCHSL
5
15
50
-
-
-
-
-
-
6
ns
ns
ns
ns
0
-
-
ns
tDIS
CS# Not Active Hold Time (Relative to CLK)
CS# High Time for read
CS# High Time for program/erase
Output Disable Time
tCLQX
tHO
Output Hold Time
tDVCH
tDSU
Data In Setup Time
2
-
-
ns
tCHDX
tDH
Data In Hold Time
5
-
-
ns
tHLCH
HOLD# Low Setup Time ( relative to CLK )
5
ns
tHHCH
HOLD# High Setup Time ( relative to CLK )
5
ns
tCHHH
HOLD# Low Hold Time ( relative to CLK )
5
ns
HOLD# High Hold Time ( relative to CLK )
5
tSHSL
tSHQZ
tCSH
2
tCHHL
ns
tHLQZ
2
tHZ
HOLD# Low to High-Z Output
6
ns
tHHQX
2
tLZ
HOLD# High to Low-Z Output
6
ns
tV
Output Valid from CLK
tCLQV
tWHSL3
tSHWL3
tDP 2
-
-
8
ns
Write Protect Setup Time before CS# Low
20
-
-
ns
Write Protect Hold Time after CS# High
100
-
-
ns
-
-
3
µs
-
-
3
µs
-
-
1.8
µs
tW
CS# High to Deep Power-down Mode
CS# High to Standby Mode without Electronic
Signature read
CS# High to Standby Mode with Electronic
Signature read
Write Status Register Cycle Time
-
15
50
ms
tPP
Page Programming Time
-
1.3
5
ms
tSE
0.3
6
tRES1 2
tRES2 2
Sector Erase Time
-
0.09
tBE
Block Erase Time
-
0.5
2
s
tCE
Chip Erase Time
-
25
50
s
tSR
Software Reset
Latency
WIP = write operation
-
-
28
µs
WIP = not in write operation
-
-
0
µs
Note: 1. tCH + tCL must be greater than or equal to 1/ fC
2. Value guaranteed by characterization, not 100% tested in production.
3. Only applicable as a constraint for a Write status Register instruction when Status Register Protect Bit is set at 1.
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or modifications due to changes in technical specifications.
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EN25QH32
Figure 30. Serial Output Timing
Figure 31. Input Timing
Figure 32. Hold Timing
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or modifications due to changes in technical specifications.
Rev. E, Issue Date: 2012/01/30
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EN25QH32
ABSOLUTE MAXIMUM RATINGS
Stresses above the values so mentioned above may cause permanent damage to the device. These
values are for a stress rating only and do not imply that the device should be operated at conditions up
to or above these values. Exposure of the device to the maximum rating values for extended periods of
time may adversely affect the device reliability.
Parameter
Value
Unit
Storage Temperature
-65 to +150
C
Plastic Packages
-65 to +125
C
Output Short Circuit Current1
200
mA
Input and Output Voltage
(with respect to ground) 2
-0.5 to +4.0
V
Vcc
-0.5 to +4.0
V
Notes:
1.
No more than one output shorted at a time. Duration of the short circuit should not be greater than one second.
2.
Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, inputs may undershoot Vss to –1.0V for periods of
up to 50ns and to –2.0 V for periods of up to 20ns. See figure below. Maximum DC voltage on output and I/O pins is Vcc + 0.5
V. During voltage transitions, outputs may overshoot to Vcc + 1.5 V for periods up to 20ns. See figure below.
RECOMMENDED OPERATING RANGES 1
Parameter
Value
Ambient Operating Temperature
Industrial Devices
-40 to 85
Operating Supply Voltage
Vcc
Full: 2.7 to 3.6
Unit
C
V
Notes:
1. Recommended Operating Ranges define those limits between which the functionality of the device is guaranteed.
Vcc
+1.5V
Maximum Negative Overshoot Waveform
Maximum Positive Overshoot Waveform
This Data Sheet may be revised by subsequent versions
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or modifications due to changes in technical specifications.
Rev. E, Issue Date: 2012/01/30
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EN25QH32
Table 15. DATA RETENTION and ENDURANCE
Parameter Description
Data Retention Time
Erase/Program Endurance
Test Conditions
Min
Unit
150°C
10
Years
125°C
20
Years
-40 to 85 °C
100k
cycles
Table 16. CAPACITANCE
( VCC = 2.7-3.6V)
Parameter Symbol
Parameter Description
Test Setup
Max
Unit
CIN
Input Capacitance
VIN = 0
6
pF
COUT
Output Capacitance
VOUT = 0
8
pF
Note : Sampled only, not 100% tested, at TA = 25°C and a frequency of 20MHz.
This Data Sheet may be revised by subsequent versions
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or modifications due to changes in technical specifications.
Rev. E, Issue Date: 2012/01/30
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EN25QH32
PACKAGE MECHANICAL
Figure 33. SOP 200 mil ( official name = 208 mil )
SYMBOL
DIMENSION IN MM
NOR
1.975
0.15
1.825
5.275
7.90
5.275
1.27
0.425
0.65
MIN.
MAX
A
1.75
2.20
A1
0.05
0.25
A2
1.70
1.95
D
5.15
5.40
E
7.70
8.10
E1
5.15
5.40
e
----b
0.35
0.50
L
0.5
0.80
0
0
0
θ
0
4
8
Note : 1. Coplanarity: 0.1 mm
2. Max. allowable mold flash is 0.15 mm
at the pkg ends, 0.25 mm between leads.
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or modifications due to changes in technical specifications.
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EN25QH32
Figure 34. VDFN 8 ( 5x6 mm )
Controlling dimensions are in millimeters (mm).
DIMENSION IN MM
MIN.
NOR
MAX
A
0.70
0.75
0.80
A1
0.00
0.02
0.04
A2
--0.20
--D
5.90
6.00
6.10
E
4.90
5.00
5.10
D2
3.30
3.40
3.50
E2
3.90
4.00
4.10
e
--1.27
--b
0.35
0.40
0.45
L
0.55
0.60
0.65
Note : 1. Coplanarity: 0.1 mm
SYMBOL
This Data Sheet may be revised by subsequent versions
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or modifications due to changes in technical specifications.
Rev. E, Issue Date: 2012/01/30
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EN25QH32
Figure 35. PDIP8
SYMBOL
A
A1
A2
D
E
E1
L
eB
Θ0
DIMENSION IN INCH
MIN.
NOR
MAX
----0.210
0.015
----0.125
0.130
0.135
0.355
0.365
0.400
0.300
0.310
0.320
0.245
0.250
0.255
0.115
0.130
0.150
0.310
0.350
0.375
0
7
15
This Data Sheet may be revised by subsequent versions
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or modifications due to changes in technical specifications.
Rev. E, Issue Date: 2012/01/30
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EN25QH32
Figure 36. 16 LEAD SOP 300 mil
SYMBOL
DIMENSION IN MM
NOR
MAX
--2.65
0.20
0.30
--2.40
0.25
0.30
10.30
10.50
--10.65
7.50
7.60
1.27
----0.51
--1.27
MIN.
A
--A1
0.10
A2
2.25
C
0.20
D
10.10
E
10.00
E1
7.40
e
--b
0.31
L
0.4
θ
00
50
Note : 1. Coplanarity: 0.1 mm
80
This Data Sheet may be revised by subsequent versions
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or modifications due to changes in technical specifications.
Rev. E, Issue Date: 2012/01/30
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EN25QH32
Figure 37. 24-ball Thin Profile Fine-Pitch Ball Grid Array (6 x 8 mm) Package
SYMBOL
DIMENSIONIN MM
A
MIN.
- --
NOR
- --
MAX
1.20
A1
0.27
- --
0.37
0.21 REF
0.54 REF
A2
A3
D
E
6
BSC
8
BSC
D1
- --
3.00
- --
E1
e
- -- --
5.00
1.00
- -- --
b
- --
0.40
- --
This Data Sheet may be revised by subsequent versions
©2004 Eon Silicon Solution, Inc.,
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Rev. E, Issue Date: 2012/01/30
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EN25QH32
Purpose
Eon Silicon Solution Inc. (hereinafter called “Eon”) is going to provide its products’ top marking on
ICs with < cFeon > from January 1st, 2009, and without any change of the part number and the
compositions of the Ics. Eon is still keeping the promise of quality for all the products with the
same as that of Eon delivered before. Please be advised with the change and appreciate your
kindly cooperation and fully support Eon’s product family.
Eon products’ Top Marking
cFeon Top Marking Example:
cFeon
Part Number: XXXX-XXX
Lot Number: XXXXX
Date Code:
XXXXX
For More Information
Please contact your local sales office for additional information about Eon memory solutions.
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or modifications due to changes in technical specifications.
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EN25QH32
ORDERING INFORMATION
EN25QH32
-
104
H
I
P
PACKAGING CONTENT
P = RoHS compliant
TEMPERATURE RANGE
I = Industrial (-40°C to +85°C)
PACKAGE
H = 8-pin 200mil SOP
W = 8-pin VDFN (5x6mm)
Q = 8-pin PDIP
F = 16-pin 300mil SOP
BB = 24-ball TFBGA (6 x 8 x 1.2mm)
SPEED
104 = 104 MHz
BASE PART NUMBER
EN = Eon Silicon Solution Inc.
25QH = 3V Serial Flash with 4KB Uniform-Sector,
Dual and Quad I/O
32 = 32 Megabit (4096K x 8)
This Data Sheet may be revised by subsequent versions
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or modifications due to changes in technical specifications.
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EN25QH32
Revisions List
Revision No Description
Date
A
2011/01/05
B
C
D
E
Initial Release
1. Update Read SFDP Mode and Unique ID Number (5Ah) description on
page 44.
2. Update Write Status Register Cycle Time from 10 (typ.) /15 (max.) ms to 15
(typ.) / 50 (max.) ms on page 51.
2011/04/18
3. Rename 24 Ball package from BGA to TFBGA.
1. Add the note “5. This flow cannot release the device from Deep power
down mode.” on page 17.
2. Correct the typo of 6 dummy clocks for EBh command on page 28.
2011/05/31
3. Update Read SFDP Mode and Unique ID Number (5Ah) description on
page 44.
1. Update Figure 2. BLOCK DIAGRAM on page 4.
2. Update the Serial Flash Discoverable Parameters (SFDP) table on page 2011/11/28
45, 46, 47, 48 and 49.
Update Unique ID Number from 64 bits to 96 bits on page 50.
2012/01/30
This Data Sheet may be revised by subsequent versions
©2004 Eon Silicon Solution, Inc.,
63
or modifications due to changes in technical specifications.
Rev. E, Issue Date: 2012/01/30
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