ETC AF4GSDI

Revision 3.7
ATP Industrial Grade SD Card Specification
ATP Industrial Grade SD Card Specification
AF512SDI-5ACXX
AF1GSDI-5ACXX
AF2GSDI-5ADXX
AF4GSDI-5ACXX
AF8GSDI-5ACXX
Revision 3.7
Your Ultimate Memory Solution!
1
ATP Confidential & Proprietary
Revision 3.7
ATP Industrial Grade SD Card Specification
Disclaimer:
ATP Electronics Inc. shall not be liable for any errors or omissions that may appear in this document, and
disclaims responsibility for any consequences resulting from the use of the information set forth herein.
The information in this manual is subject to change without notice.
ATP general policy does not recommend the use of its products in life support applications where in a failure or
malfunction of the product may directly threaten life or injury.
All parts of the ATP documentation are protected by copyright law and all rights are reserved. This
documentation may not, in whole or in part, be copied, photocopied, reproduced, translated, or reduced to any
electronic medium or machine-readable form without prior consent, in writing, from ATP Corporation.
The information set forth in this document is considered to be “Proprietary” and “Confidential” property
owned by ATP.
Revision History
Date
Version
April 15th, 2008
August 13th, 2008
1.0
1.1
Sep. 19th, 2010
1.2
Mar. 4th, 2011
2.0
May. 24th, 2011
2.1
May. 31st, 2011
2.2
Jul. 6th, 2011
2.3
th
Jul. 20 , 2011
Jul. 27th, 2011
2.4
3.0
Nov. 1st, 2011
3.1
th
Nov. 17 , 2011
3.2
Mar. 13th, 2012
3.3
Mar. 29th, 2012
3.4
st
Jun. 21 , 2012
3.5
Changes compared to previous issue
- Base version
- Add 8GB item
- Combine SDHC product spec with SD product spec
- Update the product performance
- Add Bend,Torque, Salt Spray, Solar Radiation certification
- Add ESD, Water, Dust proof certification
- Update MTBF
- Update P/N
- Update MTBF
- Revise 8GB P/N
- Revise performance
- Add density 16GB
- Update performance
- Revise P/N
- Update performance
- Revise
- Revise
- Add 4GB/8GB density
- Add ATP SD life monitor tool
- Update Performance
- Add new features: StaticDataRefresh and SD Life Monitoring Tool
- Add TBW (Total Bytes Written) information
- Add 1GB density and performance
- Add SPI mode information in Chapter 7
- Separate specification by models
- Revise endurance information
Your Ultimate Memory Solution!
2
ATP Confidential & Proprietary
Revision 3.7
ATP Industrial Grade SD Card Specification
Aug. 6th, 2012
3.6
Sep. 19th, 2012
3.7
- Update AF512SDI-5ACXX
- Product line up
AF512SDI-5ACXX, AF1GSDI-5ACXX, AF2GSDI-5ADXX,
AF4GSDI-5ACXX, AF8GSDI-5ACXX
- Update Data Retention information
Your Ultimate Memory Solution!
3
ATP Confidential & Proprietary
Revision 3.7
ATP Industrial Grade SD Card Specification
Table of Contents
1
ATP Industrial Grade SD/SDHC Card Overview ....................................................................... 6
1.1
1.2
1.3
2
ATP Product Availability........................................................................................................................6
Main Features ..........................................................................................................................................7
Application ..............................................................................................................................................7
Product Specifications .................................................................................................................... 8
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
3
Environment Specifications ....................................................................................................................8
Reliability ................................................................................................................................................9
Data Retention ...................................................................................................................................... 10
Performance ......................................................................................................................................... 10
Electrical Characteristics ...................................................................................................................... 11
Extra Features....................................................................................................................................... 11
Global Wear Leveling- Longer Life Expectancy ................................................................................. 12
StaticDataRefresh Technology – Ensure Data Integrity ....................................................................... 12
SD Life Monitoring Tool – Lifespan check ......................................................................................... 13
Physical Dimension (Units in MM) ..................................................................................................... 14
Mechanical Form Factor (Units in MM) .............................................................................................. 14
Electrical Characteristics ............................................................................................................. 15
3.1
3.2
4
DC Characteristics................................................................................................................................ 15
AC Characteristics................................................................................................................................ 16
SD Card Hardware System .......................................................................................................... 20
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
5
SD Card Description ............................................................................................................................ 20
SD BUS Topology ............................................................................................................................... 21
SD Card Hardware Interface ................................................................................................................ 22
Bus Signal Line Load ........................................................................................................................... 23
Hot Insertion and Removal................................................................................................................... 24
Power up .............................................................................................................................................. 24
Compatibility to Multi Media Card ...................................................................................................... 25
Card Capacity ....................................................................................................................................... 25
Card Registers ............................................................................................................................... 27
5.1
5.2
5.3
5.4
5.5
5.6
5.7
6
OCR Register ....................................................................................................................................... 27
CID Register ......................................................................................................................................... 27
CSD Register ........................................................................................................................................ 29
RCA Register ....................................................................................................................................... 34
SCR Register ........................................................................................................................................ 34
SSR Register ........................................................................................................................................ 36
CSR Register ........................................................................................................................................ 36
SD Card Functional Description.................................................................................................. 37
6.1
6.2
6.2.1
SD BUS Protocol ................................................................................................................................. 37
Command ............................................................................................................................................. 40
Command Types and Format ........................................................................................................................... 40
Your Ultimate Memory Solution!
4
ATP Confidential & Proprietary
Revision 3.7
6.2.2
6.2.3
ATP Industrial Grade SD Card Specification
Command Classes ............................................................................................................................................ 41
• Detailed Command Description .................................................................................................................... 43
6.3
Card State Transition Table.................................................................................................................. 50
Responses .......................................................................................................................................................... 53
6.4
SD Card Status ..................................................................................................................................... 56
6.4.1
6.4.2
6.5
6.5.1
6.5.2
6.6
6.6.1
6.6.2
6.6.3
6.6.4
7
Card Status ....................................................................................................................................................... 56
SD Status ......................................................................................................................................................... 60
Card Identification Mode and Data Transfer Mode ............................................................................. 64
Card Identification Mode ................................................................................................................................. 64
Data Transfer Mode ......................................................................................................................................... 68
Error Handling ..................................................................................................................................... 70
Error Correction Code (ECC)........................................................................................................................... 70
Cyclic Redundancy Check (CRC) .................................................................................................................... 70
CRC and Illegal Command .............................................................................................................................. 71
Read, Write and Erase Time-out ...................................................................................................................... 71
SPI Mode........................................................................................................................................ 73
7.1
7.2
7.3
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.3.6
7.3.7
Introduction .......................................................................................................................................... 73
SPI BUS Topology............................................................................................................................... 73
SPI Bus Protocol .................................................................................................................................. 74
Mode Selection and Initialization ..................................................................................................................... 75
Bus Transfer Protection ................................................................................................................................... 77
Data Read......................................................................................................................................................... 77
Data Write ........................................................................................................................................................ 78
Erase & Write Protect Management ................................................................................................................ 79
Read CID/CSD Registers ................................................................................................................................. 80
Reset Sequence ................................................................................................................................................ 80
Your Ultimate Memory Solution!
5
ATP Confidential & Proprietary
Revision 3.7
ATP Industrial Grade SD Card Specification
1 ATP Industrial Grade SD/SDHC Card Overview
1.1 ATP Product Availability
Figure 1-1: Product Pictures
ATP P/N
CAPACITY
AF512SDI-5ACXX
512MB
AF1GSDI-5ACXX
1GB
*AF2GSDI-5ADXX
2GB
*AF4GSDI-5ACXX
4GB
*AF8GSDI-5ACXX
8GB
Table 1-1: Capacities
*Note: Support by project, please contact ATP for more information.
Your Ultimate Memory Solution!
6
ATP Confidential & Proprietary
Revision 3.7
ATP Industrial Grade SD Card Specification
1.2 Main Features

Compatible with SD Specifications Version 2.00

Support SD mode, SPI mode

High reliability, operating at -40oC to 85oC

SLC (Single-Level-Cell) NAND Flash

Water proof, Dust proof and ESD proof

SIP (System-In-Package) process

Resistance to Shock and Vibration

Enhanced endurance by Global Wear Leveling algorithm

SaticDataRefresh technology to ensure data integrity in read operations

Available Life Monitor Tool to check the remaining life of ATP SD/SDHC card

Enhanced power cycling support

Support BCH ECC up to 40bits/1KByte

Supports CPRM

Form factor: 32 x 24 x 2.1mm

RoHS compliant

CE & FCC certification

Controlled BOM

Customized service: adjustable CID registers, firmware & setting and label by projects
1.3 Application
ATP Industrial Grade SD/SDHC cards are designed for demanding industrial applications, such as
handheld computing, military/aerospace, automotive, marine navigation, embedded systems,
communication equipment or networking, medical equipment, and automation, where mission-critical
data requires the highest level of reliability, durability, and data integrity.
Your Ultimate Memory Solution!
7
ATP Confidential & Proprietary
Revision 3.7
ATP Industrial Grade SD Card Specification
2 Product Specifications
2.1 Environment Specifications
TYPE
Temperature
Humidity
MEASUREMENT
-40 C to 85 C
Non-Operation
-40oC to 85oC
Operation
25oC, 10% ~ 95% RH, non-condensing
Non-Operation
40oC, 10% ~ 93% RH, non-condensing
10N to the center of the card, 250 cycles,
30 cycles/minute
0.15N-m or +/-2.5°, 30 cycles/minute,
1000 cycles
Non-Operation
Torque Test
Non-Operation
Non-Operation
35℃,Over 85% RH,5% Salt Concentration,
24 hours
Non-Operation
40℃ ,Irradiation 1000W/m², 24 hours
Non-Operation
254nm, 15Ws/cm2
Non-Operation
150cm/Free fall, total 6 drops
Table 2-1: Environment
Your Ultimate Memory Solution!
8
o
Operation
Bend Test
Salt Spray Test
(MIL-STD-883G
Method1009.8)
Solar Radiation Test
UV Light Exposure Test
(ISO 7816-1)
Drop Test
o
ATP Confidential & Proprietary
Revision 3.7
ATP Industrial Grade SD Card Specification
2.2 Reliability
TYPE
Number of insertions
Endurance Technology
MEASUREMENT
10,000 minimum
SLC NAND Flash block endurance:
512MB / 2GB / 4GB / 8GB: 60,000 P/E cycles
1GB: 100,000 P/E cycles
Global Wear Leveling algorithm
512MB
1GB
TBW
(Total Bytes Written)
2GB
4GB
8GB
MTBF(@ 25oC)
6.1
12.3
20
40
24
48
48
96
96
192
Terabytes random write
Terabytes sequential write
Terabytes random write
Terabytes sequential write
Terabytes random write
Terabytes sequential write
Terabytes random write
Terabytes sequential write
Terabytes random write
Terabytes sequential write
>2,000,000 hours
Table 2-2: Reliability
Note: Endurance for flash cards can be predicted based on the usage conditions applied to the device, the internal NAND
flash cycles, the write amplification factor, and the wear leveling efficiency of the flash devices.
Your Ultimate Memory Solution!
9
ATP Confidential & Proprietary
Revision 3.7
ATP Industrial Grade SD Card Specification
2.3 Data Retention
512MB/2GB/4GB/8GB SD card
Endurance Used
Number of P/E Cycles Used
(block level)
Corresponding Data Retention at
25C use condition
10% P/E cycles
6,000 Cycles
10 years
100% P/E cycles
60,000 Cycles
1 year
Endurance Used
Number of P/E Cycles Used
(block level)
Corresponding Data Retention at
25C use condition
10% P/E cycles
10,000 Cycles
10 years
100% P/E cycles
100,000 Cycles
1 year
1GB SD card
Table 2-3: Data Retention
Note 1: Data retention refers to the ability of a memory bit to retain its data state over a period of time after the
data is written in NAND Flash regardless of whether the part is powered on or powered off.
A data retention failure is when there is at least 1 bit of data that cannot be read or is read incorrectly.
Note 2: NAND Flash suppliers refer to JEDEC JESD47 & JESD22 for Data Retention testing.
Based on the information provided by NAND Flash suppliers, ATP targets Data Retention as above table for
reference.
2.4 Performance
Model P/N
AF512SDI-5ACXX
AF1GSDI-5ACXX
AF2GSDI-5ADXX
AF4GSDI-5ACXX
AF8GSDI-5ACXX
Seq. Read
(KB/s)
19579
18989
20634
20469
20317
Seq. Write
(KB/s)
14998
17009
11296
18720
16377
Random Read
(KB/s)
17855
17123
18980
18196
18196
Random Write
(KB/s)
5078
5371
4154
6081
5577
Table 2-4: Performance
Note: Tested by HDBench 3.40 beta6 with 40MB file size. The performance may vary depending on the configuration,
firmware, setting, application and testing environment.
Your Ultimate Memory Solution!
10
ATP Confidential & Proprietary
Revision 3.7
ATP Industrial Grade SD Card Specification
2.5 Electrical Characteristics
TYPE
Card supported Voltage
Card supported Frequency
MEASUREMENT
2.7~3.6V
0~50 MHz
Data Bus Width Supported
1 or 4 bits
Table 2-5: Electrical Characteristics
2.6 Extra Features
TYPE
Water Proof
Dust Proof
ESD Proof
RoHS Compliant
MEASUREMENT
IEC 60529 Edition 2.1: 2001-02—IPX7, below 1000mm
water, 30min
IEC 60529 Edition 2.1: 2001-02—IP6X
IEC 61000-4-2:
contact pad +/- 4KV,
non-contact pad (Coupling plane discharge) +/- 8KV,
non-contact pad (Air discharge) +/- 15KV
Yes
Table 2-6: Extra Features
Your Ultimate Memory Solution!
11
ATP Confidential & Proprietary
Revision 3.7
ATP Industrial Grade SD Card Specification
2.7 Global Wear Leveling- Longer Life Expectancy
The program / erase cycle of each sector/page/block is finite. Writing constantly on the same spot
will cause the flash to wear out quickly. Furthermore, bit errors are not proportioned to P/E cycles;
sudden death may occur when the block is close to its P/E cycle limit. Then unrecoverable bit errors
will cause fatal data loss (especially for system data or FAT).
Global wear leveling algorithm evenly distributes the P/E cycles of each block to minimize the
possibility of one block exceeding its max P/E cycles before the rest. In return, the life expectancy of
memory storage device is prolonged and the chance/occurrence of unrecoverable bit errors could be
reduced.
2.8 StaticDataRefresh Technology – Ensure Data Integrity
Over time the error bits accumulate to the threshold in the flash memory cell and eventually
become uncorrectable despite using the ECC engine. In the traditional handling method, the data is
moved to a different location in the flash memory; despite the corrupted data is beyond repaired before
the transition.
To prevent data corruption, the SD card monitors the error bit levels in every operation; when it
reaches the preset threshold value, StaticDataRefresh is achieved by erasing and re-programming the
data into the same block or into another block. After the re-programming operation is completed, the
controller reads the data and compares the data/parity to ensure data integrity.
Your Ultimate Memory Solution!
12
ATP Confidential & Proprietary
Revision 3.7
ATP Industrial Grade SD Card Specification
2.9 SD Life Monitoring Tool – Lifespan check
ATP provides SD Life Monitoring Tool, which can automatically identify ATP memory cards and
check the remaining life of ATP microSD / SD cards under Windows 2000/XP/Vista/7. Users can thus
evaluate ATP memory card’s health status at run time and receive an early warning before its life ends.
User Friendly Life Bar
Remaining Life %
Figure 2-9: SD Life Monitoring
Note: The SD card will be busy while SD Life Monitoring Tool is retrieving the information from the
SD card. Due to this reason, the user cant' execute this software from the same SD card that is being
monitored.
Your Ultimate Memory Solution!
13
ATP Confidential & Proprietary
Revision 3.7
ATP Industrial Grade SD Card Specification
2.10 Physical Dimension (Units in MM)
TYPE
Length
Width
Thickness
Weight
MEASUREMENT
32mm +/- 0.1mm
24mm +/- 0.1mm
2.1mm +/- 0.15mm
2.0 gram Max.
Table 2-10 Physical Dimension
2.11 Mechanical Form Factor (Units in MM)
Figure 2-11: Physical Dimension
Your Ultimate Memory Solution!
14
ATP Confidential & Proprietary
Revision 3.7
ATP Industrial Grade SD Card Specification
3 Electrical Characteristics
3.1 DC Characteristics
Figure 3-1: Bus Signal Level
PARAMETER
Supply Voltage
Operating Current
Standby Current
Input Leakage Current
Output Leakage Current
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
SYMBOL
MIN
VDD
2.7
ICC1
ISB
ILI
-10
ILO
-10
VIH
0.625 x VDD
VIL
Vss -0.3
VOH
0.75x VDD
VOL
-
TYPICAL
3.3
50
-
Table 3-1: DC Characteristics
Your Ultimate Memory Solution!
15
ATP Confidential & Proprietary
MAX
3.6
200
10
10
VDD + 0.3
0.25 x VDD
0.125 x VDD
UNIT
V
mA
µA
µA
µA
V
V
V
V
REMARK
Revision 3.7
ATP Industrial Grade SD Card Specification
3.2 AC Characteristics
Figure 3-2: Timing diagram data input/output referenced to clock (Default)
High Speed Mode Bus Timing:
Parameter
Symbol
Min
Max
Unit
Remark
Clock CLK (All values are referred to min (VIH) and max (VIL)
Clock frequency Data Transfer Mode
Clock low time
Clock high time
Clock rise time
Clock fall time
fPP
tWL
tWH
tTLH
tTHL
0
7
7
-
50
3
3
MHz
ns
ns
ns
ns
Ccard <= 10 pF(1 card)
Ccard <= 10 pF(1 card)
Ccard <= 10 pF(1 card)
Ccard <= 10 pF(1 card)
Ccard <= 10 pF(1 card)
tISU
tIH
6
2
-
ns
ns
Ccard <= 10 pF(1 card)
Ccard <= 10 pF(1 card)
Inputs CMD, DAT (referenced to CLK)
Input set-up time
Input hold time
Your Ultimate Memory Solution!
16
ATP Confidential & Proprietary
Revision 3.7
ATP Industrial Grade SD Card Specification
Outputs CMD, DAT (referenced to CLK)
Output Delay time during Data Transfer
Mode
tODLY
-
14
ns
CL <= 40 pF(1 card)
Table 3-2: Bus Timing - Parameters Values (High Speed Mode)
Default Bus Timing(Backward Compatible):
Parameter
Symbol
Min
Max
Unit
Remark
Clock CLK (All values are referred to min (VIH) and max (VIL)
Clock frequency Data Transfer Mode
Clock frequency Identification Mode
Clock low time
Clock high time
Clock rise time
Clock fall time
fPP
fOD
tWL
tWH
tTLH
tTHL
0
0
10
10
-
25
400
10
10
MHz
KHz
ns
ns
ns
ns
Ccard <= 10 pF(1 card)
Ccard <= 10 pF(1 card)
Ccard <= 10 pF(1 card)
Ccard <= 10 pF(1 card)
Ccard <= 10 pF(1 card)
Ccard <= 10 pF(1 card)
tISU
tIH
5
5
-
ns
ns
Ccard <= 10 pF(1 card)
Ccard <= 10 pF(1 card)
tODLY
-
14
ns
CL <= 40 pF(1 card)
Inputs CMD, DAT (referenced to CLK)
Input set-up time
Input hold time
Outputs CMD, DAT (referenced to CLK)
Output Delay time during Data Transfer
Mode
Table 3-3: Bus Timing - Parameters Values (Default)
(1) 0Hz means to stop the clock. The given minimum frequency range is for cases were continues clock is required.
Your Ultimate Memory Solution!
17
ATP Confidential & Proprietary
Comment [Leo1]: 100K 最低是否要求
Revision 3.7
ATP Industrial Grade SD Card Specification
Figure 3-3: Timing diagram data input/output referenced to clock (High-Speed)
Your Ultimate Memory Solution!
18
ATP Confidential & Proprietary
Revision 3.7
ATP Industrial Grade SD Card Specification
PARAMETER
SYMBOL
MIN
MAX
Clock CLK (All values are referred to min (VIH) and max (VIL),
Clock frequency Data
fPP
0
50
Transfer Mode
Clock low time
tWL
7
Clock high time
tWH
7
Clock rise time
tTLH
3
Clock fall time
tTHL
3
Inputs CMD, DAT (referenced to CLK)
Input set-up time
tISU
6
Input hold time
tIH
2
Outputs CMD, DAT (referenced to CLK)
Output Delay time during
tODLY
0
14
Data Transfer Mode
Output Hold time
tOH
2.5
Total System capacitance for
CL
40
each line
UNIT
MHz
ns
ns
ns
ns
ns
ns
ns
ns
pF
Table 3-3: Bus Timing - Parameters Values (High-Speed)
Your Ultimate Memory Solution!
19
ATP Confidential & Proprietary
REMARK
Comment [Leo2]: 是否要求 100K 最低？
Revision 3.7
ATP Industrial Grade SD Card Specification
4 SD Card Hardware System
4.1 SD Card Description
Figure 4-1: SD Card Function Block Diagram
PIN #
1
2
3
4
5
6
7
8
9
NAME
CD/
DAT32
CMD
VSS1
VDD
CLK
VSS2
DAT0
DAT1
DAT2
SD INTERFACE
TYPE
DESCRIPTION
Card Detect /Data Line
I/O/PP
(Bit 3)
PP
Command/ Response
S
Supply Voltage Ground
S
Supply Voltage
I
Clock
S
Supply Voltage Ground
I/O/PP Data Line (Bit 0)
I/O/PP Data Line (Bit 1)
I/O/PP Data Line (Bit 2)
NAME
CS
DI
VSS
VDD
SCLK
VSS2
DO
RSV
RSV
Table 4-1: Pad Assignment
Your Ultimate Memory Solution!
20
ATP Confidential & Proprietary
SPI INTERFACE
TYPE DESCRIPTION
Chip Select (Active
I
Low)
I/PP
Data In
S
Supply Voltage Ground
S
Supply Voltage
I
Clock
S
Supply Voltage Ground
O/PP Data Out
Revision 3.7
ATP Industrial Grade SD Card Specification
1) S: power supply; I: input; O: output using push-pull drivers; PP: I/O using push-pull drivers;
2) The extended DAT Lines (Dat1-DAT3) are input on power up. They start to operate as DAT lines
after SET_BUS_WIDTH command. The Host shall keep its own DAT1-DAT3 lines in input mode,
as well, while they are not used.
3) After power up this line is input with 50Kohm pull-up (can be used for card detection or SPD mode
selection). The pull-up should be disconnected by user, during regular data transfer, with
SET_CLR_CARD_DETECT (ACMD42) command
Each card has a set of information registers. Please refer to chapter 5 for the details of registers.
NAME
CID
WIDT
128H
RCA
16
CSD
128
SCR
64
OCR
SSR
CSR
32
512
32
DESCRIPTION
Card identification number; card individual number for identification.
Relative card address; local system address of a card, dynamically
suggested by the card and approved by the host during initialization.
Card Specific Data; information about the card operation conditions.
SD Configuration Register; information about the SD Card’s Special
Features capabilities.
Operation conditions register.
SD Status; information about the card proprietary features.
Card Status; information about the card status.
Table 4-2: SD Card registers
4.2 SD BUS Topology
The SD Card bus has a single master (application), multiple slaves (cards), synchronous star topology.
Clock, power and ground signals are common to all cards. Command (CMD) and data (DAT0 - DAT3)
signals are dedicated to each card providing continues point to point connection to all the cards.
During initialization process commands are sent to each card individually, allowing the application to
detect the cards and assign logical addresses to the physical slots. Data is always sent (received) to
(from) each card individually. However, in order to simply the handling of the card stack, after the
initialization process, all commands may be sent concurrently to all cards. Addressing information is
provided in the command packet.
SD bus allows dynamic configuration of the number of data lines. After power up, by default, the SD
Card will use only DAT0 for data transfer. After initialization the host can change the bus width
(number of active data lines). This feature allows easy trade off between HW cost and system
performance.
Note that while DAT1-DAT3 are not in use, the related Host’s DAT lines should be in tri-state
(input mode).
Your Ultimate Memory Solution!
21
ATP Confidential & Proprietary
Revision 3.7
ATP Industrial Grade SD Card Specification
Figure 4-2: SD Card system bus Topology
4.3 SD Card Hardware Interface
The SD Card has six communication lines and three supply lines:
• CMD: Command is a bidirectional signal. The host and card drivers are operating in push pull mode.
• DAT0-3: Data lines are bidirectional signals. Host and card drivers are operating in push pull mode
• CLK: Clock is a host to card signal. CLK operates in push pull mode
• VDD: VDD is the power supply line for all cards.
• VSS1, VSS2 are two ground lines.
In addition to those lines that are connected to the internal card circuitry there are two contacts of the
Write Protect/Card Detect switch that are part of the socket. Those contacts are not mandatory but if
they exist they should be connected as given in the following figure. When DAT3 is used for card
detection, RDAT for DAT3 should be unconnected and another resistor should be connected to the
ground.
RDAT and RCMD are pull-up resistors protecting the CMD and the DAT lines against bus floating when
no card is inserted or when all card drivers are in a high-impedance mode. The host shall pull-up all
DAT0-3 lines by RDAT, even if the host uses SD Card as 1 bit mode- only in SD mode. Also, the host
shall pull-up all "RSV" lines in SPI mode, even though they are not used. RWP is used for the Write
Protect/Card Detection switch.
Your Ultimate Memory Solution!
22
ATP Confidential & Proprietary
Revision 3.7
ATP Industrial Grade SD Card Specification
Figure 4-3: Bus circuitry diagram
4.4 Bus Signal Line Load
The total capacitance CL of each line of the SD bus is the sum of the bus master capacitance CHOST, the
bus capacitance CBUS itself and the capacitance CCARD of each card connected to this line:
CL = CHOST + CBUS + N*CCARD
N is the number of connected cards.
PARAMETER
Pull-up resistance for CMD
SYMBOL MIN
RCMD
10
MAX. UNIT
100
Kohm
REMARK
to prevent bus floating
Pull-up resistance for DAT
RDAT
100
Kohm
to prevent bus floating
Total bus capacitance for each CL
signal line
40
pF
1 card
CHOST+CBUS shall
not exceed 30 pF
Single card capacitance
Maximum signal line
inductance
Pull-up resistance inside card
(pin1)
10
16
pF
nH
90
Kohm
10
CCARD
RDAT3
10
Table 4-3: Bus Signal Line Load
Your Ultimate Memory Solution!
23
ATP Confidential & Proprietary
fPP <= 20 MHz
May be used for
card detection
Revision 3.7
ATP Industrial Grade SD Card Specification
4.5 Hot Insertion and Removal
To guarantee the proper sequence of card pin connection during hot insertion, the use of either a special
hot-insertion capable card connector or an auto-detect loop on the host side (or some similar
mechanism) is mandatory. No card shall be damaged by inserting or removing a card into the SD Card
bus even when the power (VDD) is up. Data transfer operations are protected by CRC codes, therefore
any bit changes induced by card insertion and removal can be detected by the SD Card bus master. The
inserted card must be properly reset also when CLK carries a clock frequency fPP. Each card shall have
power protection to prevent card (and host) damage. Data transfer failures induced by removal/insertion
are detected by the bus master. They must be corrected by the application, which may repeat the issued
command.
4.6 Power up
The power up of the SD Card bus is handled locally in each SD Card and in the bus master.
Figure 4-4: Power-up diagram
• ‘Power up time’ is defined as voltage rising time from 0 volt to VDD min and depends on application
parameters such as the maximum number of SD Cards, the bus length and the characteristic of the
Your Ultimate Memory Solution!
24
ATP Confidential & Proprietary
Revision 3.7
ATP Industrial Grade SD Card Specification
power supply unit.
• ‘Supply ramp up time’ provides the time that the power is built up to the operating level (the bus
master supply voltage) and the time to wait until the SD card can accept the first command.
• The host shall supply power to the card so that the voltage is reached to Vdd_min within 250ms and
start to supply at least 74 SD clocks to the SD card with keeping CMD line to high. In case of SPI mode,
CS shall be held to high during 74 clock cycles.
• After power up (including hot insertion, i.e. inserting a card when the bus is operating) the SD Card
enters the idle state. In case of SD host, CMD0 is not necessary. In case of SPI host, CMD0 shall be the
first command to send the card to SPI mode.
• CMD8 is newly added in the Physical Layer Specification Version 2.00 to support multiple voltage
ranges and used to check whether the card supports supplied voltage. The version 2.00 host shall issue
CMD8 and verify voltage before card initialization. The host that does not support CMD8 shall supply
high voltage range.
• ACMD41 is a synchronization command used to negotiate the operation voltage range and to poll the
cards until they are out of their power-up sequence. In case the host system connects multiple cards, the
host shall check that all cards satisfy the supplied voltage. Otherwise, the host should select one of the
cards and initialize.
4.7 Compatibility to Multi Media Card
The SD Card protocol is designed to be a super-set of the Multi Media Card Version 2.11 protocol. For
complete details refer to Multi Media Card specification.
4.8 Card Capacity
• Standard Capacity SD Memory Cards supports capacity up to and including 2 G bytes (231 bytes). All
versions of the Physical Specifications define the Standard Capacity SD Memory Card.
• High Capacity SD Memory Cards supports capacity more than 2 G bytes (231 bytes) and this version
of specification limits capacity up to and including 32 GB. High Capacity SD Memory Card is newly
defined from the Physical Layer Specification Version 2.00. Only hosts that are compliant to the
Physical Layer Specification version 2.00 or higher and the SD File System Specification Ver2.00 can
access High Capacity SD Memory Cards. Other hosts fail to initialize High Capacity SD Memory Cards.
Your Ultimate Memory Solution!
25
ATP Confidential & Proprietary
Revision 3.7
ATP Industrial Grade SD Card Specification
Figure 4-5: Hosts-Cards Usability
Your Ultimate Memory Solution!
26
ATP Confidential & Proprietary
Revision 3.7
ATP Industrial Grade SD Card Specification
5 Card Registers
Within the card interface seven registers are defined: OCR, CID, CSD, RCA, SCR, SSR and CSR.
These can be accessed only by corresponding commands. The OCR, CID, CSD and SCR registers carry
the card/content specific information, while the RCA register is configuration register storing actual
configuration parameters and SSR and CSR are two status fields.
5.1 OCR Register
The 32-bit operation conditions register stores the VDD voltage profile of the card. In addition, this
register includes a status information bit. This status bit is set if the card power up procedure has been
finished.
OCR BIT POSITION
VDD VOLTAGE WINDOW
0-6
reserved
7
1.7-1.95
8-14
2.0-2.6
15
2.7-2.8
16
2.8-2.9
17
2.9-3.0
18
3.0-3.1
19
3.1-3.2
20
3.2-3.3
21
3.3-3.4
22
3.4-3.5
23
3.5-3.6
24-29
reserved
30
Card Capacity Status 1
31
card power up status bit 2
1) This bit is valid only when the card power up status bit is set.
2) This bit is set to LOW if the card has not finished the power up routine
Table 5-1: OCR register definition
The supported voltage range is coded as shown in Table 5-1. A voltage range is not supported if the
corresponding bit value is set to LOW. As long as the card is busy, the corresponding bit (31) is set to
LOW.
5.2 CID Register
The Card IDentification (CID) register is 128 bits wide. It contains the card identification information
used during the card identification phase. Every individual flash card shall have a unique identification
Your Ultimate Memory Solution!
27
ATP Confidential & Proprietary
Revision 3.7
ATP Industrial Grade SD Card Specification
number. The structure of the CID register is defined in the following paragraphs:
NAME
Manufacturer ID
OEM/Application ID
Product name
Product revision
Product serial number
reserved
Manufacturing date
CRC7 checksum
not used, always ’1’
FIELD
WIDTH
CID-SLICE
MID
8
[127:120]
OID
16
[119:104]
PNM
40
[103:64]
PRV
8
[63:56]
PSN
32
[55:24]
-4
[23:20]
MDT
12
[19:8]
CRC
7
[7:1]
1
[0:0]
Table 5-2: The CID fields
• MID
An 8 bit binary number identifies the card manufacturer. The MID number is controlled, defined and
allocated to a SD Card manufacturer by the SD Group. This procedure is established to ensure
uniqueness of the CID register.
• OID
A 2 ASCII string characters that identifies the card OEM and/or the card contents (when used as a
distribution media either on ROM or FLASH cards). The OID number is controlled, defined and
allocated to a SD Card manufacturer by the SD Group. This procedure is established to
ensure uniqueness of the CID register.
• PNM
The product name is a string, 5 ASCII characters long.
• PRV
The product revision is composed of two Binary Coded Decimal (BCD) digits, four bits each,
representing an “n.m” revision number. The “n” is the most significant nibble and “m” is the least
significant nibble. As an example, the PRV binary value field for product revision “6.2” will be: 0110
0010
• PSN
The Serial Number is 32 bits of binary number.
• MDT
The manufacturing date composed of two hexadecimal digits, one is 8 bit representing the year(y) and
the other is four bits representing the month(m). The “m” field [11:8] is the month code. 1 = January.
The “y” field [19:12] is the year code. 0 = 2000. As an example, the binary value of the Date field for
Your Ultimate Memory Solution!
28
ATP Confidential & Proprietary
Comment [Leo3]: 是否要介绍 ATP 的 CID
设置
Revision 3.7
ATP Industrial Grade SD Card Specification
production date “April 2001” will be: 00000001 0100.
• CRC
CRC7 checksum (7 bits). This is the checksum of the CID contents.
5.3 CSD Register
The Card-Specific Data register provides information on how to access the card contents. The CSD
defines the data format, error correction type, maximum data access time, whether the DSR register can
be used etc. The programmable part of the register (entries marked by W or E, see below) can be
hanged by CMD27. The type of the entries in the table below is coded as follows: R = readable, W(1) =
writable once, W = multiple writable.
CSD_STRUCTURE
TAAC
NSAC
WIDT
H
2
6
8
8
CELL
TYPE
R
R
R
R
CSDSLICE
[127:126]
[125:120]
[119:112]
[111:104]
TRAN_SPEED
CCC
READ_BL_LEN
READ_BL_PARTIAL
WRITE_BLK_MISALIGN
READ_BLK_MISALIGN
DSR_IMP
C_SIZE
8
12
4
1
1
1
1
6
22
R
R
R
R
R
R
R
R
R
[103:96]
[95:84]
[83:80]
[79:79]
[78:78]
[77:77]
[76:76]
[75:70]
[69:48]
-
1
R
[47:47]
ERASE_BLK_EN
SECTOR_SIZE
WP_GRP_SIZE
WP_GRP_ENABLE
1
7
7
1
2
3
4
1
5
R
R
R
R
R
R
R
R
R
[46:46]
[45:39]
[38:32]
[31:31]
[30:29]
[28:26]
[25:22]
[21:21]
[20:16]
NAME
FIELD
CSD structure
reserved
data read access-time-1
data read access-time-2 in CLK
cycles (NSAC*100)
max. data transfer rate
card command classes
max. read data block length
partial blocks for read allowed
write block misalignment
read block misalignment
DSR implemented
reserved
device size
reserved
erase single block enable
erase sector size
write protect group size
write protect group enable
reserved
write speed factor
max. write data block length
partial blocks for write allowed
reserved
R2W_FACTOR
WRITE_BL_LEN
WRITE_BL_PARTIAL
-
Your Ultimate Memory Solution!
29
ATP Confidential & Proprietary
Revision 3.7
ATP Industrial Grade SD Card Specification
File format group
copy flag (OTP)
permanent write protection
temporary write protection
File format
reserved
CRC
not used, always’1’
FILE_FORMAT_GRP
COPY
PERM_WRITE_PROTECT
TMP_WRITE_PROTECT
FILE_FORMAT
CRC
-
1
1
1
1
2
2
7
1
R
R/W(1)
R/W(1)
R/W
R
R
R/W
-
[15:15]
[14:14]
[13:13]
[12:12]
[11:10]
[9:8]
[7:1]
[0:0]
Table 5-3: The CSD Register fields
The following sections describe the CSD fields and the relevant data types. If not explicitly defined
otherwise, all bit strings are interpreted as binary coded numbers starting with the left bit first.
• CSD_STRUCTURE
Version number of the related CSD structure
CSD_STRUCTURE
CSD STRUCTURE
VERSION
0
CSD version 1.0
1
2-3
CSD version 2.0
reserved
VALID FOR SD CARD PHYSICAL
SPECIFICATION VERSION
Version 1.0-1.10
Version 2.00/Standard Capacity
Version 2.00 /High Capacity
Table 5-4: CSD register structure
• TAAC
Defines the asynchronous part of the data access time.
TAAC BIT POSITION
2:0
CODE
time unit
0=1ns, 1=10ns, 2=100ns, 3=1μs,
4=10μs, 5=100μs, 6=1ms, 7=10ms
time value
0=reserved, 1=1.0, 2=1.2, 3=1.3,
4=1.5, 5=2.0, 6=2.5, 7=3.0, 8=3.5,
9=4.0, A=4.5, B=5.0, C=5.5, D=6.0,
E=7.0, F=8.0
6:3
Your Ultimate Memory Solution!
30
ATP Confidential & Proprietary
Revision 3.7
ATP Industrial Grade SD Card Specification
7
reserved
Table 5-5: TAAC access time definition
• NSAC
Defines the worst case for the clock dependent factor of the data access time. The unit for NSAC is 100
clock cycles. Therefore, the maximal value for the clock dependent part of the data access time is 25.5k
clock cycles. The total access time NAC is the sum of TAAC and NSAC. It has to be computed by the
host for the actual clock rate. The read access time should be interpreted as a typical delay for the first
data bit of a data block or stream.
• TRAN_SPEED
The following table defines the maximum data transfer rate per one data line - TRAN_SPEED:
TRAN_SPEED BIT
CODE
transfer rate unit
2:0
0=100kbit/s, 1=1Mbit/s, 2=10Mbit/s,
3=100Mbit/s, 4... 7=reserved
time value
0=reserved, 1=1.0, 2=1.2, 3=1.3, 4=1.5,
6:3
5=2.0, 6=2.5, 7=3.0, 8=3.5, 9=4.0,
A=4.5, B=5.0, C=5.5, D=6.0, E=7.0,
F=8.0
7
reserved
Table 5-6: Maximum data transfer rate definition
Note that for current SD Cards that field is always 0_0110_010b (032h) which is equal to 25MHz - the
mandatory maximum operating frequency of SD Card. In High-Speed mode, that field is always
0_1011_010b (05Ah) which is equal to 50MHz. And when the timing mode returns to the default by
CMD6 or CMD0 command, its value will be 032h.
• CCC
The SD Card command set is divided into subsets (command classes). The card command class register
CCC defines which command classes are supported by this card. A value of ‘1’ in a CCC bit means that
the corresponding command class is supported.
CCC BIT
0
1
SUPPORTED CARD
COMMAND CLASS
class 0
class 1
......
11
class 11
Table 5-7: Supported card command classes
Your Ultimate Memory Solution!
31
ATP Confidential & Proprietary
Revision 3.7
ATP Industrial Grade SD Card Specification
• READ_BL_LEN
The maximum read data block length is computed as 2READ_BL_LEN. The maximum block length might
therefore be in the range 512...2048 bytes. Note that in SD Card the WRITE_BL_LEN is always equal
to READ_BL_LEN
READ_BL_LEN
BLOCK LENGTH
0-8
reserved
9
29 = 512 Bytes
......
11
12-15
211 = 2048 Bytes
reserved
REMARK
Table 5-8: Data block length
• READ_BL_PARTIAL (always = 1 in SD Card)
Partial Block Read is always allowed in SD Card. It means that smaller blocks can be used as well. The
minimum block size will be one byte.
• WRITE_BLK_MISALIGN
Defines if the data block to be written by one command can be spread over more than one physical
block of the memory device. The size of the memory block is defined in WRITE_BL_LEN.
WRITE_BLK_MISALIGN=0 signals that crossing physical block boundaries is invalid.
WRITE_BLK_MISALIGN=1 signals that crossing physical block boundaries is allowed.
• READ_BLK_MISALIGN
Defines if the data block to be read by one command can be spread over more than one physical
block of the memory device. The size of the memory block is defined in READ_BL_LEN.
READ_BLK_MISALIGN=0 signals that crossing physical block boundaries is invalid.
READ_BLK_MISALIGN=1 signals that crossing physical block boundaries is allowed.
• DSR_IMP
Defines if the configurable driver stage is integrated on the card. If set, a driver stage register (DSR)
must be implemented also.
Your Ultimate Memory Solution!
32
ATP Confidential & Proprietary
Revision 3.7
ATP Industrial Grade SD Card Specification
• C_SIZE
This field is expanded to 22 bits and can indicate up to 2 TBytes (It is the same as the maximum
memory space specified by a 32-bit block address.)
This parameter is used to calculate the user data area capacity in the SD memory card (not include the
protected area). The user data area capacity is calculated from C_SIZE as follows:
memory capacity = (C_SIZE+1) * 512K byte
As the maximum capacity of the Physical Layer Specification Version 2.00 is 32 GB, the upper 6 bits
of his field shall be set to 0.
• ERASE_BLK_EN
This field is fixed to 1, which means the host can erase one or multiple units of 512 bytes.
• SECTOR_SIZE
This field is fixed to 7Fh, which indicates 64 KBytes. This value does not relate to erase operation.
Version 2.00 cards indicates memory boundary by AU size and this field should not be used.
• WP_GRP_SIZE
This field is fixed to 00h. The High Capacity SD Memory Card does not support write protected groups.
• WP_GRP_ENABLE
This field is fixed to 00h. The High Capacity SD Memory Card does not support write protected groups.
• R2W_FACTOR
This field is fixed to 2h, which indicates 4 multiples. Write timeout can be calculated by multiplying
the read access time and R2W_FACTOR. However, the host should not use this factor and should use
250 ms for write timeout.
• WRITE_BL_LEN
This field is fixed to 9h, which indicates WRITE_BL_LEN=512 Byte.
• WRITE_BL_PARTIAL
This field is fixed to 0, which indicates partial block read is inhibited and only unit of block access is
allowed.
• FILE_FORMAT_GRP
This field is set to 0. Host should not use this field.
.
Your Ultimate Memory Solution!
33
ATP Confidential & Proprietary
Revision 3.7
ATP Industrial Grade SD Card Specification
• COPY
Defines if the contents is original (= ‘0’) or has been copied (=’1’). The COPY bit for OTP and MTP
devices, sold to end consumers, is set to ‘1’ which identifies the card contents as a copy. The COPY bit
is an one time programmable bit.
• PERM_WRITE_PROTECT
Permanently protects the whole card content against overwriting or erasing (all write and erase
commands for this card are permanently disabled). The default value is ‘0’, i.e. not permanently write
protected.
• TMP_WRITE_PROTECT
Temporarily protects the whole card content from being overwritten or erased (all write and erase
commands for this card are temporarily disabled). This bit can be set and reset. The default value is ‘0’,
i.e. not write protected.
• FILE_FORMAT
This field is set to 0.
• CRC
The CRC field carries the check sum for the CSD contents. The checksum has to be recalculated by the
host for any CSD modification. The default corresponds to the initial CSD contents.
5.4 RCA Register
The writable 16-bit relative card address register carries the card address that is published by the card
during the card identification. This address is used for the addressed host-card communication after the
card identification procedure. The default value of the RCA register is 0x0000. The value 0x0000 is
reserved to set all cards into the Stand-by State with CMD7.
5.5 SCR Register
In addition to the CSD register there is another configuration register that named - SD CARD
Configuration Register (SCR). SCR provides information on SD Card's special features that were
configured into the given card. The size of SCR register is 64 bit. This register is set in the factory by
ATP.
The following table describes the SCR register content.
Your Ultimate Memory Solution!
34
ATP Confidential & Proprietary
Revision 3.7
ATP Industrial Grade SD Card Specification
DESCRIPTION
FIELD
CELL
TYP
SCR
SLICE
SCR Structure
SCR_STRUCTURE
WIDT
H
4
SD Card - Spec. Version
SD_SPEC
4
R
[59:56]
data_status_after erases
DATA_STAT_AFTER_ERASE 1
R
[55:55]
SD Security Support
DAT Bus widths
supported
reserved
reserved for manufacturer
usage
SD_SECURITY
3
R
[54:52]
SD_BUS_WIDTHS
4
R
[51:48]
-
16
R
[47:32]
-
32
R
[31:0]
R
[63:60]
Table 5-16: The SCR Fields
• SCR_STRUCTURE
Version number of the related SCR structure in the SD Card Physical Layer Specification.
SCR_STRUCTURE
0
1-15
SCR STRUCTURE
VERSION
SCR version No. 1.0
reserved
VALID FOR SD PHYSICAL LAYER
SPECIFICATION VERSION
Version 1.01-2.00
Table 5-9: SCR register structure version
• SD_SPEC
Describes the SD Card Physical Layer Specification version supported by this card.
SD_SPEC
0
1
2
3-15
PHYSICAL LAYER SPECIFICATION
VERSION NUMBER
Version 1.0-1.01
Version 1.10
Version 2.00
reserved
Table 5-10: SD Card Physical Layer Specification Version
• DATA_STAT_AFTER_ERASE
Defines the data status after erase, whether it is ‘0’ or ‘1’.
• SD_SECURITY
Your Ultimate Memory Solution!
35
ATP Confidential & Proprietary
Revision 3.7
ATP Industrial Grade SD Card Specification
Describes the security algorithm supported by the card.
SD_SECURITY
0
1
2
3
4-7
SUPPORTED ALGORITHM
no security
Not used
Version 1.01
Version 2.0
reserved
Table 5-11: SD Supported security algorithm
• SD_BUS_WIDTHS
Describes all the DAT bus widths that are supported by this card.
SD_BUS_WIDTHS
Bit 0
Bit 1
Bit 2
Bit 3 [MSB]
SUPPORTED
BUS WIDTHS
1 bit (DAT0)
reserved
4 bit (DAT0-3)
reserved
Table 5-12: SD Card Supported Bus Widths
5.6 SSR Register
SD Status; information about the card proprietary features (See 6.5)
5.7 CSR Register
Card Status; information about the card status (See 6.5).
Your Ultimate Memory Solution!
36
ATP Confidential & Proprietary
Revision 3.7
ATP Industrial Grade SD Card Specification
6 SD Card Functional Description
6.1 SD BUS Protocol
Communication over the SD bus is based on command and data bit streams which are initiated by a
start bit and terminated by a stop bit.
• Command: a command is a token which starts an operation. A command is sent from the host
either to a single card (addressed command) or to all connected cards (broadcast command). A
command is transferred serially on the CMD line.
• Response: a response is a token which is sent from an addressed card, or (synchronously) from
all connected cards, to the host as an answer to a previously received command. A response is
transferred serially on the CMD line.
• Data: data can be transferred from the card to the host or vice versa. Data is transferred via the
data lines.
Figure 6-1: “no response” And “no data” Operations
Card addressing is implemented using a session address, assigned to the card during the initialization
phase. The basic transaction on the SD bus is the command/response transaction. This type of bus
transactions transfers their information directly within the command or response structure. In addition,
some operations have a data token.
Data transfers to/from the SD Card are done in blocks. Data blocks always were succeeded by CRC bits.
Single and multiple block operations are defined. Note that the Multiple Block operation mode is better
for faster write operation. A multiple block transmission is terminated when a stop command follows
on the CMD line. Data transfer can be configured by the host to use single or multiple data lines.
Your Ultimate Memory Solution!
37
ATP Confidential & Proprietary
Revision 3.7
ATP Industrial Grade SD Card Specification
Figure 6-2: (Multiple) Block Read Operation
The block write operation uses a simple busy signaling of the write operation duration on the DAT0
data line regardless of the number of data lines used for transferring the data
Figure 6-3: (Multiple) Block Write Operation
Command tokens have the following coding scheme:
Figure 6-4: Command Token Format
Your Ultimate Memory Solution!
38
ATP Confidential & Proprietary
Revision 3.7
ATP Industrial Grade SD Card Specification
Figure 6-5: Response Token Format
In the CMD line the MSB bit is transmitted first the LSB bit is the last. When the wide bus option is
used, the data is transferred 4 bits at a time. Start and end bits, as well as the CRC bits, are transmitted
for every one of the DAT lines. CRC bits are calculated and checked for every DAT line individually.
The CRC status response and Busy indication will be sent by the card to the host on DAT0 only
(DAT1-DAT3 during that period are don’t care).
There are two types of Data packet format for the SD card.
(1) Usual data (8 bit width) The usual data (8 bit width) are sent in LSB (Least Significant Byte) first,
MSB (Most Significant Byte) last manner. But in the individual byte it is MSB (Most Significant Bit)
first, LSB (Least Significant Bit) last.
Figure 6-6: Data packet format - Usual data
Your Ultimate Memory Solution!
39
ATP Confidential & Proprietary
Revision 3.7
ATP Industrial Grade SD Card Specification
(2) Wide width data (SD Memory Register) The wide width data is shifted from MSB bit.
Figure 6-7: Data packet format - Wide width data
6.2 Command
6.2.1 Command Types and Format
All communication between host and cards is controlled by the host (master). The host sends
commands of two types: broadcast and addressed (point-to-point) commands.
• Broadcast commands
Broadcast commands are intended for all cards. Some of these commands require a response.
• Addressed (point-to-point) commands
The addressed commands are sent to the addressed card and cause a response from this card.
• Command Format
All commands have a fixed code length of 48 bits, needing a transmission time of 2.4 μs @ 20 MHz
Your Ultimate Memory Solution!
40
ATP Confidential & Proprietary
Revision 3.7
ATP Industrial Grade SD Card Specification
Bit position 47
Width (bits) 1
46
1
Value
‘1’
x
transmission command
bit
index
‘0’
start
Description bit
[45:40]
6
[39:8]
32
[7:1]
7
0
1
x
x
argument
CRC7
‘1’
end
bit
Table 6-1: Command Format
A command always starts with a start bit (always ‘0’), followed by the bit indicating the direction of
transmission (host = ‘1’). The next 6 bits indicate the index of the command, this value being
interpreted as a binary coded number (between 0 and 63). Some commands need an argument (e.g. an
address), which is coded by 32 bits. A value denoted by ‘x’ in the table above indicates this variable is
dependent on the command. All commands are protected by a CRC. Every command codeword is
terminated by the end bit (always ‘1’). All commands and their arguments are listed in Table 6-3-Table
6-11.
6.2.2 Command Classes
The command set of the SD Card system is divided into several classes (See Table 6-2). Each class
supports a set of card functionalities.
Class 0, 2, 4, 5 and 8 are mandatory supported by ATP SD Cards. The other classes are optional. The
supported Card Command Classes (CCC) are coded as a parameter in the card specific data (CSD)
register of each card, providing the host with information on how to access the card.
1
2
3
4
5
6
7
8
9
10
11
block read
Reserved
block write
erase
write
protection
lock card
application
specific
I/O mode
switch
reserved
SUPPORTED
COMMANDS
class
description
basic
0
reserved
CARD
COMMAND
CLASS
CMD0
CMD2
CMD3
CMD4
CMD5
CMD6
CMD7
CMD8
Mandatory
Mandatory
Mandatory
Mandatory
Optional
Mandatory
Mandatory
Mandatory
+
+
+
+
+
+
+
+
Your Ultimate Memory Solution!
41
ATP Confidential & Proprietary
Comment [Leo4]: ATP 支持?
Revision 3.7
CMD9
CMD10
CMD12
CMD13
CMD15
CMD16
CMD17
CMD18
CMD24
CMD25
CMD27
CMD28
CMD29
CMD30
CMD32
CMD33
CMD34-37
CMD38
CMD42
CMD50
CMD52
CMD53
CMD55
CMD56
CMD57
ACMD6
ACMD13
ACMD22
ACMD23
ACMD41
ACMD42
ACMD51
ATP Industrial Grade SD Card Specification
Mandatory
Mandatory
Mandatory
Mandatory
Mandatory
Mandatory
Mandatory
Mandatory
Mandatory
Mandatory
Mandatory
Optional
Optional
Optional
Mandatory
Mandatory
Optional
Mandatory
Optional
Optional
Optional
Optional
Mandatory
Mandatory
Optional
Mandatory
Mandatory
Mandatory
Mandatory
Mandatory
Mandatory
Mandatory
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
Table 6-2: Card Command Classes (CCCs)
Your Ultimate Memory Solution!
42
ATP Confidential & Proprietary
Revision 3.7
ATP Industrial Grade SD Card Specification
6.2.3 • Detailed Command Description
The following tables define in detail all SD Card bus commands.
CMD
INDEX
TYPE
ARGUMENT
RESP
ABBREVIATION
COMMAND DESCRIPTION
CMD0
bc
[31:0] stuff bits
-
GO_IDLE_STATE
resets all cards to idle state
CMD1
reserved
CMD2
bcr
[31:0] stuff bits
R2
ALL_SEND_CID
CMD3
bcr
[31:0] stuff bits
R6
SEND_RELATIVE_
ADDR
CMD5
reserved for I/O cards (refer to "SDIO Card Specification")
asks any card to send the CID numbers on
the CMD line (any card that is connected to
the host will respond)
ask the card to publish a new relative
address (RCA)
SELECT/DESELECT_
CARD
command toggles a card between the standby and transfer states or between the
programming and disconnect states. In both
cases the card is selected by its own relative
address and gets deselected by any other
address; address 0 deselects all. In case that
the RCA equal 0 then the host may do one of
the following: - Use other RCA number to
perform card deselection. - Re-send CMD3
to change its RCA number to other than 0
and then use CMD7with RCA=0 for card
de-selection.
R7
SEND_IF_COND
Sends SD Memory Card interface condition,
which includes host supply voltage
information and asks the card whether card
supports voltage. Reserved bits shall be set
to '0'.
[31:16] RCA
[15:0] stuff bits
R2
SEND_CSD
addressed card sends its card-specific data
(CSD) on the CMD line.
[31:16] RCA
[15:0] stuff bits
R2
SEND_CID
addressed card sends its card identification
(CID) on CMD the line.
ac
[31:0] stuff bits
R1b
STOP_
TRANSMISSION
forces the card to stop transmission
CMD13
ac
[31:16] RCA
[15:0] stuff
bits
R1
SEND_STATUS
addressed card sends its status
register.
CMD14
reserved
CMD15
ac
[31:16] RCA
[15:0] stuff bits
-
GO_INACTIVE_
STATE
sets the card to inactive state in order to
protect the card stack against
communication breakdowns.
ac
[31:16] RCA
[15:0] stuff bits
CMD8
bcr
[31:12]reserve
d bits
[11:8]supply
voltage(VHS)
[7:0]check
pattern
CMD9
ac
CMD10
ac
CMD11
reserved
CMD12
CMD7
R1b
(only
from
the
selected
card)
Table 6-3: Basic commands (class 0)
Your Ultimate Memory Solution!
43
ATP Confidential & Proprietary
Revision 3.7
CMD
INDEX
TYPE
ATP Industrial Grade SD Card Specification
ARGUMENT
RESP
ABBREVIATION
CMD16
ac
[31:0] block
length
R1
SET_BLOCKLEN
CMD17
adtc
[31:0] data
address
R1
READ_SINGLE_ BLOCK
CMD18
adtc
[31:0] data
address
R1
READ_MULTIPLE_BLOCK
CMD19
...
CMD23
reserved
COMMAND DESCRIPTION
In the case of a Standard Capacity SD
Memory Card, this command sets the
block length (in bytes) for all following
block commands (read, write, lock).
Default block length is fixed to 512
Bytes.
Set length is valid for memory access
commands only if partial block read
operation are allowed in CSD.
In the case of a High Capacity SD
Memory Card, block length set by
CMD16
command does not affect the memory
read and write commands. Always 512
Bytes fixed block length is used. This
command is effective for
LOCK_UNLOCK
command.
In both cases, if block length is set
larger
than 512Bytes, the card sets the
BLOCK_LEN_ERROR bit.
In the case of a Standard Capacity SD
Memory Card, this command, this
command reads a block of the size
selected by the SET_BLOCKLEN
command1.
In the case of a High Capacity Card,
block length is fixed 512 Bytes
regardless of the
SET_BLOCKLEN command.
continuously transfers data blocks from
card to host until interrupted by a
STOP_TRANSMISSION command.
1) The data transferred must not cross a physical block boundary unless READ_BLK_MISALIGN is set in the CSD.
Table 6-2: Block oriented read commands (class 2)
Your Ultimate Memory Solution!
44
ATP Confidential & Proprietary
Revision 3.7
CMD
INDEX
TYPE
ATP Industrial Grade SD Card Specification
ARGUMENT
RESP
ABBREVIATION
CMD16
ac
[31:0] block
length
R1
SET_BLOCKLEN
CMD24
adtc
[31:0] data
address
R1
WRITE_BLOCK
CMD25
adtc
CMD26
CMD27
[31:0] data
R1
address
Reserved For Manufacturer
adtc
[31:0] stuff
R1
bits
WRITE_MULTIPLE_BLOCK
PROGRAM_CSD
COMMAND DESCRIPTION
In the case of a Standard Capacity SD
Memory Card, this command sets the
block length (in bytes) for all following
block commands (read, write, lock).
Default block length is fixed to 512
Bytes.
Set length is valid for memory access
commands only if partial block read
operation are allowed in CSD.
In the case of a High Capacity SD
Memory Card, block length set by
CMD16
command does not affect the memory
read and write commands. Always 512
Bytes fixed block length is used. This
command is effective for
LOCK_UNLOCK
command.
In both cases, if block length is set larger
than 512Bytes, the card sets the
BLOCK_LEN_ERROR bit.
In the case of a Standard Capacity SD
Memory Card, this command writes a
block of the size selected by the
SET_BLOCKLEN command1.
In the case of a High Capacity Card,
block length is fixed 512 Bytes
regardless
of the SET_BLOCKLEN command.
continuously writes blocks of data until a
STOP_TRANSMISSION follows.
programming of the programmable bits
of the CSD.
1) The data transferred must not cross a physical block boundary unless WRITE_BLK_MISALIGN is set in the CSD. In
case that write partial blocks is not supported then the block length=default block length (given in CSD).
Table 6-4: Block oriented write commands (class 4)
Your Ultimate Memory Solution!
45
ATP Confidential & Proprietary
Revision 3.7
CMD
INDEX
ATP Industrial Grade SD Card Specification
TYPE
ARGUMENT
RESP
ABBREVIATION
CMD28
ac
[31:0] data
address
R1b
SET_WRITE_PROT
CMD29
ac
[31:0] data
address
R1b
CLR_WRITE_PROT
CMD30
adtc
[31:0] write
protect data
address
R1
SEND_WRITE_PROT
CMD31
reserved
COMMAND DESCRIPTION
if the card has write protection fea-tures,
this command sets the write protection
bit of the addressed group. The
properties of write protection are coded
in the card specific data
(WP_GRP_SIZE).
if the card provides write protection
features, this command clears the write
protection bit of the addressed group.
if the card provides write protection
features, this command asks the card to
send the status of the write protection
bits.1
1)32 write protection bits (representing 32 write protect groups starting at the specified address) followed by 16 CRC bits
are transferred in a payload format via the data line. The last (least significant) bit of the protection bits corresponds to the
first addressed group. If the addresses of the last groups are outside the valid range, then the corresponding write protection
bits shall be set to zero
Table 6-5: Block oriented write protection commands (class 6)
CMD
INDEX
TYPE
ARGUMENT
RESP
ABBREVIATION
COMMAND DESCRIPTION
CMD32
ac
R1
ERASE_WR_BLK_START
CMD33
ac
R1
ERASE_WR_BLK_END
CMD38
ac
[31:0] data
address
[31:0] data
address
[31:0] stuff
bits
R1b
ERASE
sets the address of the first write-block to
be erased.
sets the address of the last write block of
the continuous range to be erased.
erases all previously selected write
blocks.
CMD39
reserved
Non Valid in SD Card - Reserved for
MultiMediaCard I/O mode
CMD40
CMD41
reserved
Table 6-6: Erase commands (class 5)
Your Ultimate Memory Solution!
46
ATP Confidential & Proprietary
Revision 3.7
CMD
INDEX
ATP Industrial Grade SD Card Specification
TYPE
ARGUMENT
RESP
ABBREVIATION
COMMAND DESCRIPTION
In the case of a Standard Capacity SD
Memory Card, this command sets the
block length (in bytes) for all following
CMD16
ac
[31:0] block
length
R1
SET_BLOCKLEN
CMD42
adtc
[31:0] stuff
bits.
R1
LOCK_UNLOCK
CMD43-49
CMD51
reserved
reserved
Table 6-7: Lock card (class 7)
Your Ultimate Memory Solution!
47
ATP Confidential & Proprietary
block commands (read, write, lock).
Default block length is fixed to 512
Bytes.
Set length is valid for memory access
commands only if partial block read
operation are allowed in CSD.
In the case of a High Capacity SD
Memory Card, block length set by
CMD16
command does not affect the memory
read and write commands. Always 512
Bytes fixed block length is used. This
command is effective for
LOCK_UNLOCK
command.
In both cases, if block length is set
larger
than 512Bytes, the card sets the
BLOCK_LEN_ERROR bit.
Used to set/reset the password or
lock/unlock the card. The size of the
data block is set by the
SET_BLOCK_LEN command.
Revision 3.7
ATP Industrial Grade SD Card Specification
CMD
INDEX
TYPE
ARGUMENT
RESP
ABBREVIATION
CMD55
ac
[31:16] RCA
[15:0] stuff
bits
R1
APP_CMD
CMD56
adtc
[31:1] stuff
bits. [0]:
RD/WR1
R1
GEN_CMD
CMD5859
CMD6063
COMMAND DESCRIPTION
Indicates to the card that the next
command is an application specific
command rather than a standard
command
Used either to transfer a data block to
the card or to get a data block from the
card for general purpose/application
specific commands. In the case of a
Standard Capacity SD Memory Cards,
the size of the data block shall be set by
the SET_BLOCK_LEN command. In
the case of a High Capacity SD
Memory Cards, the size of the data
block is fixed to 512 byte. The host sets
RD/WR=1 for reading data from the
card and sets to 0
for writing data to the card.
reserved
reserved for manufacturer
1) RD/WR: “1” the host gets a block of data from the card. “0” the host sends block of data to the card. All the application
specific commands (given in Table 21) are supported if Class 8 is allowed (mandatory in SD Card).
Table 6-8: Application specific commands (class 8)
CMD
INDEX
TYPE
CMD52.
CMD54
reserved for I/O mode (refer to "SDIO Card Specification")
ARGUMENT
RESP
ABBREVIATION
COMMAND DESCRIPTION
Table 6-9: I/O mode commands (class 9)
The following table describes all the application specific commands supported/reserved by the SD Card.
All the following ACMDs shall be preceded with APP_CMD command (CMD55).
CMD
INDEX
TYPE
ARGUMENT
RESP
ABBREVIATION
Your Ultimate Memory Solution!
48
ATP Confidential & Proprietary
COMMAND
DESCRIPTION
Revision 3.7
ACMD6
ac
ACMD13
ACMD17
ATP Industrial Grade SD Card Specification
[31:2] stuff bits
[1:0]bus width
R1
SET_BUS_WIDTH
adtc
[31:0] stuff bits
reserved
R1
SD_STATUS
ACMD18
--
--
--
ACMD19
to
ACMD21
reserved
--
ACMD22
adtc
[31:0] stuff bits
R1
SEND_NUM_WR_BLOCKS
ACMD23
ac
[31:23] stuff bits
[22:0]Number of
blocks
R1
SET_WR_BLK_ERASE_COUNT
ACMD24
reserved
ACMD25
--
--
--
--
ACMD26
--
--
--
--
ACMD38
--
--
--
--
ACMD39
to
ACMD40
reserved
bcr
[31]reserved bit
[30]HCS(OCR[30])
[29:24]reserved bits
[23:0] VDD Voltage
Window(OCR[23:0])
ACMD42
ac
[31:1] stuff bits
[0]set_cd
R1
SET_CLR_CARD_DETECT
ACMD43
--
--
--
--
ACMD41
R3
SD_SEND_OP_COND
Your Ultimate Memory Solution!
49
ATP Confidential & Proprietary
Defines the data bus width
(’00’=1bit or ’10’=4 bits
bus) to be used for data
transfer. The allowed data
bus widths are given in SCR
register.
Send the SD Card status.
Reserved for SD security
applications1
Send the number of the
written (without errors) write
blocks. Responds with
32bit+CRC data block. If
WRITE_BL_PARTIAL='0',
the unit of ACMD22 is
always 512byte.If
WRITE_BL_PARTIAL='1',
the unit of ACMD22 is a
block length which was used
when the write command
was executed.
Set the number of write
blocks to be pre-erased
before writing (to be used for
faster Multiple Block WR
command). “1”=default (one
wr block)(2).
Reserved for SD security
applications1
Reserved for SD security
applications1
Reserved for SD security
applications1
Asks the accessed card to
send its operating condition
register (OCR) content in the
response on the CMD line.
Connect[1]/Disconnect[0]
the 50KOhm pull-up resistor
on CD/DAT3 (pin 1) of the
card.
Reserved for SD security
applications1
Revision 3.7
ATP Industrial Grade SD Card Specification
ACMD49
ACMD51
adtc
[31:0] stuff bits
R1
Reads the SD Configuration
Register (SCR).
SEND_SCR
(1) Refer to “SD Memory Card Security Specification” for detailed explanation about the SD Security Features
(2) Command STOP_TRAN (CMD12) shall be used to stop the transmission in Write Multiple Block whether the pre-erase
(ACMD23) feature is used or not.
Table 6-10: Application Specific Commands used/reserved by SD Card
CMD
INDEX
RESP
ABBREVIATION
COMMAND
DESCRIPTION
R1
SWITCH_
FUNC
Checks switchable
function (mode 0)
and switch card
function (mode 1).
TYPE
ARGUMENT
CMD6
adtc
[31] Mode
0:Check function
1:Switch function
[30:24] reserved (All ’0’)
[23:20] reserved for function group 6
(All ’0’ or 0xF)
[19:16] reserved for function group 5
(All ’0’ or 0xF)
[15:12] reserved for function group 4
(All ’0’ or 0xF)
[11:8] reserved for function group 3 (All ’0’
or 0xF)
[7:4] function group 2 for command system
[3:0] function group 1 for access mode
CMD34
CMD35
CMD36
CMD37
CMD50
CMD57
Reserved for each command system set by switch function command (CMD6).
Table 6-11: Switch function commands (class 10)
6.3 Card State Transition Table
Table 6-12 defines the card state transitions in dependency of the received command.
idle
TRIGGER OF STATE
CHANGE
CLASS
INDEPENDENT
“Operation Complete”
class 0
CMD0
CMD2
CMD3
ready
iden
CURRENT STATE
stby tran data rcv
dis
ina
-
-
-
-
-
-
-
tran
stby
-
idle
-
idle
ident
-
idle
stby
idle
stby
idle
-
idle
-
idle
-
idle
-
idle
-
-
Your Ultimate Memory Solution!
50
prg
changes to
ATP Confidential & Proprietary
Revision 3.7
CMD4
CMD7, card is
addressed
CMD7, card is not
addressed
CMD8
CMD9
CMD10
CMD12
CMD13
CMD15
class 2
CMD16
CMD17
CMD18
class 4
CMD16
CMD24
CMD25
CMD27
class 6
CMD28
CMD29
CMD30
class 5
CMD32
CMD33
CMD38
class 7
CMD42
class 8
CMD55
CMD56; RD/WR = 0
CMD56; RD/WR = 1
ACMD6
ACMD13
ATP Industrial Grade SD Card Specification
-
-
-
stby
-
-
-
-
-
-
-
-
-
tran
-
-
-
-
prg
-
-
-
-
stby
stby
stby
-
dis
-
-
idle
-
-
-
stby
stby
stby
ina
tran
ina
tran
data
ina
prg
rcv
ina
prg
ina
dis
ina
-
-
-
-
-
tran
data
data
-
-
-
-
-
see class 2
-
-
-
rcv
rcv
rcv
-
-
-
-
-
-
-
-
-
prg
prg
data
-
-
-
-
-
-
-
-
-
tran
tran
prg
-
-
-
-
-
-
-
-
-
rcv
-
-
-
-
-
idle
-
-
-
stby
-
tran
rcv
data
tran
data
data
-
rcv
-
prg
-
dis
-
-
Your Ultimate Memory Solution!
51
ATP Confidential & Proprietary
Revision 3.7
ACMD22
ACMD23
ACMD18,25,26,38,
43,44,45,46,47,48,49
ACMD41, card VDD
range compatible
ACMD41, card is busy
ACMD41, card VDD
range not compatible
ACMD42
ACMD51
class 9
CMD52-CMD54
class 10
CMD6
CMD34-37,50,57
class 11
CMD41;
CMD43...CMD49,
CMD58-CMD59
CMD60...CMD63
ATP Industrial Grade SD Card Specification
CURRENT STATE
idle
ready
ident stby tran dat
rcv prg dis ina
data tran Refer to “SD Card Security Specification” for explanation about the SD
Security Features
ready
-
-
-
-
-
-
-
-
-
idle
-
-
-
-
-
-
-
-
-
ina
-
-
-
-
-
-
-
-
-
-
-
-
-
tran
data
-
-
-
-
-
data
tran
-
-
-
-
-
refer to "SDIO Card Specification"
-
-
-
-
reserved
reserved for manufacturer
Table 6-12: Card state transition table
Your Ultimate Memory Solution!
52
ATP Confidential & Proprietary
Revision 3.7
ATP Industrial Grade SD Card Specification
Responses
All responses are sent via the command line CMD. The response transmission always starts with the
left bit of the bit string corresponding to the response codeword. The code length depends on the
response type.
A response always starts with a start bit (always ‘0’), followed by the bit indicating the direction of
transmission (card = ‘0’). A value denoted by ‘x’ in the tables below indicates a variable entry. All
responses except for the type R3 (see below) are protected by a CRC. Every command codeword is
terminated by the end bit (always ‘1’). There are five types of responses for SD Card. Their formats are
defined as follows:
• R1 (normal response command): code length 48 bit. The bits 45:40 indicate the index of the
command to be responded to, this value being interpreted as a binary coded number (between 0 and 63).
The status of the card is coded in 32 bits. Note that in case that data transfer to the card is involved then
a busy signal may appear on the data line after the transmission of each block of data. The host shell
check for busy after data block transmission.
Bit position 47
Width (bits) 1
46
1
Value
‘0’
x
transmission command
bit
index
‘0’
start
Description
bit
[45:40]
6
[39:8]
32
[7:1]
7
x
x
card status
CRC7
Table 6-13: Response R1
• R1b is identical to R1 with an optional busy signal transmitted on the data line. The card may become
busy after receiving these commands based on its state prior to the command reception. The Host shell
check for busy at the response. Refer to Chapter 4.12.3 for detailed description and timing diagrams.
• R2 (CID, CSD register): code length 136 bits. The contents of the CID register are sent as a response
to the commands CMD2 and CMD10. The contents of the CSD register are sent as a response to
CMD9. Only the bits [127...1] of the CID and CSD are transferred, the reserved bit [0] of these
registers is replaced by the end bit of the response.
Bit position 135
Width (bits) 1
134
1
Value
‘0’
‘111111’
x
transmission
CID or CSD register
reserved
bit
incl. internal CRC7
Table 6-14: Response R2
‘0’
start
Description
bit
[133:128]
6
Your Ultimate Memory Solution!
53
ATP Confidential & Proprietary
[127:1]
127
0
1
‘1’
end
bit
Revision 3.7
ATP Industrial Grade SD Card Specification
• R3 (OCR register): code length 48 bits. The contents of the OCR register is sent as a response to
ACMD41.
Bit position
Width (bits)
47
1
46
1
Value
‘0’
start
bit
‘0’
‘111111’
transmission
reserved
bit
Description
[45:40]
6
[39:8]
32
[7:1]
7
0
1
x
OCR
register
‘1111111’
‘1’
end
bit
reserved
Table 6-15: Response R3
• R6 (Published RCA response): code length 48 bit. The bits 45:40 indicate the index of the
Bit position 47
46
[45:40]
[39:8] Argument field
[7:1]
0
Width (bits) 1
1
6
16
16
7
1
‘0’
Value
Description start
bit
‘0’
x
transmission command
bit
index
(‘000011’)
x
New
published
RCA
[31:16]
of
the card
x
x
[15:0] card
CRC
status bits:
7
23,22,19,12:0
(see Table
30)
‘1’
end
bit
Table 6-16: Response R6
command to be responded to - in that case it will be ‘000011’ (together with bit 5 in the status bits it
means = CMD3). The 16 MSB bits of the argument field are used for the Published RCA number.
• R7(Card interface condition): Code length is 48 bits. The card support voltage information is sent by
the response of CMD8. Bits 19-16 indicate the voltage range that the card supports. The card that
accepted the supplied voltage returns R7 response. In the response, the card echoes back both the
voltage range and check pattern set in the argument.
Bit position
47
46
[45:40]
Width (bits)
1
1
6
‘0’
‘0’
‘001000’
Value
[39:20]
[19:16]
[15:8]
[7:1]
0
20
4
8
7
1
‘00000h’
x
x
x
‘1’
Your Ultimate Memory Solution!
54
ATP Confidential & Proprietary
Revision 3.7
Description
ATP Industrial Grade SD Card Specification
start transmission command reserved
bit
bit
index
bits
echoback
voltage
of
accepted
check
pattern
Table 6-17: Response R7
Table 6-18 shows the format of 'voltage accepted' in R7.
voltage accepted
0000b
0001b
0010b
0100b
1000b
Others
Value Definition
Not Defined
2.7-3.6V
Reserved for Low Voltage Range
Reserved
Reserved
Not Defined
Table 6-18: Voltage Accepted in R7
Your Ultimate Memory Solution!
55
ATP Confidential & Proprietary
CRC
7
end
bit
Revision 3.7
ATP Industrial Grade SD Card Specification
6.4 SD Card Status
SD Card supports two card status field as follows:
- ‘Card Status’: compatible to the MultiMediaCard protocol.
- ‘SD_Status’: Extended status field of 512bits that supports special features of the SD Card and
future Application Specific features.
6.4.1
Card Status
The response format R1 contains a 32-bit field named card status. This field is intended to transmit the
card’s status information (which may be stored in a local status register) to the host. If not specified
otherwise, the status entries are always related to the previous issued command. The semantics of this
register is according to the CSD entry SPEC_VERS, indicating the version of the response formats
(possibly used for later extensions). Table 6-19 defines the different entries of the status. The type and
clear condition fields in the table are abbreviated as follows:
• Type:
E: Error bit.
S: Status bit.
R: Detected and set for the actual command response.
X: Detected and set during command execution. The host must poll the card by issuing the status
command in order to read these bits.
• Clear Condition:
A: According to the card current state.
B: Always related to the previous command. Reception of a valid command will clear it (with a delay
of one command).
C: Clear by read.
Your Ultimate Memory Solution!
56
ATP Confidential & Proprietary
Revision 3.7
Bit
s
ATP Industrial Grade SD Card Specification
Identifier
Type
Value
Description
’0’= no error
’1’= error
’0’= no error
’1’= error
The command’s argument was out of the
allowed range for this card.
A misaligned address which did not match the
block length was used in the command.
The transferred block length is not allowed for
this card, or the number of transferred bytes
does not match the block length.
An error in the sequence of erase commands
occurred.
An invalid selection of write-blocks for erase
occurred.
Clear
Condition
31
OUT_OF_RANGE
ERX
30
ADDRESS_ERROR
ERX
29
BLOCK_LEN_ERROR
ERX
28
ERASE_SEQ_ERROR
ER
27
ERASE_PARAM
ERX
26
WP_VIOLATION
ERX
’0’= not
protected
’1’= protected
Attempt to program a write protected block.
C
SX
‘0’ = card
unlocked
‘1’ = card
locked
When set, signals that the card is locked by the
host
A
25
Bits
CARD_IS_LOCKED
Identifier
’0’= no error
’1’= error
’0’= no error
’1’= error
Type
24
LOCK_UNLOCK_
FAILED
ER
X
23
COM_CRC_ERROR
ER
22
ILLEGAL_COMMAND
ER
21
CARD_ECC_FAILED
ER
X
20
CC_ERROR
ER
X
ERROR
ER
X
19
’0’= no error
’1’= error
Value
‘0’ = no
error
‘1’ =
error
’0’= no
error
’1’=
error
’0’= no
error
’1’=
error
’0’=
success
’1’=
failure
’0’= no
error
’1’=
error
’0’= no
error
’1’=
error
Description
C
C
C
C
Clear
Condition
Set when a sequence or password error has been
detected in lock/unlock card command.
C
The CRC check of the previous command failed.
B
Command not legal for the card state
B
Card internal ECC was applied but failed to
correct the data.
C
Internal card controller error
C
A general or an unknown error occurred during
the operation.
C
Your Ultimate Memory Solution!
57
C
ATP Confidential & Proprietary
Revision 3.7
17,
18
16
ATP Industrial Grade SD Card Specification
reserved
CSD_OVERWRITE
’0’= no
error
’1’=
error
ER
X
can be either one of the following errors:
- The read only section of the CSD does not
match the card content.
- An attempt to reverse the copy (set as original)
or permanent WP (unprotected) bits was made.
C
Only partial address space was erased due to
existing write pro tected blocks.
C
The command has been executed without using
the internal ECC.
A
An erase sequence was cleared before executing
because an out of erase sequence command was
received
C
The state of the card when receiving the
command. If the command execution causes a
state change, it will be visible to the host in the
response to the next command. The four bits are
interpreted as a binary coded number between 0
and 15.
B
corresponds to buffer empty signaling on the bus
A
The card will expect ACMD, or
indication that the command has
been interpreted as ACMD
C
’0’= not
protected
15
WP_ERASE_SKIP
SX
14
CARD_ECC_DISABLED
SX
13
ERASE_RESET
SR
12:9
CURRENT_STATE
SX
8
READY_FOR_DATA
SX
7,6
reserved
5
APP_CMD
4
reserved
3
AKE_SEQ_ERROR
2,1,
0
reserved
’1’=
protected
’0’=
enabled
1’=
disabled
’0’=
cleared
’1’= set
0 = idle
1=
ready
2 = ident
3 = stby
4 = tran
5 = data;
6 = rcv;
7 = prg
8 = dis
9-14 =
reserved
15 =
reserved
’0’= not
ready
’1’=
ready
‘0’ =
Disabled
‘1’ =
Enabled
SR
ER
‘0’ = no
error ‘1’
= error
Error in the sequence of authenti cation process
Table 6-19: Card status
Your Ultimate Memory Solution!
58
ATP Confidential & Proprietary
Revision 3.7
ATP Industrial Grade SD Card Specification
The following table defines for each command responded by a R1 response the affected bits in the
status field. An ‘x’ means the error/status bit may be set in the response to the respective command.
Response Format 1 Status bit #
CMD#
31
30
29
28
27
26
25
24
3
x
6
x
x
22
21
20
x
x
x
x
x
x
x
x
x
x
x
x
19
18
17
x
x
x
x
x
x
x
x
x
x
x
16
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
26
x
x
x
x
x
x
x
x
27
x
x
x
x
x
x
x
x
x
x
13
x
x
17
x
x
18
x
x
24
x
x
25
x
x
x
16
14
13
12
:9
x
8
5
x
x
12
15
x
x
7
x
23
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
28
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
29
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
30
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
32
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
33
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
42
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
55
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
56
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
38
ACMD
6
ACMD
13
ACMD
22
ACMD
23
ACMD
42
ACMD
51
x
Table 6-18: Card status field / command - cross reference
Your Ultimate Memory Solution!
59
ATP Confidential & Proprietary
x
x
x
Revision 3.7
ATP Industrial Grade SD Card Specification
6.4.2 SD Status
The SD Status contains status bits that are related to the SD Card proprietary features and may be used
for future application specific usage. The size of the SD Status is one data block of 512bit. The content
of this register is transmitted to the Host over the DAT bus along with 16 bit CRC. The SD Status is
sent to the host over the DAT bus if ACMD13 is sent (CMD55 followed with CMD13). ACMD13 can
be sent to a card only in ‘tran_state’ (card is selected). SD Status structure is described in bellow. The
same abbreviation for ‘type’ and ‘clear condition’ were used as for the Card Status above.
Bits
Identifier
Type
511:
510
DAT_BUS_WIDTH
SR
509
SECURED_MODE
SR
508:
496
reserved
495:
480
SD_CARD_TYPE
SR
Value
’00’= 1 (default)
‘01’= reserved
‘10’= 4 bit width
‘11’= reserved
’0’= Not in the mode
’1’= In Secured Mode
’ 00xxh’= SD Memory
Cards as defined in
Physical Spec Ver1.012.00 (’x’=don’t care).
The following cards are
currently defined:
’ 0000’= Regular SD
RD/WR Card.
Description
Clear
Condition
Shows the currently defined data bus
width that was defined by
SET_BUS_WIDTH command
A
Card is in Secured Mode of operation
A
In the future, the 8 LSBs will be used
to define different variations of an SD
Memory Card (Each bit will define
different SD Types). The 8 MSBs
will
be used to define SD Cards that do
not comply with current
A
’ 0001’= SD ROM Card
479:
448
SIZE_OF_PROTEC
TED_AREA
SR
447:
440
439:
432
SPEED_CLASS
SR
PERFORMANCE_M
OVE
SR
431:
428
427:
424
423:
408
407:
402
AU_SIZE
SR
401:
400
399:312
311:0
in units of
MULT*BLOCK_LEN
refer to CSD register
Speed Class of the card
(See below)
Performance of move
indicated by 1 [MB/s]
step. (See below)
Size of AU (See below)
The actual area =
(SIZE_OF_PROTECTED_AREA) *
MULT * BLOCK_LEN.
(See below)
Number of AUs to be
erased at a time
Timeout value for erasing
areas specified by
UNIT_OF_ERASE_AU
Fixed offset value added
to erase time.
A
(See below)
A
(See below)
A
(See below)
A
(See below)
A
(See below)
A
reserved
ERASE_SIZE
SR
ERASE_TIMEOUT
SR
ERASE_OFFSET
SR
reserved
reserved
Table 6-19: SD Card Status
Your Ultimate Memory Solution!
60
A
ATP Confidential & Proprietary
Revision 3.7
ATP Industrial Grade SD Card Specification
• SIZE_OF_PROTECTED_AREA
Setting this field differs between Standard and High Capacity Cards.
In the case of a Standard Capacity Card, the capacity of protected area is calculated as follows:
Protected Area = SIZE_OF_PROTECTED_AREA_* MULT * BLOCK_LEN.
SIZE_OF_PROTECTED_AREA is specified by the unit in MULT*BLOCK_LEN.
In the case of a High Capacity Card, the capacity of protected area is specified in this field:
Protected Area = SIZE_OF_PROTECTED_AREA
SIZE_OF_PROTECTED_AREA is specified by the unit in byte.
• SPEED_CLASS
This 8-bit field indicates the Speed Class and the value can be calculated by Pw/2.
SPEED_CLASS
00h
01h
02h
03h
04h – FFh
Value Definition
Class 0
Class 2
Class 4
Class 6
Reserved
Table 6-20: Speed Class Code Field
• PERFORMANCE_MOVE
This 8-bit field indicates Pm and the value can be set by 1 [MB/sec] step. If the card does not move
used RUs, Pm should be considered as infinity. Setting to FFh means infinity. The minimum value of
Pm
is defined by in Table 6-21.
PERFORMANCE_MOVE
00h
01h
02h
.......
FEh
FFh
Value Definition
Not Defined
1 [MB/sec]
2 [MB/sec]
......
254 [MB/sec]
Infinity
Table 6-21: Performance Move Field
Your Ultimate Memory Solution!
61
ATP Confidential & Proprietary
Revision 3.7
ATP Industrial Grade SD Card Specification
• AU_SIZE
This 4-bit field indicates AU Size and the value can be selected in power of 2 from 16 KB.
AU_SIZE
0h
1h
2h
3h
4h
5h
6h
7h
8h
9h
Ah – Fh
Value
Definition
Not Defined
16 KB
32 KB
64 KB
128 KB
256 KB
512 KB
1 MB
2 MB
4 MB
Reserved
Table 6-22: AU_SIZE Field
The maximum AU size, depends on the card capacity, is defined in
Table 6-23. The card can set any AU size between RU size and maximum AU size.
Capacity
Maximum AU Size
16 MB – 64 MB
512 KB
128 MB-256 MB
1 MB
512 MB
2 MB
1 GB – 32 GB
4 MB
Table 6-23: Maximum AU size
• ERASE_SIZE
This 16-bit field indicates NERASE. When NERASE numbers of AUs are erased, the timeout value is
specified by ERASE_TIMEOUT (Refer to ERASE_TIMEOUT). The host should determine proper
number of AUs to be erased in one operation so that the host can indicate progress of erase operation. If
this field is set to 0, the erase timeout calculation is not supported.
ERASE_SIZE
0000h
0001h
0002
0003
.......
FFFFh
Value Definition
Erase Time-out Calculation is not supported.
1 AU
2 AU
3 AU
.......
65535 AU
Table 6-24: Erase Size Field
Your Ultimate Memory Solution!
62
ATP Confidential & Proprietary
Revision 3.7
ATP Industrial Grade SD Card Specification
• ERASE_TIMEOUT
This 6-bit field indicates the TERASE and the value indicates erase timeout from offset when multiple
AUs are erased as specified by ERASE_SIZE. The range of ERASE_TIMEOUT can be defined as up
to 63 seconds and the card manufacturer can choose any combination of ERASE_SIZE and
ERASE_TIMEOUT depending on the implementation. Once ERASE_TIMEOUT is determined, it
determines the ERASE_SIZE. The host can determine timeout for any number of AU erase by the
Equation (6). Refer to 4.14 for the concept of calculating erase timeout. If ERASE_SIZE field is set to
0, this field shall be set to 0.
ERASE_TIMEOUT
00
01
02
03
.......
63
Value Definition
Erase Time-out Calculation is not supported.
1 [sec]
2 [sec]
3 [sec]
.......
63 [sec]
Table 6-24: Erase Timeout Field
• ERASE_OFFSET
This 2-bit field indicates the TOFFSET and one of four values can be selected. The erase offset adjusts
the line by moving in parallel on the upper side. Refer to Figure 4-33 and Equation (6) in 4.14. This
field is meaningless if ERASE_SIZE and ERASE_TIMEOUT fields are set to 0.
ERASE_OFFSET
0h
1h
2h
3h
Value Definition
0 [sec]
1 [sec]
2 [sec]
3 [sec]
Table 6-25: Erase Offset Field
Your Ultimate Memory Solution!
63
ATP Confidential & Proprietary
Revision 3.7
ATP Industrial Grade SD Card Specification
6.5 Card Identification Mode and Data Transfer Mode
Two operation modes are defined for the SD Card system:
• Card identification mode
The host will be in card identification mode after reset and while it is looking for new cards on the bus.
Cards will be in this mode after reset until the SEND_RCA command (CMD3) is received.
• Data transfer mode
Cards will enter data transfer mode once their RCA is first published. The host will enter data transfer
mode after identifying all the cards on the bus. The following table shows the dependencies between
operation modes and card states. Each state in the SD Card state diagram (see Figure 6-8) is associated
with one operation mode:
CARD STATE
Inactive State
Idle State
Ready State
Identification State
Stand-by State
Transfer State
Sending-data State
Receive-data State
Programming State
Disconnect State
OPERATION MODE
inactive
card identification
mode
data transfer mode
Table 6-26: Overview of Card States vs. Operation modes
While in card identification mode the host resets all the cards that are in card identification mode,
validates operation voltage range, identifies cards and asks them to publish Relative Card Address
(RCA). This operation is done to each card separately on its own CMD line. All data communication in
the Card Identification Mode uses the command line (CMD) only.
6.5.1 Card Identification Mode
While in card identification mode the host resets all the cards that are in card identification mode,
validates operation voltage range, identifies cards and asks them to publish Relative Card Address
(RCA). This operation is done to each card separately on its own CMD line. All data communication in
the Card Identification Mode uses the command line (CMD) only. During the card identification
process, the card shall operate in the SD clock frequency of the identification clock rate fOD .
Your Ultimate Memory Solution!
64
ATP Confidential & Proprietary
Revision 3.7
ATP Industrial Grade SD Card Specification
The command GO_IDLE_STATE (CMD0) is the software reset command and sets each card into Idle
State regardless of the current card state. Cards in Inactive State are not affected by this command.
After power-on by the host, all cards are in Idle State, including the cards that have been in Inactive
State before. After power-on or CMD0, all cards’ CMD lines are in input mode, waiting for start bit of
the next command. The cards are initialized with a default relative card address (RCA=0x0000) and
with a default driver stage register setting (lowest speed, highest driving current capability).
At the start of communication between the host and the card, the host may not know the card supported
voltage and the card may not know whether it supports the current supplied voltage. The host issues a
reset command (CMD0) with a specified voltage while assuming it may be supported by the card. To
verify the voltage, a following new command (CMD8) is defined in the Physical Layer Specification
Version 2.00. SEND_IF_COND (CMD8) is used to verify SD Memory Card interface operating
condition. The card checks the validity of operating condition by analyzing the argument of CMD8 and
the host checks the validity by analyzing the response of CMD8. The supplied voltage is indicated by
VHS filed in the argument. The card assumes the voltage specified in VHS as the current supplied
voltage. Only 1-bit of VHS shall be set to 1 at any given time. Both CRC and check pattern are used for
the host to check validity of communication between the host and the card. If the card can operate on
the supplied voltage, the response echoes back the supply voltage and the check pattern that were set in
the command argument. If the card cannot operate on the supplied voltage, it returns no response and
stays in idle state. It is mandatory to issue CMD8 prior to first ACMD41 for initialization of High
Capacity SD Memory Card (See Figure 6-27). Receipt of CMD8 makes the cards realize that the host
supports the Physical Layer Version 2.00 and the card can enable new functions. It is also mandatory
for low-voltage host to send CMD8 before ACMD41. In case that a Dual Voltage Card is not receiving
CMD8 the card will work as a high-voltage only card, and in this case that a low voltage host didn't
send CMD8 the card will go to inactive at ACMD41. SD_SEND_OP_COND (ACMD41) is designed
to provide SD Memory Card hosts with a mechanism to identify and reject cards which do not match
the VDD range desired by the host. This is accomplished by the host sending the required VDD voltage
window as the operand of this command. Cards which cannot perform data transfer in the specified
range shall discard themselves from further bus operations and go into Inactive State. The levels in the
OCR register shall be defined accordingly. Note that ACMD41 is application specific command,
therefore APP_CMD (CMD55) shall always precede ACMD41. The RCA to be used for CMD55 in
idle_state shall be the card’s default RCA = 0x0000. After the host issues a reset command (CMD0) to
reset the card, the host shall issue CMD8 prior to ACMD41 to re-initialize the SD Memory card.
Your Ultimate Memory Solution!
65
ATP Confidential & Proprietary
Revision 3.7
ATP Industrial Grade SD Card Specification
Figure 6-27: SD Card state diagram (card identification mode)
By setting the OCR to zero in the argument of ACMD41, the host can query each card and determine
the common voltage range before sending out-of-range cards into the Inactive State (query mode). This
query should be used if the host is able to select a common voltage range or if a notification to the
application of non usable cards in the stack is desired. The card does not start initialization if ACMD41
is issued as a query. Afterwards, the host may choose a voltage for operation and reissue ACMD41 with
this condition, sending incompatible cards into the Inactive State. During the initialization procedure,
the host is not allowed to change the operating voltage range.
After the bus is activated the host starts card initialization and identification process (See Figure 6-28).
The initialization process starts with SD_SEND_OP_COND (ACMD41) by setting its operational
conditions and the HCS bit in the OCR. The HCS (Host Capacity Support) bit set to 1 indicates that the
host supports High Capacity SD Memory card. The HCS (Host Capacity Support) bit set to 0 indicates
that the host does not support High Capacity SD Memory card.
Receiving of CMD8 expands the ACMD41 function; HCS in the argument and CCS (Card Capacity
Your Ultimate Memory Solution!
66
ATP Confidential & Proprietary
Revision 3.7
ATP Industrial Grade SD Card Specification
Status) in the response. HCS is ignored by cards, which didn’t respond to CMD8. However the host
should set HCS to 0 if the card returns no response to CMD8. Standard Capacity SD Memory Card
ignores HCS. If HCS is set to 0, High Capacity SD Memory Card never return ready statue (keep busy
bit to 0). The busy bit in the OCR is used by the card to inform the host that initialization of ACMD41
is
completed. Setting the busy bit to 0 indicates that the card is still initializing. Setting the busy bit to 1
indicates completion of initialization. The host repeatedly issues ACMD41 until the busy bit is set to 1.
The card checks the operational conditions and the HCS bit in the OCR only at the first ACMD41.
While
repeating ACMD41, the host shall not issue another command except CMD0.
If the card responds to CMD8, the response of ACMD41 includes the CCS field information. CCS is
valid when the card returns ready (the busy bit is set to 1). CCS=1 means that the card is a High
Capacity SD Memory Card.
CCS=0 means that the card is a Standard Capacity SD Memory Card.
The host performs the same initialization sequence to all of the new cards in the system. Incompatible
cards are sent into Inactive State. The host then issues the command ALL_SEND_CID (CMD2), to
each
card to get its unique card identification (CID) number. Card that is unidentified (i.e. which is in Ready
State) sends its CID number as the response (on the CMD line). After the CID was sent by the card it
goes into Identification State. Thereafter, the host issues CMD3 (SEND_RELATIVE_ADDR) asks the
card to publish a new relative card address (RCA), which is shorter than CID and which is used to
address the card in the future data transfer mode. Once the RCA is received the card state changes to
the Stand-by State. At this point, if the host wants to assign another RCA number, it can ask the card to
publish a new number by sending another CMD3 command to the card. The last published RCA is the
actual RCA number of the card.
The host repeats the identification process, i.e. the cycles with CMD2 and CMD3 for each card in the
system.
Your Ultimate Memory Solution!
67
ATP Confidential & Proprietary
Revision 3.7
ATP Industrial Grade SD Card Specification
Figure 6-28: Card Initialization and Identification Flow (SD mode)
6.5.2 Data Transfer Mode
Until the end of Card Identification Mode the host must remain at fOD frequency because some cards
may have operating frequency restrictions during the card identification mode. In Data Transfer Mode
the host may operate the card in fPP frequency range. The host issues SEND_CSD (CMD9) to obtain
the Card Specific Data (CSD register), e.g. block length, card storage capacity, etc.
CMD7 is used to select one card and put it into the Transfer State. When CMD7 is issued with the
reserved relative card address “0x0000”, all cards are put back to Stand-by State (Note that it is the
responsibility of the Host to reserve the RCA=0 for card de-selection).
Your Ultimate Memory Solution!
68
ATP Confidential & Proprietary
Revision 3.7
ATP Industrial Grade SD Card Specification
Figure 6-29: SD Card state diagram (data transfer mode)
Your Ultimate Memory Solution!
69
ATP Confidential & Proprietary
Revision 3.7
ATP Industrial Grade SD Card Specification
6.6 Error Handling
To correct defects in the memory field inside card the card include error correction codes in the payload
data (ECC). This correction is intended to correct static errors. Additionally two methods of detecting
errors generated during the data transfer (dynamic errors) via a cyclic redundancy check (CRC) are
implemented
6.6.1 Error Correction Code (ECC)
The ATP SD Card is free of static errors. All errors are covered inside the card, even errors occurring
during the lifetime of the card are covered for the user. The only effect which may be notified by the
end user is, that the overall memory capacity may be reduced by small number of blocks. All flash
handling is done on card, so that no external error correction is needed.
6.6.2 Cyclic Redundancy Check (CRC)
The CRC is intended for protecting SD Card commands, responses and data transfer against
transmission errors on the SD Card bus. One CRC is generated for every command and checked for
every response on the CMD line. For data blocks one CRC per transferred block is generated. The CRC
is generated and checked as described in the following.
• CRC7
The CRC7 check is used for all commands, for all responses except type R3, and for the CSD and CID
registers. The CRC7 is a 7-bit value and is computed as follows:
generator polynomial: G(x) = x7 + x3 + 1.
M(x) = (first bit) * xn + (second bit) * xn-1 +...+ (last bit) * x0
CRC[6...0] = Remainder [(M(x) * x7) / G(x)]
The first bit is the most left bit of the corresponding bitstring (of the command, response, CID or CSD).
The degree n of the polynomial is the number of CRC protected bits decreased by one. The number of
bits to be protected is 40 for commands and responses (n = 39), and 120 for the CSD and CID (n =
119).
• CRC16
In case of one DAT line usage (as in MultiMediaCard) than the CRC16 is used for payload protection
in block transfer mode. The CRC check sum is a 16-bit value and is computed as follows:
generator polynomial G(x) = x16 +x12 +x5 +1
Your Ultimate Memory Solution!
70
ATP Confidential & Proprietary
Revision 3.7
ATP Industrial Grade SD Card Specification
M(x) = (first bit) * xn + (second bit)* xn-1 +...+ (last bit) * x0
CRC[15...0] = Remainder [(M(x) * x16) / G(x)]
The first bit is the first data bit of the corresponding block. The degree n of the polynomial denotes the
number of bits of the data block decreased by one (e.g. n = 4095 for a block length of 512 bytes). The
generator polynomial G(x) is a standard CCITT polynomial. The code has a minimal distance d=4 and
is used for a payload length of up to 2048 Bytes (n <= 16383). The same CRC16 method is used in
single DAT line mode and in wide bus mode. In wide bus mode, the CRC16 is done on each line
separately.
6.6.3 CRC and Illegal Command
All commands are protected by CRC (cyclic redundancy check) bits. If the addressed card’s CRC check
fails, the card does not respond and the command is not executed. The card does not change its state,
and COM_CRC_ERROR bit is set in the status register. Similarly, if an illegal command has been
received, the card will not change its state, will not response and will set the ILLEGAL_COMMAND
error bit in the status register. Only the non-errodata neous state branches are shown in the state
diagrams contains a complete state transition description.
There are different kinds of illegal commands:
• Commands which belong to classes not supported by the card (e.g. write commands in read only
cards).
• Commands not allowed in the current state (e.g. CMD2 in Transfer State).
• Commands which are not defined (e.g. CMD5).
6.6.4 Read, Write and Erase Time-out
The times after which a time-out condition for read operations occurs are (card independent) either 100
times longer than the typical access times for these operations given below or 100ms (the lower of
them). The times after which a time-out condition for Write/Erase operations occurs are (card
independent) either 100 times longer than the typical program times for these operations given below
or 250ms (the lower of them). A card shall complete the command within this time period, or give up
and return an error message. If the host does not get any response with the given time out it should
assume the card is not going to respond anymore and try to recover (e.g. reset the card, power cycle,
reject, etc.). The typical access and program times are defined as follows:
• Read
The read access time is defined as the sum of the two times given by the CSD parameters TAAC and
NSAC . These card parameters define the typical delay between the end bit of the read command and
Your Ultimate Memory Solution!
71
ATP Confidential & Proprietary
Revision 3.7
ATP Industrial Grade SD Card Specification
the start bit of the data block. This number is card dependent and should be used by the host to calculate
throughput and the maximal frequency for stream read.
• Write
The R2W_FACTOR field in the CSD is used to calculate the typical block program time obtained by
multiplying the read access time by this factor. It applies to all write/erase commands (e.g.
SET(CLR)_WRITE_PROTECT, PROGRAM_CSD and the block write commands).
• Erase
The duration of an erase command will be (order of magnitude) the number of write blocks
(WRITE_BL) to be erased multiplied by the block write delay.
Your Ultimate Memory Solution!
72
ATP Confidential & Proprietary
Revision 3.7
ATP Industrial Grade SD Card Specification
7 SPI Mode
7.1 Introduction
The SPI mode consists of a secondary communication protocol which is offered by SD Cards. This
mode is a subset of the SD Card protocol, designed to communicate with a SPI channel, The interface
is selected during the first reset command after power up (CMD0) and cannot be changed once the part
is powered on.
7.2 SPI BUS Topology
The ATP SD Card SPI interface is compatible with SPI hosts available on the market. As any other SPI
device the ATP SD Card SPI channel consists of the following four signals:
CS:
Host to card Chip Select signal.
CLK:
Host to card clock signal
DataIn:
Host to card data signal.
DataOut:
Card to host data signal.
Another SPI common characteristic are byte transfers, which is implemented in the card as well. All
data tokens are multiples of bytes (8 bit) and always byte aligned to the CS signal.
The card identification and addressing methods are replaced by a hardware Chip Select (CS) signal.
There are no broadcast commands. For every command, a card (slave) is selected by asserting (active
low) the CS signal (see Figure 7-1).
The CS signal must be continuously active for the duration of the SPI transaction (command, response
and data). The only exception occurs during card programming, when the host can deassert the CS
signal without affecting the programming process.
The SPI interface uses the 7 out of the SD 9 signals (DAT1 and DAT 2 are not used, DAT3 is the CS
signal) of the SD bus.
Your Ultimate Memory Solution!
73
ATP Confidential & Proprietary
Revision 3.7
ATP Industrial Grade SD Card Specification
Figure 7-1: SD Card system (SPI mode) bus topology
7.3 SPI Bus Protocol
While the SD Memory Card channel is based on command and data bit streams that are initiated by a
start bit and terminated by a stop bit, the SPI channel is byte oriented. Every command or data block is
built of 8-bit bytes and is byte aligned to the CS signal (i.e. the length is a multiple of 8 clock cycles).
The card starts to count SPI bus clock cycle at the assertion of the CS signal. Every command or data
token shall be aligned to 8-clock cycle boundary. Similar to the SD Memory Card protocol, the SPI
messages consist of command, response and datablock tokens. All communication between host and
cards is controlled by the host (master). The host starts every bus transaction by asserting the CS signal
low. The selected card always responds to the command as opposed to the SD mode. When the card
encounters a data retrieval problem in a read operation, it will respond with an error response (which
replaces the expected data block) rather than by a timeout as in the SD mode. Additionally, every data
block sent to the card during write operations will be responded with a data response token.
In the case of a Standard Capacity Memory Card, a data block can be as big as one card write block and
as small as a single byte. Partial block read/write operations are enabled by card options specified in the
CSD register. In the case of a High Capacity SD Memory Card, the size of data block is fixed to 512
bytes. The block length set by CMD16 is only used for CMD42 and not used for memory data transfer.
So, partial block read/write operations are also disabled. Furthermore, Write Protected commands
Your Ultimate Memory Solution!
74
ATP Confidential & Proprietary
Revision 3.7
ATP Industrial Grade SD Card Specification
(CMD28, CMD29 and CMD30) are not supported.
Figure 7-2: SPI Mode Initialization Flow
7.3.1 Mode Selection and Initialization
The SD Card is powered up in the SD mode. It will enter SPI mode if the CS signal is asserted
(negative) during the reception of the reset command (CMD0). If the card recognizes that the SD mode
is required it will not respond to the command and remain in the SD mode. If SPI mode is required, the
card will switch to SPI and respond with the SPI mode R1 response. The only way to return to the SD
mode is by entering the power cycle. In SPI mode, the SD Card protocol state machine in SD mode is
not observed. All the SD Card commands supported in SPI mode are always available. Figure 7-3
shows the initialization sequence of SPI mode. SEND_IF_COND (CMD8) is used to verify SD
Memory Card interface operating condition. The argument format of CMD8 is the same as defined in
SD mode and the response format of CMD8 is defined in Section 7.3.2.6. The card checks the validity
of operating condition by analyzing the argument of CMD8 and the host checks the validity by
analyzing the response of CMD8. The supplied voltage is indicated by VHS filed in the argument. The
card assumes the voltage specified in VHS as the current supplied voltage. Only 1-bit of VHS shall be
Your Ultimate Memory Solution!
75
ATP Confidential & Proprietary
Revision 3.7
ATP Industrial Grade SD Card Specification
set to 1 at any given time. Check pattern is used for the host to check validity of communication
between the host and the card. If the card indicates an illegal command, the card is legacy and does not
support CMD8. If the card supports CMD8 and can operate on the supplied voltage, the response
echoes back the supply voltage and the check pattern that were set in the command argument. If VCA
in the response is set to 0, the card cannot operate on the supplied voltage. If check pattern is not
matched, CMD8 communication is not valid. In this case, it is recommended to retry CMD8 sequence.
Figure 7-3: SPI Mode Initialization Flow
READ_OCR (CMD58) is designed to provide SD Memory Card hosts with a mechanism to identify
cards that do not match the VDD range desired by the host. If the host does not accept voltage range, it
shall not proceed further initialization sequence. The levels in the OCR register shall be defined
accordingly. SD_SEND_OP_COND (ACMD41) is used to start initialization and to check if the card
has completed initialization. It is mandatory to issue CMD8 prior to the first ACMD41. Receiving of
CMD8 expands the CMD58 and ACMD41 function; HCS (High Capacity Support) in the argument of
ACMD41 and CCS (Card Capacity Status) in the response of CMD58. HCS is ignored by the card,
which didn’t accept CMD8. Standard Capacity SD Memory Card ignores HCS. The “in idle state” bit
Your Ultimate Memory Solution!
76
ATP Confidential & Proprietary
Revision 3.7
ATP Industrial Grade SD Card Specification
in the R1 response of ACMD41 is used by the card to inform the host if initialization of ACMD41 is
completed. Setting this bit to “1” indicates that the card is still initializing. Setting this bit to “0”
indicates completion of initialization. The host repeatedly issues ACMD41 until this bit is set to “0”.
The card checks the HCS bit in the OCR only at the first ACMD41. While repeating ACMD41, the
host shall not issue another command except CMD0. After initialization is completed, the host should
get CCS information in the response of CMD58. CCS is valid when the card accepted CMD8 and after
the completion of initialization. CCS=1 means that the card is a High Capacity SD Memory Card.
CCS=0 means that the card is a Standard Capacity SD.
7.3.2 Bus Transfer Protection
Every SD Card token transferred on the bus is protected by CRC bits. In SPI mode, the SD Card offers
a non protected mode which enables systems built with reliable data links to exclude the hardware or
firmware required for implementing the CRC generation and verification functions. In the nonprotected mode the CRC bits of the command, response and data tokens are still required in the tokens.
However, they are defined as ‘don’t care’ for the transmitter and ignored by the receiver.
The SPI interface is initialized in the non-protected mode. However, the RESET command (CMD0)
which is used to switch the card to SPI mode, is received by the card while in SD mode and, therefore,
must have a valid CRC field.
Since CMD0 has no arguments, the content of all the fields, including the CRC field, are constants and
need not be calculated in run time. A valid reset command is:
0x40, 0x0, 0x0, 0x0, 0x0, 0x95
The host can turn the CRC option on and off using the CRC_ON_OFF command (CMD59).
7.3.3 Data Read
The SPI mode supports single block read and Multiple Block read operations (CMD17 or CMD18 in
the SD Card protocol). Upon reception of a valid read command the card will respond with a response
token followed by a data token of the length defined in a previous SET_BLOCKLEN (CMD16)
command (refer to Figure 7-3).
Figure 7-3: Single Block Read operation
Your Ultimate Memory Solution!
77
ATP Confidential & Proprietary
Revision 3.7
ATP Industrial Grade SD Card Specification
In case of a data retrieval error, the card will not transmit any data. Instead, a special data error token
will be sent to the host. Figure 7-4 shows a data read operation which terminated with an error token
rather than a data block.
Figure 7-4: Read operation - data error
In case of Multiple block read operation every transferred block has its suffixed of 16 bit CRC. Stop
transmission command (CMD12) will actually stop the data transfer operation (the same as in SD Card
operation mode).
Figure 7-5: Multiple Block Read operation
7.3.4 Data Write
In SPI mode the SD Card supports single block and Multiple block write commands. Upon reception of
a valid write command (CMD24 or CMD25 in the SD Card protocol), the card will respond with a
response token and will wait for a data block to be sent from the host. CRC suffix, block length and
start address restrictions are (with the exception of the CSD parameter WRITE_BL_PARTIAL
controlling the partial block write option) identical to the read operation.
Your Ultimate Memory Solution!
78
ATP Confidential & Proprietary
Revision 3.7
ATP Industrial Grade SD Card Specification
Figure 7-6: Single Block Write operation
Every data block has a prefix of ’Start Block’ token (one byte).
After a data block has been received, the card will respond with a data-response token. If the data block
has been received without errors, it will be programmed. As long as the card is busy programming, a
continuous stream of busy tokens will be sent to the host (effectively holding the DataOut line low).
In Multiple Block write operation the stop transmission will be done by sending ’Stop Tran’ token
instead of ’Start Block’ token at the beginning of the next block. In case of Write Error indication (on
the data response) the host shall use SEND_NUM_WR_BLOCKS (ACMD22) in order to get the
number of well written write blocks.
Figure 7-7: Multiple Block Write operation
While the card is busy, resetting the CS signal will not terminate the programming process. The card
will release the DataOut line (tri-state) and continue with programming. If the card is reselected before
the programming is finished, the DataOut line will be forced back to low and all commands will be
rejected. Resetting a card (using CMD0) will terminate any pending or active programming operation.
This may destroy the data formats on the card. It is in the responsibility of the host to prevent it.
7.3.5 Erase & Write Protect Management
The erase and write protect management procedures in the SPI mode are identical to those of the SD
mode. While the card is erasing or changing the write protection bits of the predefined sector list, it will
Your Ultimate Memory Solution!
79
ATP Confidential & Proprietary
Revision 3.7
ATP Industrial Grade SD Card Specification
be in a busy state and hold the DataOut line low. Figure 7-8 illustrates a ‘no data’ bus transaction with
and without busy signaling.
Figure 7-8: ‘No data’ operations
7.3.6 Read CID/CSD Registers
Unlike the SD Card protocol (where the register contents is sent as a command response), reading the
contents of the CSD and CID registers in SPI mode is a simple read-block transaction. The card will
respond with a standard response token followed by a data block of 16 bytes suffixed with a 16 bit CRC.
The data time out for the CSD command cannot be set to the cards TAAC since this value is stored in
the card’s CSD. Therefore the standard response time-out value (NCR) is used for read latency of the
CSD register.
7.3.7
Reset Sequence
The SD Card requires a defined reset sequence. After power on reset or CMD0 (software reset) the card
enters an idle state. At this state the only valid host commands are ACMD41 (SD_SEND_OP_COND),
CMD58 (READ_OCR) and CMD59 (CRC_ON_OFF). CMD1 (SEND_OP_COND) is also valid - that
means that in SPI mode CMD1 and ACMD41 have the same behavior. After Power On, once the card
accepted valid ACMD41, it will be able to accept also CMD1 even if used after re-initializing (CMD0)
the card.
The host must poll the card (by repeatedly sending CMD1 or ACMD41) until the ‘in-idle-state’ bit in
the card response indicates (by being set to 0) that the card completed its initialization processes and is
ready for the next command.
In SPI mode, as opposed to SD mode, ACMD41 (or CMD1 as well) has no operands and does not
return the contents of the OCR register. Instead, the host may use CMD58 (available in SPI mode only)
to read the OCR register. Furthermore, it is in the responsibility of the host to refrain from accessing
cards that do not support its voltage range. The usage of CMD58 is not restricted to the initializing
phase only, but can be issued at any time.
Your Ultimate Memory Solution!
80
ATP Confidential & Proprietary
Revision 3.7
ATP Industrial Grade SD Card Specification
Your Ultimate Memory Solution!
81
ATP Confidential & Proprietary