Preliminary Data Sheet ICE4N65D Product Summary ICE4N65D N-Channel Enhancement Mode MOSFET HALOGEN Features • Low rDS(on) • Ultra Low Gate Charge • High dv/dt capability • High Unclamped Inductive Switching (UIS) capability • High peak current capability • Increased transconductance performance • Optimized design for high performance power systems FREE ID TA=25oC 4A Max V(BR)DSS ID=250uA 650V Min rDS(on) VGS=10V 0.85Ω Typ Qg VDS=480V 21nC Typ D G S T0252 Standard Metal Heatsink ICEMOS AND ITS SISTER COMPANY 3D SEMI OWN THE FUNDAMENTAL PATENTS FOR SUPERJUNCTION MOSFETS. THE MAJORITY OF THESE PATENTS HAVE 17 to 20 YEARS OF REMAINING LIFE. THIS PORTFOLIO HAS GRANTED PATENTS ISSUED IN USA, CHINA, KOREA, JAPAN, TAIWAN & EUROPE. Maximum ratings b , at Tj=25oC, unless otherwise specified Parameter Continuous drain current 1=Gate, 2=Drain, 3=Source. Symbol c ID Conditions Value Unit Tc=25oC 4 A Tc=100oC 2.6 A Pulsed drain current ID, pulse Tc=25oC 12 A Avalanche energy, single pulse E AS ID=2A 80 mJ Avalanche current, repetitive I AR limited by Tjmax 2 A MOSFET dv/dt ruggedness dv/dt VDS=480V, ID=4A, Tj=125oC 50 V/ns Gate source voltage VGS Power dissipation Ptot Operating and storage temperature Tj, Tstg Static ±20 AC (f>1Hz) ±30 Tc=25oC 40 -55 to +150 V W o C a When mounted on 1inch square 2oz copper clad FR-4 b Preliminary Data Sheet – Specifications subject to change c Limited by Tjmax SP-4N65D-000-0 11/22/2013 1 Preliminary Data Sheet ICE4N65D Parameter Symbol Conditions Values Min Typ Max - - 3.1 Unit Thermal characteristics Thermal resistance, junctioncase a RthJC o Thermal resistance, junctionambient a RthJA leaded - - 68 Soldering temperature, wave soldering only allowed at leads T sold 1.6mm (0.063in.) from case for 10 s - - 260 Electrical characteristics Gate source leakage current o C b , at T =25°C, unless otherwise specified j Static characteristics Drain-source breakdown voltage V(BR)DSS VGS(th) Gate threshold voltage Zero gate voltage drain current C/W IDSS IGSS Drain-source on-state resistance RDS (on) Gate resistance RG VGS=0 V, ID=250µA 650 700 - VDS=VGS, ID=250µA VDS=650V, VGS=0V, o Tj=25 C 2.1 3 3.9 - 0.1 1 - - 100 VGS=±20 V, VDS=0V VGS=10V, ID=2A, o Tj=25 C VGS=10V, ID=2A, o Tj=150 C - - 100 - 0. 85 0.95 - 2.2 - f=1 MHZ, open drain - 6 - - 635 - - 365 - - 6 - - 7 - - 6 - - 3.5 - - 54 7 - VDS=650V, VGS=0V, o Tj=150 C V µA nA Ω Ω Dynamic characteristics Input capacitance Ciss Output capacitance Reverse transfer capacitance Coss Transconductance gfs Turn-on delay time Rise time td(on) Turn-off delay time td(off) Fall time tf SP-4N65D-000-0 11/22/2013 Crss Tr VGS=0 V, VDS=25 V, f=1 MHz VDS>2*ID*RDS, ID=2A VDS=380V, VGS=10V, ID=4A, RG=4Ω (External) - pF S ns - 2 Preliminary Data Sheet ICE4N65D Parameter Symbol Conditions Values Unit Min Typ Max - 4.6 - - 6.4 - - 21 - - 5.5 - V - 0.9 1.2 V - 277 - ns - 2.6 - µC - 20 - A Gate charge characteristics Gate to source charge Qgs Gate to drain charge Qgd Gate charge total Qg Gate plateau voltage Vplateau VDS=480 V, ID=4A, VGS=0 to 10 V nC Reverse Diode Diode forward voltage VSD Reverse recovery time trr Reverse recovery charge Qrr Peak reverse recovery current Irm SP-4N65D-000-0 11/22/2013 VGS=0V, IS=IF VRR=480V, IS=IF, diFIdt=100 A/µS 3 Preliminary Data Sheet ICE4N65D Transfer Characteristics Output Characteristics 12 12 VGS=10 to 7V 6V 10 ID - Drain Current (A) ID - Drain Current (A) 10 8 6 5V 4 8 6 4 TJ = 150˚C 2 2 25˚C 0 0 0 5 10 15 0 20 2 4 6 8 VGS - Gate-to-Source (V) VDS - Drain-to-Source Voltage (V) On Resistance vs Junction Temperature On Resistance vs Drain Current 4.0 RDS(on) - On State Resistance (Normalized) RDS(on) - On-State Resistance (Ω) 2.0 1.8 1.6 1.4 1.2 VGS = 10V 1.0 0.8 0.6 0.4 3.5 VGS = 10V ID = 2A 3.0 2.5 2.0 1.5 1.0 0.5 0.2 0.0 0.0 0 2 4 6 8 ID - Drain current (A) 10 12 -50 9 1.3 VGS(th) - Gate Threshold Voltage (Normalized) 1.4 8 VDS = 480V ID = 4A 6 0 25 50 75 100 125 150 Gate Threshold Voltage vs Junction Temperature 10 7 -25 TJ - Junction Temperature (˚C) Gate Charge VGS - Gate-to-Source Voltage (V) 10 5 4 3 2 1 1.2 1.1 ID = 250μA 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0 0 5 10 15 Qg - Total Gate Charge (nC) SP-4N65D-000-0 11/22/2013 20 25 -50 -25 0 25 50 75 100 125 150 TJ - Junction Temperature (˚C) 4 Preliminary Data Sheet ICE4N65D Capacitance Drain-to-Source Breakdown Voltage vs. Junction Temperature 1.2 V(BR)DSS - Drain-to-Source Breakdown Voltage (Normalized) 100000 C-Capacitance (pF) 10000 Ciss 1000 Coss 100 10 Crss 1 0 200 400 VDS - Drain-to-Source Voltage (V) ID = 1mA 1.0 0.9 0.8 -50 600 -25 0 25 50 75 100 TJ - Junction Temperature (˚C) 125 150 Transient Thermal Response, Junction-to-Case Maximum Rated Forward Biased Safe Operating Area 100 10 10us 100us 1 1ms 0.1 RDS(on) Limit Package Limit Thermal Limit 10ms DC 0.01 r(t), Transient Thermal Resistance (Normalized) 1.00 Single Pulse, Tc = 25oC, Tj=150oC, VGS = 10V ID - Drain Current (A) 1.1 0.5 0.2 0.1 0.10 0.05 0.02 0.01 Single Pulse 0.00 1 10 100 VDS - Drain-to-Source Voltage (V) SP-4N65D-000-0 11/22/2013 1000 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 1.0E+00 t - Time (seconds) 5 Preliminary Data Sheet ICE5N65D SP-4N65D-000-0 11/22/2013 6 Preliminary Data Sheet ICE5N65D COMMON DIMENSIONS SYMBOL mm MIN NOM MAX A 2.20 2.30 2.38 A1 0.00 - 0.10 A2 0.97 1.07 1.17 b 0.72 0.78 0.85 b1 0.71 0.76 0.81 b3 5.23 5.33 5.46 c 0.47 0.53 0.58 c1 0.46 0.51 0.56 D 6.00 6.10 6.20 D1 5.30 REF E 6.50 6.60 6.70 E1 4.70 4.83 4.92 e SP-4N65D-000-0 11/22/2013 2.286 BSC H 9.90 10.10 10.30 L 1.40 1.50 1.70 L1 2.90 REF L2 0.51 BSC L3 0.90 - 1.25 L4 0.60 0.80 1.00 L5 1.70 1.80 1.90 θ 0⁰ - 8⁰ θ1 5⁰ 7⁰ 9⁰ θ2 5⁰ 7⁰ 9⁰ 7 Preliminary Data Sheet ICE4N65D ICEMOS SUPERJUNCTION PATENT PORTFOLIO ICEMOS GRANTED PATENTS US7,429,772 US7,439,178 US7,446,018 US7,579,607 US7,723,172 US7,795,045 US7,846,821 US7,944,018 US8,012,806 US8,030,133 3D SEMI PATENTS LICENSED TO ICEMOS US7,041,560B2 US7,023,069B2 US7,364,994 US7,227,197B2 US7,304,944B2 US7,052,982B2 US7,339,252 US7,410,891 US7,439,583 US7,227,197B2 US6,635,906 US6,936,867 US7,015,104 US9,109,110 US7,271,067 US7,354,818 US7,052,982, US7,199,006B2 Note: additional patents in China, Korea, Japan, Taiwan, Europe have also been granted to IceMOS and 3D Semi for Superjunction MOSFETs with 70 additional Patent applications in process in the USA and the above listed countries. SP-4N65D-000-0 11/22/2013 8 Preliminary Data Sheet ICE4N65D Marking Information YY = Last two digits of the year WW = Work week calendar on Icemos subcon assembly & test house * = Initial for Icemos subcon assembly and test house YYWW * XXXX00 IC4N65 XXXX = Wafer Lot ID 00 = may be used for wafer ID in a special case. = "00" is used unless specified. ICE4N65 = ICE is Icemos logo and 4N65 is a designated device part number SP-4N65D-000-0 11/22/2013 9