INNOVASIC IA186ER

IA186ER/IA188ER
16-Bit/8-Bit Microcontrollers with RAM
Data Sheet
February 25, 2013
IA186ER/IA188ER
16-Bit/8-Bit Microcontrollers with RAM
Data Sheet
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Data Sheet
February 25, 2013
Copyright
2013 by Innovasic, Inc.
Published by Innovasic, Inc.
5635 Jefferson St. NE, Suite A, Albuquerque, NM 87109
AMD, Am186, and Am188 are trademarks of Advanced Micro Devices, Inc.
MILES™ is a trademark of Innovasic, Inc.
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TABLE OF CONTENTS
List of Figures ..................................................................................................................................8
List of Tables ...................................................................................................................................9
Conventions ...................................................................................................................................12
Acronyms and Abbreviations ........................................................................................................13
1.
Introduction...........................................................................................................................14
1.1 General Description.....................................................................................................14
1.2 Features .......................................................................................................................14
2.
Packaging, Pin Descriptions, and Physical Dimensions .......................................................15
2.1 Packages and Pinouts ..................................................................................................15
2.1.1 IA186ER LQFP Package ................................................................................16
2.1.2 IA188ER LQFP Package ................................................................................19
2.1.3 LQFP Physical Dimensions ............................................................................22
2.1.4 IA186ER PQFP Package ................................................................................23
2.1.5 IA188ER PQFP Package ................................................................................26
2.1.6 PQFP Physical Dimensions ............................................................................29
2.2 Pin Descriptions ..........................................................................................................30
2.2.1 a19/pio9, a18/pio8, a17/pio7, a16–a0—Address Bus (synchronous
outputs with tristate) .......................................................................................30
2.2.2 ad15–ad8 (IA186ER)—Address/data bus (level-sensitive synchronous
inouts with tristate) .........................................................................................30
2.2.3 ad7–ad0—Address/Data bus (level-sensitive synchronous inouts with
tristate) ............................................................................................................30
2.2.4 ao15–ao8 (IA188ER)—Address-only bus (level-sensitive
synchronous outputs with tristate) ..................................................................30
2.2.5 ale—Address Latch Enable (synchronous output) .........................................31
2.2.6 ardy—Asynchronous Ready (level-sensitive asynchronous input) ................31
2.2.7 bhe_n/aden_n (IA186ER)—Bus High Enable (synchronous output
with tristate)/Address Enable (input with internal pull-up) ............................31
2.2.8 clkouta—Clock Output A (synchronous output) ............................................32
2.2.9 clkoutb—Clock Output B (synchronous output) ............................................32
2.2.10 den_n/pio5—Data Enable Strobe (synchronous output with tristate) ............32
2.2.11 drq1/pio13–drq0/pio12—DMA Requests (synchronous level-sensitive
inputs) .............................................................................................................32
2.2.12 dt/r_n/pio4—Data Transmit or Receive (synchronous output with
tristate) ............................................................................................................32
2.2.13 gnd—Ground ..................................................................................................32
2.2.14 hlda—Bus Hold Acknowledge (synchronous output) ....................................33
2.2.15 hold—Bus Hold Request (synchronous level-sensitive input) .......................33
2.2.16 int0—Maskable Interrupt Request 0 (asynchronous input) ............................33
2.2.17 int1/select_n—Maskable Interrupt Request 1/Slave Select (both are
asynchronous inputs) ......................................................................................33
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2.2.18 int2/inta0_n/pio31—Maskable Interrupt Request 2 (asynchronous
input)/Interrupt Acknowledge 0 (synchronous output) ..................................34
2.2.19 int3/inta1_n/irq—Maskable Interrupt Request 3 (asynchronous
input)/Interrupt Acknowledge 1 (synchronous output)/Interrupt
Request (synchronous output) ........................................................................34
2.2.20 int4/pio30—Maskable Interrupt Request 4 (asynchronous input)..................34
2.2.21 lcs_n/once0_n—Lower Memory Chip Select (synchronous output
with internal pull-up)/ONCE Mode Request (input) ......................................35
2.2.22 mcs2_n—mcs0_n (pio24, pio15, pio 14)—Midrange Memory Chip
Selects (synchronous outputs with internal pull-up) ......................................35
2.2.23 mcs3_n/rfsh_n/pio25—Midrange Memory Chip Select (synchronous
output with internal pull-up)/Automatic Refresh (synchronous output) ........35
2.2.24 nmi—Nonmaskable Interrupt (synchronous edge-sensitive input) ................35
2.2.25 pcs3_n–pcs0_n (pio19–pio16)—Peripheral Chip Selects 3–0
(synchronous outputs) .....................................................................................36
2.2.26 pcs5_n/a1/pio3—Peripheral Chip Select 5 (synchronous
output)/Latched Address Bit 1 (synchronous output) .....................................36
2.2.27 pcs6_n/a2/pio2—Peripheral Chip Select 6 (synchronous
output)/latched Address Bit 2 (synchronous output) ......................................36
2.2.28 pio31–pio0—Programmable I/O Pins (asynchronous input/output
open-drain) ......................................................................................................37
2.2.29 rd_n—Read strobe (synchronous output with tristate) ...................................37
2.2.30 res_n—Reset (asynchronous level-sensitive input) ........................................37
2.2.31 rfsh2_n/aden_n (IA188ER)—Refresh 2 (synchronous output with
tristate)/Address Enable (input with internal pull-up) ....................................37
2.2.32 rxd/pio28—Receive Data (asynchronous input) ............................................37
2.2.33 s0_n, s1_n (imdis_n), s0_n (sren_n) —Bus Cycle Status (synchronous
outputs with tristate) .......................................................................................38
2.2.34 s6/clksel1_n/pio29—Bus Cycle Status Bit 6 (synchronous
output)/Clock Divide by 2 (input with internal pull-up) ................................38
2.2.35 sclk/pio20 —Serial Clock (synchronous outputs with tristate) ......................39
2.2.36 sdata/pio21 —Serial Data (synchronous inout) ..............................................39
2.2.37 sden1/pio23 – sden0/pio22 —Serial Data Enables (synchronous
outputs with tristate) .......................................................................................39
2.2.38 srdy/pio6—Synchronous Ready (synchronous level-sensitive input) ............39
2.2.39 tmrin0/pio11—Timer Input 0 (synchronous edge-sensitive input) ................39
2.2.40 tmrin1/pio0—Timer Input 1 (synchronous edge-sensitive input) ..................39
2.2.41 tmrout0/pio10—Timer Output 0 (synchronous output) .................................40
2.2.42 tmrout1/pio1—Timer Output 1 (synchronous output) ...................................40
2.2.43 txd/pio27—Transmit Data (asynchronous output) .........................................40
2.2.44 ucs_n/once1_n—Upper Memory Chip Select (synchronous
output)/ONCE Mode Request 1 (input with internal pull-up) ........................40
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4.
5.
Data Sheet
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2.2.45 uzi_n/clksel2_n/pio26—Upper Zero Indicate (synchronous
output)/clock select 2 (input, pullup) ..............................................................40
2.2.46 vcc—Power Supply (input)..............................................................................40
2.2.47 whb_n (IA186ER)—Write High Byte (synchronous output with
tristate) ............................................................................................................41
2.2.48 wlb_n/wb_n—Write Low Byte (IA186ER) (synchronous output with
tristate)/Write Byte (IA188ER) (synchronous output with tristate) ...............41
2.2.49 wr_n—Write Strobe (synchronous output) ....................................................41
2.2.50 x1—Crystal Input (input) ...............................................................................41
2.2.51 x2—Crystal Input (input) ...............................................................................41
2.3 Pins Used by Emulators ..............................................................................................41
Maximum Ratings, Thermal Characteristics, and DC Parameters .......................................43
Device Architecture ..............................................................................................................44
4.1 Bus Interface and Control ...........................................................................................44
4.2 Clock and Power Management ...................................................................................46
4.3 System Clocks .............................................................................................................46
4.4 Power-Save Mode .......................................................................................................47
4.5 Initialization and Reset ................................................................................................47
4.6 Reset Configuration Register ......................................................................................47
4.7 Chip Selects .................................................................................................................47
4.8 Chip - Select Timing ...................................................................................................47
4.9 Ready- and Wait-State Programming..........................................................................48
4.10 Chip Select Overlap ....................................................................................................48
4.11 Upper Memory Chip Select.........................................................................................49
4.12 Low Memory Chip Select ...........................................................................................49
4.13 Midrange Memory Chip Selects .................................................................................49
4.14 Peripheral Chip Selects ...............................................................................................50
4.15 Refresh Control ...........................................................................................................50
4.16 Interrupt Control ..........................................................................................................50
4.16.1 Interrupt Types................................................................................................51
4.17 Timer Control ..............................................................................................................52
4.18 Direct Memory Access (DMA) ...................................................................................53
4.19 DMA Operation...........................................................................................................53
4.20 DMA Channel Control Registers ................................................................................54
4.21 DMA Priority ..............................................................................................................54
4.22 Asynchronous Serial Port ............................................................................................54
4.23 Synchronous Serial Port ..............................................................................................55
4.24 Programmable I/O (PIO) .............................................................................................55
4.25 Watchdog Timer ..........................................................................................................57
4.26 Internal Memory ..........................................................................................................58
Peripheral Architecture .........................................................................................................58
5.1 Control and Registers ..................................................................................................58
5.1.1 RELREG (0feh) ..............................................................................................60
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5.1.2
5.1.3
5.1.4
5.1.5
5.1.6
5.1.7
5.1.8
5.1.9
5.1.10
5.1.11
5.1.12
5.1.13
5.1.14
5.1.15
5.1.16
5.1.17
5.1.18
5.1.19
5.1.20
5.1.21
5.1.22
5.1.23
5.1.24
5.1.25
5.1.26
5.1.27
5.1.28
5.1.29
5.1.30
5.1.31
5.1.32
5.1.33
5.1.34
5.1.35
5.1.36
5.1.37
5.1.38
5.1.39
5.1.40
5.1.41
5.1.42
Data Sheet
February 25, 2013
RESCON (0f6h)..............................................................................................60
PRL (0f4h) ......................................................................................................61
PDCON (0f0h) ................................................................................................61
WDTCON (0e6h) ...........................................................................................62
EDRAM (0e4h) ..............................................................................................63
CDRAM (0e2h) ..............................................................................................64
MDRAM (0e0h) .............................................................................................64
D1CON (0dah) and D0CON (0cah) ...............................................................64
D1TC (0d8h) and D0TC (0c8h) .....................................................................66
D1DSTH (0d6h) and D0DSTH (0c6h) ...........................................................67
DIDSTL (0d4h) and D0DSTL (0c4h) ............................................................67
D1SRCH (0d2h) and D0SRCH (0c2h) ...........................................................67
D1SRCL (0d0h) and D0SRCL (0c0h) ............................................................68
IMCS (0ach) ...................................................................................................68
MPCS (0a8h) ..................................................................................................69
MMCS (0a6h) .................................................................................................70
PACS (0a4h) ...................................................................................................71
LMCS (0a2h) ..................................................................................................73
UMCS (0a0h)..................................................................................................74
SPBAUD (088h) .............................................................................................75
SPRD (086h) ...................................................................................................76
SPTD (084h) ...................................................................................................76
SPSTS (082h) .................................................................................................77
SPCT (080h) ...................................................................................................78
PDATA1 (07ah) and PDATA0 (074h) ...........................................................80
PDIR1 (078h) and PDIR0 (072h) ...................................................................82
PIOMODE1 (076h) and PIOMODE0 (070h) .................................................82
T1CON (05eh) and T0CON (056h) ................................................................83
T2CON (066h) ................................................................................................84
T2COMPA (062h), T1COMPB (05ch), T1COMPA (05ah),
T0COMPB (054h), and T0COMPA (052h) ...................................................85
T2CNT (060h), T1CNT (058h), and T0CNT (050h) .....................................86
SPICON (044h) (Master Mode) .....................................................................86
WDCON (042h) (Master Mode) ....................................................................87
I4CON (040h) (Master Mode) ........................................................................87
I3CON (03eh) and I2CON (03ch) (Master Mode) .........................................88
I1CON (03ah) and I0CON (038h) (Master Mode) .........................................88
TCUCON (032h) (Master Mode) ...................................................................89
T2INTCON (03ah), T1INTCON (038h), and T0INTCON (032h)
(Slave Mode) ..................................................................................................90
DMA1CON (036h) and DMA0CON (034h) (Master Mode).........................90
DMA1CON (036h) and DMA0CON (034h) (Slave Mode) ...........................90
INTSTS (030h) (Master Mode) ......................................................................91
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6.
7.
8.
9.
10.
Data Sheet
February 25, 2013
5.1.43 INTSTS (030h) (Slave Mode) ........................................................................91
5.1.44 REQST (02eh) (Master Mode) .......................................................................92
5.1.45 REQST (02eh) (Slave Mode) .........................................................................93
5.1.46 INSERV (02ch) (Master Mode) .....................................................................93
5.1.47 INSERV (02ch) (Slave Mode)........................................................................94
5.1.48 PRIMSK (02ah) (Master and Slave Mode) ....................................................95
5.1.49 IMASK (028h) (Master Mode) .......................................................................95
5.1.50 IMASK (028h) (Slave Mode) .........................................................................96
5.1.51 POLLST (026h) (Master Mode) .....................................................................97
5.1.52 POLL (024h) (Master Mode)..........................................................................97
5.1.53 EOI (022h) End-Of-Interrupt Register (Master Mode) ..................................98
5.1.54 EOI (022h) Specific End-Of-Interrupt Register (Slave Mode) ......................98
5.1.55 INTVEC (020h) Interrupt Vector Register (Slave Mode) ..............................99
5.1.56 SSR (018h)......................................................................................................99
5.1.57 SSD0 (016h) and SSD1 (014h).......................................................................99
5.1.58 SSC (012h)....................................................................................................100
5.1.59 SSS (010h) ....................................................................................................100
5.2 Reference Documents ...............................................................................................101
AC Specifications ...............................................................................................................101
Instruction Set Summary Table ..........................................................................................130
7.1 Key to Abbreviations Used in Instruction Set Summary Table ................................140
7.1.1 Operand Address Byte ..................................................................................140
7.1.2 Modifier Field ...............................................................................................140
7.1.3 Auxiliary Field ..............................................................................................141
7.1.4 r/m Field........................................................................................................141
7.1.5 Displacement ................................................................................................141
7.1.6 Immediate Bytes ...........................................................................................141
7.1.7 Segment Override Prefix ..............................................................................141
7.1.8 Segment Register ..........................................................................................142
7.2 Explanation of Notation Used in Instruction Set Summary Table ............................142
7.2.1 Opcode ..........................................................................................................142
7.2.2 Flags Affected After Instruction ...................................................................143
Innovasic/AMD Part Number Cross-Reference Table .......................................................144
Revision History .................................................................................................................145
For Additional Information.................................................................................................146
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LIST OF FIGURES
Figure 1. IA186ER LQFP Package Diagram ................................................................................16
Figure 2. IA188ER LQFP Package Diagram ................................................................................19
Figure 3. LQFP Package Dimensions ...........................................................................................22
Figure 4. IA186ER PQFP Package Diagram ................................................................................23
Figure 5. IA188ER PQFP Package Diagram ................................................................................26
Figure 6. PQFP Package Dimensions ...........................................................................................29
Figure 7. Functional Block Diagram ............................................................................................45
Figure 8. Crystal Configuration ....................................................................................................46
Figure 10. Read Cycle.................................................................................................................109
Figure 11. Multiple Read Cycles ................................................................................................110
Figure 12. Write Cycle ................................................................................................................112
Figure 13. Multiple Write Cycles ...............................................................................................113
Figure 14. PSRAM Read Cycle ..................................................................................................115
Figure 15. PSRAM Write Cycle .................................................................................................117
Figure 16. PSRAM Refresh Cycle ..............................................................................................119
Figure 17. Internal RAM Show Read Cycle ...............................................................................120
Figure 18. Interrupt Acknowledge Cycle....................................................................................121
Figure 19. Software Halt Cycle ..................................................................................................123
Figure 20. Clock—Active Mode.................................................................................................124
Figure 21. Clock—Power-Save Mode ........................................................................................124
Figure 22. srdy—Synchronous Ready ........................................................................................125
Figure 23. ardy—Asynchronous Ready......................................................................................126
Figure 24. Peripherals .................................................................................................................126
Figure 25. Reset 1 .......................................................................................................................127
Figure 26. Reset 2 .......................................................................................................................127
Figure 27. Bus Hold Entering .....................................................................................................128
Figure 28. Bus Hold Leaving ......................................................................................................128
Figure 29. Synchronous Serial Interface .....................................................................................129
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LIST OF TABLES
Table 1. IA186ER LQFP Numeric Pin Listing .............................................................................17
Table 2. IA186ER LQFP Alphabetic Pin Listing .........................................................................18
Table 3. IA188ER LQFP Numeric Pin Listing .............................................................................20
Table 4. IA188ER LQFP Alphabetic Pin Listing .........................................................................21
Table 5. IA186ER PQFP Numeric Pin Listing .............................................................................24
Table 6. IA186ER PQFP Alphabetic Pin Listing .........................................................................25
Table 7. IA188ER PQFP Numeric Pin Listing .............................................................................27
Table 8. IA188ER PQFP Alphabetic Pin Listing .........................................................................28
Table 9. Bus Cycle Types for bhe_n and ad0 ...............................................................................31
Table 10. Bus Cycle Types for s2_n, s1_n, and s0_n ...................................................................38
Table 11. IA186ER and IA188ER Absolute Maximum Ratings ..................................................43
Table 12. IA186ER and IA188ER Thermal Characteristics .........................................................43
Table 13. DC Characteristics Over Industrial Operating Ranges .................................................43
Table 14. Interrupt Types ..............................................................................................................51
Table 15. Default Status of PIO Pins at Reset ..............................................................................56
Table 16. Peripheral Control Registers .........................................................................................59
Table 17. Peripheral Control Block Relocation Register..............................................................60
Table 18. Reset Configuration Register ........................................................................................60
Table 19. Processor Release Level Register .................................................................................61
Table 20. Power-Save Control Register........................................................................................61
Table 21. Watchdog Timer Control Register ................................................................................62
Table 22. Enable Dynamic RAM Refresh Control Register.........................................................63
Table 23. Count for Dynamic RAM Refresh Control Register ....................................................64
Table 24. Memory Partition for Dynamic RAM Refresh Control Register .................................64
Table 25. DMA Control Registers ................................................................................................64
Table 26. DMA Transfer Count Registers ....................................................................................66
Table 27. DMA Destination Address High Register ....................................................................67
Table 28. DMA Destination Address Low Register .....................................................................67
Table 29. DMA Source Address High Register............................................................................68
Table 30. DMA Source Address Low Register ............................................................................68
Table 31. Internal Memory Chip Select Register .........................................................................68
Table 32. MCS and PCS Auxiliary Register ................................................................................69
Table 33. Midrange Memory Chip Select Register ......................................................................70
Table 34. Peripheral Chip Select Register ....................................................................................72
Table 35. Low-Memory Chip Select Register ..............................................................................73
Table 36. Upper-Memory Chip Select Register ...........................................................................74
Table 37. Baud Rates ....................................................................................................................75
Table 38. Serial Port Baud Rate Divisor Registers .......................................................................76
Table 39. Serial Port Receive Data Register .................................................................................76
Table 40. Serial Port Transmit Data Register ...............................................................................77
Table 41. Serial Port Status Register ............................................................................................77
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Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
Table 81.
Table 82.
Table 83.
Table 84.
Data Sheet
February 25, 2013
Serial Port Control Register ..........................................................................................78
PIO Pin Assignments ....................................................................................................80
PDATA 0 ......................................................................................................................81
PDATA 1 ......................................................................................................................81
PIO Mode and PIO Direction Settings .........................................................................82
PDIR0 ...........................................................................................................................82
PDIR1 ...........................................................................................................................82
PIOMODE0 ..................................................................................................................82
PMODE1 ......................................................................................................................83
Timer 0 and Timer 1 Mode and Control Registers .......................................................83
Timer 2 Mode and Control Registers ...........................................................................84
Timer Maxcount Compare Registers ............................................................................85
Timer Count Registers ..................................................................................................86
Serial Port Interrupt Control Registers .........................................................................86
Watchdog Timer Interrupt Control Register .................................................................87
INT4 Control Register ..................................................................................................87
INT2/INT3 Control Register ........................................................................................88
INT0/INT1 Control Register ........................................................................................89
Timer Control Unit Interrupt Control Register .............................................................89
Timer Interrupt Control Register ..................................................................................90
DMA and Interrupt Control Register (Master Mode) ...................................................90
DMA and Interrupt Control Register (Slave Mode) .....................................................91
Interrupt Status Register (Master Mode) ......................................................................91
Interrupt Status Register (Slave Mode) ........................................................................92
Interrupt Request Register (Master Mode) ...................................................................92
Interrupt Request Register (Slave Mode) .....................................................................93
In-Service Register (Master Mode) ..............................................................................94
In-Service Register (Slave Mode).................................................................................94
Priority Mask Register ..................................................................................................95
Interrupt MASK Register (Master Mode) ....................................................................96
Interrupt MASK Register (Slave Mode) .......................................................................96
POLL Status Register ...................................................................................................97
Poll Register ..................................................................................................................98
End-of-Interrupt Register ..............................................................................................98
Specific End-of-Interrupt Register................................................................................98
Interrupt Vector Register ..............................................................................................99
Synchronous Serial Receive Register ...........................................................................99
Synchronous Serial Transmit Registers ........................................................................99
Synchronous Serial Control Registers ........................................................................100
Synchronous Serial Status Registers...........................................................................100
AC Characteristics Over Industrial Operating Ranges (50 MHz) ..............................102
Alphabetic Key to Waveform Parameters ..................................................................105
Numeric Key to Waveform Parameters ......................................................................107
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Table 85.
Table 86.
Table 87.
Table 88.
Table 89.
Table 91.
Table 92.
Table 93.
Table 94.
Table 95.
Table 96.
Table 97.
Table 98.
Table 99.
Data Sheet
February 25, 2013
Read Cycle Timing .....................................................................................................111
Write Cycle Timing ....................................................................................................114
PSRAM Read Cycle Timing.......................................................................................116
PSRAM Write Cycle Timing ......................................................................................118
PSRAM Refresh Cycle ...............................................................................................119
Interrupt Acknowledge Cycle Timing ........................................................................122
Software Halt Cycle Timing .......................................................................................123
Clock Timing ..............................................................................................................125
Ready and Peripheral Timing .....................................................................................127
Reset and Bus Hold Timing ........................................................................................129
Synchronous Serial Interface Timing .........................................................................130
Instruction Set Summary ............................................................................................130
Innovasic/AMD Part Number Cross-Reference .........................................................144
Revision History .........................................................................................................145
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CONVENTIONS
Arial Bold
Designates headings, figure captions, and table captions.
Blue
Designates hyperlinks (PDF copy only).
Italics
Designates emphasis or caution related to nearby information. Italics is also
used to designate variables, refer to related documents, and to differentiate
terms from other common words (e.g., “During refresh cycles, the a and ad
buses may not have the same address during the address phase of the ad bus
cycle.” “The hold latency time [time between the hold and hlda] depends on
the current processor activity when the hold is received.”).
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16-Bit/8-Bit Microcontrollers with RAM
Data Sheet
February 25, 2013
ACRONYMS AND ABBREVIATIONS
AMD
BIC
CDRAM
CSC
DA
DMA
EOI
ISR
LMCS
LQFP
MC
MDRAM
MILES™
MMCS
NMI
PCB
PIO
PLL
POR
PQFP
PSRAM
RCU
RoHS
SFNM
UART
UMCS
Advanced Micro Devices
Bus Interface and Control
Count for Dynamic RAM
Chip Selects and Control
Disable Address
Direct Memory Access
End of Interrupt
Interrupt Service Routine
Low-Memory Chip Select
Low-Profile Quad Flat Package
Maximum Count
Memory Partition for Dynamic RAM
Managed IC Lifetime Extension System
Midrange Memory Chip Select
nonmaskable interrupt
peripheral control block
programmable I/O
phase-lock-loop
power-on reset
Plastic Quad Flat Package
Pseudo-Static RAM
Refresh Control Unit
Restriction of Hazardous Substances
Special Fully Nested mode
Universal Asynchronous Receiver-Transmitter
Upper Memory Chip Select
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IA186ER/IA188ER
16-Bit/8-Bit Microcontrollers with RAM
1.
Data Sheet
February 25, 2013
Introduction
The IA186ER/IA188ER is a form, fit, and function replacement for the original Advanced Micro
Devices Am186ER/Am188ER family of microcontrollers. Innovasic produces replacement ICs
using its MILESTM, or Managed IC Lifetime Extension System cloning technology. This
technology produces replacement ICs far more complex than “emulation” while ensuring they
are compatible with the original IC. MILESTM captures the design of a clone so it can be
produced even as silicon technology advances. MILESTM also verifies the clone against the
original IC so that even the “undocumented features” are duplicated.
1.1
General Description
The IA186ER/IA188ER family of microcontrollers replaces obsolete Am186ER/188ER devices,
allowing customers to retain existing board designs, software compilers/assemblers and
emulation tools, thereby avoiding expensive redesign efforts.
The IA186ER/IA188ER microcontrollers are an upgrade for the 80C186/80C188 microcontroller
designs, with integrated peripherals to provide increased functionality and reduce system costs.
The Innovasic devices are created to satisfy requirements of embedded products designed for
telecommunications, office automation and storage, and industrial controls.
1.2
Features
Pin-for-pin compatible with Am186ER/Am188ER devices
All features are retained, including:
o A phase-lock loop (PLL) allowing same crystal/system clock frequency
o 8086/8088 instruction set with additional 186 instruction set extensions
o Programmable interrupt controller
o Two Direct Memory Access (DMA) channels
o Three 16-bit timers
o Internal 32K bytes of Memory
o Programmable chip select logic and wait-state generator
o Dedicated watchdog timer
o Independent asynchronous serial port (UART)
 DMA capability
 Hardware flow control
 7-, 8-, or 9-bit data capability
Synchronous Serial Port
o Half duplex bidirectional data transfer
Up to 32 programmable I/O pins (PIO)
Pseudo-static/dynamic RAM controller
Fully static CMOS design
50 MHz operation at industrial operating conditions
+3.3 VDC power supply
-40C to +85C Operating Temperature
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2.
Data Sheet
February 25, 2013
Packaging, Pin Descriptions, and Physical Dimensions
Information on the packages and pin descriptions for the IA186ER and the IA188ER is provided
separately. Refer to sections, figures, and tables for information on the device of interest.
Innovasic’s part number for these devices is marked as “18x” to indicate the same device will be
ordered for the 186 and 188 versions of each particular package style (See Section 8). Please
refer to this data sheet for specific use of the pins for the 186 and 188 versions. Please also note
that the data bus width of the IA18xER is selectable between 16-bit (IA186ER) or 8-bit
(IA188ER) upon powerup. For 8-bit operation tie the whb_n pin to ground. Reference pin
descriptions appropriate for the selected strapping option.
2.1
Packages and Pinouts
The Innovasic IA186ER and IA188ER microcontroller is available in the following packages:
100-Pin Low-Profile Quad Flat Package (LQFP), equivalent to original TQFP package
100-Pin Plastic Quad Flat Package (PQFP), equivalent to original PQFP package
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2.1.1
Data Sheet
February 25, 2013
IA186ER LQFP Package
drq0/pio12
drq1/pio13
tmrin0/pio11
tmrout0/pio10
tmrout1/pio1
tmrin1/pio0
res_n
gnd
mcs3_n/rfsh_n/pio25
mcs2_n/pio24
vcc
pcs0_n/pio16
pcs1_n/pio17
gnd
pcs2_n/pio18
pcs3_n/pio19
vcc
pcs5_n/a1/pio3
pcs6_n/a2/pio2
lcs_n/once0_n
ucs_n/once1_n
int0
int1/select_n
int2/inta0_n/pio31
int3/inta1_n/irq
The pinout for the IA186ER LQFP package is as shown in Figure 1. The corresponding pinout
is provided in Tables 1 and 2.
IA186ER
LQFP
int4/pio30
mcs1_n/pio15
mcs0_n/pio14
den_n/pio5
dt/r_n/pio4
nmi
srdy/pio6
hold
hlda
wlb_n
whb_n
gnd
a0
a1
vcc
a2
a3
a4
a5
a6
a7
a8
a9
a10
a11
sclk/pio20
bhe_n/aden_n
wr_n
rd_n
ale
ardy
s2_n
s1_n/imdis_n
s0_n/sren_n
gnd
x1
x2
vcc
clkouta
clkoutb
gnd
a19/pio9
a18/pio8
vcc
a17/pio7
a16
a15
a14
a13
a12
ad0
ad8
ad1
ad9
ad2
ad10
ad3
ad11
ad4
ad12
ad5
gnd
ad13
ad6
vcc
ad14
ad7
ad15
s6/clksel1_n/pio29
uzi_n/clksel2_n/pio26
txd/pio27
rxd/pio28
sdata/pio21
sden1/pio23
sden0/pio22
Figure 1. IA186ER LQFP Package Diagram
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Data Sheet
February 25, 2013
Table 1. IA186ER LQFP Numeric Pin Listing
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Name
ad0
ad8
ad1
ad9
ad2
ad10
ad3
ad11
ad4
ad12
ad5
gnd
ad13
ad6
vcc
ad14
ad7
ad15
s6/clksel1_n/pio29
uzi_n/clksel2_n/pio26
txd/pio27
rxd/pio28
sdata/pio21
sden1/pio23
sden0/pio22
sclk/pio20
bhe_n/aden_n
wr_n
rd_n
ale
ardy
s2_n
s1_n/imdis_n
s0_n/sren_n
Pin
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
Name
gnd
x1
x2
vcc
clkouta
clkoutb
gnd
a19/pio9
a18/pio8
vcc
a17/pio7
a16
a15
a14
a13
a12
a11
a10
a9
a8
a7
a6
a5
a4
a3
a2
vcc
a1
a0
gnd
whb_n
wlb_n
hlda
Pin
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
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Name
hold
srdy/pio6
nmi
dt/r_n/pio4
den_n/pio5
mcs0_n/pio14
mcs1_n/pio15
int4/pio30
int3/inta1_n/irq
int2/inta0_n/pio31
int1/select_n
int0
ucs_n/once1_n
lcs_n/once0_n
pcs6_n/a2/pio2
pcs5_n/a1/pio3
vcc
pcs3_n/pio19
pcs2_n/pio18
gnd
pcs1_n/pio17
pcs0_n/pio16
vcc
mcs2_n/pio24
mcs3_n/rfsh_n/pio25
gnd
res_n
tmrin1/pio0
tmrout1/pio1
tmrout0/pio10
tmrin0/pio11
drq1/pio13
drq0/pio12
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16-Bit/8-Bit Microcontrollers with RAM
Data Sheet
February 25, 2013
Table 2. IA186ER LQFP Alphabetic Pin Listing
Name
a0
a1
a2
a3
a4
a5
a6
a7
a8
a9
a10
a11
a12
a13
a14
a15
a16
a17/pio7
a18/pio8
a19/pio9
ad0
ad1
ad2
ad3
ad4
ad5
ad6
ad7
ad8
ad9
ad10
ad11
ad12
ad13
Pin
63
62
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
43
42
1
3
5
7
9
11
14
17
2
4
6
8
10
13
Name
ad14
ad15
ale
ardy
bhe_n/aden_n
clkouta
clkoutb
den_n/pio5
drq0/pio12
drq1/pio13
dt/r_n/pio4
gnd
gnd
gnd
gnd
gnd
gnd
hlda
hold
int0
int1/select_n
int2/inta0_n/pio31
int3/inta1_n/irq
int4/pio30
lcs_n/once0_n
mcs0_n/pio14
mcs1_n/pio15
mcs2_n/pio24
mcs3_n/rfsh_n/pio25
nmi
pcs0_n/pio16
pcs1_n/pio17
pcs2_n/pio18
Pin
16
18
30
31
27
39
40
72
100
99
71
12
35
41
64
87
93
67
68
79
78
77
76
75
81
73
74
91
92
70
89
88
86
Name
pcs3_n/pio19
pcs5_n/a1/pio3
pcs6_n/a2/pio2
rd_n
res_n
rxd/pio28
s0_n/sren_n
s1_n/imdis_n
s2_n
s6/clksel1_n/pio29
sclk/pio20
sdata/pio21
sden0/pio22
sden1/pio23
srdy/pio6
tmrin0/pio11
tmrin1/pio0
tmrout0/pio10
tmrout1/pio1
txd/pio27
ucs_n/once1_n
uzi_n/clksel2_n/pio26
vcc
vcc
vcc
vcc
vcc
vcc
whb_n
wlb_n
wr_n
x1
x2
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Pin
85
83
82
29
94
22
34
33
32
19
26
23
25
24
69
98
95
97
96
21
80
20
15
38
44
61
84
90
65
66
28
36
37
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2.1.2
Data Sheet
February 25, 2013
IA188ER LQFP Package
drq0/pio12
drq1/pio13
tmrin0/pio11
tmrout0/pio10
tmrout1/pio1
tmrin1/pio0
res_n
gnd
mcs3_n/rfsh_n/pio25
mcs2_n/pio24
vcc
pcs0_n/pio16
pcs1_n/pio17
gnd
pcs2_n/pio18
pcs3_n/pio19
vcc
pcs5_n/a1/pio3
pcs6_n/a2/pio2
lcs_n/once0_n
ucs_n/once1_n
int0
int1/select_n
int2/inta0_n/pio31
int3/inta1_n/irq
The pinout for the IA188ER LQFP package is as shown in Figure 2. The corresponding pinout
is provided in Tables 3 and 4.
IA188ER
LQFP
int4/pio30
mcs1_n/pio15
mcs0_n/pio14
den_n/pio5
dt/r_n/pio4
nmi
srdy/pio6
hold
hlda
wb_n
gnd
gnd
a0
a1
vcc
a2
a3
a4
a5
a6
a7
a8
a9
a10
a11
sclk/pio20
rfsh2_n/aden_n
wr_n
rd_n
ale
ardy
s2_n
s1_n/imdis_n
s0_n/sren_n
gnd
x1
x2
vcc
clkouta
clkoutb
gnd
a19/pio9
a18/pio8
vcc
a17/pio7
a16
a15
a14
a13
a12
ad0
ao8
ad1
ao9
ad2
ao10
ad3
ao11
ad4
ao12
ad5
gnd
ao13
ad6
vcc
ao14
ad7
ao15
s6/clksel1_n/pio29
uzi_n/clksel2_n/pio26
txd/pio27
rxd/pio28
sdata/pio21
sden1/pio23
sden0/pio22
Figure 2. IA188ER LQFP Package Diagram
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Table 3. IA188ER LQFP Numeric Pin Listing
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Name
ad0
ao8
ad1
ao9
ad2
ao10
ad3
ao11
ad4
ao12
ad5
gnd
ao13
ad6
vcc
ao14
ad7
ao15
s6/clksel1_n/pio29
uzi_n/clksel2_n/pio26
txd/pio27
rxd/pio28
sdata/pio21
sden1/pio23
sden0/pio22
sclk/pio20
rfsh2_n/aden_n
wr_n
rd_n
ale
ardy
s2_n
s1_n/imdis_n
s0_n/sren_n
Pin
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
Name
gnd
x1
x2
vcc
clkouta
clkoutb
gnd
a19/pio9
a18/pio8
vcc
a17/pio7
a16
a15
a14
a13
a12
a11
a10
a9
a8
a7
a6
a5
a4
a3
a2
vcc
a1
a0
gnd
gnd
wb_n
hlda
Pin
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
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Name
hold
srdy/pio6
nmi
dt/r_n/pio4
den_n/pio5
mcs0_n/pio14
mcs1_n/pio15
int4/pio30
int3/inta1_n/irq
int2/inta0_n/pio31
int1/select_n
int0
ucs_n/once1_n
lcs_n/once0_n
pcs6_n/a2/pio2
pcs5_n/a1/pio3
vcc
pcs3_n/pio19
pcs2_n/pio18
gnd
pcs1_n/pio17
pcs0_n/pio16
vcc
mcs2_n/pio24
mcs3_n/rfsh_n/pio25
gnd
res_n
tmrin1/pio0
tmrout1/pio1
tmrout0/pio10
tmrin0/pio11
drq1/pio13
drq0/pio12
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Data Sheet
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Table 4. IA188ER LQFP Alphabetic Pin Listing
Name
a0
a1
a2
a3
a4
a5
a6
a7
a8
a9
a10
a11
a12
a13
a14
a15
a16
a17/pio7
a18/pio8
a19/pio9
Pin
63
62
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
43
42
Name
ao13
ao14
ao15
ardy
clkouta
clkoutb
den_n/pio5
drq0/pio12
drq1/pio13
dt/r_n/pio4
gnd
gnd
gnd
gnd
gnd
gnd
gnd
hlda
hold
int0
Pin
13
16
18
31
39
40
72
100
99
71
12
35
41
64
65
87
93
67
68
79
Name
pcs3_n/pio19
pcs5_n/a1/pio3
pcs6_n/a2/pio2
rd_n
res_n
rfsh2_n/aden_n
rxd/pio28
s0_n/sren_n
s1_n/imdis_n
s2_n
s6/clksel1_n/pio29
sclk/pio20
sdata/pio21
sden0/pio22
sden1/pio23
srdy/pio6
tmrin0/pio11
tmrin1/pio0
tmrout0/pio10
tmrout1/pio1
Pin
85
83
82
29
94
27
22
34
33
32
19
26
23
25
24
69
98
95
97
96
ad0
ad1
ad2
ad3
ad4
ad5
ad6
ad7
ale
ao8
ao9
ao10
ao11
ao12
1
3
5
7
9
11
14
17
30
2
4
6
8
10
int1/select_n
int2/inta0_n/pio31
int3/inta1_n/irq
int4/pio30
lcs_n/once0_n
mcs0_n/pio14
mcs1_n/pio15
mcs2_n/pio24
mcs3_n/rfsh_n/pio25
nmi
pcs0_n/pio16
pcs1_n/pio17
pcs2_n/pio18
78
77
76
75
81
73
74
91
92
70
89
88
86
txd/pio27
ucs_n/once1_n
uzi_n/clksel2_n/pio26
vcc
vcc
vcc
vcc
vcc
vcc
wb_n
wr_n
x1
x2
21
80
20
15
38
44
61
84
90
66
28
36
37
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2.1.3
Data Sheet
February 25, 2013
LQFP Physical Dimensions
The physical dimensions for the LQFP are as shown in Figure 3.
Legend:
Symbol
A
A1
A2
b
c
D
D1
E
E1
e
L
L1
R1
R2
S
θ
θ1
θ2
θ3
Millimeter
Inch
Min Nom Max Min Nom Max
–
–
1.60
–
– 0.063
0.05
–
0.15 0.002 – 0.006
1.35 1.40 1.45 0.053 0.055 0.057
0.17 0.22 0.27 0.007 0.009 0.011
0.09
–
0.20 0.004 – 0.008
15.85 16.00 16.15 0.624 0.630 0.636
13.90 14.00 14.10 0.547 0.551 0.555
15.85 16.00 16.15 0.624 0.630 0.636
13.90 14.00 14.10 0.547 0.551 0.555
0.50 BSC
0.020 BSC
0.45 0.60 0.75 0.018 0.024 0.030
1.00 REF
0.039 REF
0.08
–
– 0.003 –
–
0.08
–
0.20 0.003 – 0.008
0.20
–
– 0.008 –
–
0°
3.5° 7°
0° 3.5° 7°
0°
–
–
0°
–
–
11° 12° 13° 11° 12° 13°
11° 12° 13° 11° 12° 13°
Note:
Control dimensions are in millimeters.
Figure 3. LQFP Package Dimensions
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Data Sheet
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IA186ER PQFP Package
sdata/pio21
rxd/pio28
txd/pio27
uzi_n/clksel2_n/pio26
s6/clksel1_n/pio29
ad15
ad7
ad14
vcc
ad6
ad13
gnd
ad5
ad12
ad4
ad11
ad3
ad10
ad2
ad9
The pinout for the IA186ER PQFP package is as shown in Figure 4. The corresponding pinout is
provided in Tables 5 and 6.
®
IA186ER
IA186ES
PQFP
TQFP
ad1
ad8
ad0
drq0/pio12
drq1/pio13
tmrin0/pio11
tmrout0/pio10
tmrout1/pio1
tmrin1/pio0
res_n
gnd
mcs3_n/rfsh_n/pio25
mcs2_n/pio24
vcc
pcs0_n/pio16
pcs1_n/pio17
gnd
pcs2_n/pio18
pcs3_n/pio19
vcc
pcs5_n/a1/pio3
pcs6_n/a2/pio2
lcs_n/once0_n
ucs_n/once1_n
int0
int1/select_n
int2/inta0_n/pio31
int3/inta1_n/irq
int4/pio30
mcs1_n/pio15
a8
a7
a6
a5
a4
a3
a2
vcc
a1
a0
gnd
whb_n
wlb_n
hlda
hold
srdy/pio6
nmi
dt/r_n/pio4
den_n/pio5
mcs0_n/pio14
sden1/pio23
sden0/pio22
sclk/pio20
bhe_n/aden_n
wr_n
rd_n
ale
ardy
s2_n
s1_n/imdis_n
s0_n/sren_n
gnd
x1
x2
vcc
clkouta
clkoutb
gnd
a19/pio9
a18/pio8
vcc
a17/pio7
a16
a15
a14
a13
a12
a11
a10
a9
Figure 4. IA186ER PQFP Package Diagram
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Table 5. IA186ER PQFP Numeric Pin Listing
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Name
sden1/pio23
sden0/pio22
sclk/pio20
bhe_n/aden_n
wr_n
rd_n
ale
ardy
s2_n
s1_n/imdis_n
s0_n/sren_n
gnd
x1
x2
vcc
clkouta
clkoutb
gnd
a19/pio9
a18/pio8
vcc
a17/pio7
a16
a15
a14
a13
a12
a11
a10
a9
a8
a7
a6
a5
Pin
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
Name
a4
a3
a2
vcc
a1
a0
gnd
whb_n
wlb_n
hlda
hold
srdy/pio6
nmi
dt/r_n/pio4
den_n/pio5
mcs0_n/pio14
mcs1_n/pio15
int4/pio30
int3/inta1_n/irq
int2/inta0_n/pio31
int1/select_n
int0
ucs_n/once1_n
lcs_n/once0_n
pcs6_n/a2/pio2
pcs5_n/a1/pio3
vcc
pcs3_n/pio19
pcs2_n/pio18
gnd
pcs1_n/pio17
pcs0_n/pio16
vcc
Pin
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
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Name
mcs2_n/pio24
mcs3_n/rfsh_n/pio25
gnd
res_n
tmrin1/pio0
tmrout1/pio1
tmrout0/pio10
tmrin0/pio11
drq1/pio13
drq0/pio12
ad0
ad8
ad1
ad9
ad2
ad10
ad3
ad11
ad4
ad12
ad5
gnd
ad13
ad6
vcc
ad14
ad7
ad15
s6/clksel1_n/pio29
uzi_n/clksel2_n/pio26
txd/pio27
rxd/pio28
sdata/pio21
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16-Bit/8-Bit Microcontrollers with RAM
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Table 6. IA186ER PQFP Alphabetic Pin Listing
Name
a0
a1
a2
a3
a4
a5
a6
a7
a8
a9
a10
a11
a12
a13
a14
a15
a16
a17/pio7
a18/pio8
a19/pio9
ad0
ad1
ad2
ad3
ad4
ad5
ad6
ad7
ad8
ad9
ad10
ad11
ad12
ad13
Pin
40
39
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
20
19
78
80
82
84
86
88
91
94
79
81
83
85
87
90
Name
ad14
ad15
ale
ardy
bhe_n/aden_n
clkouta
clkoutb
den_n/pio5
drq0/pio12
drq1/pio13
dt/r_n/pio4
gnd
gnd
gnd
gnd
gnd
gnd
hlda
hold
int0
int1/select_n
int2/inta0_n/pio31
int3/inta1_n/irq
int4/pio30
lcs_n/once0_n
mcs0_n/pio14
mcs1_n/pio15
mcs2_n/pio24
mcs3_n/rfsh_n/pio25
nmi
pcs0_n/pio16
pcs1_n/pio17
pcs2_n/pio18
Pin
93
95
7
8
4
16
17
49
77
76
48
12
18
41
64
70
89
44
45
56
55
54
53
52
58
50
51
68
69
47
66
65
63
Name
pcs3_n/pio19
pcs5_n/a1/pio3
pcs6_n/a2/pio2
rd_n
res_n
rxd/pio28
s0_n/sren_n
s1_n/imdis_n
s2_n
s6/clksel1_n/pio29
sclk/pio20
sdata/pio21
sden0/pio22
sden1/pio23
srdy/pio6
tmrin0/pio11
tmrin1/pio0
tmrout0/pio10
tmrout1/pio1
txd/pio27
ucs_n/once1_n
uzi_n/clksel2_n/pio26
vcc
vcc
vcc
vcc
vcc
vcc
whb_n
wlb_n
wr_n
x1
x2
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Pin
62
60
59
6
71
99
11
10
9
96
3
100
2
1
46
75
72
74
73
98
57
97
15
21
38
61
67
92
42
43
5
13
14
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16-Bit/8-Bit Microcontrollers with RAM
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Data Sheet
February 25, 2013
IA188ER PQFP Package
sdata/pio21
rxd/pio28
txd/pio27
uzi_n/clksel2_n/pio26
s6/clksel1_n/pio29
ao15
ad7
ao14
vcc
ad6
ao13
gnd
ad5
ao12
ad4
ao11
ad3
ao10
ad2
ao9
The pinout for the IA188ER PQFP package is as shown in Figure 5. The corresponding pinout is
provided in Tables 7 and 8.
IA188ER
IA186ES
PQFP
TQFP
ad1
ao8
ad0
drq0/pio12
drq1/pio13
tmrin0/pio11
tmrout0/pio10
tmrout1/pio1
tmrin1/pio0
res_n
gnd
mcs3_n/rfsh_n/pio25
mcs2_n/pio24
vcc
pcs0_n/pio16
pcs1_n/pio17
gnd
pcs2_n/pio18
pcs3_n/pio19
vcc
pcs5_n/a1/pio3
pcs6_n/a2/pio2
lcs_n/once0_n
ucs_n/once1_n
int0
int1/select_n
int2/inta0_n/pio31
int3/inta1_n/irq
int4/pio30
mcs1_n/pio15
a8
a7
a6
a5
a4
a3
a2
vcc
a1
a0
gnd
gnd
wb_n
hlda
hold
srdy/pio6
nmi
dt/r_n/pio4
den_n/pio5
mcs0_n/pio14
sden1/pio23
sden0/pio22
sclk/pio20
rfsh2_n/aden_n
wr_n
rd_n
ale
ardy
s2_n
s1_n/imdis_n
s0_n/sren_n
gnd
x1
x2
vcc
clkouta
clkoutb
gnd
a19/pio9
a18/pio8
vcc
a17/pio7
a16
a15
a14
a13
a12
a11
a10
a9
Figure 5. IA188ER PQFP Package Diagram
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February 25, 2013
Table 7. IA188ER PQFP Numeric Pin Listing
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Name
sden1/pio23
sden0/pio22
sclk/pio20
rfsh2_n/aden_n
wr_n
rd_n
ale
ardy
s2_n
s1_n/imdis_n
s0_n/sren_n
gnd
x1
x2
vcc
clkouta
clkoutb
gnd
a19/pio9
a18/pio8
vcc
a17/pio7
a16
a15
a14
a13
a12
a11
a10
a9
a8
a7
a6
a5
Pin
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
Name
a4
a3
a2
vcc
a1
a0
gnd
gnd
wb_n
hlda
hold
srdy/pio6
nmi
dt/r_n/pio4
den_n/pio5
mcs0_n/pio14
mcs1_n/pio15
int4/pio30
int3/inta1_n/irq
int2/inta0_n/pio31
int1/select_n
int0
ucs_n/once1_n
lcs_n/once0_n
pcs6_n/a2/pio2
pcs5_n/a1/pio3
vcc
pcs3_n/pio19
pcs2_n/pio18
gnd
pcs1_n/pio17
pcs0_n/pio16
vcc
Pin
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
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Name
mcs2_n/pio24
mcs3_n/rfsh_n/pio25
gnd
res_n
tmrin1/pio0
tmrout1/pio1
tmrout0/pio10
tmrin0/pio11
drq1/pio13
drq0/pio12
ad0
ao8
ad1
ao9
ad2
ao10
ad3
ao11
ad4
ao12
ad5
gnd
ao13
ad6
vcc
ao14
ad7
ao15
s6/clksel1_n/pio29
uzi_n/clksel2_n/pio26
txd/pio27
rxd/pio28
sdata/pio21
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16-Bit/8-Bit Microcontrollers with RAM
Data Sheet
February 25, 2013
Table 8. IA188ER PQFP Alphabetic Pin Listing
Name
a0
a1
a2
a3
a4
a5
a6
a7
a8
a9
a10
a11
a12
a13
a14
a15
a16
a17/pio7
a18/pio8
a19/pio9
ad0
ad1
ad2
ad3
ad4
ad5
ad6
ad7
ale
ao8
ao9
ao10
ao11
ao12
Pin
40
39
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
20
19
78
80
82
84
86
88
91
94
7
79
81
83
85
87
Name
ao13
ao14
ao15
ardy
clkouta
clkoutb
den_n/pio5
drq0/pio12
drq1/pio13
dt/r_n/pio4
gnd
gnd
gnd
gnd
gnd
gnd
gnd
hlda
hold
int0
int1/select_n
int2/inta0_n/pio31
int3/inta1_n/irq
int4/pio30
lcs_n/once0_n
mcs0_n/pio14
mcs1_n/pio15
mcs2_n/pio24
mcs3_n/rfsh_n/pio25
nmi
pcs0_n/pio16
pcs1_n/pio17
pcs2_n/pio18
Pin
90
93
95
8
16
17
49
77
76
48
12
18
41
42
64
70
89
44
45
56
55
54
53
52
58
50
51
68
69
47
66
65
63
Name
pcs3_n/rts1_n/rtr1_n/pio19
pcs5_n/a1/pio3
pcs6_n/a2/pio2
rd_n
res_n
rfsh2_n/aden_n
rxd/pio28
s0_n/sren_n
s1_n/imdis_n
s2_n
s6/clksel1_n/pio29
sclk/pio20
sdata/pio21
sden0/pio22
sden1/pio23
srdy/pio6
tmrin0/pio11
tmrin1/pio0
tmrout0/pio10
tmrout1/pio1
txd/pio27
ucs_n/once1_n
uzi_n/clksel2_n/pio26
vcc
vcc
vcc
vcc
vcc
vcc
wb_n
wr_n
x1
x2
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Pin
62
60
59
6
71
4
99
11
10
9
96
3
100
2
1
46
75
72
74
73
98
57
97
15
21
38
61
67
92
43
5
13
14
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2.1.6
Data Sheet
February 25, 2013
PQFP Physical Dimensions
The physical dimensions for the PQFP are as shown in Figure 6.
Legend
Symbol
A
A1
A2
B
C
D
D1
E
E1
e
L
L1
Y
θ
Millimeter
Min Nom Max
–
– 3.40
0.25
–
–
2.73 2.85 2.97
0.25 0.30 0.38
0.13 0.15 0.23
23.00 23.20 23.40
19.90 20.00 20.10
17.00 17.20 17.40
13.90 14.00 14.10
0.65 BSC.
0.73 0.88 1.03
1.60 BSC.
–
– 0.10
–
0
7
Inch
Min Nom Max
–
– 0.134
0.010 –
–
0.107 0.112 0.117
0.010 0.012 0.015
0.005 0.006 0.009
0.906 0.913 0.921
0.783 0.787 0.791
0.669 0.677 0.685
0.547 0.551 0.555
0.026 BSC.
0.029 0.035 0.041
0.063 BSC.
–
– 0.004
–
0
7
Notes:
1. Dimensions D1 and E1 do not include
mold protrusion, but mold mismatch is
included. Allowable protrusion is
0.25mm/0.010 per side.
2. Dimension B does not include Dambar
protrusion. Allowable protrusion is
0.08mm/0.003 total in excess of the B
dimension at maximum material
condition. Dambar cannot be located on
the lower radius or the foot.
3. Controlling dimension: millimeter.
Figure 6. PQFP Package Dimensions
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2.2
2.2.1
Data Sheet
February 25, 2013
Pin Descriptions
a19/pio9, a18/pio8, a17/pio7, a16–a0—Address Bus (synchronous outputs with
tristate)
These pins are the system’s source of non-multiplexed I/O or memory addresses and occur one
half clkouta cycle before the multiplexed address/data bus (ad15–ad0 for the IA186ER or ao15–
ao8 and ad7–ad0 for the IA188ER). The address bus is tristated during a bus hold or reset.
2.2.2
ad15–ad8 (IA186ER)—Address/data bus (level-sensitive synchronous inouts
with tristate)
These pins are the system’s source of time-multiplexed I/O or memory addresses and data. The
address function of these pins can be disabled (see bhe_n/aden_n pin description). If the address
function of these pins is enabled, the address will be present on this bus during t1 of the bus cycle
and data will be present during t2, t3, and t4 of the same bus cycle.
If whb_n is not active, these pins are tristated during t2, t3, and t4 of the bus cycle.
The address/data bus is tristated during a bus hold or reset.
These pins can be used to load the internal Reset Configuration register (RESCON, offset 0F6h)
with configuration data during a power-on reset (POR).
2.2.3
ad7–ad0—Address/Data bus (level-sensitive synchronous inouts with tristate)
These pins are the system’s source of time-multiplexed low-order byte of the addresses for I/O or
memory and 8-bit data. The low-order address byte will be present on this bus during t1 of the
bus cycle and the 8-bit data will be present during t2, t3, and t4 of the same bus cycle.
The address function of these pins can be disabled (see bhe_n/aden_n pin description).
If wlb_n (IA186ER) is not active, these pins are tristated during t2, t3, and t4 of the bus cycle.
The address/data bus is tristated during a bus hold or reset.
2.2.4
ao15–ao8 (IA188ER)—Address-only bus (level-sensitive synchronous outputs
with tristate)
The address-only bus will contain valid high-order address bits during the bus cycle (t1, t2, t3, and
t4) if the bus is enabled.
These pins are combined with ad7–ad0 to complete the multiplexed address bus and are tristated
during a bus hold or reset condition.
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ale—Address Latch Enable (synchronous output)
This signal indicates the presence of an address on the address/data bus (ad15–ad0 for the
IA186ER or ao15–ao8 and ad7–ad0 for the IA188ER), which is guaranteed to be valid on the
falling edge of ale.
2.2.6
ardy—Asynchronous Ready (level-sensitive asynchronous input)
This asynchronous signal provides an indication to the microcontroller that the addressed I/O
device or memory space will complete a data transfer. This active high signal is asynchronous
with respect to clkouta and if the falling edge of ardy is not synchronized to clkouta, an
additional clock cycle may be added
Signal ardy should be tied high to maintain a permanent assertion of the ready condition. On the
other hand, if the ardy signal is not used by the system it should be tied low, which passes
control to the srdy signal.
2.2.7
bhe_n/aden_n (IA186ER)—Bus High Enable (synchronous output with
tristate)/Address Enable (input with internal pull-up)
The bhe_n and address bit ad0 or a0 inform the system which bytes of the data bus (upper, lower,
or both) are involved in the current memory access bus cycle as shown Table 9.
Table 9. Bus Cycle Types for bhe_n and ad0
bhe_n
0
0
1
1
ad0
0
1
0
1
Type of Bus Cycle
Word Transfer
High-Byte Transfer (Bits [15–8])
Low-Byte Transfer (Bits [7–0])
Refresh
The bhe_n does not require latching and during bus hold and reset is tristated. It is asserted
during t1 and remains so through t3 and tw.
The high- and low-byte write enable functions of bhe_n and ad0 are performed by whb_n and
wlb_n, respectively.
When using the ad bus, DRAM refresh cycles are indicated by bhe_n/aden_n and ad0 both being
high. During refresh cycles the a and ad buses may not have the same address during the
address phase of the ad bus cycle necessitating the use of ad0 as a determinant for the refresh
cycle rather than a0.
An additional signal is used for Pseudo-Static RAM (PSRAM) refreshes (see mcs3_n/rfsh_n pin
description).
There is a weak internal pull-up on bhe_n/aden_n obviating the need for an external pull-up and
reducing power consumption.
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Data Sheet
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Holding aden_n high or letting it float during POR passes control of the address function of the
ad bus (ad15–ad0) during LCS and UCS bus cycles from aden_n to the Disable Address (DA) bit
in Low-Memory Chip Select (LMCS) and Upper Memory Chip Select (UMCS) registers. When
the address function is selected, the memory address is placed on the a19–a0 pins.
Holding aden_n low during POR, both the address and data are driven onto the ad bus
independently of the DA bit setting. This pin is normally sampled one clock cycle after the
rising edge of res_n.
2.2.8
clkouta—Clock Output A (synchronous output)
This pin is the internal clock output to the system. Bits [9–8] and Bits [2–0] of the Power-Save
Control register (PDCON) control the output of this pin, which may be tristated, output the
internal processor frequency (divide by two, x1 or x4), or output the power save frequency
(internal processor frequency after divisor). The clkouta can be used as a full-speed clock source
in power-save mode. The AC timing specifications that are clock-related refer to clkouta, which
remains active during reset and hold conditions.
2.2.9
clkoutb—Clock Output B (synchronous output)
This pin is an additional clock output to the system. Bits [11–10] and [2–0] of the Power-Save
Control register (PDCON) control the output of this pin, which may be tristated, internal
processor frequency (divide by two, x1 or x4), or may output the power-save frequency (internal
processor frequency after divisor). The clkoutb remains active during reset and hold conditions.
2.2.10 den_n/pio5—Data Enable Strobe (synchronous output with tristate)
This pin provides an output enable to an external bus data bus transmitter or receiver. This
signal is asserted during I/O, memory, and interrupt acknowledge processes and is deasserted
when dt/r_n undergoes a change of state. It is tristated for a bus hold or reset.
2.2.11 drq1/pio13–drq0/pio12—DMA Requests (synchronous level-sensitive inputs)
An external device that is ready for DMA channel 1 or 0 to carry out a transfer indicates to the
microcontroller this readiness on these pins. They are level triggered, internally synchronized,
not latched, and must remain asserted until handled.
2.2.12 dt/r_n/pio4—Data Transmit or Receive (synchronous output with tristate)
The microcontroller transmits data when dt/r_n is set high and receives data when this pin is
asserted low. It floats during a reset or bus hold condition.
2.2.13 gnd—Ground
Six or seven pins, depending on package, connect the microcontroller to the system ground.
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2.2.14 hlda—Bus Hold Acknowledge (synchronous output)
This pin is set high to signal the system that the microcontroller has ceded control of the local
bus, in response to a high on the hold signal by an external bus master, after the microcontroller
has completed the current bus cycle. The assertion of hlda is accompanied by the tristating of
den_n, rd_n, wr_n, s2_n–s0_n, ad15–ad0, s6, a19–a0, bhe_n, whb_n, wlb_n, and dt/r_n,
followed by the driving high of the chip selects ucs_n, lcs_n, mcs3_n–mcs0_n, pcs6_n–pcs5_n,
and pcs3_n–pcs0_n. The external bus master releases control of the local bus by the deassertion
of hold that in turn induces the microcontroller to deassert the hlda. The microcontroller can
take control of the bus if necessary (to execute a refresh for example), by deasserting hlda
without the bus master first deasserting hold. This requires that the external bus master be able
to deassert hold to permit the microcontroller to access the bus.
2.2.15 hold—Bus Hold Request (synchronous level-sensitive input)
This pin is set high to signal the microcontroller that the system requires control of the local bus.
The hold latency time (time between the hold and hlda) depends on the current processor activity
when the hold is received. A hold request is second only to a DRAM or PSRAM refresh request
in priority of processor activity requests. If a hold request is received at the moment a DMA
transfer starts, the hold latency can be up to 4 bus cycles. (This happens only on the IA186ER
when a word transfer is taking place from an odd to an odd address.) This means that the latency
may be 16 clock cycles without wait states. Furthermore, if lock transfers are being performed,
then the latency is increased during the locked transfer.
2.2.16 int0—Maskable Interrupt Request 0 (asynchronous input)
The int0 pin provides an indication that an interrupt request has occurred, and provided that int0
is not masked, program execution will continue at the location specified by the INT0 vector in
the interrupt vector table. Although interrupt requests are asynchronous, they are synchronized
internally and may be edge- or level-triggered. To ensure that it is recognized, the assertion of
the interrupt request must be maintained until it is handled.
2.2.17 int1/select_n—Maskable Interrupt Request 1/Slave Select (both are asynchronous
inputs)
The int1 pin provides an indication that an interrupt request has occurred, and provided that int1
is not masked, program execution will continue at the location specified by the int1 vector in the
interrupt vector table. Although interrupt requests are asynchronous, they are synchronized
internally and may be edge- or level-triggered. To ensure that it is recognized, the assertion of
the interrupt request must be maintained until it is handled.
The select_n pin provides an indication to the microcontroller that an interrupt type has been
placed on the address/data bus when the internal Interrupt Control Unit is slaved to an external
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interrupt controller. Before this can occur, however, the int0 pin must have already indicated an
interrupt request.
2.2.18 int2/inta0_n/pio31—Maskable Interrupt Request 2 (asynchronous input)/Interrupt
Acknowledge 0 (synchronous output)
The int2 pin provides an indication that an interrupt request has occurred, and provided that int2
is not masked, program execution will continue at the location specified by the int2 vector in the
interrupt vector table. Although interrupt requests are asynchronous, they are synchronized
internally and may be edge- or level-triggered. To ensure that it is recognized, the assertion of
the interrupt request must be maintained until it is handled. When int0 is configured for cascade
mode, int2 changes its function to inta0_n.
The inta0_n function indicates to the system that the microcontroller requires an interrupt type in
response to the interrupt request int0 when the microcontroller’s Interrupt Control Unit is in
cascade mode. The peripheral device that issued the interrupt must provide the interrupt type.
2.2.19 int3/inta1_n/irq—Maskable Interrupt Request 3 (asynchronous input)/Interrupt
Acknowledge 1 (synchronous output)/Interrupt Request (synchronous output)
The int3 pin provides an indication that an interrupt request has occurred. If int3 is not masked,
program execution will continue at the location specified by the int3 vector in the interrupt
vector table. Although interrupt requests are asynchronous, they are synchronized internally and
may be edge- or level-triggered. To ensure that it is recognized, the assertion of the interrupt
request must be maintained until it is handled. When int1 is configured to be in cascade mode,
int3 changes its function to inta1_n.
The inta1_n function indicates to the system that the microcontroller requires an interrupt type in
response to the interrupt request int1 when the microcontroller’s Interrupt Control Unit is in
cascade mode. The peripheral device that issued the interrupt must provide the interrupt type.
Irq allows the microcontroller to output an interrupt request to the external master interrupt
controller when the Interrupt Control Unit of the microcontroller is in slave mode.
2.2.20 int4/pio30—Maskable Interrupt Request 4 (asynchronous input)
The int4 pin provides an indication that an interrupt request has occurred, and provided that int4
is not masked, program execution will continue at the location specified by the int4 vector in the
interrupt vector table. Although interrupt requests are asynchronous, they are synchronized
internally and may be edge- or level-triggered. To ensure that it is recognized, the assertion of
the interrupt request must be maintained until it is handled.
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2.2.21 lcs_n/once0_n—Lower Memory Chip Select (synchronous output with internal
pull-up)/ONCE Mode Request (input)
The lcs_n pin provides an indication that a memory access is occurring to the lower memory
block. The size of the Lower Memory Block and its base address are programmable, with the
size adjustable up to 512 Kbytes. The lcs_n pin is held high during bus hold.
The once0_n pin (ONCE – ON Circuit Emulation) and its companion pin, once1_n, define the
microcontroller mode during reset. These two pins are sampled on the rising edge of res_n and if
both are asserted low the microcontroller starts in ONCE mode, else it starts normally. In ONCE
mode, all pins are tristated and remain so until a subsequent reset. To prevent the
microcontroller from entering ONCE mode inadvertently, this pin has a weak pull-up that is only
present during reset. This pin is not tristated during bus hold.
2.2.22 mcs2_n—mcs0_n (pio24, pio15, pio 14)—Midrange Memory Chip Selects
(synchronous outputs with internal pull-up)
The mcs2_n and mcs0_n pins provide an indication that a memory access is in progress to the
first, second or third midrange memory block. The size of the Midrange Memory Blocks and its
base addresses are programmable. The mcs2_n – mcs0_n are held high during bus hold and
have weak pull-ups that are only present during reset.
2.2.23 mcs3_n/rfsh_n/pio25—Midrange Memory Chip Select (synchronous output with
internal pull-up)/Automatic Refresh (synchronous output)
The mcs3_n pin provides an indication that a memory access is in progress to the fourth region
of the midrange memory block. The size of the Midrange Memory Block and its base address
are programmable. The mcs3_n is held high during bus hold and has a weak pull-up that is
present only during reset.
The rfsh_n signal is timed for auto refresh to PSRAM or DRAM devices. The refresh pulse is
output only when the PSRAM or DRAM mode bit is set (EDRAM register Bit [15]). This pulse
is of 1.5 clock-pulse duration with the rest of the refresh cycle made up of a deassertion period
such that the overall refresh time is met. This pin is not tristated during a bus hold.
2.2.24 nmi—Nonmaskable Interrupt (synchronous edge-sensitive input)
Unlike int4 – int0, this is the highest priority interrupt signal and cannot be masked. Upon the
assertion of this interrupt (transition from Low to High), program execution is transferred to the
nonmaskable interrupt vector in the interrupt vector table and this interrupt is initiated at the next
instruction boundary. For recognition to be assured, the nmi pin must be held high for at least a
clkouta period so that the transition from low to high is latched and synchronized internally. The
interrupt will begin at the next instruction boundary.
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The nmi is not involved in the priority resolution process that deals with the maskable interrupts
and does not have an associated interrupt flag. This allows for a new nmi request to interrupt an
nmi service routine that is already underway. When an interrupt is taken by the processor the
interrupt flag IF is cleared, disabling the maskable interrupts. If the maskable interrupts are
reenabled during the nmi service routine (e.g., by use of STI instruction), the priority resolution
of maskable interrupts will be unaffected by the servicing of the non-maskable interrupt (NMI).
Note: For this reason, it is strongly recommended that the NMI interrupt
service routine does not enable the maskable interrupts.
2.2.25 pcs3_n–pcs0_n (pio19–pio16)—Peripheral Chip Selects 3–0 (synchronous
outputs)
The pcs3_n–pcs0_n pins provide an indication that a memory access is underway for the
corresponding region of the peripheral memory block (I/O or memory address space). The base
address of the peripheral memory block is programmable. The pins are held high during both
bus hold and reset. These outputs are asserted with the ad address bus over a 256-byte range
each.
2.2.26 pcs5_n/a1/pio3—Peripheral Chip Select 5 (synchronous output)/Latched Address
Bit 1 (synchronous output)
The pcs5_n signal provides an indication that a memory access is underway for the sixth region
of the peripheral memory block (I/O or memory address space). The base address of the
peripheral memory block is programmable. The pcs5_n is held high during both bus hold and
reset. This output is asserted with the ad address bus over a 256-byte range.
This a1 pin provides an internally latched address bit 1 to the system when the EX bit (Bit [7]) in
the mcs_n and pcs_n auxiliary (MPCS) register is 0. It retains its previously latched value
during a bus hold.
2.2.27 pcs6_n/a2/pio2—Peripheral Chip Select 6 (synchronous output)/latched Address
Bit 2 (synchronous output)
The pcs6_n signal provides an indication that a memory access is underway for the seventh
region of the peripheral memory block (I/O or memory address space). The base address of the
peripheral memory block is programmable. The pcs6_n is held high during both bus hold and
reset. This output is asserted with the ad address bus over a 256-byte range.
The a2 pin provides an internally latched address bit [2] to the system when the EX bit (Bit [7])
in the mcs_n and pcs_n auxiliary (MPCS) register is 0. It retains its previously latched value
during a bus hold.
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2.2.28 pio31–pio0—Programmable I/O Pins (asynchronous input/output open-drain)
There are 32 individually programmable I/O pins provided (see Table 15, Default Status of PIO
Pins at Reset).
2.2.29 rd_n—Read strobe (synchronous output with tristate)
The rd_n pin provides an indication to the system that a memory or I/O read cycle is underway.
It will not be asserted before the ad bus is floated during the address to data transition. The rd_n
pin is tristated during bus hold.
2.2.30 res_n—Reset (asynchronous level-sensitive input)
The res_n pin forces a reset of the microcontroller. Its Schmitt trigger allows POR generation
via an RC network. When this signal is asserted, the microcontroller immediately terminates its
present activity, clears its internal logic, and transfers CPU control to the reset address, FFFF0h.
The res_n must be asserted for at least 1 ms. Because it is synchronized internally it may be
asserted asynchronously to clkouta. Furthermore, vcc must be within specification and clkouta
must be stable for more than four of its clock periods for the period that res_n is asserted.
The microcontroller starts to fetch instructions 6.5 clkouta clock periods after the deassertion of
res_n.
2.2.31 rfsh2_n/aden_n (IA188ER)—Refresh 2 (synchronous output with tristate)/Address
Enable (input with internal pull-up)
The rfsh2_n indicates that a DRAM refresh cycle is being performed when it is asserted low.
However, this is not valid in PSRAM mode where mcs3_n/rfsh_n is used instead.
If the aden_n pin is held high during POR, the ad bus (ao15–ao8 and ad7–ad0 for the IA188ER)
is controlled during the address portion of the lcs and ucs bus cycles by the DA bit (Bit [7]) in
the lcs and ucs registers. If the DA bit is 1, the address is accessed on the a19–a0 pins, reducing
power consumption. The weak pull-up on this pin obviates the necessity of an external pull-up.
If the aden_n pin is held low during POR, the ad bus is used for both addresses and data without
regard for the setting of the DA bits. The rfsh2_n/aden_n is sampled one crystal clock cycle
after the rising edge of res_n and is tristated during bus holds and ONCE mode.
2.2.32 rxd/pio28—Receive Data (asynchronous input)
This signal connects asynchronous serial receive data from the system to the asynchronous serial
port.
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2.2.33 s0_n, s1_n (imdis_n), s0_n (sren_n) —Bus Cycle Status (synchronous outputs
with tristate)
These three signals inform the system of the type of bus cycle in progress. The s2_n may be
used to indicate whether the current access is to memory or I/O, and s1_n may be used to
indicate whether data is being transmitted or received. These signals are tristated during bus
hold and hold acknowledge. The coding for these pins is presented in Table 10.
imdis_n: Internal Memory Disable (input, pullup); if low during reset, internal memory is
disabled.
sren_n: Show Read Enable (input, pullup); if low during reset, reads from internal memory are
driven on the external address/data bus.
Table 10. Bus Cycle Types for s2_n, s1_n, and s0_n
s2_n
0
0
0
0
1
1
1
1
s1_n
0
0
1
1
0
0
1
1
s0_n
0
1
0
1
0
1
0
1
Bus Cycle
Interrupt acknowledge
Read data from I/O
Write data to I/O
Halt
Instruction fetch
Read data from memory
Write data to memory
None (passive)
2.2.34 s6/clksel1_n/pio29—Bus Cycle Status Bit 6 (synchronous output)/Clock Divide
by 2 (input with internal pull-up)
The s6 signal is high during the second and remaining cycle periods (i.e., t2 – t4), indicating that a
DMA-initiated bus cycle is underway. The s6 is tristated during bus hold or reset.
Combined with uzi_n/clksel2_n to select clock mode. If low, input clock is divided by two and
the PLL is disabled. Default, because of pull-ups, is for x4 clock mode. This pin is sampled on
the rise of reset.
Note: If this pin is used as pio29 and configured as an input, care should be
taken that it is not driven low during POR.
Because this pin has an internal pull-up, it is not necessary to drive the pin high even though it
defaults to an input PIO.
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2.2.35 sclk/pio20 —Serial Clock (synchronous outputs with tristate)
Because this pin provides a slave device with a synchronous serial clock it permits
synchronization of the transmit and receive data exchanges between the slave and the
microcontroller. The sclk is the result of dividing the internal clock by 2, 4, 8, or 16, depending
on the contents of the Synchronous Serial Control (SSC) register Bits [5–4]. Accessing either
the SSR or SSD registers activates the sclk for eight cycles. When sclk is not active, the
microcontroller holds it high.
2.2.36 sdata/pio21 —Serial Data (synchronous inout)
The sdata pin connects a slave device to synchronous serial transmit and receive data. The last
value is retained on this pin when it is inactive.
2.2.37 sden1/pio23 – sden0/pio22 —Serial Data Enables (synchronous outputs with
tristate)
The sden1–sden0 pins facilitate the transfer of data on ports 1 and 0 of the Synchronous Serial
Interface (SSI). Either sden1 or sden0 is asserted by the microcontroller at the start of the data
transfer and is de-asserted when the transfer is completed. These pins are held low by the
microcontroller when they are inactive.
2.2.38 srdy/pio6—Synchronous Ready (synchronous level-sensitive input)
This signal is an active high input synchronized to clkouta and indicates to the microcontroller
that a data transfer will be completed by the addressed memory space or I/O device.
In contrast to the Asynchronous Ready (ardy), which requires internal synchronization, srdy
permits easier system timing because it already synchronized. Tying srdy high will always assert
this ready condition. Tying it low will give control to ardy.
2.2.39 tmrin0/pio11—Timer Input 0 (synchronous edge-sensitive input)
This signal may be either a clock or control signal for the internal Timer 0. The timer is
incremented by the microcontroller after it synchronizes a rising edge of tmrin0. When not used,
tmrin0 must be tied high, or when used as pio11, it is pulled up internally.
2.2.40 tmrin1/pio0—Timer Input 1 (synchronous edge-sensitive input)
This signal may be either a clock or control signal for the internal Timer 1. The timer is
incremented by the microcontroller after it synchronizes a rising edge of tmrin1. When not used,
tmrin1 must be tied high, or when used as pio0, it is pulled up internally.
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2.2.41 tmrout0/pio10—Timer Output 0 (synchronous output)
This signal provides the system with a single pulse or a continuous waveform with a
programmable duty cycle. It is tristated during a bus hold or reset.
2.2.42 tmrout1/pio1—Timer Output 1 (synchronous output)
This signal provides the system with a single pulse or a continuous waveform with a
programmable duty cycle. It is tristated during a bus hold or reset.
2.2.43 txd/pio27—Transmit Data (asynchronous output)
This pin provides the system with asynchronous serial transmit data from the serial port.
2.2.44 ucs_n/once1_n—Upper Memory Chip Select (synchronous output)/ONCE Mode
Request 1 (input with internal pull-up)
The ucs_n pin provides an indication that a memory access is in progress to the upper memory
block. The size of the Upper Memory Block and its base address are programmable, with the
size adjustable up to 512 Kbytes. The ucs_n pin is held high during bus hold.
After power-on-reset, ucs_n is asserted low and program execution begins at FFFF0h. Its default
configuration is a 64-Kbyte memory range from F0000h to FFFFFh.
The once0_n pin (ONCE – ON Circuit Emulation) and its companion pin, once1_n, define the
microcontroller mode during reset. These two pins are sampled on the rising edge of res_n and if
both are asserted low the microcontroller starts in ONCE mode, else it starts normally. In ONCE
mode, all pins are tristated and remain so until a subsequent reset. To prevent the
microcontroller from entering ONCE mode inadvertently, this pin has a weak pull-up that is only
present during reset. This pin is not tristated during bus hold.
2.2.45 uzi_n/clksel2_n/pio26—Upper Zero Indicate (synchronous output)/clock select 2
(input, pullup)
This pin allows the designer to determine if an access to the interrupt vector table is in progress
by ORing it with Bits [15–10] of the address and data bus (ad15–ad10 on the IA186ER and
ao15–ao10 on the IA188ER). The uzi_n is the logical OR of the inverted a19–a16 bits. It asserts
in the first period of a bus cycle and is held throughout the cycle.
clksel2_n is combined with s6/clksel1_n/pio29 to select clock mode. If low, part enters clock
mode x1. Default, because of pull-ups, is for x4 clock mode. This is sampled on the rise of reset.
2.2.46 vcc—Power Supply (input)
These pins supply power (+3.3V +10%) to the microcontroller.
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2.2.47 whb_n (IA186ER)—Write High Byte (synchronous output with tristate)
The whb_n and wlb_n pins indicate to the system which bytes of the data bus (upper, lower, or
both) are taking part in a write cycle. The whb_n is asserted with ad15–ad8 and is the logical
OR of bhe_n and wr_n. It is tristated during reset.
2.2.48 wlb_n/wb_n—Write Low Byte (IA186ER) (synchronous output with tristate)/Write
Byte (IA188ER) (synchronous output with tristate)
The wlb_n and whb_n pins indicate to the system which bytes of the data bus (upper, lower, or
both) are taking part in a write cycle. The wlb_n is asserted with ad7–ad0 and is the logical OR
of ad0 and wr_n. It is tristated during reset.
On the IA188ER microcontroller, wb_n provides an indication that a write to the bus is
occurring. It shares the same early timing as that of the non-multiplexed address bus, and is
associated with ad7–ad0. It is tristated during reset.
2.2.49 wr_n—Write Strobe (synchronous output)
The wr_n pin indicates to the system that the data currently on the bus is to be written to a
memory or I/O device. It is tristated during a bus hold or reset.
2.2.50 x1—Crystal Input (input)
The x1 and x2 pins are the connections for a fundamental-mode, parallel-resonant crystal used
by the internal oscillator circuit. An external clock source for the microcontroller is connected to
x1. The x2 pin is left unconnected.
2.2.51 x2—Crystal Input (input)
The x1 and x2 pins are the connections for a fundamental-mode, parallel-resonant crystal used
by the internal oscillator circuit. An external clock source for the microcontroller is connected to
x1. The x2 pin is left unconnected.
2.3
Pins Used by Emulators
The following pins are used by emulators:
a19–a0
ao15–ao8 (on the IA188ER)
ad7–ad0
ale
bhe_n/aden_n (on the IA186ER)
clkouta
rfsh2_n/aden_n (on the IA188ER)
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rd_n
s2_n–s0_n
s6/clksel1_n
uzi_n/clksel2_n
Emulators require that s6/clksel1_n and uzi_n/clksel2_n be configured as their normal functions
(i.e., as s6 and uzi_n, respectively). Holding bhe_n/aden_n (IA186ER) or rfsh_n/aden_n
(IA188ER) low during the rising edge of res_n, will cause s6 and uzi_n to be configured in their
normal functions at reset instead of PIOs.
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3.
Data Sheet
February 25, 2013
Maximum Ratings, Thermal Characteristics, and DC Parameters
The absolute maximum ratings, thermal characteristics, and DC parameters are provided in
Tables 11 through 13, respectively.
Table 11. IA186ER and IA188ER Absolute Maximum Ratings
Parameter
Storage Temperature
Voltage on any Pin with Respect to vss
Rating
−40°C to +150°C
−0.3V to +(vcc + 0.3) V
Table 12. IA186ER and IA188ER Thermal Characteristics
Symbol
TA
Characteristic
Ambient Temperature
Value
-40°C to 85°C
Table 13. DC Characteristics Over Industrial Operating Ranges
Symbol
VCC
VIL
VIL1
VIH
VOL
VOH
ICC
Parameter Description
Supply Voltage (@ 3.3V Operation)
Input Low Voltage
Clock Input Low Voltage
Input High Voltage
Output Low Voltages
Output High Voltages
Power Supply Current @ 0 C
ILI
ILO
Input Leakage Current
Output Leakage Current
Test Conditions
–
–
–
–
IOL = 2 - 2.4 mA
IOH = −2.4 mA @ 2.4 V
vcc = 3.3 V
–
–
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Min
3.0
−
−
2.0
–
2.4
–
Max
3.6
0.8
0.8
vcc +2.2
0.40
vcc +0.5
5.9
–
–
10
10
Unit
V
V
V
V
V
V
mA/
MHz
A
A
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4.
Data Sheet
February 25, 2013
Device Architecture
A functional block diagram of the IA186ER/IA188ER is shown in Figure 7. This
microcontroller consists of the following functional blocks.
Bus Interface and Control (BIC)
32 Kbytes RAM
Peripheral Control and Registers
Chip Selects and Control (CSC)
Programmable I/O
Clock and Power Management
DMA
Interrupt Controller
Timers
Asynchronous Serial Port
Synchronous Serial Interface
Watchdog Timer
Instruction Decode and Execution
4.1
Bus Interface and Control
BIC manages all accesses to external memory, external peripherals and the internal 32 Kbyte
RAM. These peripherals may be mapped either in memory space or I/O space. The BIC
supports both multiplexed and non-multiplexed bus operations. Multiplexed address and data
are provided on the ad15–ad0 bus, while a non-multiplexed address is provided on the a19–a0
bus. The a bus provides address information for the entire bus cycle (t1–t4), while the ad bus
provides address information only during the first phase of the bus cycle (t1). For more details
regarding bus cycles, see the AC waveforms at the end of this datasheet.
The IA186ER microcontroller provides two signals that serve as byte write enables, write high
byte (whb_n) and write low byte (wlb_n). The IA188ER microcontroller requires only a single
write byte (wb_n) signal to support its 8-bit data bus. The whb_n is the logical OR of the bhe_n
and wr_n. The wlb_n is the logical OR of ad0 and wr_n. The wb_n is low whenever a byte is
written to the IA188ER data bus ad7–ad0.
The byte write enables are driven in conjunction with the non-multiplexed address bus a19–a0 to
support the timing requirements of common SRAMs.
The BIC also provides support for PSRAM devices. PSRAM is supported in only the lower chip
select (lcs_n) area. In order to support PSRAM, the CSC must be appropriately programmed
(see Section 4.7, Chip Selects).
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vcc
Watchdog
Timer
a[19:0]
ad[15:0]
ale
den_n
wr_n
wlb_n
whb_n
rd_n
Bus Interface
And Control
gnd
Data Sheet
February 25, 2013
uzi_n/clksel2_n
s6/clksel1_n
hold
hlda
srdy
den_n
ardy
dt/r_n
s2_n
s1_n/imdis_n
s0_n/sren_n
IA186ER/IA188ER
16-Bit/8-Bit Microcontrollers with RAM
Clock and
Power
Management
Direct Memory
Access
32 Kbytes
RAM
Interrupt
Controller
(
Peripheral Control
and Registers
)
clkouta
clkoutb
drq0
drq1
int4
int3/inta1_n/irq
int2/inta0_n
int1/select_n
int0
nmi
tmrin0
Timers
tmrout0
lcs_n/once0_n
tmrin1
mcs3_n/rfsh_n
tmrout1
ucs_n/once1_n
pcs5_n/a1
pcs6_n/a2
Chip Selects and
Control
Asynchronous
Serial Port
mcs2_n–mcs0_n
pcs3_n–pcs0_n
txd0
rxd0
sclk
pio[31:0]
Synchronous
Serial Port
Programmable I/O
sden0
sden1
sdata
res_n
Instruction
Decode and
Execution
Figure 7. Functional Block Diagram
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4.2
Data Sheet
February 25, 2013
Clock and Power Management
A phase-lock-loop (PLL) and a second programmable system clock output (clkoutb) are included
in the clock and power management unit. See Figure 8.
C1
x1
IA186ER/
IA188ER
C2
x2
Crystal
Recommended
range of values for
C1 and C2 are:
C1 = 15 pF ±20%
C2 = 22 pF ±20%
Figure 8. Crystal Configuration
4.3
System Clocks
If required, the internal oscillator can be driven by an external clock source that should be
connected to x1, leaving x2 unconnected.
The clock outputs clkouta and clkoutb may be enabled or disabled individually (Power-Save
Control register (PDCON) Bits [11–8]). These clock control bits allow one clock output to run
at the internal system frequency and the other to run at the power-save frequency (see Figure 9).
Figure 9. Organization of Clock
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4.4
Data Sheet
February 25, 2013
Power-Save Mode
The CPU and peripherals operate at a slower clock frequency when in power save mode,
reducing power consumption and thermal dissipation. Should an interrupt occur, the
microcontroller returns to its normal operating frequency automatically on the internal clock’s
next rising edge in t3. Any clock-dependent devices should be reprogrammed for the change in
frequency during the power-save mode period.
4.5
Initialization and Reset
res_n (Reset) must be held low for 1 mS during power-up to initialize the microcontroller
correctly. This operation makes the device cease all instruction execution and local bus activity.
The microcontroller begins instruction execution at physical address FFFF0h when res_n
becomes inactive and after an internal processing interval with ucs_n is asserted and three wait
states. Reset also sets up certain registers to predetermined values and resets the Watchdog
timer.
4.6
Reset Configuration Register
The data on the address/data bus (ad15–ad0 for the IA186ER, ao15–ao8 and ad7–ad0 for the
IA188ER) are written into the Reset Configuration register when reset is low. This data is held
in the Reset Configuration register after Reset is de-asserted. This configuration data may be
placed on the address/data bus by using weak external pull-up and pull-down resistors or applied
to the bus by an external driver, as the processor does not drive the bus during reset. It is a
method of supplying the software with some initial data after a reset; for example, option jumper
positions.
4.7
Chip Selects
Chip-select generation is programmable for memories and peripherals. Programming is also
available to produce ready- and wait-state generation plus latched address bits a1 and a2. For all
memory and I/O cycles, the chip-select lines are active within their programmed areas,
regardless of whether they are generated by the internal DMA unit or the CPU.
There are six chip-select outputs for memories and a further six for peripherals whether in
memory or I/O space. The memory chip-selects are able to address three memory ranges,
whereas the peripheral chip-selects are used to address 256-byte blocks that are offset from a
programmable base address. Writing to a chip-select register enables the related logic even if the
pin in question has another function (e.g., if the pin is programmed to be a PIO). In addition,
there is a chip-select for the internal memory.
4.8
Chip - Select Timing
For normal timing, the ucs_n and lcs_n outputs are asserted with the non-multiplexed address
bus. The other chip selects assert with the multiplexed address/databus.
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4.9
Data Sheet
February 25, 2013
Ready- and Wait-State Programming
Each of the memory or peripheral chip-select lines can require a ready signal that can be the ardy
or srdy signal. The chip-select control registers (UMCS, LMCS, MMCS, PACS, and MPCS)
each have a single bit that selects whether the external ready signal is to be used or not (R2, Bit
[2]). R1 and R0 (Bits [1–0]) in these registers control the number of wait states that are inserted
during each access to a memory or peripheral location (from 0 to 3). The control registers for
pcs3_n–pcs0_n use three bits, R3, R1–R0 (Bits [3], [1–0]) to provide 5, 7, 9, and 15 wait-states
in addition to the original values of 0 to 3 wait states.
In the case where an external ready has been selected as required, internally programmed waitstates will always be completed before the external ready can finish or extend a bus cycle. As an
example, consider a system in which the number of wait states to be inserted has been set to 3.
The external ready pin is sampled by the processor during the first wait cycle. The access is
completed after 7 cycles (4 cycles plus 3 wait cycles) if the ready is asserted. Alternatively, if
the ready is not asserted during the first wait cycle, the access is prolonged until ready is asserted
and two more wait states are inserted followed by t4.
4.10
Chip Select Overlap
Overlapping chip selects are configurations where more than one chip select is asserted for the
same physical address. For example, if PCS is configured in I/O space with LCS or any other
chip select configured for memory, address 00000h is not overlapping the chip selects.
Note: It is not recommended that multiple chip-select signals be asserted for
the same physical address, although it may be inescapable in certain
systems. If this is the case, then all overlapping chip-selects must have the
same external ready configuration and the same number of wait states to be
inserted into access cycles.
Internal signals are employed to access the peripheral control block (PCB) and these signals
serve as chip selects that are configured with no wait states and no external ready. Therefore, the
PCB can be programmed with addresses that overlap external chip selects only if these chip
selects are configured in the same manner.
Note: Caution is advised in the use of the DA bit in the LMCS or UMCS
registers when overlapping an additional chip select with either the lcs_n or
ucs_n. Setting the DA bit to 1 prevents the address from being driven onto
the AD bus for all accesses for which the respective chip select is active,
including those for which multiple selects are active.
The mcs_n and pcs_n pins are dual-purpose pins, either as chip selects or PIO inputs or outputs.
However, the respective ready- and wait-state configurations for their chip-select function will
be in effect regardless of the function for which these pins are programmed. This requires that
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even if these pins are configured as PIO and enabled (by writing to the MMCS and MPCS
registers for the mcs_n chip selects and to the PACS and MPCS registers for the pcs_n chip
selects), the ready- and wait-state settings for them must agree with those for any overlapping
chip selects as though they were configured as chip selects.
Although pcs4_n is not available as an external pin, it has ready- and wait-state logic and must
follow the rules for overlapping chip-selects. Conversely, pins pcs6_n and pcs5_n have readyand wait-state logic that is disabled when configured as address bits a2 and a1, respectively.
Note: If chip-select configuration rules are not followed, the processor may
hang with the appearance of waiting for a ready signal even in a system
where ready (ardy or srdy) is always set to 1.
4.11
Upper Memory Chip Select
The ucs_n chip select is for the top of memory. On reset, the microcontroller begins fetching
and executing instructions at memory location FFFF0h. As a result, upper memory is usually
used for instruction memory. To this end, ucs_n is active on reset and has a memory range of
64 Kbytes (F0000h to FFFFFh) by default, along with external ready required and 3 wait states
automatically inserted. The lower boundary of ucs_n is programmable to provide ranges of 64 to
512 Kbytes.
4.12
Low Memory Chip Select
The lcs_n chip-select is for lower memory. As the interrupt vector table is at the bottom of
memory beginning at 00000h, this pin us usually used for control data memory. Unlike ucs_n,
this pin is inactive on reset, but can be activated by any read or write to the LMCS register.
4.13
Midrange Memory Chip Selects
There are four midrange chip selects, mcs3_n–mcs0_n, which may be used in a user-located
memory block. With some exceptions, the base address of the memory block may be located
anywhere in the 1-Mbyte memory address space (those used by the ucs_n and lcs_n chip selects,
as well as the pcs6_n, pcs5_n, and pcs3_n–pcs0_n, are excluded). If the pcs_n chip selects are
mapped to I/O space, then the MCS address range can overlap the PCS address range.
Both the Midrange Memory Chip Select (MMCS) register and the MCS and PCS auxiliary
(MPCS) registers are used to program the four midrange chip selects. The MPCS register is used
to configure the block size, whereas the MMCS register configures the base address, the ready
condition, and the wait states of the memory block accessed by the mcs_n pin. The chip selects
(mcs3_n–mcs0_n) are activated by performing a write operation of the MMCS and MPCS
registers. The assertion of the MCS outputs occurs with the same timing as the multiplexed AD
address bus (ad15–ad0 on the IA186ER or ao15–ao8 and ad7–ad0 on the IA188ER). The a19–
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a0 may be used for address selection, but the timing will be delayed by a half clock cycle over
the timing used for the ucs_n and lcs_n.
4.14
Peripheral Chip Selects
There are six peripheral chip selects (pcs6_n, pcs5_n, and pcs3_n–pcs0_n) that may be used
within a user-defined memory or I/O block. The base address of this user-defined memory block
can be located anywhere within the 1-Mbyte memory address space except for the spaces
associated with the ucs_n, lcs_n, and mcs_n chip selects. Or it may be programmed to the
64 Kbyte I/O space. The pcs4_n pin is not available.
Both the Peripheral Chip Select (PACS) register and the MCS and PCS Auxiliary register
(MPCS) registers are used to program the six peripheral chip selects pcs6_n, pcs5_n, and
pcs3_n–pcs0_n. The PACS register sets the base address, the ready condition, and the wait
states for the pcs3_n–pcs0_n outputs.
The MPCS register configures pcs6_n and pcs5_n pins as either chip selects or address pins a1
and a2, respectively. When these pins are chip selects, the MPCS register also configures them
as being active during memory or I/O bus cycles and their ready condition and wait states.
None of the pcs_n pins are active at reset. Both the Peripheral Chip Select (PACS) register and
the MCS and PCS Auxiliary register (MPCS) registers must be read or written to activate the
pcs_n pins as chip selects.
The pcs6_n and pcs5_n may be programmed to have 0 to 3 wait states, whereas pcs3_n–pcs0_n
may be programmed to have these and 5, 7, 9, or 15 wait states.
4.15
Refresh Control
The Refresh Control Unit (RCU) generates refresh bus cycles. The RCU generates a memory
read request after a programmable period of time to the bus interface unit.
The ENA bit in the Enable RCU register (EDRAM) enables refresh cycles, operating off the
processor internal clock. If the processor is in power-save mode, the RCU must be reconfigured
for the new clock rate.
If the hlda pin is asserted when a refresh request is initiated (indicating a bus hold condition), the
processor disables the hlda pin to allow a refresh cycle to be performed. The external circuit bus
master must deassert the hold signal for at least one clock period to permit the execution of the
refresh cycle.
4.16
Interrupt Control
Interrupt requests originate from a variety of internal and external sources that are arranged by
the internal interrupt controller in priority order and presented one by one to the processor.
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Six external interrupt sources—five maskable (int4–int0) and one nonmaskable (NMI)—are
connected to the processor and six internal interrupt sources (three timers, two DMA channels,
and the asynchronous serial port that are not brought out to external pins).
The five external maskable interrupt request pins can be used as direct interrupt requests.
However, should more interrupts be needed, int3–int0 may be used with the 82C59A-compatible
external interrupt controller. By programming the internal interrupt controller to slave mode, an
82C59A-compatible external interrupt controller can be used as the system master. Interrupt
nesting can be used in all cases that permit interrupts of a higher priority to interrupt those of a
lower priority.
When an interrupt is accepted, other interrupts are disabled, but may be re-enabled by setting the
Interrupt Enable Flag (IF) in the Processor Status Flags register during the Interrupt Service
Routine (ISR). Setting IF permits interrupts of equal or greater priority to interrupt the currently
running ISR.
Further interrupts from the same source will be blocked until the corresponding bit in the
In-Service register (INSERV) is cleared. Special Fully Nested mode (SFNM) is invoked for int0
and int1 by the SFNM bit in the INT0 and INT1 control register, respectively, when this bit is set
to 1. In this mode, a new interrupt may be generated by these sources regardless of the in-service
bit. The following table shows the priorities of the interrupts at POR.
4.16.1 Interrupt Types
Table 14 presents interrupt names, types, vector table address, End-of-Interrupt (EOI) type,
overall priority, and related instructions.
Table 14. Interrupt Types
Interrupt
Type
00h
01h
02h
03h
04h
05h
06h
Vector Table
Address
00h
04h
08h
0ch
10h
14h
18h
EOI Type
NA
NA
NA
NA
NA
NA
NA
Overall
Priority
1
1A
1B
1
1
1
1
ESC Opcode Exceptiona,c
07h
1ch
NA
1
Timer 0 Interruptd,e
Timer 1 Interruptd,e
Timer 2 Interruptd,e
08h
12h
13h
20h
48h
4ch
08h
08h
08h
2A
2B
2C
Interrupt Name
Divide Error Exceptiona
Trace Interruptb
Non-maskable Interrupt (NMI)
Breakpoint Interrupta
INT0 Detected Overflow Exceptiona
Array Bounds Exceptiona
Unused Opcode Exceptiona
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Related
Instructions
DIV, IDIV
All
–
INT3
INT0
BOUND
Undefined
Opcodes
ESC
Opcodes
–
–
–
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Reserved
DMA 0 Interrupte
DMA 1 Interrupte
INT0 Interrupt
INT1 Interrupt
INT2 Interrupt
INT3 Interrupt
INT4 Interruptf
Watchdog Timer Interruptf
Asynchronous Serial Port Interruptf
Reserved
Data Sheet
February 25, 2013
09h
0ah
0bh
0ch
0dh
0eh
0fh
10h
11h
14h
15h–1fh
28h
2ch
30h
34h
38h
3ch
40h
44h
50h
54h–7ch
–
0ah
0bh
0ch
0dh
0eh
0fh
10h
11h
14h
–
–
3
4
5
6
7
8
9
9
9
–
–
–
–
–
–
–
–
–
–
–
–
Note: If the priority levels are not changed, the default priority level will be used for the interrupt sources.
aInstruction execution generates interrupts.
bPerformed in the same manner as for the 8086 and 8088.
cAn ESC opcode causes a trap.
dBecause only one IRQ is generated for the three timers, they share priority level with respect to other
sources. The timers have an interrupt priority order among themselves (2A > 2B > 2C).
eThese interrupt types are programmable in slave mode.
fNot available in slave mode.
4.17
Timer Control
The IA186ER and IA188ER each have three 16-bit programmable timers. Timer 0 and Timer 1
each has an input and output connected to external pins that permits it to count or to time events
as well as to produce variable duty-cycle waveforms or non-repetitive waveforms. Timer 1 can
also be configured as a Watchdog timer.
Because Timer 2 does not have external connections, it is confined to internal functions such as
real-time coding, time-delay applications, a prescaler for Timer 0 and Timer 1, or to synchronize
DMA transfers.
The Peripheral Control Block contains eleven 16-bit registers to control the programmable
timers. Each timer-count register holds the present value of its associated timer and may be read
from or written to whether or not the timer is in operation. The microcontroller increments the
value of the timer-count register when a timer event takes place.
The value stored in a timer’s associated maximum count register determines its maximum count
value. Upon reaching it, the timer count register is reset to 0 in the same clock cycle that this
count was attained. The timer count register does not store this maximum value. Both Timer 0
and Timer 1 have a primary and a secondary maximum count register that permits each to
alternate between two discrete maximum values.
Timer 0 and Timer 1 may have the maximum count registers configured in either primary only or
both primary and secondary. If the primary only is configured to operate, on reaching the
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maximum count, the output pin will go low for one clock period. If both the primary and
secondary registers are enabled, the output pin reflects the state of the register in control at the
time. This generates the required waveform that is dependent on the two values in the maximum
count registers.
Because they are polled every fourth clock period, the timers can operate at a quarter of the
internal clock frequency. Although an external clock may be used, the timer output may take six
clock cycles to respond to the input.
4.18
Direct Memory Access (DMA)
DMA frees the CPU from involvement in transferring data between memory and peripherals
over either one or both high-speed DMA channels. Data may be transferred from memory to
I/O, I/O to memory, memory to memory, or I/O to I/O. DMA channels can be connected to the
asynchronous serial port.
The IA186ER supports the transfer of both bytes and words to and from even or odd addresses.
It does not support word transfers to memory that is configured for byte accesses. The IA188ER
does not support word transfers at all. Each data transfer will take two bus cycles (a minimum of
8 clock cycles).
There are four sources of DMA requests for both DMA channels:
The channel request pin (drq1–drq0)
Timer 2
The system software
Asynchronous serial port
Each channel may be programmed to have a different priority either to resolve a simultaneous
DMA request or to interrupt a transfer on the other channel.
4.19
DMA Operation
The PCB contains six registers for each DMA channel to control and specify the operation of the
channel:
Two registers to store a 20-bit source address
Two registers to store a 20-bit destination address
One 16-bit transfer-count register
One 16-bit control register
The number of DMA transfers required is designated in the DMA Transfer Count register and
may contain up to 64 Kbytes or words. It will end automatically. DMA channel function is
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defined by the control registers. Like the other five registers, these may be changed at any time
(including during a DMA transfer) and are implemented immediately.
4.20
DMA Channel Control Registers
See Section 5.1.9, D1CON (0dah) and D0CON (0cah). The DMA channel control registers
specify the following:
Whether the data destination is in memory or I/O space (Bit [15])
Whether the destination address is incremented, decremented, or unchanged after each
transfer (Bits [14–13])
Whether the data source is in memory or I/O space (Bit [12])
Whether the source address is incremented, decremented, or unchanged after each
transfer (Bits [11–10])
Whether DMA transfers cease upon reaching a designated count (Bit [9])
Whether the last transfer generates an interrupt (Bit [8])
Synchronization mode (Bits [7–6])
The relative priority of one DMA channel with respect to the other (Bit [5])
Acceptance of DMA requests from Timer 2 (Bit [4])
Byte or Word transfers (Bit [0])
4.21
DMA Priority
With the exception of word accesses to odd memory locations or between locked memory
addresses, DMA transfers have a higher priority than CPU transfers. Because the CPU cannot
access memory during a DMA transfer and a DMA transfer cannot be suspended by an interrupt
request, continuous DMA activity will increase interrupt delay. An NMI request halts any DMA
activity, however, enabling the CPU to respond promptly to the request.
4.22
Asynchronous Serial Port
The asynchronous serial port employs standard industry communication protocols in its
implementation of full duplex, bi-directional data transfers. The port can be either the source or
destination of DMA transfers.
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The following features are supported:
Full-duplex data transfers
7- or 8-bit data transfers
Odd, even, or no parity
One or two stop bits
Error detection provided by parity, framing, or overrun errors
DMA to and from the port
The port has its own maskable interrupt
The port has an independent baud-rate generator
Maximum baud rate is 1/32 of the processor clock
Transmit and receive lines are double-buffered
In power-save mode the baud rate generator divide factor must be re-programmed to compensate
for the change in clock rate.
4.23
Synchronous Serial Port
The synchronous serial port allows the microcontrollers to communicate with ASICs that are
required to be programmed but have a pin shortage. The four-pin interface allows half-duplex,
bi-directional data transfer at a maximum of 25 Mbits/sec.
The synchronous serial interface of the IA186ER/ IA188ER operates as the master port in a
master/slave arrangement.
There are four pins in the synchronous serial interface for communication with the system
elements. These pins are two enables (SDEN0 and SDEN1), a clock (SCLK), and a data pin
(SDATA).
In power-save mode, the baud rate generator divide factor must be re-programmed to
compensate for the change in clock rate.
4.24
Programmable I/O (PIO)
Thirty-two pins are programmable as I/O signals (PIO). Table 15 presents them in both numeric
and alphabetic order. Because programming a pin as a PIO disables its normal function, it
should be done only if the normal function is not required. A PIO pin can be programmed as an
input or output with or without a weak pull-up or pull-down. A PIO pin can be also programmed
as an open-drain output. Each PIO pin regains default status after a POR.
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Table 15. Default Status of PIO Pins at Reset
PIO No.
0
1
2
3
4
5
6
7b
8b
9b
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26b,c
27
28
29b,c
30
31
Associated Pin
tmrin1
tmrout1
pcs6_n/a2
pcs5_n/a1
dt/r_n
den_n
srdy
a17
a18
a19
tmrout0
tmrin0
drq0
drq1
mcs0_n
mcs1_n
pcs0_n
pcs1_n
pcs2_n
pcs3_n
sclk
sdata
sden0
sden1
mcs2_n
mcs3_n/rfsh_n
uzi_n/clksel2_n
txd/pio27
rxd/pio28
s6/clksel1_n
int4
int2
Power-On
Reset Status
Input with pull-up
Input with pull-down
Input with pull-up
Input with pull-up
Normal operationa
Normal operationa
Normal operationa
Normal operationa
Normal operationa
Normal operationa
Input with pull-down
Input with pull-up
Input with pull-up
Input with pull-up
Input with pull-up
Input with pull-up
Input with pull-up
Input with pull-up
Input with pull-up
Input with pull-up
Input with pull-up
Input with pull-up
Input with pull-down
Input with pull-down
Input with pull-up
Input with pull-up
Input with pull-up
Input with pull-up
Input with pull-up
Input with pull-up
Input with pull-up
Input with pull-up
Associated Pin
a17
a18
a19
den_n
drq0
drq1
dt/r_n
int2
int4
mcs0_n
mcs1_n
mcs2_n
mcs3_n/rfsh_n
pcs0_n
pcs1_n
pcs2_n
pcs3_n
pcs5_n/a1
pcs6_n/a2
rxd/pio28
s6/clksel1_n
sclk
sdata
sden0
sden1
srdy
tmrin0
tmrin1
tmrout0
tmrout1
txd/pio27
uzi_n/clksel2_n
PIO No.
7
8
9
5
12
13
4
31
30
14
15
24
25
16
17
18
19
3
2
28
29
20
21
22
23
6
11
0
10
1
27
26
Power-On
Reset Status
Normal operationa
Normal operationa
Normal operationa
Normal operationa
Input with pull-up
Input with pull-up
Normal operationa
Input with pull-up
Input with pull-up
Input with pull-up
Input with pull-up
Input with pull-up
Input with pull-up
Input with pull-up
Input with pull-up
Input with pull-up
Input with pull-up
Input with pull-up
Input with pull-up
Input with pull-up
Input with pull-upb,c
Input with pull-up
Input with pull-up
Input with pull-down
Input with pull-down
Normal operationd
Input with pull-up
Input with pull-up
Input with pull-down
Input with pull-down
Input with pull-up
Input with pull-up
aInput with pullup option available when used as PIO.
bEmulators use these pins and also a15–a0, ad15–ad0 (IA186ER), ale, bhe_n (IA186ER), clkouta, nmi, res_n,
and s2_n–s0_n.
cIf bhe_n/aden_n (IA186ER) or rfsh_n/aden_n (IA188ER) is held low during POR, these pins will revert to normal
operation.
dInput with pulldown option available when used as PIO.
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These default status settings may be changed as desired.
After POR, a19–a17, the three most significant bits of the address bus, start with their normal
function, allowing the processor to begin fetching instructions from the boot address FFFF0h.
Normal function is also the default setting for dt/r_n, den_n, and srdy after POR.
If the ad15–ad0 bus override is enabled, s6/clksel1_n and uzi_n/clksel2_n automatically return to
normal operation. The ad15–ad0 bus override is enabled if either the bhe_n/aden_n for the
IA186ER or the rfsh2_n/aden_n for the IA188ER is held low during POR.
4.25
Watchdog Timer
The WDT operates in real WDT fashion and may be used to prevent loss of control in the event
that software does not respond in an expected manner. The WDT is active after reset, has a
maximum timeout count, and is programmed for system reset mode. The WDT control register
(WDTCON) may be written to only once after reset. This is accomplished by writing 3333h,
then CCCCh followed by the new configuration data to the WDTCON register. Provided they
do not include access to the WDTCON register, any number of operations may be performed
between these two words, including memory and I/O reads and writes.
Writing AAAAh then 5555h to the WDTCON register resets the current count. This count
cannot be read. Provided they do not include access to the WDTCON register, any number of
operations may be performed between these two words, including memory and I/O reads and
writes. Use of these sequences is intended to prevent executing code from blocking a WDT
event. With the WDT, a maximum 1.34-second timeout period is possible in a 50-MHz system.
The WDT can be programmed to generate either an NMI or a system reset when it times out. If
programmed to generate an NMI, the NMIFLAG (Bit [12]) in the WDTCON register will be set
when it occurs. This flag should be tested by the NMI interrupt service routine (ISR) to establish
whether the WDT or an external source generated the interrupt. If set by writing the 3333h and
CCCCh sequence followed by the configuration data that includes clearing NMIFLAG, the ISR
should clear this flag. If the NMIFLAG is set while a second WDT timeout occurs, a WDT
system reset is generated in place of a second NMI interrupt.
The RSTFLAG (Bit [13]) in the WDTCON register is set if a WDT reset is generated, due to one
WDT occurrence while the WDT is programmed to generate resets, or because a WDT event
occurred with the NMIFLAG set. This permits system initialization code to distinguish between
a WDT reset and hardware reset and take appropriate action. The RSTFLAG is cleared by a read
or write to the WDTCON register. During a WDT reset, the external pins are not re-sampled,
ensuring that clocking, reset configuration register, and any other features that are user
programmable during reset do not change when a WDT system reset occurs. All other activities
are the same as those of a normal system reset.
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4.26
Data Sheet
February 25, 2013
Internal Memory
Integrated 32 Kbyte of internal RAM provides the same performance as zero wait state external
memory. This memory is configured with an internal chip select register.
5.
Peripheral Architecture
5.1
Control and Registers
The on-chip peripherals in the IA186ER/IA188ER are controlled from a 256-byte block of
internal registers. Although these registers are actually located in the peripherals they control,
they are addressed within a single 256-byte block of I/O space and are treated as a functional
unit. A list of these registers is presented in Table 16.
Write operations performed on the IA188ER should be 8-bit writes, resulting in 16-bit data
transfers to the Peripheral Control Block (PCB) register. Only word reads should be performed
to the PCB registers. If unaligned read and write accesses are performed on either the IA186ER
or IA188ER, indeterminate behavior may result.
Note: Adhere to these instructions while writing code to avoid errors.
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Table 16. Peripheral Control Registers
Register Name
Offset
Peripheral Control Block Registers
PCB Relocation Register
FEh
Reset Configuration Register
F6h
Processor Release Level Register
F4h
Power-Save Control Register
F0h
Watchdog Timer
E6h
Enable RCU Register
E4h
Clock Prescaler Register
E2h
Memory Partition Register
E0h
DMA Registers
DMA1 Control Register
DAh
DMA1 Transfer Count Register
D8h
DMA1 Destination Address High Register D6h
DMA1 Destination Address Low Register D4h
DMA1 Source Address High Register
D2h
DMA1 Source Address Low Register
D0h
DMA0 Control Register
CAh
DMA0 Transfer Count Register
C8h
DMA0 Destination Address High Register C6h
DMA0 Destination Address Low Register C4h
DMA0 Source Address High Register
C2h
DMA0 Source Address Low Register
C0h
Chip-Select Registers
Internal Memory Chip Select Register
ACh
pcs_n and mcs_n Auxiliary Register
A8h
Mid-Range Memory Chip-Select Register A6h
Peripheral Chip-Select Register
A4h
Low-Memory Chip-Select Register
A2h
Upper-Memory Chip-Select Register
A0h
Asynchronous Serial Port Register
Serial Port Baud Rate Divisor Register
88h
Serial Port Receive Register
86h
Serial Port Transmit Register
84h
Serial Port Status Register
82h
Serial Port Control Register
80h
PIO Registers
PIO Data 1 Register
7Ah
PIO Direction 1 Register
78h
PIO Mode 1 Register
76h
PIO Data 0 Register
74h
PIO Direction 0 Register
72h
PIO Mode 0 Register
70h
Register Name
Timer Registers
Timer 2 Mode and Control Register
Timer 2 Max Count Compare A Register
Timer 2 Count Register
Timer 1 Mode and Control Register
Offset
Timer 1 Max Count Compare B Register
Timer 1 Max Count Compare A Register
Timer 1 Count Register
Timer 0 Mode and Control Register
Timer 0 Max Count Compare B Register
Timer 0 Max Count Compare A Register
Timer 0 Count Register
Interrupt Registers
Serial Port Interrupt Control Register
Watchdog Timer Control Register
INT4 Interrupt Control Register
INT3 Interrupt Control Register
INT2 Interrupt Control Register
INT1 Interrupt Control Register
INT0 Interrupt Control Register
DMA1 Interrupt Control Register
DMA0 Interrupt Control Register
5Ch
5Ah
58h
56h
54h
52h
50h
Timer Interrupt Control Register
Interrupt Status Register
Interrupt Request Register
Interrupt In-Service Register
Interrupt Priority Mask Register
Interrupt Mask Register
Interrupt Poll Status Register
Interrupt Poll Register
End-of-Interrupt (EOI) Register
Interrupt Vector Register
Serial Port 1 Registers
Synchronous Serial Receive Register
Synchronous Serial Transmit 0 Register
Synchronous Serial Transmit 1 Register
Synchronous Serial Enable Register
Synchronous Serial Status Register
32h
30h
2Eh
2Ch
2Ah
28h
26h
24h
22h
20h
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66h
62h
60h
5Eh
44h
42h
40h
3Eh
3Ch
3Ah
38h
36h
34h
18h
16h
14h
12h
10h
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5.1.1
Data Sheet
February 25, 2013
RELREG (0feh)
The Peripheral Control Block RELocation REGister maps the entire Peripheral Control Block
Register Bank to either I/O or memory space. In addition, RELREG contains a bit that places
the interrupt controller in either master or slave mode. The RELREG contains 20ffh at reset (see
Table 17).
Table 17. Peripheral Control Block Relocation Register
15
Reserved
14
S/Mn
13
Reserved
12
IO/Mn
11
10
9
8
7 6 5 4
RA19– RA8
3
2
1
0
Bit [15]—Reserved.
Bit [14]—S/Mn → When set to 1, this bit places the interrupt controller into slave mode.
When 0, it is in master mode.
Bit [13]—Reserved.
Bit [12]—IO/Mn → When set to 1, the Peripheral Control Block is mapped into memory
space. When 0, this bit maps the Peripheral Control Block Register Bank into IO space.
Bits [11–0]—RA19–RA8 → Sets the base address (upper 12 bits) of the Peripheral
Control Block Register Bank. RA7–RA0 default to 0. When Bit [12] (IO/Mn) is set to 1,
RA19–RA16 are ignored.
5.1.2
RESCON (0f6h)
The RESet CONfiguration Register latches user-defined information present at specified pins at
the rising edge of reset. The contents of this register are read-only and remain valid until the
next reset. The RESCON contains user-defined information at reset (see Table 18).
Table 18. Reset Configuration Register
15
14
13
12
11
10 9 8 7
RC15–RC0
6
5
4
3
2
1
0
Bits [15–0]—RC15–RC0 → At the rising edge of reset, the values of specified pins
(ad15–ad0 for the IA186ER and ao15–ao8 and ad7–ad0 for the IA188ER) are latched
into this register.
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5.1.3
Data Sheet
February 25, 2013
PRL (0f4h)
The Processor Release Level Register contains a code corresponding to the latest processor
production release. The PRL is a Read-Only Register. The PRL contains A800h for IA186ER
and A900h for IA188ER. See Table 19.
Table 19. Processor Release Level Register
15
14
13 12 11 10
PRL7–PRL0
9
8
7
6
5
4 3 2
Reserved
1
0
Bits [15–8]—PRL7–PRL0 → The latest Processor Release Level.
PRL Value
A8
A9
Processor
Release Level
186
188
Bits [7–0]—Reserved.
5.1.4
PDCON (0f0h)
The Power-save CONtrol Register controls several miscellaneous system I/O and timing
functions. The PDCON contains 0000h at reset (see Table 20).
Table 20. Power-Save Control Register
15
PSEN
14 13 12
Reserved
11
CBF
10
CBD
9
CAF
8
CAD
7
6 5 4
Reserved
3
2
F2
1
F1
0
F0
Bit [15]—PSEN → When set to 1, enables the power-save mode causing the internal
operating clock to be divided by the value in F2–F0. External interrupts or interrupts
from internal interrupts automatically clear PSEN. Software interrupts and exception do
not clear PSEN.
Note: The value of PSEN is not restored upon execution of an IRET
instruction.
Bits [14–12]—Reserved → These bits read back as 0.
Bit [11]—CBF → When set to 1, the clkoutb output follows the input crystal (PLL)
frequency. When 0, it follows the internal clock frequency after the clock divider.
Bit [10]—CBD → When set to 1, the clkoutb output is tri-stated. When 0, it is driven as
an output per the CBF bit.
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Bit [9]—CAF → When set to 1, the clkouta output follows the input crystal (PLL)
frequency. When 0, it follows the internal clock frequency after the clock divider.
Bit [8]—CAD → When set to 1, the clkouta output is tri-stated. When 0, it is driven as
an output per the CAF bit.
Bits [7–3]—Reserved → These bits read back as 0.
Bits [2–0]—F2–F0 → These bits control the clock divider as shown below.
Note: PSEN must be 1 for the clock divider to function.
F2
0
0
0
0
1
1
1
1
5.1.5
F1
0
0
1
1
0
0
1
1
F0
0
1
0
1
0
1
0
1
Divider Factor
0
Divide by 1 (2 )
1
Divide by 2 (2 )
2
Divide by 4 (2 )
3
Divide by 8 (2 )
4
Divide by 16 (2 )
5
Divide by 32 (2 )
6
Divide by 64 (2 )
7
Divide by 128 (2 )
WDTCON (0e6h)
The WatchDog Timer control Register provides control and status for the WDT. The WDTCON
contains c080h at reset (see Table 21).
Table 21. Watchdog Timer Control Register
15
ENA
14
WRST
13
RSTFLAG
12
NMIFLAG
11
TEST
10
9 8
RES
7
6
5
4 3 2
COUNT
1
0
Bit [15]—ENA → When set to 1, the WDT is enabled. When 0, it is disabled.
Bit [14]—WRST → When set to 1, an internal WDT reset is generated when the WDT
timeout count (COUNT) is reached. When 0, an NMI will be generated once WDT
timeout count is reached and the NMIFLAG bit is 0. If the NMIFLAG bit is 1, an
internal WDT reset is generated when the WDT timeout count is reached.
Bit [13]—RSTFLAG → When set to 1, a WDT timeout event has occurred. This bit may
be cleared by software or by an external reset.
Bit [12]—NMIFLAG → When set to 1, a WDT NMI event has occurred. This bit may
be cleared by software or by an external reset. If this bit is 1 when WDT timeout occurs,
an internal WDT reset is generated regardless of the state of WRST.
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Bit [11]—TEST → This bit is reserved for chip test and should be always set to 0.
Bits [10–8]—Reserved.
Bits [7–0]—COUNT → Control the timeout period for the WDT as follows:
Ttimeout = 2
exponent
/frequency
(Equation 1)
Where:
Ttimeout
frequency
exponent
Bit [7]
0
X
X
X
X
X
X
X
1
5.1.6
= The WDT timeout period in seconds.
= The processor frequency in hertz.
= Is based upon count as shown below:
Bit [6]
0
X
X
X
X
X
X
1
0
Bit [5]
0
X
X
X
X
X
1
0
0
Bit [4]
0
X
X
X
X
1
0
0
0
Bit [3]
0
X
X
X
1
0
0
0
0
Bit [2]
0
X
X
1
0
0
0
0
0
Bit [1]
0
X
1
0
0
0
0
0
0
Bit [0]
0
1
0
0
0
0
0
0
0
Exponent
NA
10
20
21
22
23
24
25
26
EDRAM (0e4h)
The Enable RCU Register provides control and status for the refresh counter. The EDRAM
register contains 0000h at reset (see Table 22).
Table 22. Enable Dynamic RAM Refresh Control Register
15
E
14
13
12 11
Reserved
10
9
8
7
6
5 4 3
T8–T0
2
1
0
Bit [15]—E → When set to 1, the refresh counter is enabled and mcs3_n is configured to
act as rfsh_n. Clearing E empties the refresh counter and disables refresh requests. The
refresh address is unaffected by clearing E.
Bits [14–9]—Reserved → These bits read back as 0.
Bits [8–0]—T8–T0 → These bits hold the current value of the refresh counter. They are
read-only.
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Data Sheet
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CDRAM (0e2h)
The Clock Prescaler Register determines the period between refresh cycles. The Count for
Dynamic RAM (CDRAM) register is undefined at reset (see Table 23).
Table 23. Count for Dynamic RAM Refresh Control Register
15
14
13 12 11
Reserved
10
9
8
7
6
5 4 3 2
RC8–RC0
1
0
Bits [15–9]—Reserved → These bits read back as 0.
Bits [8–0]—RC8–RC0 → These bits hold the clock count interval between refresh
cycles. In power-save mode, the refresh counter value should be adjusted to account for
the clock divider value in PDCON.
Note: This value should not be set to less than 18 (12h), else there would
never be sufficient bus cycles available for the processor to execute code.
5.1.8
MDRAM (0e0h)
The Memory Partition Register holds the a19–a13 address bits of the 20-bit base refresh address.
The MDRAM register contains 0000h at reset (see Table 24).
Table 24. Memory Partition for Dynamic RAM Refresh Control Register
15
14
13 12 11
M6–M0
10
9
8
7
6
5 4 3
Reserved
2
1
0
Bits [15–9]—M6–M0 → Upper bits corresponding to address bits a19–a13 of the 20-bit
memory refresh address. These bits are not available on the a19–a0 bus. When using
PSRAM mode, M6–M0 must be programmed to 0000000b.
Bits [8–0]—Reserved → These bits read back as 0.
5.1.9
D1CON (0dah) and D0CON (0cah)
DMA CONtrol Registers. DMA Control Registers control operation of the two DMA channels.
The D0CON and D1CON registers are fff9h at reset (see Table 25).
Table 25. DMA Control Registers
15
14
13
12
11
10 9 8
7
6
5
4
3
2
1
0
DM/IOn DDEC DINC SM/IOn SDEC SINC TC INT SYN1–SYN0 P TDRQ Res CHG ST Bn/W
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Bit [15]—DM/IOn → Destination Address Space Select selects memory or I/O space for
the destination address. When DM/IO is set to 1, the destination address is in memory
space. When 0, it is in I/O space.
Bit [14]—DDEC → Destination Decrement. When set to 1, it automatically decrements
the destination address after each transfer. The address is decremented by 1 or 2,
depending on the byte/word bit (Bn/W, Bit [0]). The address does not change if the
increment and decrement bits are set to the same value (00b or 11b).
Bit [13]—DINC → Destination Increment. When set to 1, it automatically increments
the destination address after each transfer. The address is incremented by 1 or 2,
depending on the byte/word bit (Bn/W, Bit [0]). The address does not change if the
increment and decrement bits are set to the same value (00b or 11b).
Bit [12]—SM/IOn → Source Address Space Select selects memory or I/O space for the
source address. When set to 1, the source address is in memory space. When 0, it is in
I/O space.
Bit [11]—SDEC → Source Decrement. When set to 1, it automatically decrements the
source address after each transfer. The address is decremented by 1 or 2, depending on
the byte/word bit (Bn/W, Bit [0]). The address does not change if the increment and
decrement bits are set to the same value (00b or 11b).
Bit [10]—SINC → Source Increment. When set to 1, it automatically increments the
source address after each transfer. The address is incremented by 1 or 2, depending on
the byte/word bit (Bn/W, Bit [0]). The address does not change if the increment and
decrement bits are set to the same value (00b or 11b).
Bit [9]—TC → Terminal Count. The DMA decrements the transfer count for each DMA
transfer. When set to 1, the source or destination synchronized DMA transfers terminate
when the count reaches 0. When 0, they do not. Unsynchronized DMA transfers always
end when the count reaches 0, regardless of this bit’s setting.
Bit [8]—INT → Interrupt. When this bit is set to 1, the DMA channel generates an
interrupt request on completion of the transfer count. However, for an interrupt to be
generated, the TC bit must also be set to 1.
Bits [7–6]—SYN1–SYN0 → Synchronization Type bits select channel synchronization
types as shown below. The value of these bits is ignored if TDRQ (Bit [4]) is set to 1. A
processor reset causes these bits to be set to 11b.
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Synchronization Bit Channel Selection
SYN1 SYN0
Sync Type
0
0
Unsynchronized
0
1
Source Synchronized
1
0
Destination Synchronized
1
1
Reserved
Bit [5]—P → Relative Priority. When set to 1, selects high priority for this channel
relative to the other channel during simultaneous transfers.
Bit [4]—TDRQ → Timer 2 Synchronization. When set to 1, enables DMA requests from
Timer 2. When 0, disables them.
Bit [3]—Reserved.
Bit [2]—CHG → Change Start Bit. This bit must be set to 1 to allow modification of the
ST bit during a write. During a write, when CHG is set to 0, ST is not changed when
writing the control word. The result of reading this bit is always 0.
Bit [1]—ST → Start/Stop DMA Channel. When set to 1, the DMA channel is started.
The CHG bit must be set to 1 for this bit to be modified during the register write. A
processor reset causes this bit to be set to 0.
Bit [0]—Bn/W → Byte/Word Select. When set to 1, word transfers are selected.
When 0, byte transfers are selected.
Note: Word transfers are not supported if the chip selects are programmed
for 8-bit transfers. The IA188ER does not support word transfers
5.1.10 D1TC (0d8h) and D0TC (0c8h)
DMA Transfer Count Registers. The DMA Transfer Count registers are maintained by each
DMA channel. They are decremented after each DMA cycle. The state of the TC bit in the
DMA control register has no influence on this activity. If unsynchronized transfers are
programmed or if the TC bit in the DMA control word is set, DMA activity ceases when the
transfer count register reaches 0. The D0TC and D1TC registers are undefined at reset (see
Table 26).
Table 26. DMA Transfer Count Registers
15
14
13
12
11
10 9 8 7
TC15–TC0
6
5
4
3
2
1
0
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Bits [15–0]—TC15–TC0 → DMA Transfer Count contains the transfer count for the
respective DMA channel. Its value is decremented after each transfer.
5.1.11 D1DSTH (0d6h) and D0DSTH (0c6h)
The DMA DeSTination Address High Register. The 20-bit destination address consists of these
4 bits combined with the 16 bits of the respective Destination Address Low Register. A DMA
transfer requires that two complete 16-bit registers (high and low registers) be used for both the
source and destination addresses of each DMA channel involved. These four registers must be
initialized. Each address may be incremented or decremented independently of each other after
each transfer. The addresses are incremented or decremented by two for word transfers and
incremented or decremented by one for byte transfers. They are undefined at reset (see
Table 27).
Table 27. DMA Destination Address High Register
15
14
13
12
11 10 9
Reserved
8
7
6
5
4
3 2 1 0
DDA19–DDA16
Bits [15–4]—Reserved.
Bits [3–0]—DDA19–DDA16 → DMA Destination Address High bits are driven onto
a19–a16 during the write phase of a DMA transfer.
5.1.12 DIDSTL (0d4h) and D0DSTL (0c4h)
DMA DeSTination Address Low Register. The 16 bits of these registers are combined with the
4 bits of the respective DMA Destination Address High Register to produce a 20-bit destination
address. They are undefined at reset (see Table 28).
Table 28. DMA Destination Address Low Register
15
14
13
12
11
10 9 8 7 6
DDA15–DDA0
5
4
3
2
1
0
Bits [15–0]—DDA15–DDA0 → DMA Destination Address Low bits are driven onto
a15–a0 during the write phase of a DMA transfer.
5.1.13 D1SRCH (0d2h) and D0SRCH (0c2h)
DMA SouRCe Address High Register. The 20-bit source address consists of these 4 bits
combined with the 16 bits of the respective Source Address Low Register. A DMA transfer
requires that two complete 16-bit registers in the PCB (high and low registers) be used for both
the source and destination addresses of each DMA channel involved. Each channel requires that
all four address registers be initialized. Each address may be independently incremented or
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decremented after each word transfer by 2 or by 1 for byte transfers. They are undefined at reset
(see Table 29).
Table 29. DMA Source Address High Register
15
14
13
12
11 10 9
Reserved
8
7
6
5
4
3 2 1 0
DSA19–DSA16
Bits [15–4]—Reserved.
Bits [3–0]—DSA19–DSA16 → DMA Source Address High bits are driven onto a19–a16
during the read phase of a DMA transfer.
5.1.14 D1SRCL (0d0h) and D0SRCL (0c0h)
DMA SouRCe Address Low Register. The 16 bits of these registers are combined with the 4 bits
of the respective DMA Source Address High register to produce a 20-bit source address. They
are undefined at reset (see Table 30).
Table 30. DMA Source Address Low Register
15
14
13
12
11
10 9 8 7 6
DSA15–DSA0
5
4
3
2
1
0
Bits [15–0]—DSA15–DSA0 → DMA Source Address Low bits are driven onto a15–a0
during the read phase of a DMA transfer.
5.1.15 IMCS (0ach)
Internal memory chip select register. This register controls the generation of chip select for the
Internal RAM. This memory can be mapped to any 32K byte boundary. An enable bit is used to
activate the memory rather than any write to the register. A separate control bit allows reads
from this memory to appear on the external bus. The value of this register is undefined at reset
(see Table 31).
Table 31. Internal Memory Chip Select Register
15
14 13 12 11
BA19 – BA13
10
SR
9
RE
8
7
6
5 4 3 2
Reserved
1
0
Bits [15 – 11] — Base Address → Upper five bits of 20-bit memory address to which
internal memory is mapped. Undefined at reset.
Bit [10] — SR (Show Read) → When high, drives data on the external AD bus during
read of internal memory. Zero at reset.
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Bits [9] — EN (Internal RAM Enable) → Internal memory is enabled by writing this bit
to a 1 and initializing the base address. This bit is a zero at reset.
5.1.16 MPCS (0a8h)
MCS and PCS (MPCS) Auxiliary Register. Because this register controls more than one type of
chip select, it is unlike other chip select control registers. The MPCS register contains
information for mcs3_n–mcs0_n, pcs6_n–pcs5_n, and pcs3_n–pcs0_n.
The MPCS register also contains a bit that configures the pcs6_n–pcs5_n pins as either chip
selects or as alternate sources for the a2 and a1 address bits. Either a2/a1 or pcs6_n–pcs5_n are
selected to the exclusion of the other. When programmed for address bits, these outputs can be
used to provide latched address bits for a2 and a1.
The pcs6_n–pcs5_n pins are high and not active on processor reset. When the pcs6_n–pcs5_n
are configured as address pins, an access to the MPCS register causes them to activate. They do
not require corresponding access to the PACS register to be activated. The value of the MPCS
register is undefined at reset (see Table 32).
Table 32. MCS and PCS Auxiliary Register
15
1
14
13
12 11 10
M6–M0
9
8
7
EX
6
MS
5 4 3
Reserved
2
R2
1
0
R1–R0
Bit [15]—Reserved → Set to 1.
Bits [14–8]—M6–M0 mcs_n Block Size → These seven bits determine the total memory
block size for the mcs3_n–mcs0_n chip selects. The size is divided equally among them.
The relationship between M6–M0 and the size is shown below.
Select Sizes of M6–M0 by Total Block Size
Total
Individual
Block Size Select Size
M6–M0
8K
2K
0000001b
16K
4K
0000010b
32K
8K
0000100b
64K
16K
0001000b
128K
32K
0010000b
256K
64K
0100000b
512K
128K
1000000b
Bit [7]—EX Pin Selector → This bit determines whether the pcs6_n–pcs5_n pins are
configured as chip selects or as alternate outputs for a2 and a1. When set to 2,
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they are configured as peripheral chip select pins. When 0, they become address bits a2
and a1, respectively.
Bit [6]—MS Memory/I/O Space Selector → This bit determines whether the pcs_n pins
are active during either memory or I/O bus cycles. When set to 1, the outputs are active
for memory bus cycles. When 0, they are active for I/O bus cycles.
Bits [5–3]—Reserved → Set to 1.
Bit [2]—R2 Ready Mode → This bit influences only the pcs6_n–pcs5_n chip selects.
When set to 1, external ready is ignored. When 0, it is required.
Bits [1–0]—R1–R0 Wait-State Value → These bits influence only the pcs6_n–pcs5_n
chip selects. Their value determines the number of wait states inserted into an access.
Up to three wait states can be inserted (R1–R0 = 00b to 11b).
5.1.17 MMCS (0a6h)
Midrange Memory Chip Select (MMCS) Register. Four chip-select pins, mcs3_n–mcs0_n, are
provided for use within a user-locatable memory block. Excluding the areas associated with the
ucs_n and lcs_n chip selects (and if mapped to memory, the address range of the peripheral chip
selects, pcs6_n–pcs5_n and pcs3_n–pcs0_n), the memory block base address can be located
anywhere within the 1-Mbyte memory address space. If the pcs_n chip selects are mapped to
I/O space, the mcs_n address range can overlap the pcs_n address range.
Two registers program the Midrange Chip Selects. The MMCS register determines the base
address, the ready condition, and wait states of the memory block that are accessed through the
mcs_n pins. The pcs_n and mcs_n auxiliary (MPCS) register configures the block size. On
reset, the mcs3_n–mcs0_n pins are not active. Both the MMCS and MPCS registers must be
written to activate these chip selects.
Unlike the ucs_n and lcs_n chip selects, the mcs3_n–mcs0_n outputs assert with the multiplexed
ad address bus (ad15–ad0 for the IA186ER and ao15–ao8 and ad7–ad0 for the IA188ER), rather
than the earlier timing of the a19–a0 bus. If the a19–a0 bus is used for address selection, the
timing is delayed for a half cycle later than that for ucs_n and lcs_n. The value is undefined at
reset (see Table 33).
Table 33. Midrange Memory Chip Select Register
15
14
13 12 11
BA19–BA13
10
9
8
7
6 5 4
Reserved
3
2
R2
1
0
R1–R0
Bits [15–9]—BA19–BA13 Base Address → The value of the this pin determines the base
address of the memory block that is addressed by the mcs_n chip select pins. These bits
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correspond to a19–a13 of the 20-bit memory address. The remaining bits a12–a0 of the
base address are always 0.
–
The base address may be any integer multiple of the size of the memory clock
selected in the MPCS register. For example, if the midrange block is 32 Kbytes, the
block could be located at 20000h or 28000h but not at 24000h.
–
If the lcs_n chip select is inactive, the base address of the midrange chip selects can
be set to 00000h, because the lcs_n chip select is defined to be 00000h but is unused.
Because the base address must be an integer multiple of the block size, a 512K
MMCS block size can only be used with the lcs_n chip select inactive and the base
address of the midrange chip selects set to 00000h.
Bits [8–3]—Reserved → Set to 1.
Bit [2]—R2 Ready mode → This bit determines the mcs_n chip select ready mode.
When set to 1, an external ready is ignored. When 0, it is necessary. In each case, the
number of wait states inserted in an access is determined by the value of the R1 and R0
bits.
Bits [1–0]—R1–R0 → Wait-State Value. The value of these bits determines the number
of wait states inserted in an access. Up to three wait states can be inserted (R1–R0 = 00b
to 11b).
5.1.18 PACS (0a4h)
PeripherAl Chip Select Register. These Peripheral Chip Selects are asserted over a 256-byte
range with the same timing as the ad address bus. There are six chip selects, pcs6_n–pcs5_n and
pcs3_n–pcs0_n, that are used in either the user-locatable memory or I/O blocks. The pcs4_n
chip select is not implemented in the IA186ER or IA188ER. Excluding the areas used by the
ucs_n, lcs_n, and mcs_n chip selects, the memory block can be located anywhere within the
1-Mbyte address space. These chip selects may also be configured to access the 64-Kbyte
I/O space.
Programming the Peripheral Chip Selects uses the Peripheral Chip Select (PACS) and the pcs_n
and mcs_n Auxiliary (MPCS) registers. The PACS register establishes the base address,
configures the ready mode, and determines the number of wait states for the pcs3_n–pcs0_n
outputs.
The MPCS register configures the pcs6_n–pcs5_n pins to be either chip selects or address pins
a1 and a2. When these pins are configured as chip selects, the MPCS register determines the
ready and wait states for these output pins and whether they are active during memory or I/O bus
cycles. These pins are activated as chip selects by writing to the two registers (PACS and
MPCS). They are not active on reset. To configure and activate them as address pins, it is
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necessary to write to both the PACS and MPCS registers. Pins pcs6_n–pcs5_n can be
configured for 0 to 3 wait states and pcs3_n–pcs0_n can be programmed for 0 to 15 wait states.
The value of the PACS register is undefined at reset (see Table 34).
Table 34. Peripheral Chip Select Register
15
14
13
12 11 10
BA19–BA11
9
8
7
6 5 4
Reserved
3
R3
2
R2
1
0
R1–R0
Bits [15–7]—BA19–BA11 → Base Address bits correspond to Bits [19–11] of the 20-bit
programmable base address of the peripheral chip select block and determine the base
address. Because I/O addresses are only 16 bits wide, if the pcs_n chip selects are
mapped to I/O space, Bits BA19-16 must be set to 0000b. The pcs address ranges are
shown below.
Address Ranges of pcs Chip Selects
Range
pcs_n Line
Low
High
pcs0_n
Base Address
Base Address + 255
pcs1_n
Base Address + 256
Base Address + 511
pcs2_n
Base Address + 512
Base Address + 767
pcs3_n
Base Address + 768
Base Address + 1023
Reserved
NA
NA
pcs5_n
Base Address + 1280 Base Address + 1535
pcs6_n
Base Address + 1536 Base Address + 1791
Bits [6–4]—Reserved → Set to 1.
Bit [3]—R3 → Wait State Value. See pcs3_n–pcs0_n Wait-State Encoding shown below.
pcs3_n–pcs0_n Wait-State Encoding
R3 R1 R0 Wait States
0
0
0
0
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
5
1
0
1
7
1
1
0
9
1
1
1
15
Bit [2]—R2 → Ready Mode. When set to 1, external ready is ignored. When 0, it is
required. In each case the number of wait states is determined according to the
pcs3_n–pcs0_n Wait-State Encoding shown above.
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Bits [1–0]—R1–R0 → Wait-State Value (see pcs3_n–pcs0_n Wait-State Encoding
above).
The pcs6_n–pcs5_n and pcs3_n–pcs0_n pins are multiplexed with the PIO pins. For these to
function as chip selects, the PIO mode and direction settings for these pins must be set to 0
for normal operation.
5.1.19 LMCS (0a2h)
The Low-Memory Chip Select (LMCS) Register configures the LMCS provided to facilitate
access to the interrupt vector table located at 00000h or the bottom of memory. The lcs_n pin is
not enabled at reset.
The LCS_n pin is enabled by any write to the LMCS register. The value of the LMCS register is
undefined at reset except DA, which is set to 0 (see Table 35).
Table 35. Low-Memory Chip Select Register
15
Res
14 13 12
UB2–UB0
11
10 9 8
Reserved
7
DA
6
PSE
5 4 3
Reserved
2
R2
1
0
R1–R0
Bit [15]—Reserved → Set to 0.
Bits [14–12]—UB2–UB0 → Upper Boundary. These bits define the upper boundary of
memory accessed by the lcs_n chip select. The list below presents the possible block-size
configurations (a 512-Kbyte maximum).
LMCS Block-Size Programming Values
Memory
Ending
Block Size Address UB2–UB0
64K
0FFFFh
000b
128K
1FFFFh
001b
256K
3FFFFh
011b
512K
7FFFFh
111b
Bits [11–8]—Reserved → Set to 1.
Bit [7]—DA → Disable Address. When set to 1, the multiplexed address bus is disabled,
providing reduced power consumption. When 0, the address is driven onto the address
bus ad15–ad0 during the address phase of a bus cycle. This bit is set to 0 at reset.
–
If bhe_n/aden_n (IA186ER) is held at 0 during the rising edge of res_n, the address
bus is always driven, regardless of the setting of DA.
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Bit [6]—PSE → PSRAM Mode Enable. When set to 1, PSRAM support for the lcs_n
chip select memory space is enabled. The EDRAM, MDRAM, and CDRAM RCU
registers must be configured for auto refresh before PSRAM support is enabled. Setting
the enable bit (EN) in the enable RCU register (EDRAM, offset e4h) configures the
mcs3_n/rfsh_n as rfsh_n.
Bits [5–3]—Reserved → Set to 1.
Bit [2]—R2 → Ready Mode. When set to 1, the external ready is ignored. When 0, it is
required. The value of R1–R0 bits determines the number of wait states inserted.
Bits [1–0]—R1–R0 → Wait-State Value. The value of these bits determines the number
of wait states inserted into an access to the lcs_n memory area. This number ranges from
0 to 3 (R1–R0 = 00b to 11b).
5.1.20 UMCS (0a0h)
The Upper Memory Chip Select Register configures the UMCS pin, used for the top of memory.
On reset, the first fetch takes place at memory location FFFF0h and thus this area of memory is
usually used for instruction memory. The ucs_n defaults to an active state at reset with a
memory range of 64 Kbytes (F0000h to FFFFFh), external ready required, and three wait states
automatically inserted. The upper end of the memory range always ends at FFFFFh. The lower
end of this upper memory range is programmable. The value of the UMCS register is F03Bh at
reset (see Table 36).
Table 36. Upper-Memory Chip Select Register
15
1
14 13 12
LB2–LB0
11
10 9 8
Reserved
7
DA
6
0
5 4 3
Reserved
2
R2
1
0
R1–R0
Bit [15]—Reserved → Set to 1.
Bits [14–12]—LB2–LB0 Lower Boundary → These bits determine the bottom of the
memory accessed by the ucs_n chip select. The UMCS Block-Size Programming Values
shown below list the possible block-size configurations (a 512-Kbyte maximum).
UMCS Block-Size Programming Values
Memory
Starting
Block Size Address LB2–LB0 Comments
64K
F0000h
111b
Default
128K
E0000h
110b
–
256K
C0000h
100b
–
512K
80000h
000b
–
Bits [11–8]—Reserved.
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Bit [7]—DA → Disable Address. When set to 1, the multiplexed address bus is disabled
and the address is not driven on the address bus when ucs_n is asserted, providing
reduced power consumption. When 0, the address is driven onto the address bus (ad15–
ad0) during the address phase of a bus cycle when ucs_n is asserted. This bit is set to 0 at
reset.
–
If bhe_n/aden_n (IA186ER) is held at 0 during the rising edge of res_n, the address
bus is always driven, regardless of the setting.
Bit [6]—Reserved → Set to 0.
Bits [5–3]—Reserved → Set to 1.
Bit [2]—R2 Ready Mode → When set to 1, the external ready is ignored. When 0, it is
required. The value of the R1–R0 bits determines the number of wait states inserted.
Bits [1–0]—R1–R0 Wait-State Value → The value of these bits determines the number of
wait states inserted into an access to the lcs_n memory area. This number ranges from 0
to 3 (R1–R0 = 00b to 11b).
5.1.21 SPBAUD (088h)
Serial Port BAUD Rate Divisor Register. The value in this register determines the number of
internal processor cycles in one phase (half-period) of the 32 x serial clock. The contents of
these registers must be adjusted to reflect the new processor clock frequency if power-save mode
is in effect. The baud rate divisor may be calculated from:
BAUDDIV = (Processor Frequency/(32 x baud rate)) -1
(Equation 2)
By setting the BAUDDIV to 0000h, the maximum baud rate of 1/32 of the internal processor
frequency clock is set. Setting BAUDDIV to 129 (81h) provides a baud rate of 9600 at 40 MHz.
The baud rate tolerance is +4.6% to –1.9% with respect to the actual serial port baud rate, not the
target baud rate (see Table 37).
Table 37. Baud Rates
Baud Rate
300
600
1200
2400
4800
9600
14400
Divisor Based on CPU Clock Rate
20 MHz 25 MHz 33 MHz 40 MHz
4166
5208
6875
8333
2083
2604
3437
4166
1041
1302
1718
2083
520
651
859
1041
260
325
429
520
130
162
214
260
42
53
71
85
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19200
625 Kbaud
781.25 Kbaud
1.041 Mbaud
1.25 Mbaud
31
0
NA
NA
NA
39
NA
0
NA
NA
Data Sheet
February 25, 2013
53
NA
NA
0
NA
64
1
NA
NA
0
The value of the SPBAUD register at reset is undefined (see Table 38).
Table 38. Serial Port Baud Rate Divisor Registers
15
14
13
12
11
10
9 8 7
BAUDDIV
6
5
4
3
2
1
0
Bits [15–0]—BAUDDIV Baud Rate Divisor → Defines the divisor for the internal
processor clock.
5.1.22 SPRD (086h)
Serial Port Receive Data Register. Data received over the serial port are stored in this register
until read. The data are received initially by the receive shift register (no software access)
permitting data to be received while the previous data are being read.
The RDR bit (Receive Data Ready) in the serial port status register indicates the status of the
SPRD register. A 1 indicates there is valid data in the receive register. The value of the SPRD
register is undefined at reset (see Table 39).
Table 39. Serial Port Receive Data Register
15
14
13
12 11
Reserved
10
9
8
7
6
5
4 3 2
RDATA
1
0
Bits [15–8]—Reserved.
Bits [7–0]—RDATA → Holds valid data if the RDR bit of the status register is set.
5.1.23 SPTD (084h)
Serial Port Transmit Data Register. Data is written to this register by software, with the values to
be transmitted by the serial port. Double buffering of the transmitter allows for the transmission
of data from the transmit shift register (no software access) while the next data are written into
the transmit register.
The THRE bit in the Serial Port Status register indicates whether there is valid data in the
SPTDregister. The THRE bit must be a 1 before writing data to this register to prevent
overwriting valid data that is already in the SPTD register. The value of the SPTD register is
undefined at reset (see Table 40).
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Table 40. Serial Port Transmit Data Register
15
14
13
12 11
Reserved
10
9
8
7
6
5
4 3 2
TDATA
1
0
Bits [15–8]—Reserved.
Bits [7–0]—TDATA → Holds the data to be transmitted.
5.1.24 SPSTS (082h)
Serial Port STatuS Register. This register stores information concerning the current status of the
port. The status bits are described below.
The value of the SPSTS register is undefined at reset (see Table 41).
Table 41. Serial Port Status Register
15
14
13
12 11 10
Reserved
9
8
7
6
TEMT
5
THRE
4
RDR
3
BRKI
2
FER
1
PER
0
OER
Bits [15–7]—Reserved → Set to 0.
Bit [6]—TEMT Transmitter Empty → When both the transmit shift register and the
transmit register are empty, this bit is set indicating to software that it is safe to disable
the transmitter. This bit is read-only.
Bit [5]—THRE Transmit Holding Register Empty → When this bit is 1, the
corresponding transmit holding register is ready to accept data. This is a read-only bit.
Bit [4]—RDR Receive Data Ready → When this bit is 1, the SPRD register contains
valid data. This is a read_only bit and can be reset only by reading the receive register.
Bit [3]—BRKI Break Interrupt → This bit indicates that a break has been received when
this bit is set to 1 and causes a serial port interrupt request, if RSIE is set.
Note: This bit should be reset by software.
Bit [2]—FER Framing Error Detected → When the receiver samples the rxd/pio28 line as
low when a stop bit is expected (line high), a framing error is generated setting this bit.
Note: This bit should be reset by software.
Bit [1]—PER Parity Error Detected → When a parity error is detected in either mode 1 or
3, this bit is set.
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Note: This bit should be reset by software.
Bit [0]—OER Overrun Error Detected → When new data overwrites valid data in the
receive register (because it has not been read) an overrun error is detected setting this bit.
Note: This bit should be reset by software.
5.1.25 SPCT (080h)
Serial Port ConTrol Register. This register controls both transmit and receive parts of the serial
port. The value of the SPCT register is 0000h at reset (see Table 42).
Table 42. Serial Port Control Register
15 14 13
12
DMA
Reserved
11
TXIE
10
RXIE
9
LOOP
8
BRK
7
6
5
4
BRKVAL PMODE WLGN
3
2
STP TMODE
1
RSIE
0
RMODE
Bits [15 - 13]— DMA Control Field → Enables DMA transfers to and from serial port as
follows:
DMA Bits
000
001
010
011
100
101
110
111
Receive
Transmit
No DMA
No DMA
DMA0
DMA1
DMA1
DMA0
RESERVED
DMA0
No DMA
DMA1
No DMA
No DMA
DMA0
No DMA
DMA1
DMA transfers to the serial port act as destination-synchronized transfers. DMA request
occurs when THRE is set to 1. Interrupts are disabled regardless of the state of TXIE
when DMA transfers are enabled.
DMA transfers from the serial port act as source-synchronized transfers. DMA request
occurs when RDR is set to 1. Interrupts are disabled regardless of the state of RXIE when
DMA transfers are enabled.
Bit [12]—Reserved → Set to 0.
Bit [11]—TXIE Transmitter Ready Interrupt Enable → This bit enables the generation of
an interrupt request whenever the transmit holding register is empty (THRE Bit [1]). The
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respective port does not generate interrupts when this bit is 0. Interrupts continue to be
generated as long as THRE and the TXIE are 1.
Bit [10]—RXIE Receive Data Ready Interrupt Enable → This bit enables the generation
of an interrupt request whenever the receive register contains valid data (RDR Bit [1]).
The respective port does not generate interrupts when this bit is 0. Interrupts continue to
be generated as long as RDR and the RXIE are 1.
Bit [9]—LOOP Loop Back → The serial port is placed into the loop-back mode when
this bit is set.
Bit [8]—BRK Send Break → When this bit is set to 1, the txd/pio27 pin is driven to the
value in BRKVAL, overriding any data that may be in the course of being shifted out of
the transmit shift register.
Bit [7]—BRKVAL Break Value → This is the value transmitted when BRK is asserted.
Bits [6–5]—PMODE Parity Mode →See table below. These bits define parity checking
and generation 00 at reset.
Parity
Pmode
None
0x
Odd
Even
10
11
Bit [4]—WLGN Word Length → The number of bits transmitted or received in a frame is
determined by the value of this bit. When this bit is 1, the number of data bits in a frame
is 8. When 0, it is 7. This bit is 0 at reset.
Bit [3]—STP Stop Bits → This bit specifies the number of stop bits used to indicate the
end of a frame. When this bit is 1, the number of stop bits is 2. When 0, it is 1. This bit
is 0 at reset.
Bit [2]—TMODE Transmit Mode → When this bit is 1, the transmit section of the serial
port is enabled. When 0, it is disabled.
Bit [1]—RSIE Receive Status Interrupt Enable → When an exception occurs during data
reception, an interrupt request is generated if enabled by this bit (RSIE = 1). Interrupt
requests are made for the error conditions listed in the serial port status register (BRK,
OER, PER, and FER). This bit is 0 at reset.
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Bit [0]—RMODE Receive Mode → When this bit is 1, the receive section of the serial
port is enabled. When 0, it is disabled. This bit is 0 at reset.
5.1.26 PDATA1 (07ah) and PDATA0 (074h)
PIO DATA Registers. When a PIO pin is configured as an output, the value in the
corresponding PIO data register bit is driven onto the pin. However, if the PIO pin is configured
as an input, the value on the pin is put into the corresponding bit of the PIO data register.
Table 43 lists the default states for the PIO pins.
Table 43. PIO Pin Assignments
PIO Number
0
1
2
3
4
5
6
7c
8c
9c
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Associated Pin Name
tmrin1
tmrout1
pcs6/a2
pcs5/a1
dt/r_n
den_n
srdy
a17
a18
a19
tmrout0
tmrin0
drq0
drq1
mcs0_n
mcs1_n
pcs0_n
pcs1_n
pcs2_n
pcs3_n
sclk
sdata
sden0
sden1
Power-On Reset Status
Input with pull-up
Input with pull-down
Input with pull-up
Input with pull-up
Normal operationa
Normal operationa
Normal operationb
Normal operationa
Normal operationa
Normal operationa
Input with pull-down
Input with pull-up
Input with pull-up
Input with pull-up
Input with pull-up
Input with pull-up
Input with pull-up
Input with pull-up
Input with pull-up
Input with pull-up
Input with pull-up
Input with pull-up
Input with pull-down
Input with pull-down
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Table 43. PIO Pin Assignments (Continued)
PIO Number
24
25
26c,d
27
28
29c,d
30
31
Associated Pin Name
mcs2_n
mcs3_n/rfsh_n
uzi/clksel2_n
txd/pio27
rxd/pio28
s6/clksel1_n
int4
int2
Power-On Reset Status
Input with pull-up
Input with pull-up
Input with pull-up
Input with pull-up
Input with pull-up
Input with pull-up
Input with pull-up
Input with pull-up
aWhen used as a PIO pin, it is an input with a pull-up option available.
bWhen used as a PIO pin, it is an input with a pull-down option available.
cEmulators use these pins and also a15–a0, ad15–ad0 (IA186ER), ale, bhe_n (IA186ER), clkouta, nmi, res_n,
and s2_n–s0_n.
dIf bhe_n/aden_n (IA186ER) or rfsh2_n/aden (IA188ER) is held low during POR, these pins revert to normal
operation.
The value of the PDATA registers is undefined at reset (see Tables 44 and 45).
Table 44. PDATA 0
15
14
13
12
11
10 9 8 7 6
PDATA15–PDATA0
5
4
3
2
1
0
11 10 9 8 7 6 5
PDATA31–PDATA16
4
3
2
1
0
Table 45. PDATA 1
15
14
13
12
Bits [15–0]—PDATA15–PDATA0 PIO Data 0 Bits → This register contains the values of
the bits that are either driven on, or received from, the corresponding PIO pins.
Depending on its configuration, each pin is either an output or an input. The values of
these bits correspond to those in the PIO Direction registers and PIO Mode registers.
Bits [15–0]—PDATA31–PDATA16 PIO Data 1 Bits → This register contains the values
of the bits that are either driven on, or received from, the corresponding PIO pins.
Depending on its configuration, each pin is either an output or an input. The values of
these bits correspond to those in the PIO direction registers and PIO Mode registers
The PIO pins may be operated as open-drain outputs by:
– Maintaining the data constant in the appropriate bit of the PIO data register.
– Writing the value of the data bit into the respective bit position of the PIO Direction
register, so that the output is either 0 or disabled depending on the value of the data
bit.
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5.1.27 PDIR1 (078h) and PDIR0 (072h)
PIO DIRection Registers. Each PIO pin is configured as an input or an output by the
corresponding bit in the PIO Direction register (see Table 46).
Table 46. PIO Mode and PIO Direction Settings
PIO Mode
0
0
1
1
PIO Direction
0
1
0
1
Pin function
Normal operation
PIO input with pullup/pulldown
PIO output
PIO input without pullup/pulldown
The value of the PDIR0 register is FC0Fh at reset (see Table 47).
Table 47. PDIR0
15
14
13
12
11
10 9 8 7 6
PDIR15–PDIR0
5
4
3
2
1
0
The value of the PDIR1 register is FFFFh at reset (see Table 48).
Table 48. PDIR1
15
14
13
12
11
10 9 8 7 6
PDIR31–PDIR16
5
4
3
2
1
0
Bits [15–0]—PDIR15–PDIR0 PIO Direction 0 Bits → For each bit, if the value is 1, the
pin is configured as an input. If 0, as an output. The values of these bits correspond to
those in the PIO data registers and PIO mode registers.
Bits [15–0]—PDIR31–PDIR16 PIO Direction 1 Bits → For each bit, if the value is 1, the
pin is configured as an input. If 0, as an output. The values of these bits correspond to
those in the PIO Data registers and PIO Mode registers.
5.1.28 PIOMODE1 (076h) and PIOMODE0 (070h)
PIO MODE Registers. Each PIO pin is configured as a PIO or its normal function by the
corresponding bit in the PIO mode register. The bit number of PMODE corresponds to the PIO
number (see Table 44, PIO Mode and PIO Direction Settings). The value of the PIOMODE0
register is 0000h at reset (see Table 49).
Table 49. PIOMODE0
15
14
13
12
11 10 9 8 7 6 5
PMODE15–PMODE0
4
3
2
1
0
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The value of the PIOMODE1 register is 0000h at reset (see Table 50).
Table 50. PMODE1
15
14
13
12
11 10 9 8 7 6 5
PMODE31–PMODE16
4
3
2
1
0
Bits [15–0]—PMODE15–PMODE0 PIO Mode 0 Bits → See Table 46. The values of
these bits correspond to those in the PIO data registers and PIO Mode registers.
Bits [15–0]—PMODE31–PMODE16 PIO Mode 1 Bits → See Table 46. The values of
these bits correspond to those in the PIO data registers and PIO Mode registers.
5.1.29 T1CON (05eh) and T0CON (056h)
Timer 0 and Timer 1 Mode and CONtrol Registers. These registers control the operation of
Timer 0 and Timer 1, respectively. The value of the T0CON and T1CON registers is 0000h at
reset (see Table 51).
Table 51. Timer 0 and Timer 1 Mode and Control Registers
15
EN
14
INHn
13
INT
12
RIU
11
10 9 8 7
Reserved
6
5
MC
4
RTG
3
P
2
EXT
1
ALT
0
CONT
Bit [15]—EN Enable Bit → The timer is enabled when the EN bit is 1. The timer count
is inhibited when the EN bit is 0. This bit can only be written if the INHn bit (Bit [14]) is
set to 1 in the same operation.
Bit [14]—INHn Inhibit Bit → Gates the setting of the enable (EN) bit. This bit must be
set to 1 in the same write operation that changes the enable (EN) bit. Otherwise, the EN
bit will not be changed. This bit always reads 0.
Bit [13]—INT Interrupt Bit → If set to 1, an interrupt request is generated when the
Count register reaches its maximum, MC = 1. In dual maxcount mode, an interrupt
request is generated when the count register reaches the value in Maxcount A or
Maxcount B. No interrupt requests are generated if this bit is set to 0. If an interrupt
request is generated, and the enable bit is then cleared before the interrupt is serviced, the
interrupt request will remain.
Bit [12]—RIU Register in Use Bit → This bit is set to 1 when the Maxcount Register B is
used to compare to the timer-count value. It is 0 when the Maxcount Compare A register
is used.
Bits [11–6]—Reserved → Set to 0.
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Bit [5]—MC Maximum Count → When the timer reaches its maximum count, this bit is
set to 1 regardless of the interrupt enable bit. This bit is also set every time Maxcount
Compare Register A or B is reached when in dual maxcount mode. If preferred, this bit
may be used by software polling rather than by interrupts to monitor timer status.
Bit [4]—RTG Retrigger Bit → This pin controls the timer function of the timer input pin.
When set to 1, the count is reset by a 0 to 1 transition on timrin0 or tmrin1. When 0, a
high input on tmrin0 or tmrin1 enables the count and a 0 holds the timer value. This bit
is ignored if the external clocking (EXT = 1) bit is set.
Bit [3]—P Prescaler Bit → P is ignored if external clocking is enabled (EXT = 1). Timer
2 prescales the timer when P is set to 1. Otherwise, the timer is incremented on every
fourth clkout cycle.
Bit [2]—EXT External Clock Bit → This bit determines whether an external or internal
clock is used. If EXT is 1, an external clock is used. If 0, an internal is used.
Bit [1]—ALT Alternate Compare Bit → If set to 1, the timer will count to Maxcount
Compare A, reset the count register to 0, count to Maxcount Compare B, reset the count
register to 0, and begin again at Maxcount Compare A. If 0, it will count to Maxcount
Compare A, reset the count register to 0, and begin again at Maxcount Compare A.
Maxcount Compare B is not used in this case.
Bit [0]—CONT Continuous Mode Bit → When set to 1, the timer runs continuously.
When 0, the timer stops after each count run and EN will be cleared. If CONT = 0 and
ALT = 1, the respective timer counts to the Maxcount Compare A value and resets, then
commences counting to Maxcount Compare B value, resets, and stops counting.
5.1.30 T2CON (066h)
Timer 2 Mode and CONtrol Register. This register controls the operation of Timer 2. The value
of the T2CON register is 0000h at reset (see Table 52).
Table 52. Timer 2 Mode and Control Registers
15
EN
14
INHn
13
INT
12
11
10 9 8
Reserved
7
6
5
MC
4
3 2 1
Reserved
0
CONT
Bit [15]—EN Enable Bit → The timer is enabled when the EN bit is 1. The timer count
is inhibited when the EN bit is 0. Modifying this bit by writing to the T2CON register
requires that the INH bit be set to 1 during the same write.
Bit [14]—INHn Inhibit Bit → Gates the setting of the enable (EN) bit. This bit must be
set to 1 in the same write operation that sets the enable (EN) bit. This bit always reads 0.
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Bit [13]—INT Interrupt Bit → An interrupt request is generated, by setting the INT bit to
1, when the Count register reaches its maximum, MC = 1.
Bits [12–6]—Reserved → Set to 0.
Bit [5]—MC Maximum Count → When the timer reaches its maximum count, this bit is
set to 1, regardless of the interrupt enable bit. If preferred, this bit may be used by
software polling rather than by interrupts to monitor timer status.
Bits [4–1]—Reserved → Set to 0.
Bit [0]—CONT Continuous Mode Bit → The timer will run continuously when this bit is
set to 1. The timer will stop after each count run and EN will be cleared if this bit is set
to 0.
5.1.31 T2COMPA (062h), T1COMPB (05ch), T1COMPA (05ah), T0COMPB (054h), and
T0COMPA (052h)
Timer Maxcount COMpare Registers. These registers contain the maximum count value that is
compared to the respective count register. Timer 0 and Timer 1 each have two compare
registers.
If Timer 0 and/or Timer 1 is/are configured to count and compare first to Register A and then
Register B, the tmrout0 or tmrout1 signals can be used to generate various duty-cycle wave
forms.
Timer 2 has only one compare register, T2COMPA.
If one of these timer maxcount compare registers is set to 0000h, the respective timer will count
from 0000h to FFFFh before generating an interrupt request. For example, a timer configured in
this manner with a 40-MHz clock will interrupt every 6.5536 mS.
The value of these registers is undefined at reset (see Table 53).
Table 53. Timer Maxcount Compare Registers
15
14
13
12
11
10 9 8 7
TC15–TC0
6
5
4
3
2
1
0
Bits [15–0]—TC15–TC0 Timer Compare Value → The timer will count to the value in
the respective register before resetting the count value to 0.
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5.1.32 T2CNT (060h), T1CNT (058h), and T0CNT (050h)
These registers are incremented by one every four internal clock cycles if the relevant timer is
enabled.
The Increment of Timer 0 and Timer 1 may also be controlled by external signals tmrin0 and
tmrin1 respectively, or prescaled by Timer 2.
Comparisons are made between the count registers and maxcount registers and action taken
dependent on achieving the maximum count.
The value of these registers is undefined at reset (see Table 54).
Table 54. Timer Count Registers
15
14
13
12
11
10 9 8 7
TC15–TC0
6
5
4
3
2
1
0
Bits [15–0]—TC15–TC0 Timer Count Value → This register has the value of the current
count of the related timer that is incremented every fourth processor clock in internal
clocked mode. Alternatively, the register is incremented each time the Timer 2 maxcount
is reached if using Timer 2 as a prescaler. Timer 0 and Timer 1 may be externally
clocked by tmrin0 and tmrin1 signals.
5.1.33 SPICON (044h) (Master Mode)
Serial Port Interrupt Control Register. This register controls the operation of the asynchronous
serial port interrupt source (SPI, Bit [10] in the Interrupt Request register). The value of this
register is 001Fh at reset (see Table 55).
Table 55. Serial Port Interrupt Control Registers
15
14
13
12
11 10 9
Reserved
8
7
6
5
4
Reserved
3
MSK
2 1 0
PR2–PR0
Bits [15–5]—Reserved → Set to 0.
Bit [4]—Reserved → Set to 1.
Bit [3]—MSK Mask → This bit, when 0, enables the serial port to cause an interrupt.
When this bit is 1, the serial port is prevented from generating an interrupt.
Bits [2–0]—PR2–PR0 Priority → These bits define the priority of the serial port interrupt
in relation to other interrupt signals. The interrupt priority is the lowest at 7 at reset. The
values of PR2–PR0 are shown below.
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Values of PR2–PR0 by Priority
Priority
PR2–PR0
(High) 0 000b
1
001b
2
010b
3
011b
4
100b
5
101b
6
110b
(Low) 7 111b
5.1.34 WDCON (042h) (Master Mode)
WatchDog Timer Interrupt Control Register. These registers control the operation of the
Watchdog Timer interrupt source. The value of this register is 000Fh at reset (see Table 56).
Table 56. Watchdog Timer Interrupt Control Register
15
14
13
12
11 10 9
Reserved
8
7
6
5
4
Reserved
3
MSK
2 1 0
PR2–PR0
Bits [15–5]—Reserved → Set to 0.
Bit [4]—Reserved → Set to 0.
Bit [3]—MSK Mask → This bit, when 0, enables the Watchdog Timer to cause an
interrupt. When this bit is 1 prevents the Watchdog Timer from generating an interrupt.
Bits [2–0]—PR2–PR0 Priority → These bits define the priority of the Watchdog Timer
interrupt in relation to other interrupt signals. The interrupt priority is the lowest at 7 at
reset. The values of PR2–PR0 are shown in the above table.
5.1.35 I4CON (040h) (Master Mode)
This register controls the operation of the int4 signal, which is only intended for use in fully
nested mode. The interrupt is assigned to type 10h. The value of the I4CON register is 000Fh at
reset (see Table 57).
Table 57. INT4 Control Register
15
14
13
12
11 10 9
Reserved
8
7
6
5
4
LTM
3
MSK
2 1 0
PR2–PR0
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Bits [15–5]—Reserved → Set to 0.
Bit [4]—LTM Level-Triggered Mode → The int4 interrupt may be edge- or leveltriggered, depending on the value of the bit. If LTM is 1, int4 is active high levelsensitive interrupt. If 0, it is a rising-edge triggered interrupt. The interrupt int4 must
remain active (high) until serviced.
Bit [3]—MSK Mask → The int4 signal can cause an interrupt if the MSK bit is 0. The
int4 signal cannot cause an interrupt if the MSK bit is 1.
Bits [2–0]—PR2–PR0 Priority → These bits define the priority of the interrupt in relation
to other interrupt signals. The interrupt priority is the lowest at 7 upon reset. The values
of PR2–PR0 are shown in the above table.
5.1.36 I3CON (03eh) and I2CON (03ch) (Master Mode)
INT2/INT3 CONtrol Register. The int2 and int3 are designated as interrupt type 0eh and 0fh,
respectively, and may be configured as the interrupt acknowledge pins inta0_n and inta1_n in
cascade mode. The value of these registers is 000Fh at reset (see Table 58).
Table 58. INT2/INT3 Control Register
15
14
13
12
11 10 9
Reserved
8
7
6
5
4
LTM
3
MSK
2 1 0
PR2–PR0
Bits [15–5]—Reserved → Set to 0.
Bit [4]—LTM Level-Triggered Mode → The int2 or int3 interrupt may be edge- or leveltriggered depending on the value of this bit. If LTM is 1, int2 or int3 is an active high
level-sensitive interrupt. If 0, int2 or int3 is a rising-edge-triggered interrupt. The
interrupt int2 or int3 must remain active (high) until acknowledged.
Bit [3]—MSK Mask → The int2 or int3 signal can cause an interrupt if the MSK bit is 0.
The int2 or int3 signal cannot cause an interrupt if the MSK bit is 1. The Interrupt Mask
Register has a duplicate of this bit.
Bits [2–0]—PR2–PR0 Priority → These bits define the priority of the interrupt int2 or
int3 in relation to other interrupt signals. The interrupt priority is the lowest at 7 at reset.
The values of PR2–PR0 are shown above.
5.1.37 I1CON (03ah) and I0CON (038h) (Master Mode)
INT0/INT1 CONtrol Register. The int0 and int1 are designated as interrupt type 0ch and 0dh,
respectively, and may be configured to use the interrupt acknowledge pins inta0 and inta1 in
cascade mode. The value of these registers is 000Fh at reset (see Table 59).
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Table 59. INT0/INT1 Control Register
15
14
13
12 11 10
Reserved
9
8
7
6
SFNM
5
C
4
LTM
3
MSK
2 1 0
PR2–PR0
Bits [15–7]—Reserved → Set to 0.
Bit [6]—SFNM Special Fully Nested Mode → This bit enables fully nested mode for int0
or int1 when set to 1.
Bit [5]—C Cascade Mode → This bit enables cascade mode for int0 or int1 when set
to 1.
Bit [4]—LTM Level-Triggered Mode → The int0 or int1 interrupt may be edge- or leveltriggered depending on the value of the bit. If LTM is 1, int0 or int1 is an active highlevel-sensitive interrupt. If 0, either is a rising-edge-triggered interrupt and must remain
active (high) until acknowledged.
Bit [3]—MSK Mask → The int0 or int1 signal can cause an interrupt if the MSK bit is 0.
If it is 1, they cannot. The Interrupt Mask Register has a duplicate of this bit.
Bits [2–0]—PR2–PR0 Priority → These bits define the priority of the int0 or int1 in
relation to other interrupt signals. The interrupt priority is the lowest at 7 at reset. The
values of PR2–PR0 are shown above.
5.1.38 TCUCON (032h) (Master Mode)
Timer Control Unit Interrupt CONtrol Register. The three timers have their interrupts assigned
to types 08h, 12h, and 13h and are configured by this register. The value of this register is 000Fh
at reset (see Table 60).
Table 60. Timer Control Unit Interrupt Control Register
15
14
13
12
11 10 9
Reserved
8
7
6
5
4
3
MSK
2 1 0
PR2–PR0
Bits [15–4]—Reserved → Set to 0.
Bit [3]—MSK Mask → An interrupt source may cause an interrupt if the MSK bit is 0. If
1, it cannot. The Interrupt Mask Register has a duplicate of this bit.
Bits [2–0]—PR2–PR0 Priority → These bits define the priority of the timer interrupt in
relation to other interrupt signals. The interrupt priority is the lowest at 7 at reset. The
values of PR2–PR0 are shown above.
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5.1.39 T2INTCON (03ah), T1INTCON (038h), and T0INTCON (032h) (Slave Mode)
Timer INTerrupt CONtrol Register. The three timers, Timer 2, Timer 1, and Timer 0, each have
an interrupt control register, whereas in master mode all three are masked and prioritized in one
register (TCUCON). The value of these registers is 000Fh at reset (see Table 61).
Table 61. Timer Interrupt Control Register
15
14
13
12
11 10 9
Reserved
8
7
6
5
4
3
MSK
2 1 0
PR2–PR0
Bits [15–4]—Reserved → Set to 0.
Bit [3]—MSK Mask → Any of the interrupt sources may cause an interrupt if the MSK
bit is 0. If 1, they cannot. The Interrupt Mask Register has a duplicate of this bit.
Bits [2–0]—PR2–PR0 Priority → These bits define the priority of the timer interrupts in
relation to other interrupt signals. The interrupt priority is the lowest at 7 at reset. The
values of PR2–PR0 are shown above.
5.1.40 DMA1CON (036h) and DMA0CON (034h) (Master Mode)
DMA CONtrol Register. The DMA0 and DMA1 interrupts have interrupt type 0ah and 0bh,
respectively. The value of these registers is 000Fh at reset (see Table 62).
Table 62. DMA Interrupt Control Register (Master Mode)
15
14
13
12
11 10 9
Reserved
8
7
6
5
4
3
MSK
2 1 0
PR2–PR0
Bits [15–4]—Reserved → Set to 0.
Bit [3]—MSK Mask → Any of the interrupt sources may cause an interrupt if the MSK
bit is 0. If 1, they cannot. The Interrupt Mask Register has a duplicate of this bit.
Bits [2–0]—PR2–PR0 Priority → These bits define the priority of the DMA interrupts in
relation to other interrupt signals. The interrupt priority is the lowest at 7 at reset. The
values of PR2–PR0 are shown above.
5.1.41 DMA1CON (036h) and DMA0CON (034h) (Slave Mode)
DMA CONtrol Register. The two DMA control registers maintain their original functions and
addressing that they possessed in Master Mode. The value of these registers is 000Fh at reset
(see Table 63).
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Table 63. DMA and Interrupt Control Register (Slave Mode)
15
14
13
12
11 10 9
Reserved
8
7
6
5
4
3
MSK
2 1 0
PR2–PR0
Bits [15–4]—Reserved → Set to 0.
Bit [3]—MSK Mask → Any of the interrupt sources may cause an interrupt if the MSK
bit is 0. If 1, they cannot. The Interrupt Mask Register has a duplicate of this bit.
Bits [2–0]—PR2–PR0 Priority → These bits define the priority of the DMA interrupts in
relation to other interrupt signals. The interrupt priority is the lowest at 7 at reset. The
values of PR2–PR0 are shown above.
5.1.42 INTSTS (030h) (Master Mode)
INTerrupt STatuS Register. The Interrupt status register contains the interrupt request status of
each of the three timers, Timer 2, Timer 1, and Timer 0 (see Table 64).
Table 64. Interrupt Status Register (Master Mode)
15
DHLT
14
13
12
11
10 9 8
Reserved
7
6
5
4
3
2
1
0
TMR2–TMR0
Bit [15]—DHLT DMA Halt → DMA activity is halted when this bit is 1. It is set to 1
automatically when any non-maskable interrupt occurs and is cleared to 0 when an IRET
instruction is executed. Interrupt handlers and other time-critical software may modify
this bit directly to disable DMA transfers. However, the DHLT bit should not be
modified by software if the timer interrupts are enabled as the function of this register
because an interrupt request register for the timers would be compromised.
Bits [14–3]—Reserved.
Bits [2–0]—TMR2–TMR0 Timer Interrupt Request → A pending interrupt request is
indicated by the corresponding timer, when any of these bits is 1.
Note: The TMR bit in the REQST register is a logical OR of these timer
interrupt requests.
5.1.43 INTSTS (030h) (Slave Mode)
When nonmaskable interrupts occur, the interrupt status register controls DMA operation and the
interrupt request status of each of the three timers, Timer 2, Timer 1, and Timer 0 (see Table 65).
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Table 65. Interrupt Status Register (Slave Mode)
15
DHLT
14
13
12
11
10 9 8
Reserved
7
6
5
4
3
2
1
0
TMR2–TMR0
Bit [15]—DHLT DMA Halt → DMA activity is halted when this bit is 1. It is set to 1
automatically when any non-maskable interrupt occurs and is cleared to 0 when an IRET
instruction is executed.
Bits [14–3]—Reserved.
Bits [2–0]—TMR2–TMR0 Timer Interrupt Request → A pending interrupt request is
indicated by the corresponding timer, when any of these bits is 1.
Note: The TMR bit in the REQST register is a logical OR of these timer
interrupt requests.
5.1.44 REQST (02eh) (Master Mode)
Interrupt REQueST Register. This is a read-only register and such a read results in the status of
the interrupt request bits presented to the interrupt controller. The REQST register is undefined
on reset (see Table 66).
Table 66. Interrupt Request Register (Master Mode)
15
14 13 12
Reserved
11
10
SPI
9
WD
8
7
6 5
I4–I0
4
3
2
D1–D0
1
Reserved
0
TMR
Bits [15–11]—Reserved.
Bit [10]—SPI Serial Port Interrupt Request → This is the serial port interrupt state and
when enabled is the logical OR of all the serial port 0 interrupt sources, THRE, RDR,
BRKI, FER, PER, and OER.
Bit [9]—WD Watchdog Timer Interrupt Request → When it is a 1, the watchdog
interrupt state indicates that an interrupt is pending.
Bits [8–4]—I4–I0 Interrupt Requests → When set to 1 indicates that the relevant
interrupt has a pending interrupt.
Bits [3–2]—D1–D0 DMA Channel Interrupt Request → When set to 1 indicates that the
respective DMA channel has a pending interrupt.
Bit [1]—Reserved.
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Bit [0]—TMR Timer Interrupt Request → This is the timer interrupt state and is the
logical OR of the timer interrupt requests. When set to 1 indicates that the timer control
unit has a pending interrupt.
5.1.45 REQST (02eh) (Slave Mode)
This is a read-only register and such a read results in the status of the interrupt request bits
presented to the interrupt controller.
When an internal interrupt request (D1, D0, TMR2, TMR1, or TMR0) occurs, the respective bit
is set to 1. The internally generated interrupt acknowledge resets these bits. The REQST
register contains 0000h on reset (see Table 67).
Table 67. Interrupt Request Register (Slave Mode)
15
14
13
12 11 10
Reserved
9
8
7
6
5
TMR2
4
TMR1
3
2
D1–D0
1
Reserved
0
TMR0
Bits [15–6]—Reserved.
Bit [5]—TMR2 Interrupt Requests → When set to 1 indicates that Timer 2 has a pending
interrupt.
Bit [4]—TMR1 Interrupt Requests → When set to 1 indicates that Timer 1 has a pending
interrupt.
Bits [3–2]—D1–D0 DMA Channel Interrupt Request → When set to 1 indicates that the
respective DMA channel has a pending interrupt.
Bit [1]—Reserved.
Bit [0]—TMR0 Timer Interrupt Request → When set to 1 indicates that Timer 0 has a
pending interrupt.
5.1.46 INSERV (02ch) (Master Mode)
IN-SERVice Register. The interrupt controller sets the bits in this register when the interrupt is
taken. Writing the corresponding interrupt type to the End-of-Interrupt (EOI) register clears each
of these bits.
When one of these bits is set, an interrupt request will not be generated by the microcontroller for
the respective source. This prevents an interrupt from interrupting itself if interrupts are enabled
in the ISR. This restriction is bypassed in Special Fully nested mode for the int0 and int1
sources. The INSERV register contains 0000h on reset (see Table 68).
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Table 68. In-Service Register (Master Mode)
15
14 13 12
Reserved
11
10
SPI
9
WD
8
7
6 5
I4–I0
4
3
2
D1–D0
1
Reserved
0
TMR
Bits [15–11]—Reserved.
Bit [10]—SPI Serial Port Interrupt Request → This is the serial port 0 interrupt state.
Bit [9]—WD Watchdog Timer Interrupt In-Service Request → This bit is the In-Service
state of the Watchdog Timer.
Bits [8–4]—I4–I0 Interrupt Requests → These bit indicate that the corresponding
interrupt has a pending interrupt.
Bits [3–2]—D1–D0 DMA Channel Interrupt In-Service → This bit is the In-Service state
of the respective DMA channel.
Bit [1]—Reserved.
Bit [0]—TMR Timer Interrupt Request → This is the timer interrupt state and is the
logical OR of the timer interrupt requests. When set to 1 indicates that the timer control
unit has a pending interrupt.
5.1.47 INSERV (02ch) (Slave Mode)
This is a read-only register and such a read supplies the status of the interrupt request bits
presented to the interrupt controller.
When an internal interrupt request (D1, D0, TMR2, TMR1, and TMR0) is serviced, the
respective bit is set to 1. The in-service bits are reset by writing to the EOI register. The
INSERV register contains 0000h on reset (see Table 69).
Table 69. In-Service Register (Slave Mode)
15
14
13
12 11 10
Reserved
9
8
7
6
5
TMR2
4
TMR1
3
2
D1–D0
1
Reserved
0
TMR0
Bits [15–6]—Reserved.
Bit [5]—TMR2 Timer 2 Interrupt In Service → Timer 2 is being serviced when this bit is
set to 1.
Bit [4]—TMR1 Timer 1 Interrupt In Service → Timer 1 is being serviced when this bit is
set to 1.
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Bits [3–2]—D1–D0 DMA Channel Interrupt In Service → The respective DMA channel
is being serviced when this bit is set to 1.
Bit [1]—Reserved.
Bit [0]—TMR0 Timer Interrupt In Service → Timer 0 is being serviced when this bit is
set to 1.
5.1.48 PRIMSK (02ah) (Master and Slave Mode)
PRIority MaSK Register. This register contains a value that sets the minimum priority level at
which an interrupt can be generated by a maskable interrupt. The PRIMSK register contains
0007h on reset (see Table 70).
Table 70. Priority Mask Register
15
14
13
12
11 10 9 8
Reserved
7
6
5
4
3
2
1
0
PRM2–PRM0
Bits [15–3]—Reserved → Set to 0.
Bits [2–0]—PRM2–PRM0 Priority Field Mask → This three-bit field sets the minimum
priority necessary for a maskable interrupt to generate an interrupt. Any maskable
interrupt with a numerically higher value than that contained by these three bits is
masked. The values of PR2–PR0 are shown below.
Values of PR2–PR0 by Priority
Priority
PR2–PR0
(High) 0
000b
1
001b
2
010b
3
011b
4
100b
5
101b
6
110b
(Low) 7
111b
Any unmasked interrupt can generate an interrupt if the priority level is set to 7. On the
other hand, if the priority level is set to 4, only unmasked interrupts with a priority of 0 to
4 are permitted to generate interrupts.
5.1.49 IMASK (028h) (Master Mode)
Interrupt MASK Register. The interrupt mask register is read/write. Setting a bit in this register
sets the MSK bit in the corresponding interrupt control register. Setting a bit to 1 masks the
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interrupt. The interrupt request is enabled when the corresponding bit is set to 0. The IMASK
register contains 07fdh on reset (see Table 71).
Table 71. Interrupt MASK Register (Master Mode)
15
14 13 12
Reserved
11
10
SPI
9
WD
8
7
6 5
I4–I0
4
3
2
D1–D0
1
Reserved
0
TMR
Bits [15–11]—Reserved.
Bit [10]—SPI Serial Port Interrupt Mask → Setting this bit to 1 indicates that the
asynchronous serial port interrupt is masked.
Bit [9]—WD Watchdog Timer Interrupt In-Service Request → Setting this bit to 1
indicates that the Watchdog Timer interrupt is masked.
Bits [8–4]—I4–I0 Interrupt Mask → Setting any of these bits to 1 indicates that the
relevant interrupt is masked.
Bits [3–2]—D1–D0 DMA Channel Interrupt Mask → Setting this bit to 1 indicates that
the respective DMA channel interrupt is masked.
Bit [1]—Reserved.
Bit [0]—TMR Timer Interrupt Mask → When set to 1, it indicates that the timer control
unit interrupt is masked.
5.1.50 IMASK (028h) (Slave Mode)
Interrupt MASK Register. The interrupt mask register is read/write. Setting a bit in this register
sets the MSK bit in the corresponding interrupt control register. Setting a bit to 1 masks the
interrupt request. The interrupt request is enabled when the corresponding bit is set to 0. The
IMASK register contains 003dh on reset (see Table 72).
Table 72. Interrupt MASK Register (Slave Mode)
15
14
13
12 11 10
Reserved
9
8
7
6
5
TMR2
4
TMR1
3
2
D1–D0
1
Reserved
0
TMR0
Bits [15–6]—Reserved.
Bit [5]—TMR2 Timer 2 Interrupt Mask → This bit indicates the state of the mask bit in
the Timer Interrupt Control register. When set to 1, it indicates that the interrupt request
is masked.
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Bit [4]—TMR1 Timer 1 Interrupt Mask → This bit indicates the state of the mask bit in
the Timer Interrupt Control register. When set to 1, it indicates that the interrupt request
is masked.
Bits [3–2]—D1–D0 DMA Channel Interrupt Mask → This bit indicates the state of the
mask bit in the respective DMA channel Interrupt Control register. When set to 1, it
indicates that the interrupt request is masked.
Bit [1]—Reserved.
Bit [0]—TMR0 Timer Interrupt Mask → This bit indicates the state of the mask bit in the
Timer Interrupt Control register. When set to 1, it indicates that the interrupt request is
masked.
5.1.51 POLLST (026h) (Master Mode)
POLL STatus Register. This register reflects the current state of the Poll register and can be read
without affecting its contents. However, when the Poll Register is read, it causes the current
interrupt to be acknowledged and replaced by the next interrupt. The poll status register is readonly (see Table 73).
Table 73. POLL Status Register
15
IREQ
14
13
12
11 10 9
Reserved
8
7
6
5
4
3 2 1
S4–S0
0
Bit [15]—IREQ Interrupt Request → This bit is set to 1 when an interrupt is pending.
During this state the S4–S0 bits contain valid data.
Bits [14–5]—Reserved.
Bits [4–0]—S4–S0 Poll Status → These bits show the interrupt type of the highest
priority pending interrupt.
The interrupt service routine does not begin execution automatically with the IS bit set. Rather,
the application software must execute the appropriate ISR.
5.1.52 POLL (024h) (Master Mode)
POLL Register. When the Poll Register is read, it causes the current interrupt to be
acknowledged and be replaced by the next interrupt. The poll status register reflects the current
state of the Poll register and can be read without affecting its contents. The POLL register is
read-only (see Table 74).
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Table 74. Poll Register
15
IREQ
14
13
12
11 10 9
Reserved
8
7
6
5
4
3 2 1
S4–S0
0
Bit [15]—IREQ Interrupt Request → This bit is set to 1 when an interrupt is pending.
During this state, the S4–S0 bits contain valid data.
Bits [14–5]—Reserved.
Bits [4–0]—S4–S0 Poll Status → These bits show the interrupt type of the highest
priority pending interrupt.
5.1.53 EOI (022h) End-Of-Interrupt Register (Master Mode)
The In Service flags of the In-Service register are reset when a write is made to the EOI register.
The interrupt service routine (ISR) should write to the EOI to reset the IS bit in the In-Service
register for the interrupt before executing an IRET instruction that ends an interrupt service
routine. Because it is most secure, the specific EOI reset is the preferred method for resetting the
IS bits. The EOI register is write-only (see Table 75).
Table 75. End-of-Interrupt Register
15
NSPEC
14
13
12
11 10 9
Reserved
8
7
6
5
4
3 2 1
S4–S0
0
Bit [15]—NSPEQ Non-Specific EOI → When set to 1, this bit is a non-specific EOI.
When 0, it indicates the specific EOI.
Bits [14–5]—Reserved.
Bits [4–0]—S4–S0 Source Interrupt Type → These bits show the interrupt type of the
interrupt being handled.
5.1.54 EOI (022h) Specific End-Of-Interrupt Register (Slave Mode)
A write clears the specific in-service flag indicated by L2-L0. The EOI register is write-only and
undefined at reset (see Table 76).
Table 76. Specific End-of-Interrupt Register
15
14
13
12
11 10 9 8
Reserved
7
6
5
4
3
2
1 0
L2–L0
Bits [15–3]—Reserved → Write as 0.
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Bits [2–0]—L2–L0 Interrupt Type → The priority or the IS (interrupt service) bit to be
reset is encoded in these three bits. Writing to these bits caused the issuance of an EOI
for the interrupt type (see Table 14, Interrupt Types).
5.1.55 INTVEC (020h) Interrupt Vector Register (Slave Mode)
The CPU shifts left 2 bits (multiplies by 4) an 8-bit interrupt type, generated by the interrupt
controller, to produce an offset into the interrupt vector table. The INTVEC register is undefined
at reset (see Table 77).
Table 77. Interrupt Vector Register
15
14
13
12 11
Reserved
10
9
8
7
6 5 4
T4–T0
3
2 1 0
Reserved
Bits [15–8]—Reserved → Read as 0.
Bits [7–3]—T4–T0 Interrupt Type → These five bits contain the five most significant bits
of the interrupt types used for the internal interrupt type. The least significant three bits
of the interrupt type are supplied by the interrupt controller, as set by the priority level of
the interrupt request.
Bits [2–0]—Reserved → Read as 0.
5.1.56 SSR (018h)
Synchronous Serial Receive Register. This register holds the serial data received on the SSI
port. The value of the SSR register is undefined at reset (see Table 78).
Table 78. Synchronous Serial Receive Register
15
14
13
12 11
Reserved
10
9
8
7
6
5
4 3 2
SR7-SR0
1
0
Bits [15–8]—Reserved.
Bits [7–0]—SR7–SR0 → Data received over the SDATA pin.
5.1.57 SSD0 (016h) and SSD1 (014h)
Synchronous Serial Transmit Registers. These registers hold the data to be transmitted by the
SSI ports. The value of these registers is undefined at reset (see Table 79).
Table 79. Synchronous Serial Transmit Registers
15
14
13
12 11
Reserved
10
9
8
7
6
5
4 3 2
SD7–SD0
1
0
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Bits [15–8]—Reserved.
Bits [7–0]—SD7–SD0 → Data to be transmitted over the SDATA pin.
5.1.58 SSC (012h)
Synchronous Serial Control Register. This register controls the operation of the sden1 and sden0
outputs and the baud rate of the SSI port. The sden1 and sden0 outputs are held high when the
respective bit is set to 1, but in the event that both DE1 and DE0 are set to 1 then only sden0 will
be held high. The value of the SSR register is 0000h at reset (see Table 80).
Table 80. Synchronous Serial Control Registers
15
14
13
12 11 10
Reserved
9
8
7
6
5
4
SCLKDIV
3
2
Reserved
1
DE1
0
DE0
Bits [15–6]—Reserved.
Bits [5–4]—SCLKDIV SCLK Divide → These bits set the SCLK frequency. SCLK is
the result of dividing the internal processor clock by 2, 4, 8, or 16 as shown below.
SCLKDIV
00b
01b
10b
11b
SCLK Frequency Divider
Processor Clock/2
Processor Clock/4
Processor Clock/8
Processor Clock/16
Bits [3–2]—Reserved.
Bit [1]—DE1 SDEN1 → The SDEN1 bit is held high when this bit is set to 1 and SDEN1
is held low when this bit is set to 0.
Bit [0]—DE0 SDEN0 → The SDEN0 bit is held high when this bit is set to 1 and SDEN0
is held low when this bit is set to 0.
5.1.59 SSS (010h)
Synchronous Serial Status Register. This is a read-only register that indicates the state of the SSI
port. The value of the SSR register is 0000h at reset (see Table 81).
Table 81. Synchronous Serial Status Registers
15
14
13
12
11
10 9 8
Reserved
7
6
5
4
3
2
RE/TE
1
DR/DT
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Bits [15–3]—Reserved.
Bit [2]—RE/TE Receive/Transmit Error Detect → This bit is set to 1 when a read of the
Synchronous Serial Received register or a write to one of the transmit register is detected
while the interface is busy (PB = 1). This bit is reset to 0 when the SDEN output is not
active (DE1–DE0 in the SSC register are 00h).
Bit [1]—DR/DT Data Receive/Transmit Complete → This bit is set to a 1 when the
transmission of data Bit [7] is completed (SCLK rising edge) during a transmit or receive
operation. This bit is reset by a read of the SSR register, when either the SSD0 or SSD1
register is written, when the SSS register is read (unless the SSI completes an operation
and sets the bit in the same cycle), or when both SDEN0 and SDEN1 become inactive.
Bit [0]—PB SSI Port Busy → This bit indicates that a data transmit or receive is
occurring when it is set to 1. When set to 0, it indicates that the port is ready to transmit
or receive data.
5.2
Reference Documents
Additional information on the operation and programming of the IA186ER/ IA188ER can be
found in the following Advanced Micro Devices (AMD) publications:
Am186 ER and Am188 ER Microcontrollers User’s Manual, March 1998, Publication
21684, Rev B, Amendment/1.
Am186 ER and Am188
Amendment 0.
6.
ER Data Sheet, June 2000, Publication 20732, Rev. D,
AC Specifications
Table 82 presents the AC characteristics over industrial operating ranges (50 MHz). Tables 83
and 84 present the alphabetic and numeric keys to waveform parameters, respectively. Figure 11
presents the read cycle. Figure 12 presents the multiple read cycles. Table 85 presents the read
cycle timing. Figure 13 presents the write cycle. Figure 14 presents the multiple write cycles.
Table 86 presents the write cycle timing.
Figure 15 presents the PSRAM read cycle. Table 87 presents the PSRAM read cycle timing.
Figure 16 presents the PSRAM write cycle. Table 88 presents the PSRAM write cycle timing.
Figure 17 presents the PSRAM refresh cycle. Table 89 presents the PSRAM refresh cycle
timing. Figure 18 presents the interrupt acknowledge cycle. Table 90 presents the interrupt
acknowledge cycle timing. Figure 19 presents the software halt cycle. Table 91 presents the
software halt cycle timing. Figure 20 presents the clock—active mode. Figure 21 presents the
clock—power-save mode. Table 92 presents the clock timing.
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Figure 22 presents the srdy—synchronous ready. Figure 23 presents the ardy—asynchronous
ready. Figure 24 presents the peripherals. Table 93 presents the ready and peripheral timing.
Figures 25 and 26 present Reset 1 and Reset 2, respectively. Figures 27 and 28 present the bus
hold entering and bus hold leaving, respectively. Table 94 presents the reset and bus hold
timing.
Figure 29 presents the synchronous serial interface. Table 95 presents the synchronous serial
interface timing.
Table 82. AC Characteristics Over Industrial Operating Ranges (50 MHz)
No.
Name
Description
General Timing Requirements
1 tDVCL
Data in Setup
2 tCLDX
Data in Hold
General Timing Responses
3 tCHSV
Status Active Delay
4 tCLSH
Status Inactive Delay
ad Address Valid Delay
5 tCLAV
6 tCLAX
Address Hold
8 tCHDX
Status Hold Time
9 tCHLH
ale Active Delay
10 tLHLL
ale Width
11 tCHLL
ale Inactive Delay
ad Address Valid to ale Low
12 tAVLL
ad Address Hold from ale Inactive
13 tLLAX
ad Address Valid to Clock High
14 tAVCH
ad Address Float Delay
15 tCLAZ
16 tCLCSV
mcs_n/pcs_n Inactive Delay
17 tCXCSX
mcs_n/pcs_n Hold from Command Inactive
18 tCHCSX
mcs_n/pcs_n Inactive Delay
19 tDXDL
den_n Inactive to dt/r_n Low
20 tCVCTV
Control Active Delay 1
21 tCVDEX
den_n Inactive Delay
22 tCHCTV
Control Active Delay 2
23 tLHAV
ale High to Address Valid
80 tCLCLX
lcs_n Inactive Delay
81 tCLCSL
lcs_n Active Delay
82 tCLRF
clkouta High to rfsh_n Invalid
84 tLRLL
lcs_n Precharge Pulse Width
a
All values are in nanoseconds, except where otherwise indicated.
a
Min
Max
6.6
2
–
–
0
0
0
0
0
0
tCLCH-5
0
tCLCH
tCHCL
0
0
0
tCLCH
0
0
0
0
0
7.5
0
0
0
tCLCL + tCLCH
10
10
10
10
–
10
–
10
–
–
–
15
10
–
10
–
10
14
10
–
10
10
10
–
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Table 82. AC Characteristics Over Industrial Operating Ranges (50 MHz) (Continued)
No.
Name
Description
Read Cycle Timing Responses
ad Address Float to rd_n Active
24 tAZRL
25 tCLRL
rd_n Active Delay
26 tRLRH
rd_n Pulse Width
27 tCLRH
rd_n Inactive Delay
28 tRHLH
rd_n Inactive to ale High
rd_n Inactive to ad Address Active
29 tRHAV
30 tCLDOX
Data Hold Time
Write Cycle Timing Responses
31 tCVCTX
Control Inactive Delay
32 tWLWH
wr_n Pulse Width
33 tWHLH
wr_n Inactive to ale High
34 tWHDX
Data Hold after wr_n
35 tWHDEX wr_n Inactive to den_n Inactive
41 tDSHLH
ds_n Inactive to ale Inactive
rd_n High to Data Hold on ad Bus
59 tRHDX
a Address Valid to wr_n Low
65 tAVWL
a Address Valid to rd_n Low
66 tAVRL
67 tCHCSV
clkouta High to lcs_n/usc_n Valid
clkouta High to a Address Valid
68 tCHAV
a Address Valid to whb_n/wlb_n Low
87 tAVBL
Refresh Timing Cycle Parameters
79 tCHRFD
clkouta High to rfsh_n Valid
82 tCLRF
clkouta High to rfsh_n Invalid
85 tRFCY
rfsh_n Cycle Time
86 tLCRF
lcs_n Inactive to rfsh_n Active Delay
clkin Timing (Times Four Mode)
36 tCKIN
x1 Period
37 tCLCK
x1 Low Time
38 tCHCK
x1 High Time
39 tCKHL
x1 Fall Time
40 tCKLH
x1 Rise time
clkout Timing (Times Four Mode)
42 tCLCL
clkouta Period
43 tCLCH
clkouta Low Time
44 tCHCL
clkouta High Time
45 tCH1CH2 clkouta Rise Time
46 tCL2CL1
clkouta Fall Time
61 tLOCK
Maximum PLL Lock Time
69 tCICOA
x1 to clkouta Skew
70 tCICOB
x1 to clkoutb Skew
a
Max
0
0
tCLCL
0
tCLCH
tCLCL
0
–
10
–
10
–
–
–
0
2tCLCL
tCLCH
tCLCL
tCLCH
tCLCH
0
tCLCL + tCHCL
tCLCL + tCHCL
0
0
tCHCL -1.5
10
–
–
–
–
–
–
–
–
10
10
tCHCL
0
0
6tCLCL
2tCLCL
12
12
–
–
80
35
35
–
–
125
–
–
5
5
20
9
9
–
–
–
–
–
–
–
–
3
3
1 ms
15
21
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Table 82. AC Characteristics Over Industrial Operating Ranges (50 MHz) (Continued)
No.
Name
Description
Ready and Peripheral Timing Requirements
47 tSRYCL
srdy Transition Setup Time
48 tCLSRY
srdy Transition Hold Time
49 tARYCH
ardy Resolution Transition Setup Time
50 tCLARX
ardy Active Hold Time
51 tARYCHL ardy Inactive Holding Time
52 tARYLCL ardy Setup Time
53 tINVCH
Peripheral Setup Time
54 tINVCL
drq Setup Time
Peripheral Timing Responses
55 tCLTMV
Timer Output Delay
Reset & Hold Timing Requirements
57 tRESIN
res_n Setup Time
58 tHVCL
hld Setup Time
Reset and Hold Timing Responses
62 tCLHAV
hlda Valid Delay
63 tCHCZ
Command Lines Float Delay
64 tCHCV
Command Lines Valid Delay (after Float)
Synchronous Serial Port Timing Requirements
75 tDVSH
Data Valid to sclk High
77 tSHDX
sclk High to SPI Data Hold
Synchronous Serial Port Timing Responses
71 tCLEV
clkouta Low to sden Valid
72 tCLSL
clkouta Low to sclk High
78 tSLDV
sclk Low to Data Valid
a
Min
Max
5
2
5
3
5
5
5
5
–
–
–
–
–
–
–
–
0
10
10
10
–
–
0
0
0
10
10
10
10
3
–
–
0
0
0
10
10
10
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Table 83. Alphabetic Key to Waveform Parameters
No.
Name
Description
49
51
52
87
14
12
66
65
24
45
68
38
44
67
18
22
64
63
8
9
11
79
3
69
70
39
36
40
46
50
5
6
15
43
37
42
80
81
16
30
tARYCH
tARYCHL
tARYLCL
tAVBL
tAVCH
tAVLL
tAVRL
tAVWL
tAZRL
tCH1CH2
tCHAV
tCHCK
tCHCL
tCHCSV
tCHCSX
tCHCTV
tCHCV
tCHCZ
tCHDX
tCHLH
tCHLL
tCHRFD
tCHSV
tCICOA
tCICOB
tCKHL
tCKIN
tCKLH
tCL2CL1
tCLARX
tCLAV
tCLAX
tCLAZ
tCLCH
tCLCK
tCLCL
tCLCLX
tCLCSL
tCLCSV
tCLDOX
ardy Resolution Transition Setup Time
ardy Inactive Holding Time
ardy Setup Time
a Address Valid to whb_n/wlb_n Low
ad Address Valid to Clock High
ad Address Valid to ale Low
a Address Valid to rd_n Low
a Address Valid to wr_n Low
ad Address Float to rd_n Active
clkouta Rise Time
clkouta High to a Address Valid
x1 High Time
clkouta High Time
clkouta High to lcs_n/usc_n Valid
mcs_n/pcs_n Inactive Delay
Control Active Delay 2
Command Lines Valid Delay (after Float)
Command Lines Float Delay
Status Hold Time
ale Active Delay
ale Inactive Delay
clkouta High to rfsh_n Valid
Status Active Delay
x1 to clkouta Skew
x1 to clkoutb Skew
x1 Fall Time
x1 Period
x1 Rise time
clkouta Fall Time
ardy Active Hold Time
ad Address Valid Delay
Address Hold
ad Address Float Delay
clkouta Low Time
x1 Low Time
clkouta Period
lcs_n Inactive Delay
lcs_n Active Delay
mcs_n/pcs_n Inactive Delay
Data Hold Time
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Table 83. Alphabetic Key to Waveform Parameters (Continued)
No.
Name
Description
7
2
71
62
82
27
25
4
72
48
55
83
20
31
21
17
1
75
19
58
53
54
86
23
10
13
61
84
57
85
29
59
28
26
77
78
47
35
34
33
32
tCLDV
tCLDX
tCLEV
tCLHAV
tCLRF
tCLRH
tCLRL
tCLSH
tCLSL
tCLSRY
tCLTMV
tCOAOB
tCVCTV
tCVCTX
tCVDEX
tCXCSX
tDVCL
tDVSH
tDXDL
tHVCL
tINVCH
tINVCL
tLCRF
tLHAV
tLHLL
tLLAX
tLOCK
tLRLL
tRESIN
tRFCY
tRHAV
tRHDX
tRHLH
tRLRH
tSHDX
tSLDV
tSRYCL
tWHDEX
tWHDX
tWHLH
tWLWH
Data Valid Delay
Data in Hold
clkouta Low to sden Valid
hlda Valid Delay
clkouta High to rfsh_n Invalid
rd_n Inactive Delay
rd_n Active Delay
Status Inactive Delay
clkouta Low to sclk Low
srdy Transition Hold Time
Timer Output Delay
clkouta to clkoutb Skew
Control Active Delay 1
Control Inactive Delay
den_n Inactive Delay
mcs_n/pcs_n Hold from Command Inactive
Data in Setup
Data Valid to SCLK High
den_n Inactive to dt/r_n Low
hld Setup Time
Peripheral Setup Time
drq Setup Time
lcs_n Inactive to rfsh_n Active Delay
ale High to Address Valid
ale Width
ad Address Hold from ALE Inactive
Maximum PLL Lock Time
lcs_n Precharge Pulse Width
res_n Setup Time
rfsh_n Cycle Time
rd_n Inactive to ad Address Active
rd_n High to Data Hold on ad Bus
rd_n Inactive to ale High
rd_n Pulse Width
sclk High to SPI Data Hold
sclk Low SPI Data Hold
srdy Transition Setup Time
wr_n Inactive to den_n Inactive
Data Hold after wr_n
wr_n Inactive to ale High
wr_n Pulse Width
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Table 84. Numeric Key to Waveform Parameters
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Name
tDVCL
tCLDX
tCHSV
tCLSH
tCLAV
tCLAX
tCLDV
tCHDX
tCHLH
tLHLL
tCHLL
tAVLL
tLLAX
tAVCH
tCLAZ
tCLCSV
tCXCSX
tCHCSX
tDXDL
tCVCTV
tCVDEX
tCHCTV
tLHAV
tAZRL
tCLRL
tRLRH
tCLRH
tRHLH
tRHAV
tCLDOX
tCVCTX
tWLWH
tWHLH
tWHDX
tWHDEX
tCKIN
tCLCK
tCHCK
tCKHL
tCKLH
Description
Data in Setup
Data in Hold
Status Active Delay
Status Inactive Delay
ad Address Valid Delay
Address Hold
Data Valid Delay
Status Hold Time
ale Active Delay
ale Width
ale Inactive Delay
ad Address Valid to ALE Low
ad Address Hold from ALE Inactive
ad Address Valid to Clock High
ad Address Float Delay
mcs_n/pcs_n Inactive Delay
mcs_n/pcs_n Hold from Command Inactive
mcs_n/pcs_n Inactive Delay
den_n Inactive to dt/r_n Low
Control Active Delay 1
den_n Inactive Delay
Control Active Delay 2
ale High to Address Valid
ad Address Float to rd_n Active
rd_n Active Delay
rd_n Pulse Width
rd_n Inactive Delay
rd_n Inactive to ale High
rd_n Inactive to ad Address Active
Data Hold Time
Control Inactive Delay
wr_n Pulse Width
wr_n Inactive to ale High
Data Hold after wr_n
wr_n Inactive to den_n Inactive
x1 Period
x1 Low Time
x1 High Time
x1 Fall Time
x1 Rise time
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Table 84. Numeric Key to Waveform Parameters (Continued)
No. Name
Description
42 tCLCL
clkouta Period
43 tCLCH
clkouta Low Time
44 tCHCL
clkouta High Time
45 tCH1CH2 clkouta Rise Time
46 tCL2CL1
clkouta Fall Time
47 tSRYCL
srdy Transition Setup Time
48 tCLSRY
srdy Transition Hold Time
49 tARYCH
ardy Resolution Transition Setup Time
50 tCLARX
ardy Active Hold Time
51 tARYCHL ardy Inactive Holding Time
52