SN74LVC32373A 32-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCES575 – JUNE 2004 – REVISED AUGUST 2005 FEATURES • • • • • • Member of the Texas Instruments Widebus+™ Family Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V Max tpd of 4.2 ns at 3.3 V Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C • • • • Ioff Supports Partial-Power-Down Mode Operation Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC) Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 1000-V Charged-Device Model (C101) DESCRIPTION/ORDERING INFORMATION This 32-bit transparent D-type latch is designed for 1.65-V to 3.6-V VCC operation. The SN74LVC32373A is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. It can be used as four 8-bit latches, two 16-bit latches, or one 32-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. ORDERING INFORMATION PACKAGE (1) TA –40°C to 85°C (1) LFBGA – GKE LFBGA – ZKE (Pb-free) Tape and reel ORDERABLE PART NUMBER SN74LVC32373AGKER SN74LVC32373AZKER TOP-SIDE MARKING NC373A Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus+ is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004–2005, Texas Instruments Incorporated SN74LVC32373A 32-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCES575 – JUNE 2004 – REVISED AUGUST 2005 GKE OR ZKE PACKAGE (TOP VIEW) 1 2 3 4 5 6 A B C D E F G H J K L M N P R T TERMINAL ASSIGNMENTS 2 1 2 A 1Q2 1Q1 B 1Q4 1Q3 C 1Q6 1Q5 D 1Q8 E F 3 4 5 6 1OE 1LE 1D1 1D2 GND GND 1D3 1D4 VCC VCC 1D5 1D6 1Q7 GND GND 1D7 1D8 2Q2 2Q1 GND GND 2D1 2D2 2Q4 2Q3 VCC VCC 2D3 2D4 G 2Q6 2Q5 GND GND 2D5 2D6 H 2Q7 2Q8 2OE 2LE 2D8 2D7 J 3Q2 3Q1 3OE 3LE 3D1 3D2 K 3Q4 3Q3 GND GND 3D3 3D4 L 3Q6 3Q5 VCC VCC 3D5 3D6 M 3Q8 3Q7 GND GND 3D7 3D8 N 4Q2 4Q1 GND GND 4D1 4D2 P 4Q4 4Q3 VCC VCC 4D3 4D4 R 4Q6 4Q5 GND GND 4D5 4D6 T 4Q7 4Q8 4OE 4LE 4D8 4D7 SN74LVC32373A 32-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCES575 – JUNE 2004 – REVISED AUGUST 2005 FUNCTION TABLE INPUTS OE LE D OUTPUT Q L H H H L H L L L L X Q0 H X X Z LOGIC DIAGRAM (POSITIVE LOGIC) 1OE 1LE A3 2OE A4 2LE C1 1D1 A5 A2 1D H3 H4 C1 1Q1 2D1 E5 To Seven Other Channels 3OE 3LE 4OE J4 4LE C1 3D1 1D To Seven Other Channels 2Q1 To Seven Other Channels J3 J5 E2 1D J2 T3 T4 C1 3Q1 4D1 N5 1D N2 4Q1 To Seven Other Channels 3 SN74LVC32373A 32-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCES575 – JUNE 2004 – REVISED AUGUST 2005 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range –0.5 6.5 V VI Input voltage range (2) –0.5 6.5 V –0.5 6.5 V –0.5 VCC + 0.5 state (2) UNIT VO Voltage range applied to any output in the high-impedance or power-off VO Voltage range applied to any output in the high or low state (2) (3) IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±50 mA ±100 mA Continuous current through each VCC or GND θJA Package thermal Tstg Storage temperature range (1) (2) (3) (4) impedance (4) GKE/ZKE package –65 V 40 °C/W 150 °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. The value of VCC is provided in the recommended operating conditions table. The package thermal impedance is calculated in accordance with JESD 51-7. Recommended Operating Conditions (1) VCC Supply voltage VIH High-level input voltage Operating Data retention only VCC = 1.65 V to 1.95 V MIN MAX 1.65 3.6 1.5 Low-level input voltage VI 1.7 VCC = 2.7 V to 3.6 V 2 VO Output voltage 0.35 × VCC 0.7 VCC = 2.7 V to 3.6 V 0.8 0 5.5 High or low state 0 VCC 3-state 0 5.5 VCC = 1.65 V IOH High-level output current Low-level output current ∆t/∆v Input transition rise or fall rate TA Operating free-air temperature (1) 4 V V V –4 VCC = 2.3 V –8 VCC = 2.7 V –12 VCC = 3 V –24 VCC = 1.65 V IOL V VCC = 2.3 V to 2.7 V Input voltage V 0.65 × VCC VCC = 2.3 V to 2.7 V VCC = 1.65 V to 1.95 V VIL UNIT mA 4 VCC = 2.3 V 8 VCC = 2.7 V 12 VCC = 3 V 24 –40 mA 10 ns/V 85 °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. SN74LVC32373A 32-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCES575 – JUNE 2004 – REVISED AUGUST 2005 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = –100 µA VOH 1.65 V to 3.6 V 1.65 V 1.2 IOH = –8 mA 2.3 V 1.7 2.7 V 2.2 3V 2.4 IOH = –24 mA 3V 2.2 IOL = 100 µA 1.65 V to 3.6 V 0.2 IOL = 4 mA 1.65 V 0.45 IOL = 8 mA 2.3 V 0.7 IOL = 12 mA 2.7 V 0.4 3V 0.55 IOL = 24 mA II VI = 0 to 5.5 V UNIT V V 3.6 V ±5 µA Ioff VI or VO = 5.5 V 0 ±10 µA IOZ VO = 0 to 5.5 V 3.6 V ±10 µA ICC ∆ICC (1) (2) MAX VCC – 0.2 IOH = –4 mA IOH = –12 mA VOL MIN TYP (1) VCC VI = VCC or GND IO = 0 3.6 V ≤ VI ≤ 5.5 V (2) One input at VCC – 0.6 V, 40 3.6 V Other inputs at VCC or GND 40 2.7 V to 3.6 V 500 µA µA Ci VI = VCC or GND 3.3 V 5 pF Co VO = VCC or GND 3.3 V 6.5 pF All typical values are at VCC = 3.3 V, TA = 25°C. This applies in the disabled state only. Timing Requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V MIN MAX VCC = 2.7 V MIN MAX MIN MAX VCC = 3.3 V ± 0.3 V UNIT MIN MAX tw Pulse duration, LE high 3.3 3.3 3.3 3.3 ns tsu Setup time, data before LE↓ 1.6 1.2 1.7 1.7 ns th Hold time, data after LE↓ 1 1.1 1.2 1.2 ns Switching Characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) PARAMETER tpd FROM (INPUT) D LE TO (OUTPUT) Q VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V VCC = 2.7 V VCC = 3.3 V ± 0.3 V MIN MAX MIN MAX MIN MAX MIN MAX 1.5 6.4 1 4.2 1 4.9 1.6 4.2 1.5 7.1 1 4.8 1 5.3 2.1 4.6 UNIT ns ten OE Q 1.5 6.7 1 4.7 1 5.7 1.3 4.7 ns tdis OE Q 1.5 8.4 1 5 1 6.3 2.5 5.9 ns 5 SN74LVC32373A 32-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCES575 – JUNE 2004 – REVISED AUGUST 2005 Operating Characteristics TA = 25°C TEST CONDITIONS PARAMETER Cpd 6 Power dissipation capacitance per latch Outputs enabled Outputs disabled f = 10 MHz VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V TYP TYP TYP 32 35 39 4 4 6 UNIT pF SN74LVC32373A 32-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCES575 – JUNE 2004 – REVISED AUGUST 2005 PARAMETER MEASUREMENT INFORMATION VLOAD S1 RL From Output Under Test CL (see Note A) Open GND RL TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 2.7 V 3.3 V ± 0.3 V VI tr/tf VCC VCC 2.7 V 2.7 V ≤2 ns ≤2 ns ≤2.5 ns ≤2.5 ns VM VLOAD CL RL V∆ VCC/2 VCC/2 1.5 V 1.5 V 2 × VCC 2 × VCC 6V 6V 30 pF 30 pF 50 pF 50 pF 1 kΩ 500 Ω 500 Ω 500 Ω 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tw tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM Input VM 0V tPLH VOH Output VM VOL tPHL VM VM 0V Output Waveform 1 S1 at VLOAD (see Note B) tPLH tPLZ VLOAD/2 VM tPZH VOH Output VM tPZL tPHL VM VI Output Control VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VOL + V∆ VOL tPHZ VM VOH - V∆ VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 7 PACKAGE OPTION ADDENDUM www.ti.com 24-Jun-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74LVC32373AGKER ACTIVE LFBGA GKE 96 1000 SN74LVC32373AZKER ACTIVE LFBGA ZKE 96 1000 Green (RoHS & no Sb/Br) TBD Lead/Ball Finish MSL Peak Temp (3) SNPB Level-3-220C-168 HR SNAGCU Level-3-250C-168 HR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. 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