SN74LVTH162373-EP 3.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCBS811A – JULY 2006 – REVISED JULY 2006 FEATURES • • • • • • • • • • • • • (1) Controlled Baseline – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of –55°C to 125°C Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product-Change Notification Qualification Pedigree (1) Member of the Texas Instruments Widebus™ Family Output Ports Have Equivalent 22-Ω Series Resistors, So No External Resistors Are Required Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC) Supports Unregulated Battery Operation Down to 2.7 V Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C Ioff and Power-Up 3-State Support Hot Insertion Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Distributed VCC and GND Pins Minimize High-Speed Switching Noise Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. • • • Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 500 mA Per JESD 17 ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) xxxxxxxxxxxx DL PACKAGE (TOP VIEW) 1OE 1Q1 1Q2 GND 1Q3 1Q4 VCC 1Q5 1Q6 GND 1Q7 1Q8 2Q1 2Q2 GND 2Q3 2Q4 VCC 2Q5 2Q6 GND 2Q7 2Q8 2OE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1LE 1D1 1D2 GND 1D3 1D4 VCC 1D5 1D6 GND 1D7 1D8 2D1 2D2 GND 2D3 2D4 VCC 2D5 2D6 GND 2D7 2D8 2LE xxxx DESCRIPTION/ORDERING INFORMATION The SN74LVTH162373 is a 16-bit transparent D-type latch with 3-state outputs designed for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. This device is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. ORDERING INFORMATION PACKAGE (1) TA –55°C to 125°C (1) SSOP – DL Tape and reel ORDERABLE PART NUMBER CLVTH162373MDLREP TOP-SIDE MARKING LVTH162373EP Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006, Texas Instruments Incorporated SN74LVTH162373-EP 3.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCBS811A – JULY 2006 – REVISED JULY 2006 DESCRIPTION/ORDERING INFORMATION (CONTINUED) A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without interface or pullup components. OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The outputs, which are designed to source or sink up to 12 mA, include equivalent 22-Ω series resistors to reduce overshoot and undershoot. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. This device can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs. FUNCTION TABLE (EACH 8-BIT SECTION) INPUTS OE LE D OUTPUT Q L H H H L H L L L L X Q0 H X X Z LOGIC DIAGRAM (POSITIVE LOGIC) 1OE 1LE 1 2OE 48 2LE C1 1D1 47 1D 2 24 25 C1 1Q1 2D1 36 To Seven Other Channels To Seven Other Channels 2 1D Submit Documentation Feedback 13 2Q1 SN74LVTH162373-EP 3.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCBS811A – JULY 2006 – REVISED JULY 2006 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range –0.5 4.6 V VI Input voltage range (2) –0.5 7 V –0.5 7 V –0.5 VCC + 0.5 state (2) UNIT VO Voltage range applied to any output in the high-impedance or power-off VO Voltage range applied to any output in the high state (2) IO Current into any output in the low state IO Current into any output in the high state (3) IIK Input clamp current VI < 0 IOK Output clamp current VO < 0 –50 mA 63 °C/W 150 °C θJA Package thermal Tstg Storage temperature range (5) (1) (2) (3) (4) (5) impedance (4) –65 V 30 mA 30 mA –50 mA Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. This current flows only when the output is in the high state and VO > VCC. The package thermal impedance is calculated in accordance with JESD 51-7. Long-term high-temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction of overall device life. See http://www.ti.com/ep_quality for additional information on enhanced plastic packaging. Recommended Operating Conditions (1) MIN MAX 2.7 3.6 UNIT VCC Supply voltage VIH High-level input voltage VIL Low-level input voltage VI Input voltage 5.5 V IOH High-level output current –12 mA IOL Low-level output current ∆t/∆v Input transition rise or fall rate 2 ∆t/∆VCC Power-up ramp rate 200 TA –55 (1) V 0.8 Outputs enabled Operating free-air temperature V V 12 mA 10 ns/V µs/V 125 °C All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Submit Documentation Feedback 3 SN74LVTH162373-EP 3.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCBS811A – JULY 2006 – REVISED JULY 2006 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT –1.2 V VIK VCC = 2.7 V, II = –18 mA VOH VCC = 3 V, IOH = –12 mA VOL VCC = 3 V, IOL = 12 mA 0.8 VCC = 0 or 3.6 V, VI = 5.5 V 10 Control inputs VCC = 3.6 V, VI = VCC or GND ±1 Data inputs VCC = 3.6 V II II(hold) Data inputs VCC = 3 V VI = 2 V µA 75 µA –75 5 µA –5 µA VCC = 0 to 1.5 V, VO = 0.5 V to 3 V, OE = don't care ±100 (1) µA VCC = 1.5 V to 0, VO = 0.5 V to 3 V, OE = don't care ±100 (1) µA VO = 3 V VCC = 3.6 V, VO = 0.5 V IOZPU VCC = 3.6 V, IO = 0, VI = VCC or GND ∆ICC V –5 VI = 0.8 V VCC = 3.6 V, (2) 1 VI = 0 IOZL ICC V VI = VCC IOZH IOZPD 2 Outputs high 0.19 Outputs low 5 Outputs disabled mA 0.19 VCC = 3 V to 3.6 V, One input at VCC – 0.6 V, Other inputs at VCC or GND 0.2 mA Ci VI = 3 V or 0 3 pF Co VO = 3 V or 0 9 pF (1) (2) On products compliant to MIL-PRF-38535, this parameter is not production tested. This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND. Timing Requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) VCC = 3.3 V ± 0.3 V MIN 4 tw Pulse duration, LE high tsu Setup time, data before LE↓ th Hold time, data after LE↓ Submit Documentation Feedback MAX VCC = 2.7 V MIN UNIT MAX 3 3 ns 1.3 0.6 ns 1 1.1 ns SN74LVTH162373-EP 3.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCBS811A – JULY 2006 – REVISED JULY 2006 Switching Characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) TO (OUTPUT) D Q LE Q OE Q OE Q Submit Documentation Feedback VCC = 3.3 V ± 0.3 V MIN VCC = 2.7 V MAX MIN UNIT MAX 1.8 5 5.7 1.8 4.4 4.8 2.1 5.4 6.2 2.1 4.9 4.7 1.7 5.6 7 1.7 5.3 5.9 2.3 6.3 6.6 1 7.4 6.4 ns ns ns ns 5 SN74LVTH162373-EP 3.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCBS811A – JULY 2006 – REVISED JULY 2006 PARAMETER MEASUREMENT INFORMATION 500 W From Output Under Test S1 6V Open TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH GND CL = 50 pF (see Note A) 500 W S1 Open 6V GND 2.7 V LOAD CIRCUIT 1.5 V Timing Input 0V tw tsu 2.7 V Input 1.5 V 1.5 V th 2.7 V 1.5 V Data Input 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.7 V 1.5 V Input 1.5 V 0V tPHL tPLH 1.5 V Output 1.5 V VOH VOL tPLH tPHL VOH Output 1.5 V 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 2.7 V Output Control 1.5 V 0V Output Waveform 1 S1 at 6 V (see Note B) Output Waveform 2 S1 at GND (see Note B) tPLZ tPZL 1.5 V 3V VOL + 0.3 V VOL tPHZ tPZH 1.5 V V VOH - 0.3 V OH »0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time, with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 6 1.5 V Submit Documentation Feedback PACKAGE OPTION ADDENDUM www.ti.com 18-Sep-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty CLVTH162373MDLREP ACTIVE SSOP DL 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V62/06654-01XE ACTIVE SSOP DL 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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OTHER QUALIFIED VERSIONS OF SN74LVTH162373-EP : SN74LVTH162373 • Catalog: • Military: SN54LVTH162373 NOTE: Qualified Version Definitions: - TI's standard catalog product • Catalog • Military - QML certified for Military and Defense Applications Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 5-Aug-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device CLVTH162373MDLREP Package Package Pins Type Drawing SSOP DL 48 SPQ Reel Reel Diameter Width (mm) W1 (mm) 1000 330.0 32.4 Pack Materials-Page 1 A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 11.35 16.2 3.1 16.0 32.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 5-Aug-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CLVTH162373MDLREP SSOP DL 48 1000 346.0 346.0 49.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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