TI CD54ACT161

CD54ACT161, CD74ACT161
4-BIT SYNCHRONOUS BINARY COUNTERS
SCHS298 – APRIL 2000
D
D
D
D
D
D
D
D
Inputs Are TTL-Voltage Compatible
Internal Look-Ahead for Fast Counting
Carry Output for n-Bit Cascading
Synchronous Counting
Synchronously Programmable
SCR-Latchup-Resistant CMOS Process and
Circuit Design
Exceeds 2 kV ESD Protection per
MIL-STD-883, Method 3015
Package Options Include Plastic
Small-Outline (M) Standard Plastic (E) and
Ceramic (F) DIPs
CD54ACT161 . . . F PACKAGE
CD74ACT161 . . . E OR M PACKAGE
(TOP VIEW)
CLR
CLK
A
B
C
D
ENP
GND
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
VCC
RCO
QA
QB
QC
QD
ENT
LOAD
description
The CD54ACT161 and CD74ACT161 devices are 4-bit binary counters. These synchronous, presettable
counters feature an internal carry look-ahead for application in high-speed counting designs. Synchronous
operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with
each other when so instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of
operation eliminates the output counting spikes that are normally associated with synchronous (ripple-clock)
counters. A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge of the clock
waveform.
These devices are fully programmable; that is, they can be preset to any number between 0 and 9 or 15.
Presetting is synchronous; therefore, setting up a low level at the load input disables the counter and causes
the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs.
The clear function is asynchronous. A low level at the clear (CLR) input sets all four of the flip-flop outputs low,
regardless of the levels of the CLK, load (LOAD), or enable inputs.
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without
additional gating. Instrumental in accomplishing this function are ENP, ENT, and a ripple-carry output (RCO).
Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a
high-level pulse while the count is maximum (9 or 15 with QA high). This high-level overflow ripple-carry pulse
can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the
level of CLK.
The counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that
modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of
the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the
stable setup and hold times.
The CD54ACT161 is characterized for operation over the full military temperature range of –55°C to 125°C.
The CD74ACT161 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
CD54ACT161, CD74ACT161
4-BIT SYNCHRONOUS BINARY COUNTERS
SCHS298 – APRIL 2000
FUNCTION TABLE
INPUTS
OUTPUTS
CLR
CLK
ENP
ENT
LOAD
A,B,C,D
Qn
RCO
FUNCTION
L
X
X
X
X
X
L
L
H
↑
X
X
l
l
L
L
Reset (clear)
H
↑
X
X
l
h
H
Note 1
H
↑
h
h
h
X
Count
Note 1
H
X
l
X
h
X
Note 1
H
X
X
l
h
X
qn
qn
L
Parallel load
Count
Inhibit
H = high level, L = low level, X = don’t care, h = high level one setup time prior to the CLK
low-to-high transition, l = low level one setup time prior to the CLK low-to-high transition, q = the
state of the referenced output prior to the CLK low-to-high transition, ↑ = CLK low-to-high
transition.
NOTE 1: The RCO output is high when ENT is high and the counter is at terminal count (HHHH).
logic symbol†
1
CLR
9
LOAD
ENT
ENP
CLK
A
B
C
D
10
7
2
3
CTRDIV16
CT=0
M1
M2
3CT=15
RCO
G3
G4
C5/2,3,4+
1,5D
4
5
6
[1]
[2]
[4]
[8]
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2
15
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14
13
12
11
QA
QB
QC
QD
CD54ACT161, CD74ACT161
4-BIT SYNCHRONOUS BINARY COUNTERS
SCHS298 – APRIL 2000
logic diagram (positive logic)
LOAD
ENT
ENP
9
10
15
LD†
7
RCO
CK†
CLK
CLR
A
B
C
D
2
1
CK
LD
R
M1
G2
1, 2T/1C3
G4
3D
4R
3
M1
G2
1, 2T/1C3
G4
3D
4R
4
M1
G2
1, 2T/1C3
G4
3D
4R
5
M1
G2
1, 2T/1C3
G4
3D
4R
6
14
13
12
11
QA
QB
QC
QD
† For simplicity, routing of complementary signals LD and CK is not shown on this overall logic diagram. The uses of these signals are shown
on the logic diagram of the D/T flip-flops.
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3
CD54ACT161, CD74ACT161
4-BIT SYNCHRONOUS BINARY COUNTERS
SCHS298 – APRIL 2000
logic symbol, each D/T flip-flop
LD (Load)
M1
TE (Toggle Enable)
G2
1, 2T/1C3
G4
CK (Clock)
D (Inverted Data)
3D
R (Inverted Reset)
4R
Q (Output)
logic diagram, each D/T flip-flop (positive logic)
CK
LD
TE
LD†
TG
TG
LD†
Q
TG
TG
CK†
D
TG
CK†
R
† The origins of LD and CK are shown in the logic diagram of the overall device.
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CK†
TG
CK†
CD54ACT161, CD74ACT161
4-BIT SYNCHRONOUS BINARY COUNTERS
SCHS298 – APRIL 2000
typical clear, preset, count, and inhibit sequence
The following sequence is illustrated below:
1. Clear outputs to zero (asynchronous)
2. Preset to binary 12
3. Count to 13, 14, 15, 0, 1, and 2
4. Inhibit
CLR
LOAD
A
Data
Inputs
B
C
D
CLK
ENP
ENT
QA
Data
Outputs
QB
QC
QD
RCO
12
13
14
15
0
1
Count
2
Inhibit
Preset
Async
Clear
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CD54ACT161, CD74ACT161
4-BIT SYNCHRONOUS BINARY COUNTERS
SCHS298 – APRIL 2000
absolute maximum ratings over operating free-air temperature range†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V
Input clamp current, IIK (VI < 0 V or VI > VCC) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 V or VO > VCC) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous output current, IO (VO > 0 V or VO < VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 3): E package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
M package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
3. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 4)
TA = 25°C
MIN
MAX
VCC
VIH
Supply voltage
4.5
VIL
VI
Low-level input voltage
Input voltage
0
VO
IOH
Output voltage
0
High-level output current
–24
IOL
∆t/∆v
Low-level output current
24
High-level input voltage
5.5
2
CD54ACT161
MIN
MAX
MIN
MAX
4.5
5.5
4.5
5.5
2
0.8
Input transition rise or fall rate
0
VCC
VCC
10
CD74ACT161
2
0.8
0
0
0
UNIT
V
V
0.8
V
VCC
VCC
V
–24
–24
mA
24
24
mA
10
ns
VCC
VCC
10
0
0
0
V
TA
Operating free-air temperature
– 55
125
– 40
85
°C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VOH
VOL
II
ICC
DICC
TEST CONDITIONS
VI = VIH or VIL
VI = VIH or VIL
VI = VCC or GND
VI = VCC or GND,
VCC
TA = 25°C
MIN
MAX
CD54ACT161
MIN
MAX
CD74ACT161
MIN
MAX
UNIT
IOH = –50 µA
IOH = –24 mA
IOH = –50 mA†
4.5 V
4.4
4.5 V
5.5 V
IOH = –75 mA†
IOL = 50 µA
5.5 V
4.5 V
0.1
0.1
0.1
IOL = 24 mA
IOL = 50 mA†
4.5 V
0.36
0.5
0.44
5.5 V
–
1.65
–
IOL = 75 mA†
5.5 V
–
–
1.65
5.5 V
±0.1
±1
±1
µA
5.5 V
8
160
80
µA
2.4
3
2.8
mA
IO = 0
4.4
4.4
3.94
3.7
3.8
–
3.85
–
4.5 V to
5.5 V
VI = VCC – 2.1 V
V
3.85
V
Ci
10
10
10
pF
† Test one output at a time, not exceeding 1 second duration. Measurement is made by forcing indicated current and measuring voltage to minimize
power dissipation. Test verifies a minimum 50-Ω transmission-line drive capability at 85°C and 75-Ω transmission-line drive capability at 125°C.
6
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CD54ACT161, CD74ACT161
4-BIT SYNCHRONOUS BINARY COUNTERS
SCHS298 – APRIL 2000
ACT INPUT LOAD TABLE
INPUT
UNIT LOAD
A, B, C, or D
0.13
CLK
1
CLR, ENT
0.83
LOAD
0.67
ENP
0.5
Unit Load is ∆ICC limit specified in electrical
characteristics table (e.g., 2.4 mA at 25°C).
timing requirements over recommended operating conditions (unless otherwise noted)
CD54ACT161
MIN
fclock
Clock frequency
MAX
CD74ACT161
MIN
80
CLK high or low
tw
Pulse duration
tsu
time before CLK↑
Setup time,
th
Hold time,
time after CLK↑
trec
Recovery time, CLR↑ before CLK↑
MAX
91
6.2
5.4
CLR low
6
5.3
A, B, C, or D
5
4.4
LOAD
6
5.3
A, B, C, or D
0
0
ENP or ENT
0
0
6
5.3
UNIT
MHz
ns
ns
ns
ns
switching characteristics over recommended operating conditions, CL = 50 pF (unless otherwise
noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
MIN
MAX
80
CLK
tpd
CD54ACT161
ENT
CLR
CD74ACT161
MIN
MAX
91
UNIT
MHz
RCO
4.2
16.7
4.3
Any Q
4.1
16.5
4.2
15.2
15
RCO
2.7
10.8
2.8
9.8
Any Q
4.1
16.5
4.2
15
RCO
4.1
16.5
4.2
15
TEST CONDITIONS
TYP
ns
operating characteristics, TA = 25°C
PARAMETER
Cpd
Power dissipation capacitance
No load
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66
UNIT
pF
7
CD54ACT161, CD74ACT161
4-BIT SYNCHRONOUS BINARY COUNTERS
SCHS298 – APRIL 2000
PARAMETER MEASUREMENT INFORMATION
2 × VCC
S1
R1 = 500 Ω
From Output
Under Test
Open
GND
R2 = 500 Ω
CL = 50 pF
(see Note A)
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
tw
3V
NOTE When VCC = 1.5 V, R1 and R2 = 1 kΩ.
1.5 V
Input
1.5 V
LOAD CIRCUIT
0V
VOLTAGE WAVEFORMS
PULSE DURATION
3V
CLR
Input
3V
Reference
Input
1.5 V
0V
1.5 V
0V
trec
3V
Data
Input 1.5 V
10%
1.5 V
CLK
th
tsu
0V
90%
90%
3V
1.5 V
10% 0 V
tr
VOLTAGE WAVEFORMS
RECOVERY TIME
tf
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
3V
Input
1.5 V
1.5 V
0V
tPLH
In-Phase
Output
50%
10%
tPHL
90%
90%
tr
tPHL
Out-of-Phase
Output
90%
3V
Output
Control
tPLH
50% VCC
10%
tf
50%
10%
VOH
Output
50% VCC
Waveform 1
10%
VOL S1 at 2 × V
CC
tf
(see Note B)
90%
VOH
VOL
tr
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
1.5 V
1.5 V
0V
tPLZ
tPZL
50% VCC
tPZH
Output
Waveform 2
S1 at Open
(see Note B)
50% VCC
[
VCC
VOL + 0.3 V
VOL
tPHZ
VOH
VOH – 0.3 V
0V
[
VOLTAGE WAVEFORMS
OUTPUT ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and test-fixture capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.
Phase relationships between waveforms are arbitrary.
D. For clock inputs, fmax is measured with the input duty cycle at 50%.
E. The outputs are measured one at a time with one input transition per measurement.
F. tPLH and tPHL are the same as tpd.
G. tPZL and tPZH are the same as ten.
H. tPLZ and tPHZ are the same as tdis.
Figure 1. Load Circuit and Voltage Waveforms
8
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IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright  2000, Texas Instruments Incorporated
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