TI CD74AC161M

CD54AC161, CD74AC161
4-BIT SYNCHRONOUS BINARY COUNTERS
SCHS239C – SEPTEMBER 1998 – REVISED MARCH 2003
D
D
D
D
D
D
CD54AC161 . . . F PACKAGE
CD74AC161 . . . E OR M PACKAGE
(TOP VIEW)
Internal Look-Ahead for Fast Counting
Carry Output for n-Bit Cascading
Synchronous Counting
Synchronously Programmable
SCR-Latchup-Resistant CMOS Process and
Circuit Design
Exceeds 2-kV ESD Protection per
MIL-STD-883, Method 3015
CLR
CLK
A
B
C
D
ENP
GND
description/ordering information
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
VCC
RCO
QA
QB
QC
QD
ENT
LOAD
The ’AC161 devices are 4-bit binary counters.
These synchronous, presettable counters feature
an internal carry look-ahead for application in
high-speed counting These devices are fully programmable; that is, they can be preset to any number between
0 and 9 or 15. Presetting is synchronous; therefore, setting up a low level at the load input disables the counter
and causes the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the
enable inputs.
The clear function is asynchronous. A low level at the clear (CLR) input sets all four of the flip-flop outputs low,
regardless of the levels of the CLK, load (LOAD), or enable inputs.
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without
additional gating. Instrumental in accomplishing this function are ENP, ENT, and a ripple-carry output (RCO).
Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a
high-level pulse while the count is maximum (9 or 15, with QA high). This high-level overflow ripple-carry pulse
can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the
level of CLK.
The counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that
modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of
the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the
stable setup and hold times.
ORDERING INFORMATION
PDIP – E
–55°C
55°C to 125°C
ORDERABLE
PART NUMBER
PACKAGE†
TA
SOIC – M
Tube
CD74AC161E
Tube
CD74AC161M
Tape and reel
CD74AC161M96
TOP-SIDE
MARKING
CD74AC161E
AC161M
CDIP – F
Tube
CD54AC161F3A
CD54AC161F3A
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB
design guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
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1
CD54AC161, CD74AC161
4-BIT SYNCHRONOUS BINARY COUNTERS
SCHS239C – SEPTEMBER 1998 – REVISED MARCH 2003
FUNCTION TABLE
INPUTS
OUTPUTS
CLR
CLK
ENP
ENT
LOAD
A,B,C,D
Qn
RCO
L
X
X
X
X
X
L
L
H
↑
X
X
l
l
L
L
H
↑
X
X
l
h
H
Note 1
H
↑
h
h
h
X
Count
Note 1
H
X
l
X
h
X
Note 1
H
X
X
l
h
X
qn
qn
L
FUNCTION
Reset (clear)
Parallel load
Count
Inhibit
H = high level, L = low level, X = don’t care, h = high level one setup time prior to the CLK
low-to-high transition, l = low level one setup time prior to the CLK low-to-high transition, q = the
state of the referenced output prior to the CLK low-to-high transition, and ↑ = CLK low-to-high
transition.
NOTE 1: The RCO output is high when ENT is high and the counter is at terminal count
(HHHH).
2
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CD54AC161, CD74AC161
4-BIT SYNCHRONOUS BINARY COUNTERS
SCHS239C – SEPTEMBER 1998 – REVISED MARCH 2003
logic diagram (positive logic)
LOAD
ENT
ENP
9
10
15
LD†
7
RCO
CK†
CLK
CLR
A
B
C
D
2
1
CK
LD
R
M1
G2
1, 2T/1C3
G4
3D
4R
3
M1
G2
1, 2T/1C3
G4
3D
4R
4
M1
G2
1, 2T/1C3
G4
3D
4R
5
M1
G2
1, 2T/1C3
G4
3D
4R
6
14
13
12
11
QA
QB
QC
QD
† For simplicity, routing of complementary signals LD and CK is not shown on this overall logic diagram. The uses of these signals are shown
on the logic diagram of the D/T flip-flops.
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3
CD54AC161, CD74AC161
4-BIT SYNCHRONOUS BINARY COUNTERS
SCHS239C – SEPTEMBER 1998 – REVISED MARCH 2003
logic symbol, each D/T flip-flop
LD (Load)
M1
TE (Toggle Enable)
G2
1, 2T/1C3
G4
CK (Clock)
D (Inverted Data)
3D
R (Inverted Reset)
4R
Q (Output)
logic diagram, each D/T flip-flop (positive logic)
CK
LD
TE
LD†
TG
TG
LD†
Q
TG
TG
CK†
D
TG
CK†
R
† The origins of LD and CK are shown in the logic diagram of the overall device.
4
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CK†
TG
CK†
CD54AC161, CD74AC161
4-BIT SYNCHRONOUS BINARY COUNTERS
SCHS239C – SEPTEMBER 1998 – REVISED MARCH 2003
typical clear, preset, count, and inhibit sequence
The following sequence is illustrated below:
1. Clear outputs to zero (asynchronous)
2. Preset to binary 12
3. Count to 13, 14, 15, 0, 1, and 2
4. Inhibit
CLR
LOAD
A
Data
Inputs
B
C
D
CLK
ENP
ENT
QA
Data
Outputs
QB
QC
QD
RCO
12
13
14
15
0
1
Count
2
Inhibit
Preset
Async
Clear
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5
CD54AC161, CD74AC161
4-BIT SYNCHRONOUS BINARY COUNTERS
SCHS239C – SEPTEMBER 1998 – REVISED MARCH 2003
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V
Input clamp current, IIK (VI < 0 V or VI > VCC) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 V or VO > VCC) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous output current, IO (VO > 0 V or VO < VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 3): E package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
M package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 4)
TA = 25°C
VCC
VIH
Supply voltage
High-level input voltage
–55°C to
125°C
–40°C to
85°C
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
1.5
5.5
1.5
5.5
1.5
5.5
VCC = 1.5 V
VCC = 3 V
1.2
1.2
1.2
2.1
2.1
2.1
VCC = 5.5 V
VCC = 1.5 V
3.85
3.85
0.3
0.9
0.9
0.9
VI
VO
Input voltage
0
Output voltage
0
IOH
IOL
High-level output current
–24
Low-level output current
24
∆t/∆v
Input transition rise or fall rate
1.65
VCC = 1.5 V to 3 V
VCC = 3.6 V to 5.5 V
3.85
0.3
Low-level input voltage
VCC = 3 V
VCC = 5.5 V
V
0.3
VIL
VCC
VCC
1.65
0
V
1.65
VCC
VCC
V
–24
–24
mA
24
24
mA
50
50
50
20
20
20
0
VCC
VCC
V
0
0
V
ns
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
6
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CD54AC161, CD74AC161
4-BIT SYNCHRONOUS BINARY COUNTERS
SCHS239C – SEPTEMBER 1998 – REVISED MARCH 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
IOH = –50 µA
VOH
VI = VIH or VIL
IOH = –4 mA
IOH = –24 mA
IOH = –50 mA†
IOH = –75 mA†
IOL = 50 µA
VOL
II
ICC
VI = VIH or VIL
VI = VCC or GND
VI = VCC or GND,
–55°C to
125°C
TA = 25°C
MAX
MIN
–40°C to
85°C
MAX
MIN
1.5 V
1.4
1.4
1.4
2.9
3V
2.9
2.9
4.5 V
4.4
4.4
4.4
3V
2.58
2.4
2.48
4.5 V
3.94
3.7
3.8
5.5 V
–
3.85
–
5.5 V
–
–
3.85
UNIT
MAX
V
1.5 V
0.1
0.1
0.1
3V
0.1
0.1
0.1
4.5 V
0.1
0.1
0.1
V
IOL = 12 mA
IOL = 24 mA
IOL = 50 mA†
3V
0.36
0.5
0.44
4.5 V
0.36
0.5
0.44
5.5 V
–
1.65
–
IOL = 75 mA†
5.5 V
–
–
1.65
5.5 V
±0.1
±1
±1
µA
8
160
80
µA
10
10
10
IO = 0
5.5 V
Ci
pF
† Test one output at a time, not exceeding 1-second duration. Measurement is made by forcing indicated current and measuring voltage to minimize
power dissipation. Test verifies a minimum 50-Ω transmission-line drive capability at 85°C and 75-Ω transmission-line drive capability at 125°C.
POST OFFICE BOX 655303
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CD54AC161, CD74AC161
4-BIT SYNCHRONOUS BINARY COUNTERS
SCHS239C – SEPTEMBER 1998 – REVISED MARCH 2003
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
VCC
–55°C to
125°C
MIN
fclock
Clock frequency
CLK high or low
tw
Pulse duration
CLR low
A, B, C, or D
tsu
↑
Setup time,
time before CLK↑
LOAD
A, B, C, or D
th
Hold time
time, after CLK↑
↑
ENP or ENT
trec
Recovery time, CLR↑
↑ before CLK↑
↑
POST OFFICE BOX 655303
MAX
MIN
UNIT
MAX
1.5 V
7
3.3 V ± 0.3 V
64
73
5 V ± 0.5 V
90
103
8
1.5 V
69
61
3.3 V ± 0.3 V
7.7
6.8
5 V ± 0.5 V
5.5
4.8
1.5 V
63
55
3.3 V ± 0.3 V
7
6.1
5 V ± 0.5 V
5
4.4
1.5 V
63
55
3.3 V ± 0.3 V
7
6.1
5 V ± 0.5 V
5
4.4
1.5 V
75
66
3.3 V ± 0.3 V
8.4
7.4
5 V ± 0.5 V
6
5.3
1.5 V
0
0
3.3 V ± 0.3 V
0
0
5 V ± 0.5 V
0
0
1.5 V
0
0
3.3 V ± 0.3 V
0
0
5 V ± 0.5 V
0
0
1.5 V
75
66
3.3 V ± 0.3 V
8.4
7.4
6
5.3
5 V ± 0.5 V
8
–40°C to
85°C
• DALLAS, TEXAS 75265
MHz
ns
ns
ns
ns
CD54AC161, CD74AC161
4-BIT SYNCHRONOUS BINARY COUNTERS
SCHS239C – SEPTEMBER 1998 – REVISED MARCH 2003
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
VCC
MIN
3.3 V ± 0.3 V
64
73
5 V ± 0.5 V
90
103
ENT
RCO
CLR
209
–
MHz
190
23.4
6
21
16.7
4.3
15.2
–
207
–
188
3.3 V ± 0.3 V
5.9
23.1
5.9
5 V ± 0.5 V
4.2
16.5
4.2
–
129
–
3.3 V ± 0.3 V
3.6
14.4
3.7
13.1
5 V ± 0.5 V
2.6
10.3
2.7
9.4
–
207
–
188
3.3 V ± 0.3 V
5.9
23.1
5.9
21
5 V ± 0.5 V
4.2
16.5
4.2
15
1.5 V
RCO
8
6
1.5 V
Any Q
UNIT
MAX
4.3
1.5 V
tpd
–
3.3 V ± 0.3 V
1.5 V
Any Q
MIN
7
5 V ± 0.5 V
CLK
MAX
–40°C to
85°C
1.5 V
1.5 V
RCO
–55°C to
125°C
21
15
117
–
207
–
3.3 V ± 0.3 V
5.9
23.1
5.9
21
5 V ± 0.5 V
4.2
16.5
4.2
15
TEST CONDITIONS
TYP
ns
188
operating characteristics, TA = 25°C
PARAMETER
Cpd
Power dissipation capacitance
No load
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66
UNIT
pF
9
CD54AC161, CD74AC161
4-BIT SYNCHRONOUS BINARY COUNTERS
SCHS239C – SEPTEMBER 1998 – REVISED MARCH 2003
PARAMETER MEASUREMENT INFORMATION
2 × VCC
S1
R1 = 500 Ω
From Output
Under Test
Open
GND
R2 = 500 Ω
CL = 50 pF
(see Note A)
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
tw
VCC
NOTE: When VCC = 1.5 V, R1 and R2 = 1 kΩ.
50% VCC
Input
50% VCC
LOAD CIRCUIT
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VCC
CLR
Input
VCC
Reference
Input
50% VCC
50% VCC
0V
0V
tsu
trec
VCC
Data
Input 50%
10%
50% VCC
CLK
0V
th
90%
90%
tr
VCC
50% VCC
50% VCC
tPLH
tPHL
0V
In-Phase
Output
50%
10%
90%
90%
tr
tPHL
Out-of-Phase
Output
tf
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
RECOVERY TIME
Input
VCC
50% VCC
10% 0 V
90%
tPLH
50% VCC
10%
tf
50%
10%
VCC
Output
Control
VOH
Output
50% VCC
Waveform
1
10%
VOL S1 at 2 × V
CC
tf
(see Note B)
90%
VOH
VOL
tr
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
50% VCC
50% VCC
0V
tPLZ
tPZL
50% VCC
tPZH
Output
Waveform 2
S1 at Open
(see Note B)
50% VCC
≈VCC
VOL + 0.3 V
VOL
tPHZ
VOH
VOH – 0.3 V
≈0 V
VOLTAGE WAVEFORMS
OUTPUT ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and test-fixture capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.
Phase relationships between waveforms are arbitrary.
D. For clock inputs, fmax is measured with the input duty cycle at 50%.
E. The outputs are measured one at a time with one input transition per measurement.
F. tPLH and tPHL are the same as tpd.
G. tPZL and tPZH are the same as ten.
H. tPLZ and tPHZ are the same as tdis.
I. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
10
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PACKAGE OPTION ADDENDUM
www.ti.com
29-Jun-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
CD54AC161F3A
ACTIVE
CDIP
J
16
1
TBD
A42 SNPB
N / A for Pkg Type
CD74AC161E
ACTIVE
PDIP
N
16
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
CD74AC161EE4
ACTIVE
PDIP
N
16
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
CD74AC161M
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74AC161M96
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74AC161M96E4
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74AC161ME4
ACTIVE
SOIC
D
16
CU NIPDAU
Level-1-260C-UNLIM
Package
Drawing
Pins Package Eco Plan (2)
Qty
40
Green (RoHS &
no Sb/Br)
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
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