74AC11160 SYNCHRONOUS 4-BIT DECADE COUNTER SCAS380 – D3199, AUGUST 1988 – REVISED APRIL 1993 • • • • • • • • Internal Look-Ahead for Fast Counting Carry Output for n-Bit Cascading Fully Synchronous Operation for Counting Flow-Through Architecture to Optimize PCB Layout Center-Pin VCC and GND Pin Configurations Minimize High-Speed Switching Noise EPIC (Enhanced-Performance Implanted CMOS) 1-µm Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs DW OR N PACKAGE (TOP VIEW) RCO QA QB GND GND GND GND QC QD LOAD 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 CLR CLK A B VCC VCC C D ENP ENT description This synchronous, presettable 4-bit decade counter features an internal carry look-ahead circuitry for application in high-speed counting designs. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count-enable inputs and internal gating. This mode of operation eliminates the output counting spikes that are normally associated with asynchronous (ripple clock) counters; however, counting spikes may occur on the ripple carry out output (RCO). A buffered clock input triggers the four flip-flops on the rising (positive-going) edge of the clock input waveform. This counter is fully programmable in that they may be preset to any number between 0 and 9. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs. The clear function for the 74AC11160 is synchronous and a low level at the clear input sets all four of the flip-flops outputs low, regardless of the levels of the clock, load, or enable inputs. If one of these decade counters is preset to a number between 10 and 15 or assumes such an invalid state when power is applied, it will progress to the normal sequence within two counts as shown in the state diagram. The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. Instrumental in accomplishing this function are two count-enable inputs and a ripple carry output. Both count-enable inputs (ENP and ENT) must be high to count, and ENT is fed forward to enable the ripple carry output (RCO). RCO thus enabled will produce a high-level pulse while the count is 9 (HLLH). This high-level overflow ripple carry pulse can be used to enable successive cascaded stages. Transitions at the ENP or ENT are allowed regardless of the level of the clock input. This counter features a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that will modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) will be dictated solely by the conditions meeting the setup and hold times. The 74AC11160 is characterized for operation from – 40°C to 85°C. EPIC is a trademark of Texas Instruments Incorporated. Copyright 1993, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 74AC11160 SYNCHRONOUS 4-BIT DECADE COUNTER SCAS380 –D3199, AUGUST 1988 – REVISED APRIL 1993 state diagram 0 1 2 3 4 15 5 14 6 13 7 12 11 10 9 8 logic symbol† CTRDIV10 CLR LOAD 20 10 CT = 0 M1 M2 ENT 11 G3 3CT = 9 1 ENP 12 CLK 19 A 18 [1] 2 B 17 [2] 3 C 14 [4] 8 D 13 [8] 9 G4 C5/2,3,4+ 1,5D † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 2 RCO POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 QA QB QC QD 74AC11160 SYNCHRONOUS 4-BIT DECADE COUNTER SCAS380 – D3199, AUGUST 1988 – REVISED APRIL 1993 logic diagram (positive logic)† LOAD 10 ENT 11 1 RCO ENP 12 CLK 19 CK CLR 20 R LD M1 G2 1, 2T/1C3 A 18 M1 G2 1, 2T/1C3 B 2 G4 3D 4R 3 G4 3D 4R 17 M1 G2 1, 2T/1C3 8 G4 3D 4R C 14 QA QB QC M1 G2 1, 2T/1C3 D G4 3D 4R 13 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 QD 3 74AC11160 SYNCHRONOUS 4-BIT DECADE COUNTER SCAS380 –D3199, AUGUST 1988 – REVISED APRIL 1993 output sequence Illustrated below is the following sequence: 1. Clear outputs to zero (54AC11160 and 74AC11160 are synchronous) 2. Preset to BCD seven 3. Count to eight, nine, zero, one, two, and three 4. Inhibit. CLR LOAD A B Data Inputs C D CLK ENP ENT QA QB Outputs QC QD RCO 7 8 9 0 1 2 3 Count Sync Preset Async Clear Clear 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Inhibit 74AC11160 SYNCHRONOUS 4-BIT DECADE COUNTER SCAS380 – D3199, AUGUST 1988 – REVISED APRIL 1993 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCC or GND pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±125 mA Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. recommended operating conditions (see Note 2) VCC VIH Supply voltage VCC = 3 V VCC = 4.5 V High-level input voltage VCC = 5.5 V VCC = 3 V VIL VI VO IOH IOL ∆t/∆v Low-level input voltage MIN NOM MAX 3 5 5.5 3.85 0.9 1.35 0 0 VCC = 3 V VCC = 4.5 V VCC VCC –24 –24 VCC = 4.5 V VCC = 5.5 V 24 Input transition rise or fall rate • DALLAS, TEXAS 75265 V V –4 VCC = 5.5 V VCC = 3 V TA Operating free-air temperature NOTE 2: Unused or floating inputs must be held high or low. V 1.65 Output voltage POST OFFICE BOX 655303 V 3.15 Input voltage Low-level output current V 2.1 VCC = 4.5 V VCC = 5.5 V High-level output current UNIT mA 12 mA 24 0 10 ns/ V – 40 85 °C 5 74AC11160 SYNCHRONOUS 4-BIT DECADE COUNTER SCAS380 –D3199, AUGUST 1988 – REVISED APRIL 1993 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC IOH = – 50 µA VOH Ci MAX MIN 2.9 2.9 4.5 V 4.4 4.4 5.5 V 5.4 5.4 3V 2.58 2.48 4.5 V 3.94 3.8 IOL = – 24 mA A 5.5 V 4.94 4.8 IOH = – 75 mA† 5.5 V IOL = 75 mA† VI = VCC or GND VI = VCC or GND, VI = VCC or GND UNIT V 3.85 0.1 0.1 4.5 V 0.1 0.1 5.5 V 0.1 0.1 3V 0.36 0.44 4.5 V 0.36 0.44 5.5 V 0.36 0.44 5.5 V IO = 0 MAX 3V IOL = 12 mA IOL = 24 mA II ICC TYP 3V IOH = – 4 mA IOL = 50 µA VOL TA = 25°C MIN V 1.65 5.5 V ± 0.1 ±1 µA 5.5 V 8 80 µA 5V 3.5 pF † Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms. timing requirements, VCC = 3.3 V ± 0.3 V (see Figure 1) TA = 25°C MIN MAX fclock Clock frequency tw Pulse duration tsu Setup time before CLK↑ ↑ th Hold time after CLK↑ 0 CLK low or high 66 MIN MAX UNIT 0 66 MHz 7.5 7.5 6 6 A, B, C, D 6.5 6.5 LOAD 6.5 6.5 ENT, ENP 6 6 CLR inactive 6 6 1 1 CLR low ns ns ns timing requirements, VCC = 5 V ± 0.5 V (see Figure 1) TA = 25°C MIN MAX fclock tw tsu Clock frequency 0 Pulse duration ↑ Setup time before CLK↑ 6 UNIT 0 110 MHz 4.5 4.5 CLR low 4.5 4.5 A, B, C, D 3.5 3.5 LOAD 6.5 6.5 ENT, ENP 4.5 4.5 6 6 1 1 Hold time after CLK↑ POST OFFICE BOX 655303 MAX CLK low or high CLR inactive th 110 MIN • DALLAS, TEXAS 75265 ns ns ns ns 74AC11160 SYNCHRONOUS 4-BIT DECADE COUNTER SCAS380 – D3199, AUGUST 1988 – REVISED APRIL 1993 switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER fmax tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL FROM (INPUT) TO (OUTPUT) MIN TA = 25°C TYP MAX 66 CLK RCO CLK (LOAD high) Any Q CLK (LOAD low) lo ) Any Q ENT RCO CLR MIN MAX 66 UNIT MHz 1.5 11.2 13.6 1.5 15.2 1.5 12.2 15.1 1.5 17.2 1.5 9 11.2 1.5 12.5 1.5 10.6 13.4 1.5 15.1 1.5 8.6 10.8 1.5 12.1 1.5 10.1 12.8 1.5 14.4 1.5 6 7.6 1.5 8.3 1.5 6.8 8.9 1.5 9.9 Any Q 1.5 12 15.2 1.5 17.3 RCO 1.5 14.1 17.3 1.5 19.7 ns ns ns ns ns switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER fmax tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL FROM (INPUT) TO (OUTPUT) MIN 110 110 MAX 7.8 9.5 1.5 10.7 1.5 8.5 10.6 1.5 12.1 1.5 6.3 8 1.5 8.9 1.5 7.4 9.8 1.5 11.2 1.5 6 7.5 1.5 8.4 1.5 7.1 9.4 1.5 10.7 1.5 4.2 5.5 1.5 6 1.5 5 6.7 1.5 7.5 Any Q 1.5 8.2 10.7 1.5 12.1 RCO 1.5 9.9 12.2 1.5 13.8 RCO CLK (LOAD high) Any Q CLK (LOAD low) lo ) Any Q ENT RCO UNIT MHz 1.5 CLK CLR TA = 25°C MIN TYP MAX ns ns ns ns ns operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance CL = 50 pF, POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 f = 1 MHz TYP UNIT 48 pF 7 74AC11160 SYNCHRONOUS 4-BIT DECADE COUNTER SCAS380 –D3199, AUGUST 1988 – REVISED APRIL 1993 PARAMETER MEASUREMENT INFORMATION Timing Input (see Note B) From Output Under Test VCC 50% 0V th tsu CL = 50 pF (see Note A) 500 Ω VCC Data Input 50% 50% 0V SETUP AND HOLD TIMES LOAD CIRCUIT VCC Input (see Note B) 50% 50% 0V VCC High-Level Input 50% tPLH 50% 0V In-Phase Output tw Low-Level Input tPHL 50% VCC VCC 50% tPLH tPHL 50% 0V Out-of-Phase Output VOH 50% VCC VOL 50% VCC VOH 50% VCC VOL PROPAGATION DELAY TIMES PULSE DURATION NOTES: A. CL includes probe and jig capacitance. B. Input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns. For testing fmax and pulse duration: tr = 1 to 3 ns, tf = 1 to 3 ns. C. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. 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