MM54HC173/MM74HC173 TRI-STATEÉ Quad D Flip-Flop General Description The MM54HC173/MM74HC173 is a high speed TRI-STATE QUAD D TYPE FLIP-FLOP that utilizes advanced silicongate CMOS technology. It possesses the low power consumption and high noise immunity of standard CMOS integrated circuits, and can operate at speeds comparable to the equivalent low power Schottky device. The outputs are buffered, allowing this circuit to drive 15 LS-TTL loads. The large output drive capability and TRI-STATE feature make this part ideally suited for interfacing with bus lines in a bus oriented system. The four D TYPE FLIP-FLOPS operate synchronously from a common clock. The TRI-STATE outputs allow the device to be used in bus organized systems. The outputs are placed in the TRI-STATE mode when either of the two output disable pins are in the logic ‘‘1’’ level. The input disable allows the flip-flops to remain in their present states without having to disrupt the clock. If either of the 2 input disables are taken to a logic ‘‘1’’ level, the Q outputs are fed back to Connection Diagram the inputs, forcing the flip flops to remain in the same state. Clearing is enabled by taking the CLEAR input to a logic ‘‘1’’ level. The data outputs change state on the positive going edge of the clock. The 54HC/74HC logic family is functionally as well as pinout compatible with the standard 54LS/74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground. Features Y Y Y Y Y Y Typical propagation delay: 18 ns Wide operating supply voltage range: 2 – 6V TRI-STATE outputs Low input current: 1 mA maximum Low quiescent supply current: 80 mA maximum (74HC) High output drive current: 6 mA minimum Truth Table Inputs Dual-In-Line Package Clear Clock Data Enable G1 G2 Data Output Q D H X X X X L L L X X X Q0 L H X X Q0 u L X H X Q0 u L L L L L u L L L H H u When either M or N (or both) is (are) high the output is disabled to the high-impedance state: however, sequential operation of the flip-flops is not affected. H e high level (steady state) L e low level (steady state) ue low-to-high level transition X e don’t care (any input including transitions) TL/F/5317 – 1 QO e the level of Q before the indicated steady state input conditions were established Top View Order Number MM54HC173 or MM74HC173 TRI-STATEÉ is a registered trademark of National Semiconductor Corp. C1995 National Semiconductor Corporation TL/F/5317 RRD-B30M105/Printed in U. S. A. MM54HC173/MM74HC173 TRI-STATE Quad D Flip-Flop January 1988 Absolute Maximum Ratings (Notes 1 & 2) Operating Conditions If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage (VCC) Supply Voltage (VCC) DC Input Voltage (VIN) DC Output Voltage (VOUT) Clamp Diode Current (IIK, IOK) DC Output Current, per pin (IOUT) DC VCC or GND Current, per pin (ICC) Storage Temperature Range (TSTG) Power Dissipation (PD) (Note 3) S.O. Package only Lead Temperature (TL) (Soldering 10 seconds) DC Input or Output Voltage (VIN, VOUT) b 0.5 to a 7.0V b 1.5 to VCC a 1.5V Operating Temp. Range (TA) MM74HC MM54HC b 0.5 to VCC a 0.5V g 20 mA Min 2 Max 6 0 VCC Units V V b 40 b 55 a 85 a 125 §C §C 1000 500 400 ns ns ns Input Rise or Fall Times VCC e 2.0V (tr, tf) VCC e 4.5V VCC e 6.0V g 35 mA g 70 mA b 65§ C to a 150§ C 600 mW 500 mW 260§ C DC Electrical Characteristics (Note 4) Symbol Parameter Conditions TA e 25§ C VCC 74HC TA eb40 to 85§ C Typ 54HC TA eb55 to 125§ C Units Guaranteed Limits VIH Minimum High Level Input Voltage 2.0V 4.5V 6.0V 1.5 3.15 4.2 1.5 3.15 4.2 1.5 3.15 4.2 V V V VIL Maximum Low Level Input Voltage** 2.0V 4.5V 6.0V 0.5 1.35 1.8 0.5 1.35 1.8 0.5 1.35 1.8 V V V VOH Minimum High Level Output Voltage 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V V V 3.98 5.48 3.84 5.34 3.7 5.2 V V 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 V V V VIN e VIH or VIL lIOUTl s20 mA VIN e VIH or VIL lIOUTl s6.0 mA lIOUTl s7.8 mA VOL Maximum Low Level Output Voltage VIN e VIH or VIL lIOUTl s20 mA 2.0V 4.5V 6.0V 2.0 4.5 6.0 4.5V 6.0V 2.0V 4.5V 6.0V 0 0 0 VIN e VIH or VIL lIOUTl s6.0 mA lIOUTl s7.8 mA 4.5V 6.0V 0.26 0.26 0.33 0.33 0.4 0.4 V V IIN Maximum Input Current VIN e VCC or GND 6.0V g 0.1 g 1.0 g 1.0 mA IOZ Maximum TRI-STATE Output Leakage VOUT e VCC or GND Enable e VIH 6.0V g 0.5 g 5.0 g 10 mA ICC Maximum Quiescent Supply Current VIN e VCC or GND IOUT e 0 mA 6.0V 8.0 80 160 mA Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package: b 12 mW/§ C from 65§ C to 85§ C; ceramic ‘‘J’’ package: b 12 mW/§ C from 100§ C to 125§ C. Note 4: For a power supply of 5V g 10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC e 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used. **VIL limits are currently tested at 20% of VCC. The above VIL specification (30% of VCC) will be implemented no later than Q1, CY’89. 2 AC Electrical Characteristics VCC e 5V, TA e 25§ C, CL e 45 pF, tr e tf e 6 ns Symbol Parameter Conditions Typ Guaranteed Limit Units 45 30 MHz 31 ns 18 27 ns RL e 1 kX 18 28 ns RL e 1 kX CL e 5 pF 16 25 ns Minimum Data Setup Time 20 ns Minimum Data Enable Setup Time 20 ns tH Minimum Data Hold Time 0 ns tH Minimum Data Enable Hold Time 0 ns tW Minimum Clock Pulse Width 16 ns fMAX Maximum Operating Frequency tPHL, tPLH Maximum Propagation Delay: Clock to Q tPHL Maximum Propagation Delay: Clear to Q tPZH, tPZL Maximum Output Enable Time tPHZ, tPLZ Maximum Output Disable Time tS tS AC Electrical Characteristics VCC e 2.0V to 6.0V, CL e 50 pF, tr e tf e 6 ns (unless otherwise specified) Symbol Parameter Conditions VCC TA e 25§ C Typ 74HC TA eb40 to 85§ C 54HC TA eb55 to 125§ C Units Guaranteed Limits fMAX Maximum Operating Frequency CL e 50 pF 2.0V 4.5V 6.0V 10 45 55 5 27 32 4 21 25 4 18 21 MHz MHz MHz tPHL, tPLH Maximum Propagation Delay from Clock to Q CL e 50 pF CL e 150 pF 2.0V 2.0V 80 110 175 225 220 280 262 338 ns ns CL e 50 pF CL e 150 pF 4.5V 4.5V 23 28 35 45 44 56 53 68 ns ns CL e 50 pF CL e 150 pF 6.0V 6.0V 21 26 30 38 38 48 45 57 ns ns CL e 50 pF CL e 150 pF 2.0V 2.0V 70 100 150 200 189 252 224 298 ns ns CL e 50 pF CL e 150 pF 4.5V 4.5V 20 25 30 40 38 50 45 60 ns ns CL e 50 pF CL e 150 pF 6.0V 6.0V 17 22 26 34 32 43 38 51 ns ns Maximum Output Enable Time RL e 1 kX CL e 50 pF CL e 150 pF CL e 50 pF CL e 150 pF CL e 50 pF CL e 150 pF 2.0V 2.0V 4.5V 4.5V 6.0V 6.0V 70 100 20 25 17 22 150 200 30 40 26 34 189 252 38 50 32 43 224 298 45 60 38 51 ns ns ns ns ns ns tPHZ, tPLZ Maximum Output Disable Time RL e 1 kX CL e 50 pF 2.0V 4.5V 6.0V 70 20 17 150 30 26 189 38 32 224 45 38 ns ns ns tS Minimum Data or Data Enable Setup Time 2.0V 4.5V 6.0V 100 20 17 125 25 21 150 30 25 ns ns ns tREM Minimum Removal Time 2.0V 4.5V 6.0V 90 18 15 112 22 19 135 26 22 ns ns ns tH Minimum Data or Data Enable Hold Time 2.0V 4.5V 6.0V 0 0 0 0 0 0 0 0 0 ns ns ns tW Minimum Clear or Clock Pulse Width 2.0V 4.5V 6.0V 80 16 14 100 20 17 120 24 20 ns ns ns tPHL tPZH, tPZL Maximum Propagation Delay from Clear to Q 3 30 9 8 AC Electrical Characteristics (Continued) VCC e 2.0V to 6.0V, CL e 50 pF, tr e tf e 6 ns (unless otherwise specified) Symbol Parameter Conditions VCC TA e 25§ C Typ Guaranteed Limits tTHL, tTLH Maximum Output Rise and Fall Time 2.0V 4.5V 6.0V tr, tf Maximum Input Rise and Fall Time 2.0V 4.5V 6.0V CPD Power Dissipation Capacitance CIN Maximum Input Capacitance 5 10 10 10 pF COUT Maximum Output Capacitance 10 20 20 20 pF (per flop) 25 7 5 74HC 54HC TA eb40 to 85§ C TA eb55 to 125§ C Units 60 12 10 75 15 13 90 18 15 ns ns ns 1000 500 400 1000 500 400 1000 500 400 ns ns ns 80 pF Note 5: CPD determines the no load dynamic power consumption, PD e CPD VCC2 f a ICC VCC, and the no load dynamic current consumption, IS e CPD VCC f a ICC. 4 Physical Dimensions inches (millimeters) Dual-In-Line Package Order Number MM54HC173J or MM74HC173J NS Package J16A 5 MM54HC173/MM74HC173 TRI-STATE Quad D Flip-Flop Physical Dimensions inches (millimeters) (Continued) Dual-In-Line Package Order Number MM74HC173N NS Package N16E LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. 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