54ACT825 8-Bit D Flip-Flop General Description Features The ’ACT825 is an 8-bit buffered register. They have Clock Enable and Clear features which are ideal for parity bus interfacing in high performance microprogramming systems. Also included are multiple enables that allow multi-use control of the interface. The ’ACT825 has noninverting outputs and is fully compatible with AMD’s Am29825. n n n n Outputs source/sink 24 mA Inputs and outputs are on opposite sides ’ACT825 has TTL-compatible inputs Standard Microcircuit Drawing (SMD) — ’ACT825: 5962-91611 Logic Symbols IEEE/IEC DS100254-1 DS100254-3 Pin Names Description D0–D7 Data Inputs O0–O7 Data Outputs OE1, OE2, OE3 Output Enables EN Clock Enable CLR Clear CP Clock Input FACT™ is a trademark of Fairchild Semiconductor. TRI-STATE ® is a registered trademark of National Semiconductor Corporation. © 1999 National Semiconductor Corporation DS100254 www.national.com 54ACT825 8-Bit D Flip-Flop February 1999 Connection Diagrams Pin Assignment for DIP and Flatpak Pin Assignment for LCC DS100254-4 DS100254-2 Functional Description Operation of the OE input does not affect the state of the flip-flops. The ’ACT825 has Clear (CLR) and Clock Enable (EN) pins. These pins are ideal for parity bus interfacing in high performance systems. When CLR is LOW and OE is LOW, the outputs are LOW. When CLR is HIGH, data can be entered into the flip-flops. When EN is LOW, data on the inputs is transferred to the outputs on the LOW-to-HIGH clock transition. When EN is HIGH, the outputs do not change state, regardless of the data or clock input transitions. The ’ACT825 consists of eight D-type edge-triggered flip-flops. These devices have TRI-STATE ® outputs for bus systems, organized in a broadside pinning. In addition to the clock and output enable pins, the buffered clock (CP) and buffered Output Enable (OE) are common to all flip-flops. The flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH CP transition. With OE1, OE2 and OE3 LOW, the contents of the flip-flops are available at the outputs. When one of OE1, OE2 or OE3 is HIGH, the outputs go to the high impedance state. Function Table Inputs OE CLR EN CP Dn Internal Output Q O Function H X L N L L Z High-Z H X L N H H Z High-Z H L X X X L Z Clear L L X X X L L Clear H H H X X NC Z Hold L H H X X NC NC Hold Load H H L N L L Z H H L N H H Z Load L H L N L L L Load L H L N H H H Load H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance N = LOW-to-HIGH Transition NC = No Change www.national.com 2 Logic Diagram DS100254-5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 3 www.national.com Absolute Maximum Ratings (Note 1) Junction Temperature (TJ) CDIP If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V VI = VCC +0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = −0.5V VO = VCC +0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current Per Output Pin (ICC or IGND) Storage Temperature (TSTG) 175˚C Recommended Operating Conditions −0.5V to 7.0V Supply Voltage (VCC) ’ACT Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) 54ACT Minimum Input Edge Rate (∆V/∆t) ’ACT Devices VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V −20 mA +20 mA −0.5V to VCC +0.5V −20 mA +20 mA +0.5V ± 50 mA 4.5V to 5.5V 0V to VCC 0V to VCC −55˚C to +125˚C 125 mV/ns Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recommend operation of FACT™ circuits outside databook specifications. ± 50 mA −65˚C to +150˚C DC Electrical Characteristics Symbol Parameter 54ACT TA = VCC (V) Units Conditions −55˚C to +125˚C Guaranteed Limits VIH VIL VOH VOL Minimum High Level 4.5 2.0 Input Voltage 5.5 2.0 Maximum Low Level 4.5 0.8 Input Voltage 5.5 0.8 Minimum High Level 4.5 4.4 5.5 5.4 4.5 3.70 5.5 4.70 Maximum Low Level 4.5 0.1 Output Voltage 5.5 0.1 V VOUT = 0.1V or VCC −0.1V VOUT = 0.1V V or VCC −0.1V IOUT = −50 µA V (Note 2) VIN = VIL or VIH IOH = −24 mA V IOH = −24 mA IOUT = 50 µA V (Note 2) VIN = VIL or VIH IOL = 24 mA 4.5 0.50 5.5 0.50 µA IOL = 24 mA VI = VCC, GND VI = VIL, VIH VO = VCC, GND VI = VCC −2.1V IIN Maximum Input Leakage Current 5.5 IOZ Maximum TRI-STATE Current 5.5 ± 1.0 ± 10.0 ICCT Maximum ICC/Input 5.5 1.6 mA µA (Note 3) IOLD Minimum Dynamic 5.5 50 mA IOHD Output Current 5.5 −50 mA VOLD = 1.65V Max VOHD = 3.85V Min ICC Maximum Quiescent 5.5 160 µA VIN = VCC Supply Current or GND Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. www.national.com 4 DC Electrical Characteristics (Continued) Note 4: ICC limit for 54ACT @ 25˚C is identical to 74ACT @ 25˚C. AC Electrical Characteristics 54ACT TA = −55˚C VCC Symbol Parameter (V) to +125˚C CL = 50 pF (Note 5) Min fmax Maximum Clock Fig. Units No. Max 5.0 95 MHz 5.0 1.5 11.5 ns 5.0 1.5 11.5 ns 5.0 1.5 18.0 ns 5.0 1.5 11.5 ns 5.0 1.5 12.5 ns 5.0 1.5 13.5 ns 5.0 1.5 13.0 ns Frequency tPLH Propagation Delay CP to On tPHL Propagation Delay CP to On tPHL Propagation Delay CLR to On tPZH Output Enable Time OE to On tPZL Output Enable Time OE to On tPHZ Output Disable Time OE to On tPLZ Output Disable Time OE to On Note 5: Voltage Range 5.0 is 5.0V ± 0.5V AC Operating Requirements VCC Symbol Parameter (V) (Note 6) 54ACT TA = −55˚C to +125˚C CL = 50 pF Fig. Units No. Guaranteed Minimum ts Setup Time, HIGH or LOW 5.0 4.0 ns 5.0 2.5 ns 5.0 4.0 ns 5.0 2.0 ns 5.0 6.0 ns Dn to CP th Hold Time, HIGH or LOW Dn to CP ts Setup Time, HIGH or LOW EN to CP th Hold Time, HIGH or LOW EN to CP tw CP Pulse Width HIGH or LOW tw CLR Pulse Width, LOW 5.0 7.0 ns trec CLR to CP 5.0 4.5 ns Recovery Time Note 6: Voltage Range 5.0 is 5.0V ± 0.5V 5 www.national.com Capacitance Symbol CIN CPD Typ Units Input Capacitance Parameter 4.5 pF Power Dissipation 44 pF Capacitance www.national.com 6 Conditions VCC = OPEN VCC = 5.0V Physical Dimensions inches (millimeters) unless otherwise noted 28-Terminal Ceramic Leadless Chip Carrier (L) NS Package Number E28A 24 Lead Slim (0.300" Wide) Ceramic Dual-In-Line (SD) NS Package Number J24F 7 www.national.com 54ACT825 8-Bit D Flip-Flop Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24 Lead Ceramic Flatpak (F) NS Package Number W24C LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. 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