P T CT DUC PRO PRODU E T E E L T T O U OBS UBSTIT 105DK8 S 76 F E L U B DataSISheet LH POS INTERSI 3.5A, 30V, 0.06 Ohm, Dual N-Channel LittleFET™ Power MOSFET RF1K49086 July 2000 File Number 3986.6 Features • 3.5A, 30V [ /Title This Dual N-Channel power MOSFET is manufactured using • rDS(ON) = 0.060Ω (RF1K4 an advanced MegaFET process. This process, which uses • Temperature Compensating PSPICE® Model feature sizes approaching those of LSI integrated circuits, 9086) gives optimum utilization of silicon, resulting in outstanding • Peak Current vs Pulse Width Curve /Subperformance. It is designed for use in applications such as ject • UIS Rating Curve switching regulators, switching convertors, motor drivers, (3.5A, relay drivers, and low voltage bus switches. This device can • Related Literature 30V, be operated directly from integrated circuits. - TB334 “Guidelines for Soldering Surface Mount 0.06 Components to PC Boards” Formerly developmental type TA49086. Ohm, Symbol Dual N- Ordering Information ChanPART NUMBER PACKAGE BRAND D1(8) nel LitD1(7) RF1K49086 MS-012AA RF1K49086 tleFET NOTE: When ordering, use the entire part number. For ordering in ™ S1(1) tape and reel, add the suffix 96 to the part number, i.e., RF1K4908696. G1(2) Power MOSD2(6) FET) D2(5) /Author () S2(3) G2(4) /Keywords (Intersil Corporation, Packaging Dual NJEDEC MS-012AA Channel LittleFET BRANDING DASH ™ Power 5 MOSFET, 1 2 MS3 4 012AA) /Creator () /DOCI NFO ©2001 Fairchild Semiconductor Corporation RF1K49086 Rev. A RF1K49086 Absolute Maximum Ratings TA = 25oC Unless Otherwise Specified Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (RGS = 20kΩ, Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Drain Current Continuous (Pulse Width = 5s). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed (Figure 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Pulsed Avalanche Rating (Figure 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .EAS Power Dissipation TA = 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg RF1K49086 30 30 ±20 UNITS V V V 3.5 Refer to Peak Current Curve Refer to UIS Curve A 2 0.016 -55 to 150 W W/oC oC 300 260 oC oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 125oC. Electrical Specifications TA = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS V Drain to Source Breakdown Voltage BVDSS ID = 250µA, VGS = 0V, (Figure 12) 30 - - Gate Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA, (Figure 11) Zero Gate Voltage Drain Current Gate to Source Leakage Current Drain to Source On Resistance 1 - 3 V TA = 25oC - - 1 µA TA = 150oC - - 50 µA - - ±100 nA VGS = 10V - - 0.060 Ω VGS = 4.5V - - 0.132 Ω - - 50 ns - 10 - ns tr - 30 - ns td(OFF) - 60 - ns tf - 45 - ns tOFF - - 130 ns IDSS IGSS rDS(ON) Turn-On Time tON Turn-On Delay Time td(ON) Rise Time Turn-Off Delay Time Fall Time Turn-Off Time Total Gate Charge VDS = 30V, VGS = 0V VGS = ±20V ID = 3.5A (Figures 9, 10) VDD = 15V, ID ≈ 3.5A, RL = 4.29Ω, VGS = 10V, RGS = 25Ω Qg(TOT) VGS = 0V to 20V Gate Charge at 10V Qg(10) VGS = 0V to 10V Threshold Gate Charge Qg(TH) VGS = 0V to 2V Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS Thermal Resistance Junction to Ambient RθJA VDD = 24V, ID = 3.5A, RL = 6.86Ω (Figure 14) VDS = 25V, VGS = 0V, f = 1MHz (Figure 13) - 35 45 nC - 13 17 nC - 2.3 2.9 nC - 575 - pF - 275 - pF - 100 - pF - - 62.5 oC/W MIN TYP MAX UNITS ISD = 3.5A - - 1.25 V ISD = 3.5A, dISD/dt = 100A/µs - - 45 ns Pulse Width = 1s Device mounted on FR-4 material Source to Drain Diode Specifications PARAMETER Source to Drain Diode Voltage Reverse Recovery Time ©2001 Fairchild Semiconductor Corporation SYMBOL VSD trr TEST CONDITIONS RF1K49086 Rev. A RF1K49086 Typical Performance Curves 4.0 3.5 1.0 ID, DRAIN CURRENT (A) POWER DISSIPATION MULTIPLIER 1.2 0.8 0.6 0.4 3.0 2.5 2.0 1.5 1.0 0.2 0.5 0.0 0.0 0 25 50 75 100 TA , AMBIENT TEMPERATURE (oC) 125 25 150 FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT TEMPERATURE ZθJA, NORMALIZED THERMAL IMPEDANCE 10 75 100 125 50 TA, AMBIENT TEMPERATURE (oC) 150 FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs AMBIENT TEMPERATURE DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 0.1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJA x RθJA + TA SINGLE PULSE 0.01 10-3 10-2 10-1 100 101 t, RECTANGULAR PULSE DURATION (s) 102 103 FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE TJ = MAX RATED TA = 25oC 10 5ms 10ms 1 100ms 0.1 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 1s VDSS(MAX) = 30V 0.01 0.1 1 DC 10 VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 4. FORWARD BIAS SAFE OPERATING AREA ©2001 Fairchild Semiconductor Corporation 100 200 IDM, PEAK CURRENT CAPABILITY (A) ID, DRAIN CURRENT (A) 100 TA = 25oC 100 FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: I VGS = 10V 150 - TA 125 = I25 10 TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 1 10-5 10-4 10-3 10-2 10-1 100 101 t, PULSE WIDTH (s) FIGURE 5. PEAK CURRENT CAPABILITY RF1K49086 Rev. A RF1K49086 (Continued) 20 If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R ≠ 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] 10 25 VGS = 20V ID, DRAIN CURRENT (A) IAS, AVALANCHE CURRENT (A) Typical Performance Curves STARTING TJ = 25oC STARTING TJ = 150oC 1 0.1 1 10 tAV, TIME IN AVALANCHE (ms) VGS = 4.5V 15 VGS = 4V 10 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX TA = 25oC 5 0 100 VGS = 3V 0 1.0 FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY -55oC 150oC 15 10 5 rDS(ON), ON-STATE RESISTANCE (mΩ) 250 VDD = 15V 25oC 20 1.5 3.0 4.5 6.0 VGS, GATE TO SOURCE VOLTAGE (V) ID = 0.5A 50 6 7 8 9 10 VGS = VDS, ID = 250µA 0.5 40 80 120 TJ, JUNCTION TEMPERATURE (oC) FIGURE 10. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE ©2001 Fairchild Semiconductor Corporation 5 2.0 1.0 0 4 FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT 1.5 -40 3 VGS , GATE TO SOURCE VOLTAGE (V) NORMALIZED GATE NORMALIZED ON RESISTANCE 100 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VGS = 10V, ID = 3.5A 0.0 -80 5.0 150 7.5 FIGURE 8. TRANSFER CHARACTERISTICS 2.0 4.0 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VDD = 15V ID = 7.0A ID = 3.5A ID = 1.75A 200 0 0 0 3.0 FIGURE 7. SATURATION CHARACTERISTICS 160 THRESHOLD VOLTAGE ID(ON), ON-STATE DRAIN CURRENT (A) PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 2.0 VDS, DRAIN TO SOURCE VOLTAGE (V) NOTE: Refer to Intersil Application Notes AN9321 and AN9322. 25 VGS = 5V VGS = 10V 20 1.5 1.0 0.5 0.0 -80 -40 0 40 80 120 TJ, JUNCTION TEMPERATURE (oC) 160 FIGURE 11. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE RF1K49086 Rev. A RF1K49086 Typical Performance Curves (Continued) 1000 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS = CDS + CGD ID = 250µA 1.5 750 C, CAPACITANCE (pF) 1.0 0.5 CISS 500 COSS 250 CRSS 0.0 -80 -40 0 160 0 40 80 120 TJ , JUNCTION TEMPERATURE (oC) FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE 0 25 FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE 30 VDS , DRAIN-SOURCE VOLTAGE (V) 5 10 15 20 VDS , DRAIN TO SOURCE VOLTAGE (V) 10.0 VDD = BVDSS 22.5 VDD = BVDSS RL = 8.57Ω IG(REF) = 0.75mA VGS = 10V 15 5.0 PLATEAU VOLTAGES IN DESCENDING ORDER: VDD = BVDSS VDD = 0.75 BVDSS VDD = 0.50 BVDSS VDD = 0.25 BVDSS 7.5 2.5 0 0 I G ( REF ) 20 ---------------------I G ( ACT ) t, TIME (µs) 7.5 VGS , GATE-SOURCE VOLTAGE (V) NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE 2.0 I G ( REF ) 80 ---------------------I G ( ACT ) NOTE: Refer to Intersil Application Notes AN7254 and AN7260. FIGURE 14. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT Test Circuits and Waveforms VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS tP + RG VDS IAS VDD VDD - VGS DUT 0V tP IAS 0 0.01Ω tAV FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT ©2001 Fairchild Semiconductor Corporation FIGURE 16. UNCLAMPED ENERGY WAVEFORMS RF1K49086 Rev. A RF1K49086 Test Circuits and Waveforms (Continued) tON tOFF td(ON) td(OFF) tf tr VDS RL 90% 90% + RG - VDD 10% 10% 0 90% DUT VGS 0 VGS 50% PULSE WIDTH FIGURE 18. RESISTIVE SWITCHING WAVEFORMS FIGURE 17. RESISTIVE SWITCHING TEST CIRCUIT VDS 50% 10% VDD RL Qg(TOT) VDS VGS = 20V VGS Qg(10) + VDD VGS = 2V DUT Ig(REF) VGS = 10V VGS - 0 Qg(TH) Ig(REF) 0 FIGURE 19. GATE CHARGE TEST CIRCUIT Soldering Precautions The soldering process creates a considerable thermal stress on any semiconductor component. The melting temperature of solder is higher than the maximum rated temperature of the device. The amount of time the device is heated to a high temperature should be minimized to assure device reliability. Therefore, the following precautions should always be observed in order to minimize the thermal stress to which the devices are subjected. 1. Always preheat the device. 2. The delta temperature between the preheat and soldering should always be less than 100oC. Failure to preheat the device can result in excessive thermal stress which can damage the device. ©2001 Fairchild Semiconductor Corporation FIGURE 20. GATE CHARGE WAVEFORM 3. The maximum temperature gradient should be less than 5oC per second when changing from preheating to soldering. 4. The peak temperature in the soldering process should be at least 30oC higher than the melting point of the solder chosen. 5. The maximum soldering temperature and time must not exceed 260oC for 10 seconds on the leads and case of the device. 6. After soldering is complete, the device should be allowed to cool naturally for at least three minutes, as forced cooling will increase the temperature gradient and may result in latent failure due to mechanical stress. 7. During cooling, mechanical stress or shock should be avoided. RF1K49086 Rev. A RF1K49086 PSPICE Electrical Model SUBCKT RF1K49086 2 1 3 ; rev 12/15/94 CA 12 8 1.75e-9 CB 15 14 1.80e-9 CIN 6 8 1.20e-9 DPLCAP 5 10 LDRAIN DBODY 7 5 DBDMOD DBREAK 5 11 DBKMOD DPLCAP 10 5 DPLCAPMOD DBREAK RDRAIN EBREAK 11 7 17 18 33.29 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTO 20 6 18 8 1 IT 8 17 1 ESG + GATE 1 RBREAK 17 18 RBKMOD 1 RDRAIN 5 16 RDSMOD 1e-4 RGATE 9 20 1.83 RIN 6 8 1e9 RSOURCE 8 7 RDSMOD 13.5e-3 RVTO 18 19 RVTOMOD 1 S1A S1B S2A S2B 11 6 8 EBREAK 16 VTO + EVTO 20 + 18 8 LGATE RGATE 9 LDRAIN 2 5 1e-9 LGATE 1 9 1.233e-9 LSOURCE 3 7 0.452e-9 MOS1 16 6 8 8 MOSMOD M = 0.99 MOS2 16 21 8 8 MOSMOD M = 0.01 DRAIN 2 21 6 DBODY MOS2 MOS1 CIN RIN 8 RSOURCE 7 LSOURCE 3 SOURCE S2A S1A 12 + 17 18 13 8 S1B RBREAK 15 14 13 17 18 S2B RVTO 13 CB CA + EGS 6 8 EDS + 14 5 8 IT 19 VBAT + 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD VBAT 8 19 DC 1 VTO 21 6 0.1 .MODEL DBDMOD D (IS = 2.50e-13 RS = 1.35e-2 TRS1 = 4.31e-5 TRS2 = 2.15e-5 CJO = 9.33e-10 TT = 2.08e-8) .MODEL DBKMOD D (RS = 1.14 TRS1 = 2.23e-3 TRS2 = -8.91e-6) .MODEL DPLCAPMOD D (CJO = 7.99e-10 IS = 1e-30 N = 10) .MODEL MOSMOD NMOS (VTO = 2.15 KP = 6.25 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL RBKMOD RES (TC1 = 7.74e-4 TC2 = 1.13e-6) .MODEL RDSMOD RES (TC1 = 4.5e-3 TC2 = -7.45e-7) .MODEL RVTOMOD RES (TC1 = -4.16e-3 TC2 = 2.16e-6) .MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -7.15 VOFF= -5.15) .MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -5.15 VOFF= -7.15) .MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.6 VOFF= 2.4) .MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 2.4 VOFF= -2.6) .ENDS NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991. ©2001 Fairchild Semiconductor Corporation RF1K49086 Rev. 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PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. H