RF1K49223
Data Sheet
January 2002
2.5A, 30V, 0.150 Ohm, Dual P-Channel
LittleFET™ Power MOSFET
Features
• 2.5A, 30V
The RF1K49223 Dual P-Channel power MOSFET is
manufactured using an advanced MegaFET process. This
process, which uses feature sizes approaching those of LSI
integrated circuits, gives optimum utilization of silicon,
resulting in outstanding performance. It is designed for use
in applications such as switching regulators, switching
converters, motor drivers, relay drivers, and low voltage bus
switches. This device can be operated directly from
integrated circuits.
• rDS(ON) = 0.150Ω
• Temperature Compensating PSPICE® Model
• Thermal Impedance PSPICE Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
Formerly developmental type TA49223.
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Ordering Information
Symbol
PART NUMBER
RF1K49223
PACKAGE
MS-012AA
BRAND
D1(8)
D1(7)
RF1K49223
NOTE: When ordering, use the entire part number. For ordering in
tape and reel, add the suffix 96 to the part number, i.e. RF1K4922396.
S1(1)
G1(2)
D2(6)
D2(5)
S2(3)
G2(4)
Packaging
JEDEC MS-012AA
BRANDING DASH
5
1
2
3
©2002 Fairchild Semiconductor Corporation
4
RF1K49223 Rev. B
RF1K49223
Absolute Maximum Ratings
TA= 25oC Unless Otherwise Specified
RF1K49223
UNITS
Drain to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS
Drain to Gate Voltage (RGS = 20kΩ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR
-30
V
-30
V
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS
±20
V
Drain Current
Continuous (Pulse Width = 5s). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Pulsed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM
2.5
Refer to Peak Current Curve
A
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS
Refer to UIS Curve
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD
Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
0.016
W
W/oC
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG
-55 to 150
oC
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg
300
260
oC
oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. TJ = 25oC to 125oC.
Electrical Specifications
TA = 25oC, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Drain to Source Breakdown Voltage
BVDSS
ID = 250µA, VGS = 0V, (Figure 12)
-30
-
-
V
Gate to Source Threshold Voltage
VGS(TH)
VGS = VDS, ID = 250µA, (Figure 11)
-1
-
-3
V
-
-
-1
µA
-
-
-50
µA
-
-
±100
nA
VGS = -10V
-
-
0.150
Ω
VGS = -4.5V
-
-
0.360
Ω
-
-
40
ns
-
9
-
ns
tr
-
19
-
ns
td(OFF)
-
60
-
ns
tf
-
34
-
ns
tOFF
-
-
140
ns
-
28
35
nC
-
15
19
nC
-
1.5
1.9
nC
-
580
-
pF
-
260
-
pF
-
38
-
pF
-
-
62.5
oC/W
MIN
TYP
MAX
UNITS
ISD = -2.5A
-
-
-1.25
V
ISD =-2.5A, dISD/dt = 100A/µs
-
-
49
ns
Zero Gate Voltage Drain Current
IDSS
Gate to Source Leakage Current
Drain to Source On Resistance
IGSS
rDS(ON)
Turn-On Time
tON
Turn-On Delay Time
td(ON)
Rise Time
Turn-Off Delay Time
Fall Time
Turn-Off Time
VDS = -30V,
VGS = 0V
TA = 25oC
TA = 150oC
VGS = ±20V
ID = 2.5A,
(Figure 9, 10)
VDD = -15V, ID ≅ 2.5A,
RL = 6Ω, VGS = -10V,
RGS = 25Ω
Total Gate Charge
Qg(TOT)
VGS = 0V to -20V
Gate Charge at -10V
Qg(-10)
VGS = 0V to -10V
Threshold Gate Charge
Qg(TH)
VGS = 0V to -2V
VDD = -24V,
ID ≅ 2.5A,
RL = 9.6Ω
Ig(REF) = -1.0mA
(Figure 14)
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
Thermal Resistance Junction to Ambient
RθJA
VDS = -25V, VGS = 0V,
f = 1MHz
(Figure 13)
Pulse Width = 1s
Device mounted on FR-4 material
Source to Drain Diode Specifications
PARAMETER
Source to Drain Diode Voltage
Reverse Recovery Time
©2002 Fairchild Semiconductor Corporation
SYMBOL
VSD
trr
TEST CONDITIONS
RF1K49223 Rev. B
RF1K49223
1.2
-3.0
1.0
-2.5
ID, DRAIN CURRENT (A)
POWER DISSIPATION MULTIPLIER
Typical Performance Curves
0.8
0.6
0.4
0.2
-2.0
-1.5
-1.0
-0.5
0
0
0
25
125
50
75
100
TA , AMBIENT TEMPERATURE (oC)
75
50
25
150
100
125
150
TA, AMBIENT TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
AMBIENT TEMPERATURE
ZθJA, NORMALIZED
THERMAL IMPEDANCE
10
1
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
PDM
0.1
t1
t2
0.01
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJA x RθJA + TA
SINGLE PULSE
0.001
10-5
10-4
10-3
10-1
100
10-2
t, RECTANGULAR PULSE DURATION (s)
101
102
103
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
-100
TJ = MAX RATED
TA = 25oC
-10
5ms
10ms
-1
100ms
-0.1
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
-0.01
-0.1
-1
1s
VDSS(MAX) = -30V
VGS = -20V
TA = 25oC
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
I
VGS = -10V
= I25
150 - TA
125
-10
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
DC
-10
VDS, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
©2002 Fairchild Semiconductor Corporation
IDM, PEAK CURRENT (A)
ID, DRAIN CURRENT (A)
-50
-100
-1
10-5
10-4
10-3
10-2
10-1
100
101
t, PULSE WIDTH (s)
FIGURE 5. PEAK CURRENT CAPABILITY
RF1K49223 Rev. B
RF1K49223
Typical Performance Curves
(Continued)
-20
If R = 0
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
-10
STARTING TJ = 25oC
STARTING TJ = 150oC
-1
0.1
1
10
tAV, TIME IN AVALANCHE (ms)
VGS = -20V
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
TA = 25oC
VGS = -7V
VGS = -10V
ID, DRAIN CURRENT (A)
IAS, AVALANCHE CURRENT (A)
-15
-16
VGS = -8V
VGS = -6V
-12
VGS = -5V
-8
VGS = -4.5V
-4
0
100
0
-1.5
-3.0
-4.5
-6.0
-7.5
VDS, DRAIN TO SOURCE VOLTAGE (V)
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.
FIGURE 7. SATURATION CHARACTERISTICS
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY
500
-16
150oC
-55oC
25oC
-12
-8
-4
400
ID = -5.0A
ID = -2.5A
300
ID = -1.25A
200
ID = -0.625A
100
0
0
0
-2
-4
-6
-8
VGS, GATE TO SOURCE VOLTAGE (V)
-2
-10
FIGURE 8. TRANSFER CHARACTERISTICS
NORMALIZED GATE
THRESHOLD VOLTAGE
0.5
40
80
120
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 10. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
©2002 Fairchild Semiconductor Corporation
-10
VGS = VDS, ID = -250µA
1.0
0
-8
1.2
1.5
-40
-6
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs
GATE VOLTAGE AND DRAIN CURRENT
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VGS = -10V, ID = -2.5A
0
-80
-4
VGS , GATE TO SOURCE VOLTAGE (V)
2.0
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = -15V
VDD = -15V
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
rDS(ON), DRAIN TO SOURCE
ON RESISTANCE (mΩ)
ID(ON), ON-STATE DRAIN CURRENT (A)
-20
160
1.0
0.8
0.6
0.4
-80
-40
0
40
80
120
TJ, JUNCTION TEMPERATURE (oC)
160
FIGURE 11. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
RF1K49223 Rev. B
RF1K49223
Typical Performance Curves
(Continued)
750
1.2
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
ID = -250µA
CISS
C, CAPACITANCE (pF)
600
1.1
1.0
VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS = CDS + CGD
450
COSS
300
0.9
150
CRSS
0
-40
0
40
80
120
TJ , JUNCTION TEMPERATURE (oC)
-5
-10
-15
-20
-25
VDS , DRAIN TO SOURCE VOLTAGE (V)
FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
VDS , DRAIN TO SOURCE VOLTAGE (V)
0
160
FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
-30.0
-10.0
VDD = BVDSS
VDD = BVDSS
-22.5
-7.5
RL = 12Ω
IG(REF) = -0.26mA
VGS = -10V
PLATEAU VOLTAGES IN
DESCENDING ORDER:
VDD = BVDSS
VDD = 0.75 BVDSS
VDD = 0.50 BVDSS
VDD = 0.25 BVDSS
-15.0
-7.5
-5.0
-2.5
0
0
I G ( REF )
20 ---------------------I G ( ACT )
VGS , GATE TO SOURCE VOLTAGE (V)
0.8
-80
I G ( REF )
t, TIME (µs)
80 ---------------------I G ( ACT )
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.
FIGURE 14. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT
Test Circuits and Waveforms
VDS
tAV
L
VARY tP TO OBTAIN
REQUIRED PEAK IAS
0
-
RG
+
0V
VGS
DUT
tP
IAS
VDD
IAS
VDS
tP
0.01Ω
FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT
©2002 Fairchild Semiconductor Corporation
VDD
BVDSS
FIGURE 16. UNCLAMPED ENERGY WAVEFORMS
RF1K49223 Rev. B
RF1K49223
Test Circuits and Waveforms
(Continued)
tON
tOFF
td(OFF)
td(ON)
tf
tr
0
10%
10%
RL
VDS
VGS
-
VDS
VDD
+
VGS
90%
90%
VGS
0
10%
DUT
RGS
50%
50%
PULSE WIDTH
90%
FIGURE 18. RESISTIVE SWITCHING WAVEFORMS
FIGURE 17. SWITCHING TIME TEST CIRCUIT
VDS
RL
VDS
Qg(TH)
0
VGS = -2V
VGS
-
VGS = -10V
-VGS
VDD
Qg(-10)
+
DUT
VGS = -20V
VDD
Qg(TOT)
0
Ig(REF)
FIGURE 19. GATE CHARGE TEST CIRCUIT
FIGURE 20. GATE CHARGE WAVEFORMS
Soldering Precautions
The soldering process creates a considerable thermal stress
on any semiconductor component. The melting temperature
of solder is higher than the maximum rated temperature of
the device. The amount of time the device is heated to a high
temperature should be minimized to assure device reliability.
Therefore, the following precautions should always be
observed in order to minimize the thermal stress to which the
devices are subjected.
1. Always preheat the device.
2. The delta temperature between the preheat and soldering should always be less than 100oC. Failure to preheat
the device can result in excessive thermal stress which
can damage the device.
4. The peak temperature in the soldering process should be
at least 30oC higher than the melting point of the solder
chosen.
5. The maximum soldering temperature and time must not
exceed 260oC for 10 seconds on the leads and case of
the device.
6. After soldering is complete, the device should be allowed
to cool naturally for at least three minutes, as forced cooling will increase the temperature gradient and may result
in latent failure due to mechanical stress.
7. During cooling, mechanical stress or shock should be
avoided.
3. The maximum temperature gradient should be less than
5oC per second when changing from preheating to soldering.
©2002 Fairchild Semiconductor Corporation
RF1K49223 Rev. B
RF1K49223
PSPICE Electrical Model
SUBCKT RF1K49223 2 1 3 ;rev 4/7/97
CA 12 8 7.29e-10
CB 15 14 5.01e-10
CIN 6 8 5.55e-10
LDRAIN
ESG
10
RLDRAIN
RSLC1
51
+
+
DBODY 5 7 DBODYMOD
DBREAK 7 11 DBREAKMOD
DPLCAP 10 6 DPLCAPMOD
RSLC2
5
51
EBREAK
ESLC
17
18
-
-
50
EBREAK 5 11 17 18 -35.46
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 5 10 8 6 1
EVTHRES 6 21 19 8 1
EVTEMP 6 20 18 22 1
DPLCAP
LGATE
IT 8 17 1
RDRAIN
EVTHRES
+ 19 8
EVTEMP
RGATE
GATE
1
9
20
21
DBODY
16
MWEAK
6
18 +
22
11
MMED
DBREAK
MSTRO
RLGATE
LDRAIN 2 5 1e-9
LGATE 1 9 1.27e-9
LSOURCE 3 7 4.20e-10
LSOURCE
CIN
8
SOURCE
3
7
RSOURCE
RLSOURCE
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
S1A
12
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 19.3e-3
RGATE 9 20 7.44
RLDRAIN 2 5 10
RLGATE 1 9 12.7
RLSOURCE 3 7 4.2
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 65.37e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A
S1B
S2A
S2B
DRAIN
2
5
+
8
6
S2A
13
8
14
13
S1B
CA
RBREAK
15
17
18
RVTEMP
S2B
13
CB
6
8
EGS
19
14
+
+
VBAT
5
8
EDS
-
-
IT
-
+
8
22
RVTHRES
6 12 13 8 S1AMOD
13 12 13 8 S1BMOD
6 15 14 13 S2AMOD
13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*48),2.5))}
.MODEL DBODYMOD D (IS = 3.30e-13 RS = 4.56e-2 TRS1 =6.98e-4 TRS2 =8.08e-7 CJO = 8.21e-10 TT = 3.51e-8 M=0.4)
.MODEL DBREAKMOD D (RS = 8.18e- 1TRS1 =5.28e- 3TRS2 = -7.18e-5
.MODEL DPLCAPMOD D (CJO = 2.52e-1 0IS = 1e-3 0N = 10 M=0.6)
.MODEL MMEDMOD PMOS (VTO= -1.95 KP=0.75 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=7.44)
.MODEL MSTROMOD PMOS (VTO= -2.44 KP= 7.25 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL MWEAKMOD PMOS (VTO= -1.68 KP=0.045 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=74.4 RS=0.1)
.MODEL RBREAKMOD RES (TC1 = 9.45e- 4TC2 = -1.01e-7)
.MODEL RDRAINMOD RES (TC1 = 3.69e-3 TC2 = 5.90e-6)
.MODEL RSLCMOD RES (TC1=3.46e-3 TC2= 1.26e-6)
.MODEL RSOURCEMOD RES (TC1=3.69e-3 TC2=5.90e-6)
.MODEL RVTHRESMOD RES (TC=-5.19e-4 TC2= 5.02e-6)
.MODEL RVTEMPMOD RES (TC1 = -3.54e- 3TC2 = -6.53e-7)
.MODEL S1AMOD VSWITCH (RON = 1e-5
.MODEL S1BMOD VSWITCH (RON = 1e-5
.MODEL S2AMOD VSWITCH (RON = 1e-5
.MODEL S2AMOD VSWITCH (RON = 1e-5
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
VON = 6.94 VOFF= 3.94)
VON = 3.94 VOFF= 6.94)
VON = 0.40 VOFF= -2.60)
VON = -2.60 VOFF= 0.40)
.ENDS
NOTE:For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options;IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
©2002 Fairchild Semiconductor Corporation
RF1K49223 Rev. B
RF1K49223
PSPICE Thermal Model
7
JUNCTION
REV 28 Feb 97
RF1K49223
CTHERM1 7 6 1.00e-7
CTHERM2 6 5 9.00e-4
CTHERM3 5 4 3.00e-3
CTHERM4 4 3 4.00e-2
CTHERM5 3 2 5.20e-3
CTHERM6 2 1 1.90e-2
RTHERM1
RTHERM1 7 6 7.10e-2
RTHERM2 6 5 1.90e-1
RTHERM3 5 4 5.95e-1
RTHERM4 4 3 4.27
RTHERM5 3 2 1.2e1
RTHERM6 2 1 1.04e2
RTHERM2
CTHERM1
6
CTHERM2
5
RTHERM3
CTHERM3
4
RTHERM4
CTHERM4
3
RTHERM5
CTHERM5
2
RTHERM6
CTHERM6
1
©2002 Fairchild Semiconductor Corporation
CASE
RF1K49223 Rev. B
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FASTr™
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QS™
QT Optoelectronics™
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SuperSOT™-8
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effectiveness.
reasonably expected to result in significant injury to the
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PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or
In Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Obsolete
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. H4