1 Megabit (128K x8) Page-Mode EEPROM SST29EE010 / SST29LE010 / SST29VE010 Data Sheet FEATURES: • Single Voltage Read and Write Operations – 5.0V-only for the SST29EE010 – 3.0-3.6V for the SST29LE010 – 2.7-3.6V for the SST29VE010 • Superior Reliability – Endurance: 100,000 Cycles (typical) – Greater than 100 years Data Retention • Low Power Consumption – Active Current: 20 mA (typical) for 5V and 10 mA (typical) for 3.0/2.7V – Standby Current: 10 µA (typical) • Fast Page-Write Operation – 128 Bytes per Page, 1024 Pages – Page-Write Cycle: 5 ms (typical) – Complete Memory Rewrite: 5 sec (typical) – Effective Byte-Write Cycle Time: 39 µs (typical) • Fast Read Access Time – 5.0V-only operation: 90 and 120 ns – 3.0-3.6V operation: 150 and 200 ns – 2.7-3.6V operation: 200 and 250 ns • Latched Address and Data • Automatic Write Timing – Internal VPP Generation • End of Write Detection – Toggle Bit – Data# Polling • Hardware and Software Data Protection 1 2 3 4 • TTL I/O Compatibility • JEDEC Standard – Flash EEPROM Pinouts and command sets • Packages Available – 32 Pin PDIP – 32-Pin PLCC – 32-Pin TSOP (8mm x 14mm, 8mm x 20mm) 5 6 7 PRODUCT DESCRIPTION The SST29EE010/29LE010/29VE010 are 128K x8 CMOS Page-Write EEPROMs manufactured with SST’s proprietary, high performance CMOS SuperFlash technology. The split-gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST29EE010/29LE010/29VE010 write with a single power supply. Internal Erase/Program is transparent to the user. The SST29EE010/29LE010/29VE010 conform to JEDEC standard pinouts for byte-wide memories. Featuring high performance Page-Write, the SST29EE010/29LE010/29VE010 provide a typical ByteWrite time of 39 µsec. The entire memory, i.e., 128 KBytes, can be written page-by-page in as little as 5 seconds, when using interface features such as Toggle Bit or Data# Polling to indicate the completion of a Write cycle. To protect against inadvertent write, the SST29EE010/29LE010/29VE010 have on-chip hardware and Software Data Protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, the SST29EE010/29LE010/29VE010 are offered with a guaranteed Page-Write endurance of 104 cycles. Data retention is rated at greater than 100 years. The SST29EE010/29LE010/29VE010 are suited for applications that require convenient and economical updating of program, configuration, or data memory. For all system applications, the SST29EE010/29LE010/ 29VE010 significantly improve performance and reliability, while lowering power consumption. The SST29EE010/29LE010/29VE010 improve flexibility while lowering the cost for program, data, and configuration storage applications. To meet high density, surface mount requirements, the SST29EE010/29LE010/29VE010 are offered in 32-pin TSOP and 32-lead PLCC packages. A 600-mil, 32-pin PDIP package is also available. See Figures 1 and 2 for pinouts. Device Operation The SST Page-Mode EEPROM offers in-circuit electrical write capability. The SST29EE010/29LE010/29VE010 does not require separate Erase and Program operations. The internally timed write cycle executes both erase and program transparently to the user. The SST29EE010/29LE010/29VE010 have industry standard optional Software Data Protection, which SST recommends always to be enabled. The SST29EE010/ 29LE010/29VE010 are compatible with industry standard EEPROM pinouts and functionality. Read The Read operations of the SST29EE010/29LE010/ 29VE010 are controlled by CE# and OE#, both have to be low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the © 2000 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. 304-4 11/00 S71061 1 SSF is a trademark of Silicon Storage Technology, Inc. These specifications are subject to change without notice. 8 9 10 11 12 13 14 15 16 1 Megabit Page-Mode EEPROM SST29EE010 / SST29LE010 / SST29VE010 chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. Refer to the read cycle timing diagram for further details (Figure 3). the end of the Page-Write. The page load cycle consists of loading 1 to 128 bytes of data into the page buffer. The internal write cycle consists of the TBLCO time-out and the write timer operation. During the Write operation, the only valid reads are Data# Polling and Toggle Bit. The Page-Write operation allows the loading of up to 128 bytes of data into the page buffer of the SST29EE010/ 29LE010/29VE010 before the initiation of the internal write cycle. During the internal write cycle, all the data in the page buffer is written simultaneously into the memory array. Hence, the Page-Write feature of SST29EE010/ 29LE010/29VE010 allow the entire memory to be written in as little as 5 seconds. During the internal write cycle, the host is free to perform additional tasks, such as to fetch data from other locations in the system to set up the write to the next page. In each Page-Write operation, all the bytes that are loaded into the page buffer must have the same page address, i.e. A7 through A16. Any byte not loaded with user data will be written to FFH. Write The Page-Write to the SST29EE010/29LE010/29VE010 should always use the JEDEC Standard Software Data Protection (SDP) three-byte command sequence. The SST29EE010/29LE010/29VE010 contain the optional JEDEC approved Software Data Protection scheme. SST recommends that SDP always be enabled, thus, the description of the Write operations will be given using the SDP enabled format. The three-byte SDP Enable and SDP Write commands are identical; therefore, any time a SDP Write command is issued, Software Data Protection is automatically assured. The first time the three-byte SDP command is given, the device becomes SDP enabled. Subsequent issuance of the same command bypasses the data protection for the page being written. At the end of the desired Page-Write, the entire device remains protected. For additional descriptions, please see the application notes on “The Proper Use of JEDEC Standard Software Data Protection” and “Protecting Against Unintentional Writes When Using Single Power Supply Flash Memories” in this data book. See Figures 4 and 5 for the Page-Write cycle timing diagrams. If after the completion of the three-byte SDP load sequence or the initial byte-load cycle, the host loads a second byte into the page buffer within a byteload cycle time (TBLC) of 100 µs, the SST29EE010/ 29LE010/29VE010 will stay in the page load cycle. Additional bytes are then loaded consecutively. The page load cycle will be terminated if no additional byte is loaded into the page buffer within 200 µs (TBLCO) from the last byte-load cycle, i.e., no subsequent WE# or CE# high-to-low transition after the last rising edge of WE# or CE#. Data in the page buffer can be changed by a subsequent byte-load cycle. The page load period can continue indefinitely, as long as the host continues to load the device within the byte-load cycle time of 100 µs. The page to be loaded is determined by the page address of the last byte loaded. The Write operation consists of three steps. Step 1 is the three-byte load sequence for Software Data Protection. Step 2 is the byte-load cycle to a page buffer of the SST29EE010/29LE010/29VE010. Steps 1 and 2 use the same timing for both operations. Step 3 is an internally controlled write cycle for writing the data loaded in the page buffer into the memory array for nonvolatile storage. During both the SDP three-byte load sequence and the byte-load cycle, the addresses are latched by the falling edge of either CE# or WE#, whichever occurs last. The data is latched by the rising edge of either CE# or WE#, whichever occurs first. The internal write cycle is initiated by the TBLCO timer after the rising edge of WE# or CE#, whichever occurs first. The Write cycle, once initiated, will continue to completion, typically within 5 ms. See Figures 4 and 5 for WE# and CE# controlled PageWrite cycle timing diagrams and Figures 14 and 16 for flowcharts. Software Chip-Erase The SST29EE010/29LE010/29VE010 provide a ChipErase operation, which allows the user to simultaneously clear the entire memory array to the “1” state. This is useful when the entire device must be quickly erased. The Software Chip-Erase operation is initiated by using a specific six-byte load sequence. After the load sequence, the device enters into an internally timed cycle similar to the Write cycle. During the Erase operation, the only valid read is Toggle Bit. See Table 4 for the load sequence, Figure 9 for timing diagram, and Figure 18 for the flowchart. The Write operation has three functional cycles: the Software Data Protection load sequence, the page load cycle, and the internal write cycle. The Software Data Protection consists of a specific three-byte load sequence that allows writing to the selected page and will leave the SST29EE010/29LE010/29VE010 protected at © 2000 Silicon Storage Technology, Inc. 2 S71061 304-4 11/00 1 Megabit Page-Mode EEPROM SST29EE010 / SST29LE010 / SST29VE010 Write Operation Status Detection The SST29EE010/29LE010/29VE010 provide two software means to detect the completion of a Write cycle, in order to optimize the system write cycle time. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The end of write detection mode is enabled after the rising WE# or CE# whichever occurs first, which initiates the internal write cycle. Hardware Data Protection Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a Write cycle. 1 VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 2.5V. Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down. The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid. Software Data Protection (SDP) The SST29EE010/29LE010/29VE010 provide the JEDEC approved optional Software Data Protection scheme for all data alteration operations, i.e., Write and Chip-Erase. With this scheme, any Write operation requires the inclusion of a series of three byte-load operations to precede the data loading operation. The three byte-load sequence is used to initiate the Write cycle, providing optimal protection from inadvertent write operations, e.g., during the system power-up or power-down. The SST29EE010/29LE010/29VE010 are shipped with the Software Data Protection disabled. Data# Polling (DQ7) When the SST29EE010/29LE010/29VE010 are in the internal write cycle, any attempt to read DQ7 of the last byte loaded during the byte-load cycle will receive the complement of the true data. Once the Write cycle is completed, DQ7 will show true data. The device is then ready for the next operation. See Figure 6 for Data# Polling timing diagram and Figure 15 for a flowchart. The software protection scheme can be enabled by applying a three-byte sequence to the device, during a page-load cycle (Figures 4 and 5). The device will then be automatically set into the data protect mode. Any subsequent Write operation will require the preceding three-byte sequence. See Table 4 for the specific software command codes and Figures 4 and 5 for the timing diagrams. To set the device into the unprotected mode, a six-byte sequence is required. See Table 4 for the specific codes and Figure 8 for the timing diagram. If a write is attempted while SDP is enabled the device will be in a non-accessible state for ~ 300 µs. SST recommends Software Data Protection always be enabled. See Figure 16 for flowcharts. Toggle Bit (DQ6) During the internal write cycle, any consecutive attempts to read DQ6 will produce alternating 0’s and 1’s, i.e. toggling between 0 and 1. When the Write cycle is completed, the toggling will stop. The device is then ready for the next operation. See Figure 7 for Toggle Bit timing diagram and Figure 15 for a flowchart. The initial read of the Toggle Bit will typically be a “1”. The SST29EE010/29LE010/29VE010 Software Data Protection is a global command, protecting (or unprotecting) all pages in the entire memory array once enabled (or disabled). Therefore using SDP for a single Page-Write will enable SDP for the entire array. Single pages by themselves cannot be SDP enabled or disabled. Data Protection The SST29EE010/29LE010/29VE010 provide both hardware and software features to protect nonvolatile data from inadvertent writes. 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 © 2000 Silicon Storage Technology, Inc. 3 S71061 304-4 11/00 1 Megabit Page-Mode EEPROM SST29EE010 / SST29LE010 / SST29VE010 Single power supply reprogrammable nonvolatile memories may be unintentionally altered. SST strongly recommends that Software Data Protection (SDP) always be enabled. The SST29EE010/29LE010/29VE010 should be programmed using the SDP command sequence. SST recommends the SDP Disable Command Sequence not be issued to the device prior to writing. TABLE 1: PRODUCT IDENTIFICATION Manufacturer’s ID SST29EE010 Device ID SST29LE010 Device ID SST29VE010 Device ID Please refer to the following Application Notes located at the back of this databook for more information on using SDP: • Protecting Against Unintentional Writes When Using Single Power Supply Flash Memories • The Proper Use of JEDEC Standard Software Data Protection Byte 0000 H 0001 H 0001 H 0001 H Data BF H 07 H 08 H 08 H 304 PGM T1.2 Product Identification Mode Exit In order to return to the standard read mode, the Software Product Identification mode must be exited. Exiting is accomplished by issuing the Software ID Exit (reset) operation, which returns the device to the Read operation. The Reset operation may also be used to reset the device to the Read mode after an inadvertent transient condition that apparently causes the device to behave abnormally, e.g. not read correctly. See Table 4 for software command codes, Figure 11 for timing waveform and Figure 17 for a flowchart. Product Identification The product identification mode identifies the device as the SST29EE010/29LE010/29VE010 and manufacturer as SST. This mode is accessed via software. For details, see Table 4, Figure 10 for the software ID entry and read timing diagram and Figure 17 for the ID entry command sequence flowchart. FUNCTIONAL BLOCK DIAGRAM OF SST29EE010/29LE010/29VE010 X-Decoder A16 - A0 SuperFlash Memory Address Buffer & Latches Y-Decoder and Page Latches CE# OE# WE# Control Logic I/O Buffers and Data Latches DQ7 - DQ0 © 2000 Silicon Storage Technology, Inc. 4 304 ILL B1.1 S71061 304-4 11/00 1 Megabit Page-Mode EEPROM SST29EE010 / SST29LE010 / SST29VE010 A11 A9 A8 A13 A14 NC WE# VDD NC A16 A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Standard Pinout Top View Die Up 1 2 3 4 304 ILL F01.2 FIGURE 1: PIN ASSIGNMENTS FOR 32-PIN TSOP NC VDD 4 3 2 1 32 31 30 29 NC A16 WE# A15 6 5 A6 6 28 A13 A5 7 27 A8 A4 8 26 A9 A3 9 25 A11 A2 10 24 OE# A1 11 23 A10 A0 12 22 CE# DQ0 13 21 14 15 16 17 18 19 20 DQ7 DQ5 DQ4 DQ3 32-Lead PLCC Top View DQ6 A7 VSS VDD WE# NC A14 A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A12 1 2 3 4 5 32-Pin 6 PDIP 7 8 Top View 9 10 11 12 13 14 15 16 DQ1 NC A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 5 A14 7 8 9 10 304 ILL F02.1 FIGURE 2: PIN ASSIGNMENTS FOR 32-PIN PLASTIC DIPS AND 32-LEAD PLCCS TABLE 2: PIN DESCRIPTION Symbol Pin Name A16-A7 Row Address Inputs A6-A0 DQ7-DQ0 Column Address Inputs Data Input/output CE# OE# WE# VDD Chip Enable Output Enable Write Enable Power Supply VSS NC Ground No Connection 11 Functions To provide memory addresses. Row addresses define a page for a Write cycle. Column Addresses are toggled to load page data. 12 13 To output data during Read cycles and receive input data during Write cycles. Data is internally latched during a Write cycle. The outputs are in tri-state when OE# or CE# is high. To activate the device when CE# is low. To gate the data output buffers. To control the Write operations To provide 5-volt supply (± 10%) for the SST29EE010, 3-volt supply (3.0-3.6V) for the SST29LE010 and 2.7-volt supply (2.7-3.6V) for the SST29VE010 Unconnected pins. 304 PGM T2.0 © 2000 Silicon Storage Technology, Inc. 5 S71061 304-4 11/00 14 15 16 1 Megabit Page-Mode EEPROM SST29EE010 / SST29LE010 / SST29VE010 TABLE 3: OPERATION MODES SELECTION Mode CE# Read VIL Page-Write VIL Standby VIH Write Inhibit X Write Inhibit X Software Chip-Erase VIL Product Identification Software Mode VIL SDP Enable Mode SDP Disable Mode VIL V IL OE# VIL VIH X VIL X VIH WE# VIH VIL X X VIH VIL DQ DOUT DIN High Z High Z/ DOUT High Z/ DOUT DIN Address AIN AIN X X X AIN, See Table 4 VIH VIL Manufacturer’s ID (BFH) Device ID (see notes) See Table 4 VIH VIH VIL VIL See Table 4 See Table 4 304 PGM T3.1 TABLE 4: SOFTWARE COMMAND CODES Command Sequence 1st Bus Write Cycle Addr(1) Data 5555H AAH 2nd Bus Write Cycle Addr(1) Data 2AAAH 55H 3rd Bus Write Cycle Addr(1) Data 5555H A0H 4th Bus Write Cycle Addr(1) Data Addr(2) Data 5th Bus Write Cycle Addr(1) Data 6th Bus Write Cycle Addr(1) Data 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 20H 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H 5555H AAH 2AAAH 55H 5555H 90H 5555H AAH 2AAAH 55H 5555H F0H Alternate Software 5555H ID Entry(3) AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H Software Data Protect Enable & Page-Write Software Data Protect Disable Software ChipErase Software ID Entry Software ID Exit 60H 304 PGM T4.1 Notes: (1) Address format A14-A0 (Hex), Addresses A15 and A16 are a “Don’t Care”. Page-Write consists of loading up to 128 Bytes (A6 - A0). (3) Alternate six-byte software Product-ID Command Code (4) The software Chip-Erase function is not supported by the industrial temperature part. Please contact SST, if you require this function for an industrial temperature part. Notes for Software Product ID Command Code: 1. With A14 -A1 =0; SST Manufacturer’s ID = BFH, is read with A0 = 0, SST29EE010 Device ID = 07H, is read with A0 = 1. SST29LE010/29VE010 Device ID = 08H, is read with A0 = 1. 2. The device does not remain in Software Product ID Mode if powered down. 3. This device supports both the JEDEC standard three-byte command code sequence and SST’s original six-byte command code sequence. For new designs, SST recommends the three-byte command code sequence be used. (2) © 2000 Silicon Storage Technology, Inc. 6 S71061 304-4 11/00 1 Megabit Page-Mode EEPROM SST29EE010 / SST29LE010 / SST29VE010 Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias ................................................................................................................. -55°C to +125°C Storage Temperature ...................................................................................................................... -65°C to +150°C D. C. Voltage on Any Pin to Ground Potential .............................................................................. -0.5V to VDD+ 0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential .......................................................... -1.0V to VDD+ 1.0V Voltage on A9 Pin to Ground Potential ................................................................................................. -0.5V to 14.0V Package Power Dissipation Capability (Ta = 25°C) ............................................................................................ 1.0W Through Hole Lead Soldering Temperature (10 Seconds) .................................................................................. 300°C Surface Mount Lead Soldering Temperature (3 Seconds) .................................................................................. 240°C Output Short Circuit Current(1) ........................................................................................................................ 100 mA Note: (1) Outputs shorted for no more than one second. No more than one output shorted at a time. SST29EE010 OPERATING RANGE Range Ambient Temp Commercial 0°C to +70°C Industrial -40°C to +85°C VDD 5V±10% 5V±10% SST29LE010 OPERATING RANGE Range Ambient Temp Commercial 0°C to +70°C Industrial -40°C to +85°C VDD 3.0-3.6V 3.0-3.6V SST29VE010 OPERATING RANGE Range Ambient Temp Commercial 0°C to +70°C Industrial -40°C to +85°C VDD 2.7-3.6V 2.7-3.6V 1 2 3 4 5 6 AC CONDITIONS OF TEST Input Rise/Fall Time ......... 10 ns Output Load ..................... 1 TTL Gate and CL = 100 pF 7 See Figures 12 and 13 8 9 10 11 12 13 14 15 16 © 2000 Silicon Storage Technology, Inc. 7 S71061 304-4 11/00 1 Megabit Page-Mode EEPROM SST29EE010 / SST29LE010 / SST29VE010 TABLE 5: SST29EE010 DC OPERATING CHARACTERISTICS VDD = 5V±10% Limits Symbol Parameter Min Max Units IDD Power Supply Current I SB1 I SB2 I LI I LO VIL VIH VOL VOH Read Write Standby VDD Current (TTL input) Standby VDD Current (CMOS input) Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage 30 50 3 mA mA mA 50 µA 1 10 0.8 µA µA V V V V 2.0 0.4 2.4 Test Conditions Address input = VIL/VIH, at f=1/TRC Min., VDD=VDD Max. CE#=OE#=VIL,WE#=VIH , all I/Os open. CE#=WE#=VIL, OE#=VIH, VDD =VDD Max. CE#=OE#=WE#=VIH, VDD =VDD Max. CE#=OE#=WE#=VDD -0.3V. VDD = VDD Max. VIN =GND to VDD, VDD = VDD Max. VOUT =GND to VDD, VDD = VDD Max. VDD = VDD Min. VDD = VDD Max. IOL = 2.1 mA, VDD = VDD Min. IOH = -400µA, VDD = VDD Min. 304 PGM T5.2 TABLE 6: SST29LE010/29VE010 DC OPERATING CHARACTERISTICS VDD = 3.0-3.6 FOR SST29LE010, VDD = 2.7-3.6 FOR SST29VE010 Limits Symbol Parameter Min Max Units Test Conditions Power Supply Current Address input = VIL/VIH, at f=1/TRC Min., IDD VDD=VDD Max. Read 12 mA CE#=OE#=VIL,WE#=VIH , all I/Os open. Write 15 mA CE#=WE#=VIL, OE#=VIH, VDD =VDD Max. I SB1 Standby VDD Current 1 mA CE#=OE#=WE#=VIH, VDD =VDD Max. (TTL input) I SB2 Standby VDD Current 15 µA CE#=OE#=WE#=VDD -0.3V. (CMOS input) VDD = VDD Max. I LI Input Leakage Current 1 µA VIN =GND to VDD, VDD = VDD Max. I LO Output Leakage Current 10 µA VOUT =GND to VDD, VDD = VDD Max. VIL Input Low Voltage 0.8 V VDD = VDD Min. Input High Voltage 2.0 V VDD = VDD Max. VIH VOL Output Low Voltage 0.4 V IOL = 100 µA, VDD = VDD Min. VOH Output High Voltage 2.4 V IOH = -100 µA, VDD = VDD Min. 304 PGM T6.2 © 2000 Silicon Storage Technology, Inc. 8 S71061 304-4 11/00 1 Megabit Page-Mode EEPROM SST29EE010 / SST29LE010 / SST29VE010 TABLE 7: POWER-UP TIMINGS Symbol Parameter TPU-READ(1) Power-up to Read Operation (1) TPU-WRITE Power-up to Write Operation Maximum 100 5 Units µs ms 1 304 PGM T7.0 TABLE 8: CAPACITANCE (Ta = 25 °C, f=1 MHz, other pins open) Parameter Description Test Condition I/O Pin Capacitance VI/O = 0V CI/O(1) CIN(1) Input Capacitance VIN = 0V Maximum 12 pF 6 pF 2 3 304 PGM T8.0 Note: (1)This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. 4 5 TABLE 9: RELIABILITY CHARACTERISTICS Symbol Parameter NEND Endurance TDR(1) Data Retention (1) VZAP_HBM ESD Susceptibility Human Body Model VZAP_MM(1) ESD Susceptibility Machine Model ILTH(1) Latch Up Minimum Specification 10,000 100 2000 Units Cycles Years Volts Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard A114 6 200 Volts JEDEC Standard A115 8 100 mA JEDEC Standard 78 304 PGM T9.3 Note: (1)This 7 parameter is measured only for initial qualification and after a design or process change that could affect this parameter. 9 10 11 12 13 14 15 16 © 2000 Silicon Storage Technology, Inc. 9 S71061 304-4 11/00 1 Megabit Page-Mode EEPROM SST29EE010 / SST29LE010 / SST29VE010 AC CHARACTERISTICS TABLE 10: SST29EE010 READ CYCLE TIMING PARAMETERS SST29EE010-90 SST29EE010-120 Symbol Parameter TRC Read Cycle Time TCE Chip Enable Access Time TAA TOE Min Max 90 Min Max 120 Units ns 90 120 ns Address Access Time 90 120 ns Output Enable Access Time 40 50 ns TCLZ(1) CE# Low to Active Output 0 0 ns (1) OE# Low to Active Output 0 0 ns TOLZ TCHZ(1) TOHZ(1) TOH(1) CE# High to High-Z Output 30 30 ns OE# High to High-Z Output 30 30 ns Output Hold from Address Change 0 0 ns 304 PGM T10.1 TABLE 11: SST29LE010 READ CYCLE TIMING PARAMETERS Symbol TRC TCE TAA TOE TCLZ(1) TOLZ(1) TCHZ(1) TOHZ(1) TOH(1) SST29LE010-150 SST29LE010-200 Min Max Min Max 150 200 150 200 150 200 60 100 0 0 0 0 30 50 30 50 0 0 Parameter Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time CE# Low to Active Output OE# Low to Active Output CE# High to High-Z Output OE# High to High-Z Output Output Hold from Address Change Units ns ns ns ns ns ns ns ns ns 304 PGM T11.0 TABLE 12: SST29VE010 READ CYCLE TIMING PARAMETERS Symbol TRC TCE TAA TOE TCLZ(1) TOLZ(1) TCHZ(1) TOHZ(1) TOH(1) SST29VE010-200 SST29VE010-250 Min Max Min Max 200 250 200 250 200 250 100 120 0 0 0 0 50 50 50 50 0 0 Parameter Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time CE# Low to Active Output OE# Low to Active Output CE# High to High-Z Output OE# High to High-Z Output Output Hold from Address Change Units ns ns ns ns ns ns ns ns ns 304 PGM T12.0 © 2000 Silicon Storage Technology, Inc. 10 S71061 304-4 11/00 1 Megabit Page-Mode EEPROM SST29EE010 / SST29LE010 / SST29VE010 TABLE 13: PAGE-WRITE CYCLE TIMING PARAMETERS Symbol TWC TAS TAH TCS TCH TOES TOEH TCP TWP TDS TDH TBLC(1) TBLCO(1) TIDA TSCE Parameter Write Cycle (Erase and Program) Address Setup Time Address Hold Time WE# and CE# Setup Time WE# and CE# Hold Time OE# High Setup Time OE# High Hold Time CE# Pulse Width WE# Pulse Width Data Setup Time Data Hold Time Byte Load Cycle Time Byte Load Cycle Time Software ID Access and Exit Time Software Chip-Erase SST29EE010 Min Max 10 0 50 0 0 0 0 70 70 35 0 0.05 100 200 10 20 SST29LE/VE010 Min Max 10 0 70 0 0 0 0 120 120 50 0 0.05 100 200 10 20 Units ms ns ns ns ns ns ns ns ns ns ns µs µs µs ms 1 2 3 4 5 6 7 304 PGM T13.3 Note: (1)This parameter is measured only for initial qualification and after the design or process change that could affect this parameter. 8 9 10 11 12 13 14 15 16 © 2000 Silicon Storage Technology, Inc. 11 S71061 304-4 11/00 1 Megabit Page-Mode EEPROM SST29EE010 / SST29LE010 / SST29VE010 TRC TAA ADDRESS A16-0 TCE CE# TOE OE# TOHZ TOLZ VIH WE# HIGH-Z TCHZ TOH TCLZ HIGH-Z DATA VALID DQ 7-0 DATA VALID 304 ILL F03.0 FIGURE 3: READ CYCLE TIMING DIAGRAM Three-Byte Sequence for Enabling SDP ADDRESS A16-0 5555 2AAA TAH TAS 5555 TCS TCH CE# TOES TOEH OE# TWP TBLCO TBLC WE# TDH DQ 7-0 AA 55 SW0 SW1 A0 DATA VALID TWC TDS SW2 BYTE 0 BYTE 1 BYTE 127 304 ILL F04.1 FIGURE 4: WE# CONTROLLED PAGE-WRITE CYCLE TIMING DIAGRAM © 2000 Silicon Storage Technology, Inc. 12 S71061 304-4 11/00 1 Megabit Page-Mode EEPROM SST29EE010 / SST29LE010 / SST29VE010 Three-Byte Sequence for Enabling SDP ADDRESS A16-0 5555 2AAA TAH 1 TAS 5555 TCP 2 TBLCO TBLC CE# 3 TOES TOEH OE# 4 TCS TCH WE# 5 TDH DQ 7-0 AA 55 SW0 SW1 A0 DATA VALID BYTE 0 6 TWC TDS SW2 BYTE 1 BYTE 127 304 ILL F05.1 7 FIGURE 5: CE# CONTROLLED PAGE-WRITE CYCLE TIMING DIAGRAM 8 9 10 ADDRESS A16-0 TCE 11 CE# TOES TOEH 12 OE# TOE 13 WE# DQ 7 D D# D# 14 D TWC + TBLCO 304 ILL F06.0 15 16 FIGURE 6: DATA# POLLING TIMING DIAGRAM © 2000 Silicon Storage Technology, Inc. 13 S71061 304-4 11/00 1 Megabit Page-Mode EEPROM SST29EE010 / SST29LE010 / SST29VE010 ADDRESS A16-0 TCE CE# TOEH TOES TOE OE# WE# DQ6 TWC + TBLCO TWO READ CYCLES WITH SAME OUTPUTS 304 ILL F07.0 FIGURE 7: TOGGLE BIT TIMING DIAGRAM Six-Byte Sequence for Disabling Software Data Protection ADDRESS A14-0 DQ 7-0 5555 AA 2AAA 5555 55 5555 80 2AAA AA TWC 5555 55 20 CE# OE# TBLCO TWP WE# TBLC SW0 SW1 SW2 SW3 SW4 SW5 304 ILL F08.1 FIGURE 8: SOFTWARE DATA PROTECT DISABLE TIMING DIAGRAM © 2000 Silicon Storage Technology, Inc. 14 S71061 304-4 11/00 1 Megabit Page-Mode EEPROM SST29EE010 / SST29LE010 / SST29VE010 Six-Byte Code for Software Chip-Erase ADDRESS A14-0 5555 DQ 7-0 2AAA AA 5555 55 5555 80 2AAA AA 1 TSCE 5555 55 2 10 3 CE# 4 5 OE# TBLCO TWP 6 WE# TBLC SW0 SW1 SW2 SW3 SW4 7 SW5 304 ILL F09.1 FIGURE 9: SOFTWARE CHIP-ERASE TIMING DIAGRAM 8 9 Three-Byte Sequence for Software ID Entry ADDRESS A14-0 5555 2AAA 10 0000 5555 0001 11 TAA DQ 7-0 AA 55 90 BF DEVICE ID 12 TIDA CE# 13 OE# 14 TWP WE# 15 TBLC SW0 SW1 SW2 DEVICE ID = 07H for SST29EE010 = 08H for SST29LE010/29VE010 304 ILL F10.2 FIGURE 10: SOFTWARE ID ENTRY AND READ © 2000 Silicon Storage Technology, Inc. 15 S71061 304-4 11/00 16 1 Megabit Page-Mode EEPROM SST29EE010 / SST29LE010 / SST29VE010 Three-Byte Sequence for Software ID Exit and Reset ADDRESS A14-0 DQ 7-0 5555 AA 2AAA 5555 55 F0 TIDA CE# OE# TWP WE# TBLC SW0 SW1 SW2 304 ILL F11.0 FIGURE 11: SOFTWARE ID EXIT AND RESET © 2000 Silicon Storage Technology, Inc. 16 S71061 304-4 11/00 1 Megabit Page-Mode EEPROM SST29EE010 / SST29LE010 / SST29VE010 1 VIHT VHT INPUT VHT REFERENCE POINTS OUTPUT VLT VLT 2 VILT 304 ILL F12.1 AC test inputs are driven at VIHT (2.4 V) for a logic “1” and VILT (0.4 V) for a logic “0”. Measurement reference points for inputs and outputs are VHT (2.0 V) and VLT (0.8 V). Inputs rise and fall times (10% « 90%) are <10 ns. Note: VHT–VHIGH Test VLT–VLOW Test VIHT–VINPUT HIGH Test VILT–VINPUT LOW Test 3 4 5 FIGURE 12: AC INPUT/OUTPUT REFERENCE WAVEFORMS 6 7 TEST LOAD EXAMPLE 8 VDD TO TESTER 9 RL HIGH 10 TO DUT 11 CL RL LOW 12 13 304 ILL F13.1 14 FIGURE 13: A TEST LOAD EXAMPLE 15 16 © 2000 Silicon Storage Technology, Inc. 17 S71061 304-4 11/00 1 Megabit Page-Mode EEPROM SST29EE010 / SST29LE010 / SST29VE010 Start Software Data Protect Write Command See Figure 16 Set Page Address Set Byte Address = 0 Load Byte Data Increment Byte Address By 1 No Byte Address = 128? Yes Wait TBLCO Wait for end of Write (TWC, Data# Polling bit or Toggle bit operation) Write Completed 304 ILL F14.0 FIGURE 14: WRITE ALGORITHM © 2000 Silicon Storage Technology, Inc. 18 S71061 304-4 11/00 1 Megabit Page-Mode EEPROM SST29EE010 / SST29LE010 / SST29VE010 Internal Timer Toggle Bit Data# Polling Page-Write Initiated Page-Write Initiated Page-Write Initiated 1 2 3 Write Completed Read same byte 4 Read DQ7 (Data for last byte loaded) Read a byte from page Wait TWC 5 6 No Is DQ7 = true data? 7 Yes No Does DQ6 match? 8 Write Completed 9 Yes 10 Write Completed 304 ILL F15.1 11 12 FIGURE 15: WAIT OPTIONS 13 14 15 16 © 2000 Silicon Storage Technology, Inc. 19 S71061 304-4 11/00 1 Megabit Page-Mode EEPROM SST29EE010 / SST29LE010 / SST29VE010 Software Data Protect Enable Command Sequence Software Data Protect Disable Command Sequence Write data: AAH Address: 5555H Write data: AAH Address: 5555H Write data: 55H Address: 2AAAH Write data: 55H Address: 2AAAH Write data: A0H Address: 5555H Write data: 80H Address: 5555H Load 0 to 128 Bytes of page data Optional Page Load Operation Write data: AAH Address: 5555H Write data: 55H Address: 2AAAH Wait TBLCO Write data: 20H Address: 5555H Wait TWC Wait TBLCO SDP Enabled Wait TWC SDP Disabled 304 ILL F16.1 FIGURE 16: SOFTWARE DATA PROTECTION FLOWCHARTS © 2000 Silicon Storage Technology, Inc. 20 S71061 304-4 11/00 1 Megabit Page-Mode EEPROM SST29EE010 / SST29LE010 / SST29VE010 Software Product ID Entry Command Sequence Software Product ID Exit & Reset Command Sequence 1 Write data: AAH Address: 5555H Write data: AAH Address: 5555H 2 3 Write data: 55H Address: 2AAAH Write data: 55H Address: 2AAAH Write data: 90H Address: 5555H Write data: F0H Address: 5555H 4 5 6 Pause 10 µs Pause 10 µs Read Software ID Return to normal operation 7 8 9 304 ILL F17.1 10 FIGURE 17: SOFTWARE PRODUCT COMMAND FLOWCHARTS 11 12 13 14 15 16 © 2000 Silicon Storage Technology, Inc. 21 S71061 304-4 11/00 1 Megabit Page-Mode EEPROM SST29EE010 / SST29LE010 / SST29VE010 Software Chip-Erase Command Sequence Write data: AAH Address: 5555H Write data: 55H Address: 2AAAH Write data: 80H Address: 5555H Write data: AAH Address: 5555H Write data: 55H Address: 2AAAH Write data: 10H Address: 5555H Wait TSCE Chip-Erase to FFH 304 ILL F18.2 FIGURE 18: SOFTWARE CHIP-ERASE COMMAND CODES © 2000 Silicon Storage Technology, Inc. 22 S71061 304-4 11/00 1 Megabit Page-Mode EEPROM SST29EE010 / SST29LE010 / SST29VE010 PRODUCT ORDERING INFORMATION Device SST29xE010 Speed - XXX Suffix1 - XX - Suffix2 1 XX 2 Package Modifier H = 32 leads Numeric = Die modifier 3 Package Type P = PDIP N = PLCC E = TSOP (die up) 8mm x 20mm W = TSOP (die up) 8mm x 14mm U = Unencapsulated die 4 5 6 Operating Temperature C = Commercial = 0° to 70°C I = Industrial = -40° to 85°C 7 Minimum Endurance 4 = 10,000 cycles 8 Read Access Speed 250 = 250 ns 200 = 200 ns 150 = 150 ns 120 = 120 ns 90 = 90 ns 9 10 11 Voltage E = 5.0V-only L = 3.0-3.6V V = 2.7-3.6V 12 13 14 15 16 © 2000 Silicon Storage Technology, Inc. 23 S71061 304-4 11/00 1 Megabit Page-Mode EEPROM SST29EE010 / SST29LE010 / SST29VE010 SST29EE010 Valid combinations SST29EE010-90-4C-EH SST29EE010-90-4C-WH SST29EE010-120-4C-EH SST29EE010-120-4C-WH SST29EE010-90-4C-NH SST29EE010-120-4C-NH SST29EE010-90-4I-EH SST29EE010-90-4I-NH SST29EE010-90-4I-WH SST29EE010-90-4C-PH SST29EE010-120-4C-PH SST29EE010-120-4C-U2 SST29LE010 Valid combinations SST29LE010-150-4C-EH SST29LE010-150-4C-WH SST29LE010-150-4I-EH SST29LE010-150-4I-WH SST29LE010-150-4C-NH SST29LE010-150-4I-NH SST29LE010-200-4C-U2 SST29VE010 Valid combinations SST29VE010-200-4C-EH SST29VE010-200-4C-WH SST29VE010-200-4I-EH SST29VE010-200-4I-WH SST29VE010-200-4C-NH SST29VE010-200-4I-NH SST29VE010-250-4C-U2 Example:Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. Note: The software Chip-Erase function is not supported by the industrial temperature part. Please contact SST, if you require this function for an industrial temperature part. © 2000 Silicon Storage Technology, Inc. 24 S71061 304-4 11/00 1 Megabit Page-Mode EEPROM SST29EE010 / SST29LE010 / SST29VE010 PACKAGING DIAGRAMS pin 1 index 1 1 2 CL 3 .600 .625 32 .530 .550 1.645 1.655 .065 .075 7˚ 4 PLCS. 4 .170 .200 Base Plane Seating Plane 5 .015 .050 .070 .080 Note: .045 .065 .016 .022 .008 .012 .120 .150 .100 BSC 0˚ 15˚ 6 .600 BSC 1. Complies with JEDEC publication 95 MO-015 AP dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (min/max). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .010 inches. 7 32.pdipPH-ILL.1 32-LEAD PLASTIC DUAL-IN-LINE PACKAGE (PDIP) SST PACKAGE CODE: PH 8 9 TOP VIEW SIDE VIEW BOTTOM VIEW 10 Optional Pin #1 Identifier .485 .495 .447 .453 .042 .048 2 1 .106 .112 32 .020 R. MAX. .023 x 30˚ .029 11 .030 R. .040 12 .042 .048 .585 .595 .547 .553 .013 .021 .400 BSC .026 .032 .490 .530 13 .050 BSC. 14 .015 Min. .075 .095 .050 BSC. .125 .140 Note: .026 .032 15 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (min/max). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches. 32.PLCC.NH-ILL.1 32-LEAD PLASTIC LEAD CHIP CARRIER (PLCC) SST PACKAGE CODE: NH © 2000 Silicon Storage Technology, Inc. 25 S71061 304-4 11/00 16 1 Megabit Page-Mode EEPROM SST29EE010 / SST29LE010 / SST29VE010 1.05 0.95 PIN # 1 IDENTIFIER .50 BSC .270 .170 8.10 7.90 0.15 0.05 12.50 12.30 0.70 0.50 Note: 14.20 13.80 1. Complies with JEDEC publication 95 MO-142 BA dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (min/max). 3. Coplanarity: 0.1 (±.05) mm. 32.TSOP-WH-ILL.3 32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 8MM X 14MM SST PACKAGE CODE: WH 1.05 0.95 PIN # 1 IDENTIFIER .50 BSC 8.10 7.90 0.15 0.05 18.50 18.30 0.70 0.50 Note: .27 .17 20.20 19.80 1. Complies with JEDEC publication 95 MO-142 BD dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (min/max). 3. Coplanarity: 0.1 (±.05) mm. 32.TSOP-EH-ILL.3 32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 8MM X 20MM SST PACKAGE CODE: EH Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036 www.SuperFlash.com or www.ssti.com • Literature FaxBack 888-221-1178, International 732-544-2873 © 2000 Silicon Storage Technology, Inc. 26 S71061 304-4 11/00