Preliminary Specifications CMOS LSI LE28C1001DT/DTS-90 1M-Bit (128k × 8) Page Mode EEPROM Features Single 5-Volt Read and Write Operations CMOS Flash EEPROM Technology Page-write Endurance Cycles: 104 10 Years Data Retention Low Power Consumption: Active Current: 30 mA (Max.) Standby Current: 20 µA (Max.) Fast Page-Write Operation 128 Bytes per Page Page-Write Cycle: 5 ms (typical) Complete Memory Rewrite: 5 sec. (typical) Product Description The LE28C1001D is a 128K×8 CMOS page mode EEPROM manufactured with SANYO's proprietary, high performance CMOS Flash EEPROM Technology. Breakthrough in EEPROM cell design and process architecture attain better reliability and manufacturability compared with conventional approaches. The LE28C1001D performs write in a 5-volt-only power supply environment. Internal erase/program is transparent to the user. The LE28C1001D conforms to JEDEC standard pinouts for byte-wide memories and is compatible with existing industry standard EPROM, flash EPROM and EEPROM pinouts. Featuring high performance page write, the LE28C1001D provides an typical byte-write time of 39 µ sec. The entire memory, i.e.128K bytes, can be written in as little as 5 seconds using interface such as Toggle Bit and DATA Polling to indicate the completion of a write cycle. To protect against inadvertent write, the LE28C1001D has on-chip hardware and software data protection schemes. Designed, manufactured and tested for a wide spectrum of applications, the LE28C1001D is offered with page-write endurance 104 cycles. Data retention is rated at greater than 10 years. Fast Access Time: 90 ns Latched Address and Data Automatic Write Timing with Internal VPP Generation End of Write Detection Toggle Bit DATA Polling Hardware and Software Data Protection TTL I/O Compatibility JEDEC Standard Byte-Wide EEPROM Pinouts Packages Available LE28C1001DT : 32-pin TSOP (8mm × 20mm) Normal LE28C1001DTS : 32-pin TSOP (8mm × 14mm) Normal The LE28C1001D is best suited for application that require reprogrammable nonvolatile storage of program or data memory for laptop computers, desktop computers, medical instruments, laser printers, or copiers. For all system applications, the LE28C1001D significantly improves performance and reliability, while lowering power consumption, when compared with floppy disk or EPROM approaches. In addtion, the EEPROM technology makes convenient and economical updating of codes and control programs on-line possible. The LE28C1001D improves flexibility while lowering the cost for program and configuration storage applications such as operating systems, BIOS, control programs, software I/O drivers, fonts, or archives. To meet high density, surface mount requirements, the LE28C1001D is offered in 32-pin TSOP package. Device Operation Both the high and medium endurance parts are identical in functionality and features. The LE28C1001D is compatible to industry standard pinout and functionality. *This product incorporate technology licensed from Silicon Storage Technology, Inc. This preliminary specification is subject to change without notice. SANYO Electric Co., Ltd. Semiconductor Company 1-1, 1 Chome, Sakata, Oizumi-machi, Ora-gun, GUNMA, 370-0596 JAPAN Revision 2.01-July 18,2000-AY/ay-1/17 LE28C1001DT/DTS-90 1M-Bit Page Mode EEPROM Preliminary Specifications A11 A9 A8 A13 A14 NC WE VCC NC A16 A15 A12 A7 A6 A5 A4 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 Vss DQ2 DQ1 DQ0 A0 A1 A2 A3 ( Top View ) Figure 1: Pin Assignments for 32-pin TSOP A16-A7 A6-A0 X-Address Buffers and Latches Y-Address Buffers and Latches 1M Bit EEPROM Cell Array I/O Buffers and Data Latches CE OE WE Control Logic DQ7-DQ0 Figure2: Functional Block Diagram of LE28C1001D SANYO Electric Co., Ltd. 2/17 LE28C1001DT/DTS-90 1M-Bit Page Mode EEPROM Preliminary Specifications Table 1: Pin Description Symbol Pin Name A16-A0 Address Inputs DQ7-DQ0 Data Input/Output Functions To provide memory address. Address are internally latched during write cycle. To output data during read cycle and receive input data during write cycles. Data is internally latched during a write cycle. The outputs are in tri-state when OE or CE is high. CE Chip Enable To activate the device when CE is low. Deselects and puts the device to standby when CE is high. OE Output Enable To activate the data output buffers. OE is active low. WE VCC VSS NC Write Enable To activate the write operation. WE is active low. To provide 5V±10%. Power Supply Ground No Connection Unconnected pins. Table 2: Operation Modes Selection Mode Read Write Standby Write Inhibit Product Identification CE OE WE DQ VIL VIL VIL X X VIL VIL VIH X VIL X VIL VIH VIL X X VIH VIH DOUT DIN High-Z High-Z / DOUT High-Z / DOUT Manufacturer Code (BF) AIN AIN X X X A16-A1 = VIL, A9 = 12V, A0 = VIL Device Code (07) A16-A1 = VIL, A9 = 12V, A0 = VIH Address Table 3: Software Data Protection Command Code Byte Sequence 0 1 2 3 4 5 Write Write Write Write Write Write To Enable Protection To Disable Protection Address * Data Address * Data 5555H AAH 5555H AAH 2AAAH 55H 2AAAH 55H 5555H A0H 5555H 80H 5555H AAH 2AAAH 55H 5555H 20H * Address format A14-A0 (Hex.) SANYO Electric Co., Ltd. 3/17 LE28C1001DT/DTS-90 1M-Bit Page Mode EEPROM Preliminary Specifications Table 4: Software Product ID Entry Command Code and Exit Command Code Byte Sequence 0 Write 1 Write 2 Write 3 Write 4 Write 5 Write Product ID Entry Address 5555H 2AAAH 5555H 5555H 2AAAH 5555H Product ID Exit Data AAH 55H 80H AAH 55H 60H Address* 5555H 2AAAH 5555H Data AAH 55H F0H Notes for Software Product ID Command Code: 1. Command Code Address format: A14-A0 (Hex) 2. With A16-A1=0, SANYO Manufacture Code = BFH is read with A0=0 LE28C1001D Device Code =07H is read with A0=1 3. The device does not remain in Software product ID Mode if powered down. SANYO Electric Co., Ltd. 4/17 LE28C1001DT/DTS-90 1M-Bit Page Mode EEPROM Preliminary Specifications Read The LE28C1001D product read operation is controlled by CE and OE . The host must set both pins to the low level to acquire the output data. CE is used for chip selection. When CE is at the high level, the chip will be in the unselected state and only draw the standby current. OE is used for output control. The output pins go to the high-impedance state when either CE or OE is high. See the timing waveforms (Figure 3) for details. Write The write operation starts when both CE and WE are at the low level. The write operation is executed in two stages. The first stage is a byte load cycle in which the host writes to the LE28C1001D product internal page buffer. The second stage is an internal programming cycle in which the data in the page buffer is written to the nonvolatile memory cell array. In the byte-load cycle, the address is latched on the falling edge of either CE or WE , whichever occurs later. The input data is latched on the rising edge of either CE or WE , whichever occurs first. The internal programming cycle starts if either WE or CE remains high for 200 µs (tBLCO). Once this programming cycle starts, the operation continues until the programming operation is completely done. This operation executes within 5ms (typical). Figures 4 and 5 show the WE and CE control write cycle timing diagrams, and Figure 12 shows the flowchart for this operation. In the page write operation, 128 bytes of data can be written to the LE28C1001D product internal page buffer before the internal programming cycle. All the data in the page buffer is written to the memory cell array during the 5m (typical) internal programming cycle. Therefore the LE28C1001D product page write function can rewrite all memory cells in 5 seconds (typical). The host can perform any other activities desired, such as moving data at other locations within the system and preparing the data required for next page write, during the period prior to the completion of the internal programming cycle. In the given page write operation, all the data bytes loaded into the page buffer must be for the same page address specified by address lines A7 through A16. All data was not explicitly loaded into the page buffer is set to FFH. Figure 4 shows the page write cycle timing diagram. If the host loads the second data byte into the page buffer within the 100µs byte load cycle time (tBLC) after the first byte load cycle the LE28C1001D product stop in the page load cycle thus allowing data to be loaded continuously . The page load cycle terminates if additional data is not loaded into the internal page buffer within 200µs (tBLCO) after the previous byte load cycle, as in the case where WE dose not switch from high to low after the last WE rising edge. The data in the page buffer can be rewritten in the next byte load cycle. The page load period can continue indefinitely as long as host continues to load data into the device within the 100µs byte load cycle. The page that is loaded is determined by the page address of the last byte loaded. Detecting the Write Operation State The LE28C1001D product provides two functions for detecting the completion of the write cycle. These functions are used to optimize the system write cycle time. These functions are based on detecting the states of the DATA Polling bit (DQ7) and the toggle bit (DQ6). DATA Polling (DQ7) The LE28C1001D products output to DQ7 the inverse of the last data loaded during the page and byte load cycles when the internal programming cycle is in progress. The last data loaded will be read from DQ7 when the internal programming cycle completes. Figure 6 shows the DATA Polling cycle timing diagram and Figure 13 shows the flowchart for this operation. Toggle Bit (DQ6) Data values of 0 and 1 are output alternately for DQ6, that is DQ6 is toggled between 0and 1, during the internal programming cycle. When the internal programming cycle completes this toggling is stopped and the device becomes ready to execute the next operation. Figure 7 shows the toggle bit timing diagram and Figure 13 shows the flowchart for this operation. Data Protection Hardware Data Protection Noise and glitch protection: The LE28C1001D dose not execute write operations for WE or CE pulses that are 15 ns or shorter. Power (VCC) on and cutoff detection: The programming operation is disabled when VCC is 2.5 V or lower. Write inhibit mode: Writing is disabled when OE is low and either CE is high or WE is high. Use this function to prevent writes from occurring when the power is being turned on or off. Software Data Protection (SDP) The LE28C1001D implements the optional software data protection function recognized by JEDEC. This function requires that a 3-byte load operation to be performed before a write operation data load. The 3-byte load sequence starts a page load cycle without activating any write operation. Thus this is on optimal protection scheme for unintended write cycles triggered by noise associated with powering the chip on or off. Note that the LE28C1001D is shipped with the software data protection disabled. SANYO Electric Co., Ltd. 5/17 LE28C1001DT/DTS-90 1M-Bit Page Mode EEPROM Preliminary Specifications The software data protection circuit is activated by executing a 3-byte byte load cycle. (See Figure 8). This causes the device to automatically enter data protection mode. After this, write operations require a 3-byte byte load cycle to be executed in advance. A 6-byte write sequence is required to switch the device out of this protection mode. Figure 9 shows the timing diagram. If a write operation is attempted in software protection mode, all device functions are disabled for 200µs. Figure 14 shows the flowchart for this operation. Chip Erase The LE28C1001D provide a chip erase mode that erases all of the memory cell array and sets each bit to 1 state. This mode can be effective when it is necessary to erase all data quickly. 5V Single-Voltage Power Supply Software Chip Erase The software chip erase mode operation is started by executing a specially defined 6-bytebyte load sequence, similar to page mode operation under software protection. After the load cycle is executed, the device enters an internal programming cycle similar to the write cycle. Figure 10 shows the timing diagram and Figure 16 shows the flowchart for this operation. Product Identification The device identification code is used for recognized the device and its manufacturer. This mode can be used by hardware and software. The hardware operating mode is used to recognize algorithms that match the device when an external programming unit is used. Also, users systems can recognize the product number using software product identification mode. Figure 15 shows the flowchart for this operation. The manufacturer and device codes are the same in both modes. SANYO Electric Co., Ltd. 6/17 LE28C1001DT/DTS-90 1M-Bit Page Mode EEPROM Preliminary Specifications Absolute Maximum Ratings at Ta=25°°C Symbol Parameter Ratings Unit Note -0.5V ~ 6.0V V 1 Input pin voltage -0.5V ~ VCC + 0.5V V 1,2 DQ pin voltage -0.5V ~ VCC + 0.5V V 1,2 VA9 A9 pin voltage -0.5V ~ 14V V 1,3 Pd max Allowable power dissipation 600 mW 1,4 Topr Operating temperature 0~+70 °C 1 Tstg Storage temperature -65~+150 °C 1 VCC max Supply voltage VIN VOUT Notes: 1. 2. 3. 4. The device may be destroyed by the application of stresses in excess of the maximum ratings. -1.0V to VCC+1.0V for pulses less than 20ns -1.0V to +14V for pulses less than 20ns Ta=25°C DC Recommended Operating Range at Ta=0 to +70°°C Min. Typ. Max. VCC Symbol Supply voltage Parameter 4.5 5.0 5.5 Unit V VIL Input low-level voltage -0.5 0.8 V VIH Input high-level voltage 2.0 VCC + 0.5 V DC Electrical Characteristics at Ta=0 to +70°°C,VCC=5V± ±10% Symbol Parameter Limits Min. Typ. Units Test Conditions Max. ICCR Power Supply Current (Read) 30 mA CE = OE =VIL, WE =VIH, all DQs open Address inputs= VIH / VIL, f=1/tRC(min.) ICCW Power Supply Current (Write) 50 mA CE = WE =VIL, OE =VIH ISB1 Standby VCC Current (TTL input) 3 mA CE = VIH, all DQs open Other inputs= VIH / VIL ISB2 Standby VCC Current (CMOS input) 20 µA CE = VCC - 0.3V, all DQs open Other inputs= VIH / VIL ILI Input Leakage Current 10 µA VIN= Vss ~ VCC, VCC = VCC max ILO Output Leakage Current 10 µA VIN= Vss ~ VCC, VCC = VCC max VOL Output Low Voltage 0.4 V IOL= 2.1mA, VCC = VCC min VOH Output High Voltage V IOH= -400µA, VCC = VCC min 2.4 Power-up Timings Symbol Parameter Minimum Units tPU_READ Power-up to Read Operation 10 ms tPU_WRITE Power-up to Write Operation 10 ms Capacitance at Ta=25°°C,VCC=5V± ±10%, f=1MHz Maximum Units CDQ Symbol DQ Pin Capacitance Parameter 12 pF VDQ = 0V Test Condition CIN Input Capacitance 6 pF VIN = 0V SANYO Electric Co., Ltd. 7/17 LE28C1001DT/DTS-90 1M-Bit Page Mode EEPROM Preliminary Specifications AC Characteristics at Ta=0 to +70°°C, VCC=5V± ±10% AC Condition of Test Input Rise/Fall Time ............................................................................ 10 ns Output Load.......................................................................................... 1 TTL Gate and CL=100pF Read Cycle Timing Parameters Symbol Parameter Limits Min. Units Max. tRC Read Cycle Time tCE Chip Enable Access Time 90 ns tAA Address Access Time 90 ns tOE Output Enable Access Time 50 ns tCLZ tOHZ CE OE CE OE tOH Output Hold from Address Change tOLZ tCHZ 90 ns Low to Active Output 0 ns Low to Active Output 0 ns Low to High-Z Output 40 ns Low to High-Z Output 40 ns 0 ns Page-Write Cycle Timing Parameters Symbol Parameter Limits Min. Units Typ. Max. 5 10 ms 20 ms tWC Write Cycle (erase and program) tSCE Software Chip Erase Time tAS Address Setup Time 0 ns tAH Address Hold Time 50 ns tCS 0 ns tWP WE and CE Setup Time WE and CE Hold Time OE High Setup Time OE High Hold Time CE Pulse Width WE Pulse Width 70 ns tDS Data Setup time 45 ns tDH Data Hold time tBLC Byte Load Cycle Time tCH tOES tOEH tCP 0 ns 0 ns 0 ns 70 ns 0 0.05 tBLCO Byte Load Cycle Time-out 200 ns 100 µs µs SANYO Electric Co.,Ltd. 8/17 LE28C1001DT/DTS-90 1M-Bit Page Mode EEPROM Preliminary Specifications Figure 3: Read Cycle Timing Diagram tRC A16-0 tCE CE tOE tAA OE tOHZ tOLZ VIH WE tOH tCHZ tCLZ DQ7-0 High-Z DATA VALID DATA VALID Figure 4: WE Controlled Page Write Cycle Timing Diagram tAS tAH tWC A16-0 tCS CE tCH tOES tOEH OE tWP tBLCO tBLC WE tDS DQ7-0 tDH DATA VALID Byte 0 Byte 1 Byte 127 Internal Write Starts SANYO Electric Co.,Ltd. 9/17 LE28C1001DT/DTS-90 1M-Bit Page Mode EEPROM Preliminary Specifications Figure 5: CE Controlled Write Cycle Timing Diagram tAS tAH tWC A16-0 tCP tBLCO tBLC CE tOES tOEH OE tCS tCH WE tDS DQ7-0 tDH DATA VALID Byte 0 Byte 1 Byte 127 Internal Write Starts Figure 6: DATA Polling Timing Diagram A16-0 AN AN AN AN tWC WE tCE tBLCO tOES CE tOEH OE tOE DQ7 DIN=X DOUT=X DOUT=X DOUT=X SANYO Electric Co.,Ltd. 10/17 LE28C1001DT/DTS-90 1M-Bit Page Mode EEPROM Preliminary Specifications Figure 7: Toggle Bit Timing Diagram A16-0 tWC+tBLCO WE tCE CE tOEH tOES tOE OE Two Read Cycles with same Outputs DQ6 Figure 8: Enable Software Data Protection Page Write Timing Diagram Three-byte sequence for Enable Software data protection A16-0 DQ7-0 5555 2AAA AA 55 tWC 5555 A0 CE OE tWP tBLCO tBLC 1) WE SW0 SW1 SW2 Byte 0 Byte N-1 Byte N (last byte) Page load cycle starts Internal Write Starts Note 1): The time between enabling Software Data Protect and the page load must be less than tBLCO SANYO Electric Co.,Ltd. 11/17 LE28C1001DT/DTS-90 1M-Bit Page Mode EEPROM Preliminary Specifications Figure 9: Disable Software Data Protection Timing Diagram tWC Six-byte sequence for disabling Software Data Protection A16-0 DQ7-0 5555 2AAA AA 55 5555 5555 80 2AAA AA 5555 55 20 CE OE tWP tBLC tBLCO WE SW0 SW1 SW2 SW3 SW4 SW5 Internal program starts to disable Software Data Protection Figure 10: Software Chip Erase Timing Diagram tSCE Six-byte sequence for Software Chip Erase A16-0 DQ7-0 5555 2AAA AA 55 5555 5555 80 2AAA AA 5555 55 10 CE OE tWP tBLC tBLCO WE SW0 SW1 SW2 SW3 SW4 SW5 Internal Erase Starts SANYO Electric Co.,Ltd. 12/17 LE28C1001DT/DTS-90 1M-Bit Page Mode EEPROM Preliminary Specifications Figure 11: AC Input/Output Reference Waveform 2.4V 2.0V INPUT 2.0V REFERENCE POINT 0.8V OUTPUT 0.8V 0.4V AC test inputs are driven at VOH(2.4V) for a logic 1 and at VOL(0.4V) for a logic 0. The I/O measurement reference points are VIH(2.0 V) and VIL(0.8V). The input rise and fall times (10%↔90%) must be 10ns or shorter. SANYO Electric Co.,Ltd. 13/17 LE28C1001DT/DTS-90 1M-Bit Page Mode EEPROM Preliminary Specifications Figure 12: Write Algorithm Start Software Date Protect Enable Command Set Page Address Set Byte Address = 0 Load Byte Data Increment Byte address by 1 No Byte Address = 128 ? Yes Wait T BLCO Wait for end of Write (Twc, Toggle bit or Data# Polling bit operation) Write Completed SANYO Electric Co.,Ltd. 14/17 LE28C1001DT/DTS-90 1M-Bit Page Mode EEPROM Preliminary Specifications Figure 13: Write Wait Options Internal Timer Toggle Bit Data# Polling Page Write initiated Page write initiated Page write initiated Wait Twc Read a byte from page Read DQ7 (Data for last byte loaded) Write complete Read same byte No Is DQ7 = true data ? Yes No Does DQ6 match ? Write complete Yes Write complete SANYO Electric Co.,Ltd. 15/17 LE28C1001DT/DTS-90 1M-Bit Page Mode EEPROM Preliminary Specifications Figure 14: Software Data Protect Disable Command Sequence Software Data Protect Enable Command Sequence Software Data Protect Disable Command Sequence Write data: AA Address: 5555 Write data: AA Address: 5555 Write data: 55 Address: 2AAA Write data: 55 Address: 2AAA Write data: A0 Address: 5555 Write data: 80 Address: 5555 Load 0 to 128 Bytes of page data Optional Page Load Operation Write data: AA Address : 5555 Wait Twc Write data: 55 Address: 2AAA SDP Enabled Write data: 20 Address: 5555 Wait Twc SDP Disabled SANYO Electric Co.,Ltd. 16/17 LE28C1001DT/DTS-90 1M-Bit Page Mode EEPROM Preliminary Specifications Figure 15: Software Product Command Codes Software Product ID Entry Command Sequence Figure16: Software Chip-Erase Flowchart Software Product ID Exit Command Sequence Software Chip Erase Command Sequence Write data: AA Address: 5555 Write data: AA Address: 5555 Write data: AA Address: 5555 Write data: 55 Address: 2AAA Write data: 55 Address: 2AAA Write data: 55 Address: 2AAA Write data: 80 Address: 5555 Write data: F0 Address: 5555 Write data: 80 Address: 5555 Write data: AA Address: 5555 Pause 10us Write data: AA Address: 5555 Write data: 55 Address: 2AAA Return to normal operation Write data: 55 Address: 2AAA Write data: 60 Address: 5555 Write data: 10 Address: 5555 Pause 10us Wait tSCE Chip Erase to FFH Read Software ID SANYO Electric Co.,Ltd. 17/17