TMS320DM641/TMS320DM640 Video/Imaging Fixed-Point Digital Signal Processors Data Manual Literature Number: SPRS222 June 2003 PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third–party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. 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Following are URLs where you can obtain information on other Texas Instruments products & application solutions: Products Amplifiers Applications amplifier.ti.com Audio www.ti.com/audio Data Converters dataconverter.ti.com Automotive www.ti.com/automotive DSP dsp.ti.com Broadband www.ti.com/broadband Interface interface.ti.com Digital Control www.ti.com/digitalcontrol Logic logic.ti.com Military www.ti.com/military Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork Microcontrollers microcontroller.ti.com Security www.ti.com/security Telephony www.ti.com/telephony Video & Imaging www.ti.com/video Wireless www.ti.com/wireless Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2003, Texas Instruments Incorporated Contents Contents Section Page 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 GDK BGA Package (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 GNZ BGA Package (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 Device Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 Device Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.7 CPU (DSP Core) Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8 Memory Map Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.9 Peripheral Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.10 EDMA Channel Synchronization Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.11 Interrupt Sources and Interrupt Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.12 Signal Groups Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Device 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 2.14 2.15 2.16 2.17 2.18 2.19 2.20 2.21 2.22 2.23 June 2003 13 14 14 15 18 20 21 22 25 27 45 47 49 Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Peripheral Selection at Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Device Configuration at Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Peripheral Selection After Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 2.3.1 Peripheral Configuration Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 2.3.2 Device Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 2.3.3 JTAG ID Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Multiplexed Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Debugging Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Configuration Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Device and Development-Support Tool Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Documentation Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Clock PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Multichannel Audio Serial Port (McASP0) Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 2.12.1 McASP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Video Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 VIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 EMAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 MDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Power-Supply Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 2.18.1 Power-Supply Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Power-Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Power-Down Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 IEEE 1149.1 JTAG Compatibility Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 EMIF Device Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Bootmode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 SPRS222 3 Contents Section 3 Page Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Absolute Maximum Ratings Over Operating Case Temperature Range . . . . . . . . . . . . . . . . . . . . . . 3.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 Parameter Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.1 Signal Transition Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.2 Signal Transition Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 Timing Parameters and Board Routing Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 107 107 108 109 109 109 110 4 Input and Output Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 5 Asynchronous Memory Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 6 Programmable Synchronous Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 7 Synchronous DRAM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 8 AHOLD/AHOLDA Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 9 ABUSREQ Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 10 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 11 External Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 12 Multichannel Audio Serial Port (McASP) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 13 Inter-Integrated Circuits (I2C) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 14 Host-Port Interface (HPI) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 15 Multichannel Buffered Serial Port (McBSP) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 16 Video 16.1 16.2 16.3 4 Port Timing (VP0 [DM641/DM640] and VP1 [DM641 Only]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STCLK Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Video Data and Control Timing (Video Capture Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCLKIN Timing (Video Display Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPRS222 148 148 149 150 June 2003 Contents Section 16.4 16.5 Page Video Control Input/Output and Video Display Data Output Timing With Respect to VPxCLKINx and VPxCLKOUTx (Video Display Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Video Dual-Display Sync Mode Timing (With Respect to VPxCLKINx) . . . . . . . . . . . . . . . . . . . . . . . . 152 17 Ethernet Media Access Controller (EMAC) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 18 Management Data Input/Output (MDIO) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 19 Timer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 20 General-Purpose Input/Output (GPIO) Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 21 JTAG Test-Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 22 Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 22.1 Ball Grid Array Mechanical Data Drawing (GDK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 22.2 Ball Grid Array Mechanical Data Drawing (GNZ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 June 2003 SPRS222 5 Figures List of Figures Figure Page 1–1 GDK BGA Package (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1–2 GNZ BGA Package (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1–3 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1–4 TMS320C64x CPU (DSP Core) Data Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 1–5 CPU and Peripheral Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 1–6 Peripheral Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 2–1 Peripheral Configuration Register (PERCFG) [Address Location: 0x01B3F000 – 0x01B3F003] . . . . . . 57 2–2 Peripheral Enable/Disable Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 2–3 PCFGLOCK Register Diagram [Address Location: 0x01B3 F018] – Read/Write Accesses . . . . . . . . . . . 59 2–4 Device Status Register (DEVSTAT) Description – 0x01B3 F004 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 2–5 JTAG ID Register Description – TMS320DM641/DM640 Register Value – 0x0007 902F . . . . . . . . . . . . . 61 2–6 Configuration Example A for DM641 (2 8-Bit Video Ports + 1 McASP0 + VIC + I2C0 + EMIF) . . . . . . . . 63 2–7 Configuration Example B for DM641 (1 McASP0 + 2 McBSPs + VIC + I2C0 + EMIF) . . . . . . . . . . . . . . . 64 2–8 Configuration Example A for DM640 (1 8-Bit Video Port + 1 McASP0 + VIC + I2C0 + EMIF) . . . . . . . . . 65 2–9 Configuration Example B for DM640 (1 McASP0 + 2 McBSPs + VIC + I2C0 + EMIF) . . . . . . . . . . . . . . . 66 2–10 TMS320DM64x DSP Device Nomenclature (Including the DM641 and DM640 Devices) . . . . . . . . . . . . 91 2–11 External PLL Circuitry for Either PLL Multiply Modes or x1 (Bypass) Mode . . . . . . . . . . . . . . . . . . . . . . . . 94 2–12 McASP0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 2–13 I2C0 Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 2–14 Schottky Diode Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 3–1 Test Load Circuit for AC Timing Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 3–2 Input and Output Voltage Reference Levels for AC Timing Measurements . . . . . . . . . . . . . . . . . . . . . . . 109 3–3 Rise and Fall Transition Time Voltage Reference Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 3–4 Board-Level Input/Output Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 4–1 CLKIN Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 4–2 CLKOUT4 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 4–3 CLKOUT6 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 4–4 ECLKIN Timing for EMIFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 4–5 AECLKOUT1 Timing for the EMIFA Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 4–6 AECLKOUT2 Timing for the EMIFA Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 5–1 Asynchronous Memory Read Timing for EMIFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 5–2 Asynchronous Memory Write Timing for EMIFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 6 SPRS222 June 2003 Figures Figure Page 6–1 Programmable Synchronous Interface Read Timing for EMIFA (With Read Latency = 2) . . . . . . . . . . . 119 6–2 Programmable Synchronous Interface Write Timing for EMIFA (With Write Latency = 0) . . . . . . . . . . . 120 6–3 Programmable Synchronous Interface Write Timing for EMIFA (With Write Latency = 1) . . . . . . . . . . . 121 7–1 7–2 7–3 7–4 7–5 7–6 7–7 7–8 SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM 8–1 AHOLD/AHOLDA Timing for EMIFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 9–1 ABUSREQ Timing for EMIFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 10–1 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 11–1 External/NMI Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 12–1 12–2 McASP Input Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 McASP Output Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 13–1 13–2 I2C Receive Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 I2C Transmit Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 14–1 14–2 14–3 14–4 HPI16 Read Timing (HAS Not Used, Tied High) [for DM641 Only] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HPI16 Read Timing (HAS Used) [for DM641 Only] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HPI16 Write Timing (HAS Not Used, Tied High) [for DM641 Only] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HPI16 Write Timing (HAS Used) [for DM641 Only] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 139 140 140 15–1 15–2 15–3 15–4 15–5 15–6 McBSP Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FSR Timing When GSYNC = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 143 144 145 146 147 June 2003 Read Command (CAS Latency 3) for EMIFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write Command for EMIFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ACTV Command for EMIFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DCAB Command for EMIFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DEAC Command for EMIFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REFR Command for EMIFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MRS Command for EMIFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Self-Refresh Timing for EMIFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPRS222 123 124 125 125 126 126 127 127 7 Figures Figure 16–1 16–2 16–3 16–4 16–5 Page 16–6 Video Port Capture VPxCLKINx TIming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STCLK Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Video Port Capture Data and Control Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Video Port Display VPxCLKINx Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Video Port Display Data Output Timing and Control Input/Output Timing With Respect to VPxCLKINx and VPxCLKOUTx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Video Port Dual-Display Sync Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 152 17–1 17–2 17–3 17–4 MRCLK Timing (EMAC – Receive) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MTCLK Timing (EMAC – Transmit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMAC Receive Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMAC Transmit Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 153 154 154 18–1 18–2 MDIO Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 MDIO Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 19–1 Timer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 20–1 GPIO Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 21–1 JTAG Test-Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 8 SPRS222 148 148 149 150 June 2003 Tables List of Tables Table Page 1–1 1–2 1–3 1–4 1–5 1–6 1–7 1–8 1–9 1–10 1–11 1–12 1–13 1–14 1–15 1–16 1–17 1–18 1–19 1–20 1–21 1–22 1–23 1–24 1–25 1–26 1–27 1–28 1–29 1–30 Characteristics of the DM641 Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Characteristics of the DM640 Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peripherals Available on the DM641 and DM640 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TMS320DM641/DM640 Memory Map Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMIFA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . L2 Cache Registers (C64x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quick DMA (QDMA) and Pseudo Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EDMA Registers (C64x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EDMA Parameter RAM (C64x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Selector Registers (C64x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peripheral Power-Down Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ethernet MAC (EMAC) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMAC Wrapper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EWRAP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . McBSP 0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . McBSP 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer 0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer 2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HPI Registers [DM641 Only] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GP0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCXO Interpolated Control (VIC) Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MDIO Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Video Port 0 and 1 (VP0 and VP1) Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . McASP0 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . McASP0 Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TMS320DM641/DM640 EDMA Channel Synchronization Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DM641/DM640 DSP Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 19 20 25 27 27 29 30 30 31 31 31 36 36 36 37 37 38 38 38 38 39 39 39 40 42 44 44 45 47 2–1 2–2 2–3 2–4 2–5 2–6 2–7 2–8 2–9 2–10 MAC_EN Peripheral Selection (EMAC and MDIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DM641/DM640 Device Configuration Pins (TOUT1/LENDIAN, AEA[22:19], and HD5) . . . . . . . . . . . . . Peripheral Configuration (PERCFG) Register Selection Bit Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . PCFGLOCK Register Selection Bit Descriptions – Read Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCFGLOCK Register Selection Bit Descriptions – Write Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device Status (DEVSTAT) Register Selection Bit Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JTAG ID Register Selection Bit Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DM641/DM640 Device Multiplexed Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TMS320DM641/DM640 PLL Multiply Factor Options, Clock Frequency Ranges, and Typical Lock Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 56 57 59 59 60 61 62 68 3–1 June 2003 95 Board-Level Timing Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 SPRS222 9 Tables Table 4–1 4–2 4–3 4–4 4–5 4–6 4–7 4–8 Page Timing Requirements for CLKIN for –400 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Requirements for CLKIN for –500 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Requirements for CLKIN for –600 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switching Characteristics Over Recommended Operating Conditions for CLKOUT4 . . . . . . . . . . . . . . Switching Characteristics Over Recommended Operating Conditions for CLKOUT6 . . . . . . . . . . . . . . Timing Requirements for AECLKIN for EMIFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switching Characteristics Over Recommended Operating Conditions for AECLKOUT1 for the EMIFA Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switching Characteristics Over Recommended Operating Conditions for AECLKOUT2 for the EMIFA Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 111 111 112 112 113 113 114 5–1 5–2 Timing Requirements for Asynchronous Memory Cycles for EMIFA Module . . . . . . . . . . . . . . . . . . . . . . 115 Switching Characteristics Over Recommended Operating Conditions for Asynchronous Memory Cycles for EMIFA Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 6–1 6–2 Timing Requirements for Programmable Synchronous Interface Cycles for EMIFA Module . . . . . . . . 118 Switching Characteristics Over Recommended Operating Conditions for Programmable Synchronous Interface Cycles for EMIFA Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 7–1 7–2 Timing Requirements for Synchronous DRAM Cycles for EMIFA Module . . . . . . . . . . . . . . . . . . . . . . . . 122 Switching Characteristics Over Recommended Operating Conditions for Synchronous DRAM Cycles for EMIFA Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 8–1 8–2 Timing Requirements for the AHOLD/AHOLDA Cycles for EMIFA Module . . . . . . . . . . . . . . . . . . . . . . . 128 Switching Characteristics Over Recommended Operating Conditions for the AHOLD/AHOLDA Cycles for EMIFA Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 9–1 Switching Characteristics Over Recommended Operating Conditions for the ABUSREQ Cycles for EMIFA Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 10–1 10–2 Timing Requirements for Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Switching Characteristics Over Recommended Operating Conditions During Reset . . . . . . . . . . . . . . . 130 11–1 Timing Requirements for External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 12–1 12–2 Timing Requirements for McASP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Switching Characteristics Over Recommended Operating Conditions for McASP . . . . . . . . . . . . . . . . 133 13–1 13–2 Timing Requirements for I2C Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Switching Characteristics for I2C Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 10 SPRS222 June 2003 Tables Table Page 14–1 14–2 Timing Requirements for Host-Port Interface Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Switching Characteristics Over Recommended Operating Conditions During Host-Port Interface Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 15–1 15–2 15–3 15–4 15–5 Timing Requirements for McBSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switching Characteristics Over Recommended Operating Conditions for McBSP . . . . . . . . . . . . . . . . Timing Requirements for FSR When GSYNC = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 . . . . . . . . . . . . Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 . . . . . . . . . . . . Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 . . . . . . . . . . . . Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 . . . . . . . . . . . . Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–6 15–7 15–8 15–9 15–10 15–11 16–1 16–2 16–3 16–4 16–5 16–6 16–7 17–1 17–2 17–3 17–4 Timing Requirements for Video Capture Mode for VPxCLKINx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Requirments for STCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Requirements in Video Capture Mode for Video Data and Control Inputs . . . . . . . . . . . . . . . . . Timing Requirements for Video Display Mode for VPxCLKINx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Requirements in Video Display Mode for Video Control Input Shown With Respect to VPxCLKINx and VPxCLKOUTx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switching Characteristics Over Recommended Operating Conditions in Video Display Mode for Video Data and Control Output Shown With Respect to VPxCLKINx and VPxCLKOUTx . . . . . . . . Timing Requirements for Dual-Display Sync Mode for VPxCLKINx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Requirements for MRCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Requirements for MTCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Requirements for EMAC MII Receive 10/100 Mbit/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switching Characteristics Over Recommended Operating Conditions for EMAC MII Transmit 10/100 Mbit/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 142 143 144 144 145 145 146 146 147 147 148 148 149 150 150 151 152 153 153 154 154 18–1 18–2 Timing Requirements for MDIO Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Switching Characteristics Over Recommended Operating Conditions for MDIO Output . . . . . . . . . . . . 155 19–1 19–2 Timing Requirements for Timer Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Switching Characteristics Over Recommended Operating Conditions for Timer Outputs . . . . . . . . . . . 156 20–1 20–2 Timing Requirements for GPIO Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs . . . . . . . . . . . 157 June 2003 SPRS222 11 Tables Table Page 21–1 21–2 Timing Requirements for JTAG Test Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port . . . . . . . . . . 158 22–1 22–2 Thermal Resistance Characteristics (S-PBGA Package) [GDK] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Thermal Resistance Characteristics (S-PBGA Package) [GNZ] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 12 SPRS222 June 2003 Features Features D High-Performance Digital Media Processor D D D D D (TMS320DM641/TMS320DM640) – 2.5-, 2-, 1.67-ns Instruction Cycle Time – 400-, 500-, 600-MHz Clock Rate – Eight 32-Bit Instructions/Cycle – 3200, 4000, 4800 MIPS – Fully Software-Compatible With C64x VelociTI.2 Extensions to VelociTI Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x DSP Core – Eight Highly Independent Functional Units With VelociTI.2 Extensions: – Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle – Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle – Load-Store Architecture With Non-Aligned Support – 64 32-Bit General-Purpose Registers – Instruction Packing Reduces Code Size – All Instructions Conditional Instruction Set Features – Byte-Addressable (8-/16-/32-/64-Bit Data) – 8-Bit Overflow Protection – Bit-Field Extract, Set, Clear – Normalization, Saturation, Bit-Counting – VelociTI.2 Increased Orthogonality L1/L2 Memory Architecture – 128K-Bit (16K-Byte) L1P Program Cache (Direct Mapped) – 128K-Bit (16K-Byte) L1D Data Cache (2-Way Set-Associative) – 1M-Bit (128K-Byte) L2 Unified Mapped RAM/Cache (Flexible RAM/Cache Allocation) Endianess: Little Endian, Big Endian 32-Bit External Memory Interface (EMIF) – Glueless Interface to Asynchronous Memories (SRAM and EPROM) and Synchronous Memories (SDRAM, SBSRAM, ZBT SRAM, and FIFO) D D D D D D D D D D D D D D D D D D – 1024M-Byte Total Addressable External Memory Space Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels) 10/100 Mb/s Ethernet MAC (EMAC) – IEEE 802.3 Compliant – Media Independent Interface (MII) – 8 Independent Transmit (TX) and 8 Independent Receive (RX) Channels Management Data Input/Output (MDIO) Two Configurable Video Ports (DM641) One Configurable Video Port (DM640) – Providing a Glueless I/F to Common Video Decoder and Encoder Devices – Supports Multiple Resolutions and Video Standards – Supports RAW Video I/O – Transport Stream Interface Mode VCXO Interpolated Control Port (VIC) – Supports Audio/Video Synchronization Host-Port Interface (HPI) [16-Bit] (DM641) Multichannel Audio Serial Port (McASP) – Four Serial Data Pins – Wide Variety of I2S and Similar Bit Stream Format – Integrated Digital Audio I/F Transmitter Supports S/PDIF, IEC60958-1, AES-3, CP-430 Formats Inter-Integrated Circuit (I2C) Bus Two Multichannel Buffered Serial Ports Three 32-Bit General-Purpose Timers Eight General-Purpose I/O (GPIO) Pins Flexible PLL Clock Generator IEEE-1149.1 (JTAG†) Boundary-Scan-Compatible 548-Pin Ball Grid Array (BGA) Package (GDK Suffix), 0.8-mm Ball Pitch 548-Pin Ball Grid Array (BGA) Package (GNZ Suffix), 1.0-mm Ball Pitch 0.13-µm/6-Level Cu Metal Process (CMOS) 3.3-V I/Os, 1.2-V Internal (-400, -500) 3.3-V I/Os, 1.4-V Internal (-600) PRODUCT PREVIEW 1 C64x, VelociTI.2, VelociTI, and TMS320C64x are trademarks of Texas Instruments. All trademarks are the property of their respective owners. † IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture. June 2003 SPRS222 13 Features 1.1 GDK BGA Package (Bottom View) GDK 548-PIN BALL GRID ARRAY (BGA) PACKAGE ( BOTTOM VIEW ) AF AE AD AC AB AA Y W V U T R P N M L K J H G F E PRODUCT PREVIEW D C B A 1 3 2 5 4 7 6 9 8 11 13 15 17 19 21 23 25 10 12 14 16 18 20 22 24 26 Figure 1–1. GDK BGA Package (Bottom View) 1.2 GNZ BGA Package (Bottom View) GNZ 548-PIN BALL GRID ARRAY (BGA) PACKAGE ( BOTTOM VIEW ) AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A 1 3 2 5 4 7 6 9 8 11 13 15 17 19 21 23 25 10 12 14 16 18 20 22 24 26 Figure 1–2. GNZ BGA Package (Bottom View) Bottom View 14 SPRS222 June 2003 Description 1.3 Description The TMS320C64x DSPs (including the TMS320DM641 and TMS320DM640 devices) are the highest-performance fixed-point DSP generation in the TMS320C6000 DSP platform. The TMS320DM641 and TMS320DM640 (DM641 and DM640) devices are based on the second-generation high-performance, advanced VelociTI very-long-instruction-word (VLIW) architecture (VelociTI.2) developed by Texas Instruments (TI), making these DSPs an excellent choice for digital media applications. The C64x is a code-compatible member of the C6000 DSP platform. With performance of up to 4800 million instructions per second (MIPS) at a clock rate of 600 MHz, the DM641 device offers cost-effective solutions to high-performance DSP programming challenges. The DM641/DM640 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units—two multipliers for a 32-bit result and six arithmetic logic units (ALUs)— with VelociTI.2 extensions. The VelociTI.2 extensions in the eight functional units include new instructions to accelerate the performance in video and imaging applications and extend the parallelism of the VelociTI architecture. The DM641 can produce four 32-bit multiply-accumulates (MACs) per cycle for a total of 2400 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4800 MMACS. The DM641/DM640 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000 DSP platform devices. The DM641/DM640 uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 128-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 128-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 1-Mbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. The peripheral set includes: two configurable video ports (DM641); one configurable video port (DM640); a 10/100 Mb/s Ethernet MAC (EMAC); a management data input/output (MDIO) module; a VCXO interpolated control port (VIC); one 4-bit multichannel buffered audio serial port (McASP0); an inter-integrated circuit (I2C) Bus module; two multichannel buffered serial ports (McBSPs); three 32-bit general-purpose timers; a 16-bit host-port interface (HPI16); a 16-pin general-purpose input/output port (GP0) with programmable interrupt/event generation modes; and a 32-bit glueless external memory interface (EMIFA), which is capable of interfacing to synchronous and asynchronous memories and peripherals. The DM641 device has two configurable video port peripherals (VP0 and VP1). The DM640 device has one configurable video port peripheral (VP0). These video port peripherals provide a glueless interface to common video decoder and encoder devices. All Video Port peripherals have the capability to operate as a video-capture port, a video-display port, or a transport stream interface (TSI) capture port. The DM641/DM640 video port peripherals support multiple resolutions and video standards (e. g., CCIR601, ITU–BT.656, BT.1120, SMPTE 125M, 260M, 274M, and 296M). TMS320C6000 and C6000 are trademarks of Texas Instruments. June 2003 SPRS222 15 PRODUCT PREVIEW With performance of up to 3200 million instructions per second (MIPS) at a clock rate of 400 MHz, the DM640 device offers cost-effective solutions to high-performance DSP programming challenges. Description These video port peripherals are configurable and can support either video capture and/or video display modes. For capture operation, the video port can operate as a single channel of 8-bit BT.656, 8-bit raw video, or 8-bit TSI. For display operation, the video port can operate as a single channel of 8-bit BT.656 display, 8-bit raw video display. For more details on the Video Port peripherals, see the TMS320DM642 Technical Overview (literature number SPRU615) or the TMS320C64x DSP Video Port/VCXO Interpolated Control (VIC) Port Reference Guide (literature number SPRU629). PRODUCT PREVIEW The McASP0 port supports one transmit and one receive clock zone, with four serial data pins which can be individually allocated to any of the two zones. The serial port supports time-division multiplexing on each pin from 2 to 32 time slots. The DM641/DM640 has sufficient bandwidth to support all 4 serial data pins transmitting a 192-kHz stereo signal. Serial data in each zone may be transmitted and received on multiple serial data pins simultaneously and formatted in a multitude of variations on the Philips Inter-IC Sound (I2S) format. In addition, the McASP0 transmitter may be programmed to output multiple S/PDIF, IEC60958, AES-3, CP-430 encoded data channels simultaneously, with a single RAM containing the full implementation of user data and channel status fields. McASP0 also provides extensive error-checking and recovery features, such as the bad clock detection circuit for each high-frequency master clock which verifies that the master clock is within a programmed frequency range. The VCXO interpolated control (VIC) port provides digital-to-analog conversion with resolution from 9-bits to up to 16-bits. The output of the VIC is a single bit interpolated D/A output. For more details on the VIC port, see the TMS320C64x DSP Video Port/VCXO Interpolated Control (VIC) Port Reference Guide (literature number SPRU629). The ethernet media access controller (EMAC) provides an efficient interface between the DM641/DM640 DSP core processor and the network. The DM641/DM640 EMAC supports both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex, with hardware flow control and quality of service (QOS) support. The DM641/DM640 EMAC makes use of a custom interface to the DSP core that allows efficient data transmission and reception. For more details on the EMAC, see the TMS320C6000 DSP Ethernet Media Access Controller (EMAC) / Management Data Input/Output (MDIO) Module Reference Guide (literature number SPRU628). The management data input/output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system. Once a PHY candidate has been selected by the DSP, the MDIO module transparently monitors its link state by reading the PHY status register. Link change events are stored in the MDIO module and can optionally interrupt the DSP, allowing the DSP to poll the link status of the device without continuously performing costly MDIO accesses. For more details on the MDIO, see the TMS320C6000 DSP Ethernet Media Access Controller (EMAC) / Management Data Input/Output (MDIO) Module Reference Guide (literature number SPRU628). 16 SPRS222 June 2003 Description The I2C0 port on the TMS320DM641/DM640 allows the DSP to easily control peripheral devices and communicate with a host processor. In addition, the standard multichannel buffered serial port (McBSP) may be used to communicate with serial peripheral interface (SPI) mode peripheral devices. PRODUCT PREVIEW The DM641/DM640 has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows debugger interface for visibility into source code execution. Windows is a registered trademark of the Microsoft Corporation. June 2003 SPRS222 17 Device Characteristics 1.4 Device Characteristics Table 1–1 provides an overview of the DM641 DSP. The table shows significant features of the DM641 device, including the capacity of on-chip RAM, the peripherals, the CPU frequency, and the package type with pin count. Table 1–1. Characteristics of the DM641 Processor HARDWARE FEATURES 1 EDMA (64 independent channels) 1 McASP0 (uses Peripheral Clock [AUXCLK]) 1 I2C0 (uses Peripheral Clock) PRODUCT PREVIEW DM641 EMIFA (32-bit bus width) (clock source = AECLKIN) 1 Peripherals HPI (16-bit) Not all peripherals pins are available at the same time (For more detail, see the Device Configuration section). McBSPs (internal clock source = CPU/4 clock frequency) 2 Configurable Video Ports (VP0 and VP1) 2 10/100 Ethernet MAC (EMAC) 1 Management Data Input/Output (MDIO) 1 VCXO Interpolated Control Port (VIC) 1 32-Bit Timers (internal clock source = CPU/8 clock frequency) 3 General-Purpose Input/Output Port (GP0) Size (Bytes) On-Chip Memory 1 (HPI16) 8 160K 16K-Byte (16KB) L1 Program (L1P) Cache Organization 16KB L1 Data (L1D) Cache 128KB Unified Mapped RAM/Cache (L2) CPU ID + CPU Rev ID Control Status Register (CSR.[31:16]) JTAG BSDL_ID JTAGID register (address location: 0x01B3F008) Frequency MHz Cycle Time ns Voltage Core (V) I/O (V) PLL Options BGA Package 0x0C01 0x0007902F 500, 600 2 ns (DM641-500) [500-MHz CPU, 100 MHz EMIF†] 1.67 ns (DM641-600) [600-MHz CPU, 133 MHz EMIF†] 1.2 V (-500) 1.4 V (-600) 3.3 V CLKIN frequency multiplier Bypass (x1), x6, x12 23 x 23 mm 548-Pin BGA (GDK) 27 x 27 mm 548-Pin BGA (GNZ) Process Technology µm Product Status‡ Product Preview (PP), Advance Information (AI), or Production Data (PD) Device Part Numbers (For more details on the C6000 DSP part numbering, see Figure 2–10) 0.13 µm PP TMX320DM641GDK, TMX320DM641GNZ † On this DM64x device, the rated EMIF speed affects only the SDRAM interface on the EMIF. For more detailed information, see the EMIF device speed portion of this data sheet. ‡ PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 18 SPRS222 June 2003 Device Characteristics Table 1–2 provides an overview of the DM640 DSP. The table shows significant features of the DM640 device, including the capacity of on-chip RAM, the peripherals, the CPU frequency, and the package type with pin count. Table 1–2. Characteristics of the DM640 Processor Peripherals Not all peripherals pins are available at the same time (For more detail, see the Device Configuration section). 1 EDMA (64 independent channels) 1 McASP0 (uses Peripheral Clock [AUXCLK]) 1 I2C0 (uses Peripheral Clock) 1 McBSPs (internal clock source = CPU/4 clock frequency) 2 Configurable Video Port (VP0) 1 10/100 Ethernet MAC (EMAC) 1 Management Data Input/Output (MDIO) 1 VCXO Interpolated Control Port (VIC) 1 32-Bit Timers (internal clock source = CPU/8 clock frequency) 3 General-Purpose Input/Output Port (GP0) Size (Bytes) On-Chip Memory DM640 EMIFA (32-bit bus width) (clock source = AECLKIN) PRODUCT PREVIEW HARDWARE FEATURES 8 160K 16K-Byte (16KB) L1 Program (L1P) Cache Organization 16KB L1 Data (L1D) Cache 128KB Unified Mapped RAM/Cache (L2) CPU ID + CPU Rev ID Control Status Register (CSR.[31:16]) JTAG BSDL_ID JTAGID register (address location: 0x01B3F008) Frequency MHz Cycle Time ns Core (V) Voltage PLL Options BGA Package I/O (V) 0x0C01 0x0007902F 400 2.5 ns (DM640-400) [400-MHz CPU, 100 MHz EMIF†] 1.2 V (-400) 3.3 V CLKIN frequency multiplier Bypass (x1), x6, x12 23 x 23 mm 548-Pin BGA (GDK) 27 x 27 mm 548-Pin BGA (GNZ) Process Technology µm Product Status‡ Product Preview (PP), Advance Information (AI), or Production Data (PD) Device Part Numbers (For more details on the C6000 DSP part numbering, see Figure 2–10) 0.13 µm PP TMX320DM640GDK, TMX320DM640GNZ † On this DM64x device, the rated EMIF speed affects only the SDRAM interface on the EMIF. For more detailed information, see the EMIF device speed portion of this data sheet. ‡ PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. June 2003 SPRS222 19 Device Compatibility 1.5 Device Compatibility The DM641/DM640 device is a code-compatible member of the C6000 DSP platform. The C64x DSP generation of devices has a diverse and powerful set of peripherals. The common peripheral set and pin-compatibility that the DM641 and DM640 devices offer lead to easier system designs and faster time to market. The DM640 device is a sub-set of the DM641 device and does not support an HPI peripheral or a second Video Port (VP1) peripheral. Table 1–3 identifies the peripherals that are available on the DM641 and DM640 devices. Table 1–3. Peripherals Available on the DM641 and DM640 Devices†‡ PERIPHERALS/COPROCESSORS PRODUCT PREVIEW DM641 DM640 EMIFA (32-bit bus width) √ √ EDMA (64 independent channels) √ √ 10/100 EMAC √ √ MDIO √ √ HPI (16-bit) √ — McBSPs (McBSP0, McBSP1) √ √ McASP (4-bit) √ √ 8-bit Video Port (VP0) √ √ 8-bit Video Port (VP1) √ — VIC √ √ I2C √ √ Timers (32-bit) [TIMER0, TIMER1, TIMER2] √ √ GPIOs (GP[7:0]) √ √ † — denotes peripheral/coprocessor is not available on this device. ‡ Not all peripherals pins are available at the same time. (For more details, see the Device Configuration section.) 20 SPRS222 June 2003 Functional Block Diagram 1.6 Functional Block Diagram Figure 1–3 shows the functional block diagram of the DM641/DM640 devices. SDRAM 32 SBSRAM TMS320DM641/TMS320DM640 EMIF A Timer 2 ZBT SRAM L1P Cache Direct-Mapped 16K Bytes Total Timer 1 FIFO Timer 0 SRAM C64x DSP Core Instruction Fetch 8-Bit VP0 I/O Devices Instruction Dispatch Advanced Instruction Packet OR McBSP0‡ Control Logic Instruction Decode Data Path A AND A Register File A31–A16 A15–A0 McASP0 Control 8-Bit VP1† Control Registers Enhanced DMA Controller (EDMA) L2 Cache Memory 128KBytes .L1 .S1 .M1 .D1 Data Path B Test B Register File B31–B16 B15–B0 .D2 .M2 .S2 PRODUCT PREVIEW ROM/FLASH Advanced In-Circuit Emulation Interrupt Control .L2 OR See Note A McBSP1‡ L1D Cache 2-Way Set-Associative 16K Bytes Total AND McASP0 Data PLL (x1, x6, x12) HPI† Power-Down Logic EMAC MDIO 8 GP0 16 Boot Configuration I2C0 † HPI and VP1 are not supported on the DM640 device. ‡ McBSPs: Framing Chips – H.100, MVIP, SCSA, T1, E1; AC97 Devices; SPI Devices; Codecs NOTE A: The Video Port 0 (VP0) peripheral is muxed with the McBSP0 peripheral and the McASP0 control pins (DM641/DM640). The Video Port 1 (VP1) peripheral is muxed with the McBSP1 peripheral and the McASP0 data pins (DM641 only). For more details on the multiplexed pins of these peripherals, see the Device Configurations section of this data sheet. Figure 1–3. Functional Block Diagram June 2003 SPRS222 21 CPU (DSP Core) Description 1.7 CPU (DSP Core) Description PRODUCT PREVIEW The CPU fetches VelociTI advanced very-long instruction words (VLIWs) (256 bits wide) to supply up to eight 32-bit instructions to the eight functional units during every clock cycle. The VelociTI VLIW architecture features controls by which all eight units do not have to be supplied with instructions if they are not ready to execute. The first bit of every 32-bit instruction determines if the next instruction belongs to the same execute packet as the previous instruction, or whether it should be executed in the following clock as a part of the next execute packet. Fetch packets are always 256 bits wide; however, the execute packets can vary in size. The variable-length execute packets are a key memory-saving feature, distinguishing the C64x CPUs from other VLIW architectures. The C64x VelociTI.2 extensions add enhancements to the TMS320C62x DSP VelociTI architecture. These enhancements include: • Register file enhancements • Data path extensions • Quad 8-bit and dual 16-bit extensions with data flow enhancements • Additional functional unit hardware • Increased orthogonality of the instruction set • Additional instructions that reduce code size and increase register flexibility The CPU features two sets of functional units. Each set contains four units and a register file. One set contains functional units .L1, .S1, .M1, and .D1; the other set contains units .D2, .M2, .S2, and .L2. The two register files each contain 32 32-bit registers for a total of 64 general-purpose registers. In addition to supporting the packed 16-bit and 32-/40-bit fixed-point data types found in the C62x VelociTI VLIW architecture, the C64x register files also support packed 8-bit data and 64-bit fixed-point data types. The two sets of functional units, along with two register files, compose sides A and B of the CPU [see the functional block and CPU (DSP core) diagram, and Figure 1–4]. The four functional units on each side of the CPU can freely share the 32 registers belonging to that side. Additionally, each side features a “data cross path”—a single data bus connected to all the registers on the other side, by which the two sets of functional units can access data from the register files on the opposite side. The C64x CPU pipelines data-cross-path accesses over multiple clock cycles. This allows the same register to be used as a data-cross-path operand by multiple functional units in the same execute packet. All functional units in the C64x CPU can access operands via the data cross path. Register access by functional units on the same side of the CPU as the register file can service all the units in a single clock cycle. On the C64x CPU, a delay clock is introduced whenever an instruction attempts to read a register via a data cross path if that register was updated in the previous clock cycle. In addition to the C62x DSP fixed-point instructions, the C64x DSP includes a comprehensive collection of quad 8-bit and dual 16-bit instruction set extensions. These VelociTI.2 extensions allow the C64x CPU to operate directly on packed data to streamline data flow and increase instruction set efficiency. This is a key factor for video and imaging applications. TMS320C62x is a trademark of Texas Instruments. 22 SPRS222 June 2003 CPU (DSP Core) Description The two .M functional units perform all multiplication operations. Each of the C64x .M units can perform two 16 × 16-bit multiplies or four 8 × 8-bit multiplies per clock cycle. The .M unit can also perform 16 × 32-bit multiply operations, dual 16 × 16-bit multiplies with add/subtract operations, and quad 8 × 8-bit multiplies with add operations. In addition to standard multiplies, the C64x .M units include bit-count, rotate, Galois field multiplies, and bidirectional variable shift hardware. The two .S and .L functional units perform a general set of arithmetic, logical, and branch functions with results available every clock cycle. The arithmetic and logical functions on the C64x CPU include single 32-bit, dual 16-bit, and quad 8-bit operations. The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory. The 32-bit instructions destined for the individual functional units are “linked” together by “1” bits in the least significant bit (LSB) position of the instructions. The instructions that are “chained” together for simultaneous execution (up to eight in total) compose an execute packet. A “0” in the LSB of an instruction breaks the chain, effectively placing the instructions that follow it in the next execute packet. A C64x DSP device enhancement now allows execute packets to cross fetch-packet boundaries. In the TMS320C62x/TMS320C67x DSP devices, if an execute packet crosses the fetch-packet boundary (256 bits wide), the assembler places it in the next fetch packet, while the remainder of the current fetch packet is padded with NOP instructions. In the C64x DSP device, the execute boundary restrictions have been removed, thereby, eliminating all of the NOPs added to pad the fetch packet, and thus, decreasing the overall code size. The number of execute packets within a fetch packet can vary from one to eight. Execute packets are dispatched to their respective functional units at the rate of one per clock cycle and the next 256-bit fetch packet is not fetched until all the execute packets from the current fetch packet have been dispatched. After decoding, the instructions simultaneously drive all active functional units for a maximum execution rate of eight instructions every clock cycle. While most results are stored in 32-bit registers, they can be subsequently moved to memory as bytes, half-words, or doublewords. All load and store instructions are byte-, half-word-, word-, or doubleword-addressable. For more details on the C64x CPU functional units enhancements, see the following documents: • TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189) • TMS320C64x Technical Overview (literature number SPRU395) June 2003 SPRS222 23 PRODUCT PREVIEW Another key feature of the C64x CPU is the load/store architecture, where all instructions operate on registers (as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are responsible for all data transfers between the register files and the memory. The data address driven by the .D units allows data addresses generated from one register file to be used to load or store data to or from the other register file. The C64x .D units can load and store bytes (8 bits), half-words (16 bits), and words (32 bits) with a single instruction. And with the new data path extensions, the C64x .D unit can load and store doublewords (64 bits) with a single instruction. Furthermore, the non-aligned load and store instructions allow the .D units to access words and doublewords on any byte boundary. The C64x CPU supports a variety of indirect addressing modes using either linear- or circular-addressing with 5- or 15-bit offsets. All instructions are conditional, and most can access any one of the 64 registers. Some registers, however, are singled out to support specific addressing modes or to hold the condition for conditional instructions (if the condition is not automatically “true”). CPU (DSP Core) Description src1 .L1 src2 dst long dst long src ST1b (Store Data) ST1a (Store Data) 8 8 32 MSBs 32 LSBs long src long dst dst .S1 src1 Data Path A 8 8 Register File A (A0–A31) src2 See Note A See Note A long dst dst .M1 src1 src2 PRODUCT PREVIEW LD1b (Load Data) LD1a (Load Data) 32 MSBs 32 LSBs DA1 (Address) .D1 dst src1 src2 2X 1X src2 .D2 DA2 (Address) LD2a (Load Data) LD2b (Load Data) src1 dst 32 LSBs 32 MSBs src2 .M2 src1 dst See Note A See Note A long dst Register File B (B0– B31) src2 Data Path B .S2 src1 dst long dst long src ST2a (Store Data) ST2b (Store Data) 8 8 32 MSBs 32 LSBs long src long dst dst 8 8 .L2 src2 src1 Control Register File NOTE A: For the .M functional units, the long dst is 32 MSBs and the dst is 32 LSBs. Figure 1–4. TMS320C64x CPU (DSP Core) Data Paths 24 SPRS222 June 2003 Memory Map Summary 1.8 Memory Map Summary Table 1–4 shows the memory map address ranges of the DM641/DM640 device. Internal memory is always located at address 0 and can be used as both program and data memory. The external memory address ranges in the DM641/DM640 device begin at the hex address location 0x8000 0000 for EMIFA. BLOCK SIZE (BYTES) HEX ADDRESS RANGE Internal RAM (L2) 128K 0000 0000 – 0001 FFFF Reserved 768K 0004 0000 – 000F FFFF Reserved 23M 0010 0000 – 017F FFFF External Memory Interface A (EMIFA) Registers 256K 0180 0000 – 0183 FFFF L2 Registers 256K 0184 0000 – 0187 FFFF HPI Registers (DM641 only)† 256K 0188 0000 – 018B FFFF McBSP 0 Registers 256K 018C 0000 – 018F FFFF McBSP 1 Registers 256K 0190 0000 – 0193 FFFF Timer 0 Registers 256K 0194 0000 – 0197 FFFF Timer 1 Registers 256K 0198 0000 – 019B FFFF Interrupt Selector Registers 256K 019C 0000 – 019F FFFF EDMA RAM and EDMA Registers 256K 01A0 0000 – 01A3 FFFF Reserved 512K 01A4 0000 – 01AB FFFF MEMORY BLOCK DESCRIPTION Timer 2 Registers 256K 01AC 0000 – 01AF FFFF 256K – 4K 01B0 0000 – 01B3 EFFF Device Configuration Registers 4K 01B3 F000 – 01B3 FFFF I2C0 Data and Control Registers 16K 01B4 0000 – 01B4 3FFF Reserved 32K 01B4 4000 – 01B4 BFFF McASP0 Control Registers 16K 01B4 C000 – 01B4 FFFF Reserved 192K 01B5 0000 – 01B7 FFFF Reserved 256K 01B8 0000 – 01BB FFFF Emulation 256K 01BC 0000 – 01BF FFFF Reserved 256K 01C0 0000 – 01C3 FFFF VP0 Control 16K 01C4 0000 – 01C4 3FFF VP1 Control (DM641 only)† 16K 01C4 4000 – 01C4 7FFF Reserved 32K 01C4 8000 – 01C4 FFFF Reserved GP0 Registers 192K 01C5 0000 – 01C7 FFFF EMAC Control 4K 01C8 0000 – 01C8 0FFF EMAC Wrapper 8K 01C8 1000 – 01C8 2FFF EWRAP Registers 2K 01C8 3000 – 01C8 37FF MDIO Control Registers 2K 01C8 3800 – 01C8 3FFF 3.5M 01C8 4000 – 01FF FFFF 52 0200 0000 – 0200 0033 928M – 52 0200 0034 – 2FFF FFFF Reserved QDMA Registers Reserved PRODUCT PREVIEW Table 1–4. TMS320DM641/DM640 Memory Map Summary † For the DM640 device, these memory address locations are reserved.The DM640 device does not support the HPI and VP1 peripherals. June 2003 SPRS222 25 Memory Map Summary Table 1–4. TMS320DM641/DM640 Memory Map Summary (Continued) BLOCK SIZE (BYTES) HEX ADDRESS RANGE McBSP 0 Data 64M 3000 0000 – 33FF FFFF McBSP 1 Data 64M 3400 0000 – 37FF FFFF Reserved 64M 3800 0000 – 3BFF FFFF McASP0 Data 1M 3C00 0000 – 3C0F FFFF Reserved 64M – 1M 3C10 0000 – 3FFF FFFF Reserved 832M 4000 0000 – 73FF FFFF VP0 Channel A Data 32M 7400 0000 – 75FF FFFF Reserved 32M 7600 0000 – 77FF FFFF VP1 Channel A Data (DM641 only)† 32M 7800 0000 – 79FF FFFF Reserved 32M 7A00 0000 – 7BFF FFFF Reserved 64M 7C00 0000 – 7FFF FFFF EMIFA CE0 256M 8000 0000 – 8FFF FFFF EMIFA CE1 256M 9000 0000 – 9FFF FFFF EMIFA CE2 256M A000 0000 – AFFF FFFF EMIFA CE3 256M B000 0000 – BFFF FFFF 1G C000 0000 – FFFF FFFF PRODUCT PREVIEW MEMORY BLOCK DESCRIPTION Reserved † For the DM640 device, these memory address locations are reserved.The DM640 device does not support the HPI and VP1 peripherals. 26 SPRS222 June 2003 Peripheral Register Descriptions 1.9 Peripheral Register Descriptions Table 1–5 through Table 1–28 identify the peripheral registers for the DM641/DM640 device by their register names, acronyms, and hex address or hex address range. For more detailed information on the register contents, bit names and their descriptions, see the TMS320C6000 Peripherals Reference Guide (literature number SPRU190). Table 1–5. EMIFA Registers HEX ADDRESS RANGE ACRONYM 0180 0000 GBLCTL EMIFA global control REGISTER NAME 0180 0004 CECTL1 EMIFA CE1 space control 0180 0008 CECTL0 EMIFA CE0 space control – 0180 0010 CECTL2 Reserved EMIFA CE2 space control 0180 0014 CECTL3 EMIFA CE3 space control 0180 0018 SDCTL EMIFA SDRAM control 0180 001C SDTIM EMIFA SDRAM refresh control EMIFA SDRAM extension 0180 0020 SDEXT 0180 0024 – 0180 0040 – 0180 0044 CESEC1 EMIFA CE1 space secondary control EMIFA CE0 space secondary control PRODUCT PREVIEW 0180 000C COMMENTS Reserved 0180 0048 CESEC0 0180 004C – 0180 0050 CESEC2 EMIFA CE2 space secondary control 0180 0054 CESEC3 EMIFA CE3 space secondary control 0180 0058 – 0183 FFFF – Reserved Reserved Table 1–6. L2 Cache Registers (C64x) HEX ADDRESS RANGE ACRONYM 0184 0000 CCFG 0184 2000 L2ALLOC0 L2 allocation register 0 0184 2004 L2ALLOC1 L2 allocation register 1 – REGISTER NAME Reserved 0184 2008 L2ALLOC2 L2 allocation register 2 0184 200C L2ALLOC3 L2 allocation register 3 0184 4000 L2FBAR L2 flush base address register 0184 4004 L2FWC L2 flush word count register 0184 4010 L2CBAR L2 clean base address register 0184 4014 L2CWC L2 clean word count register 0184 4020 L1PFBAR L1P flush base address register 0184 4024 L1PFWC L1P flush word count register 0184 4030 L1DFBAR L1D flush base address register 0184 4034 L1DFWC L1D flush word count register – – Reserved Reserved 0184 5000 L2FLUSH L2 flush register 0184 5004 L2CLEAN L2 clean register June 2003 COMMENTS Cache configuration register SPRS222 27 Peripheral Register Descriptions PRODUCT PREVIEW Table 1–6. L2 Cache Registers (C64x) (Continued) 28 HEX ADDRESS RANGE ACRONYM REGISTER NAME – Reserved 0184 8000 –0184 81FC MAR0 to MAR127 Reserved 0184 8200 MAR128 Controls EMIFA CE0 range 8000 0000 – 80FF FFFF 0184 8204 MAR129 Controls EMIFA CE0 range 8100 0000 – 81FF FFFF 0184 8208 MAR130 Controls EMIFA CE0 range 8200 0000 – 82FF FFFF 0184 820C MAR131 Controls EMIFA CE0 range 8300 0000 – 83FF FFFF 0184 8210 MAR132 Controls EMIFA CE0 range 8400 0000 – 84FF FFFF 0184 8214 MAR133 Controls EMIFA CE0 range 8500 0000 – 85FF FFFF 0184 8218 MAR134 Controls EMIFA CE0 range 8600 0000 – 86FF FFFF 0184 821C MAR135 Controls EMIFA CE0 range 8700 0000 – 87FF FFFF 0184 8220 MAR136 Controls EMIFA CE0 range 8800 0000 – 88FF FFFF 0184 8224 MAR137 Controls EMIFA CE0 range 8900 0000 – 89FF FFFF 0184 8228 MAR138 Controls EMIFA CE0 range 8A00 0000 – 8AFF FFFF 0184 822C MAR139 Controls EMIFA CE0 range 8B00 0000 – 8BFF FFFF 0184 8230 MAR140 Controls EMIFA CE0 range 8C00 0000 – 8CFF FFFF 0184 8234 MAR141 Controls EMIFA CE0 range 8D00 0000 – 8DFF FFFF 0184 8238 MAR142 Controls EMIFA CE0 range 8E00 0000 – 8EFF FFFF 0184 823C MAR143 Controls EMIFA CE0 range 8F00 0000 – 8FFF FFFF 0184 8240 MAR144 Controls EMIFA CE1 range 9000 0000 – 90FF FFFF 0184 8244 MAR145 Controls EMIFA CE1 range 9100 0000 – 91FF FFFF 0184 8248 MAR146 Controls EMIFA CE1 range 9200 0000 – 92FF FFFF 0184 824C MAR147 Controls EMIFA CE1 range 9300 0000 – 93FF FFFF 0184 8250 MAR148 Controls EMIFA CE1 range 9400 0000 – 94FF FFFF 0184 8254 MAR149 Controls EMIFA CE1 range 9500 0000 – 95FF FFFF 0184 8258 MAR150 Controls EMIFA CE1 range 9600 0000 – 96FF FFFF 0184 825C MAR151 Controls EMIFA CE1 range 9700 0000 – 97FF FFFF 0184 8260 MAR152 Controls EMIFA CE1 range 9800 0000 – 98FF FFFF 0184 8264 MAR153 Controls EMIFA CE1 range 9900 0000 – 99FF FFFF 0184 8268 MAR154 Controls EMIFA CE1 range 9A00 0000 – 9AFF FFFF 0184 826C MAR155 Controls EMIFA CE1 range 9B00 0000 – 9BFF FFFF 0184 8270 MAR156 Controls EMIFA CE1 range 9C00 0000 – 9CFF FFFF 0184 8274 MAR157 Controls EMIFA CE1 range 9D00 0000 – 9DFF FFFF 0184 8278 MAR158 Controls EMIFA CE1 range 9E00 0000 – 9EFF FFFF 0184 827C MAR159 Controls EMIFA CE1 range 9F00 0000 – 9FFF FFFF 0184 8280 MAR160 Controls EMIFA CE2 range A000 0000 – A0FF FFFF 0184 8284 MAR161 Controls EMIFA CE2 range A100 0000 – A1FF FFFF 0184 8288 MAR162 Controls EMIFA CE2 range A200 0000 – A2FF FFFF 0184 828C MAR163 Controls EMIFA CE2 range A300 0000 – A3FF FFFF 0184 8290 MAR164 Controls EMIFA CE2 range A400 0000 – A4FF FFFF 0184 8294 MAR165 Controls EMIFA CE2 range A500 0000 – A5FF FFFF 0184 8298 MAR166 Controls EMIFA CE2 range A600 0000 – A6FF FFFF SPRS222 COMMENTS June 2003 Peripheral Register Descriptions Table 1–6. L2 Cache Registers (C64x) (Continued) ACRONYM REGISTER NAME 0184 829C MAR167 Controls EMIFA CE2 range A700 0000 – A7FF FFFF 0184 82A0 MAR168 Controls EMIFA CE2 range A800 0000 – A8FF FFFF 0184 82A4 MAR169 Controls EMIFA CE2 range A900 0000 – A9FF FFFF 0184 82A8 MAR170 Controls EMIFA CE2 range AA00 0000 – AAFF FFFF 0184 82AC MAR171 Controls EMIFA CE2 range AB00 0000 – ABFF FFFF 0184 82B0 MAR172 Controls EMIFA CE2 range AC00 0000 – ACFF FFFF 0184 82B4 MAR173 Controls EMIFA CE2 range AD00 0000 – ADFF FFFF 0184 82B8 MAR174 Controls EMIFA CE2 range AE00 0000 – AEFF FFFF 0184 82BC MAR175 Controls EMIFA CE2 range AF00 0000 – AFFF FFFF 0184 82C0 MAR176 Controls EMIFA CE3 range B000 0000 – B0FF FFFF 0184 82C4 MAR177 Controls EMIFA CE3 range B100 0000 – B1FF FFFF 0184 82C8 MAR178 Controls EMIFA CE3 range B200 0000 – B2FF FFFF 0184 82CC MAR179 Controls EMIFA CE3 range B300 0000 – B3FF FFFF 0184 82D0 MAR180 Controls EMIFA CE3 range B400 0000 – B4FF FFFF 0184 82D4 MAR181 Controls EMIFA CE3 range B500 0000 – B5FF FFFF 0184 82D8 MAR182 Controls EMIFA CE3 range B600 0000 – B6FF FFFF 0184 82DC MAR183 Controls EMIFA CE3 range B700 0000 – B7FF FFFF 0184 82E0 MAR184 Controls EMIFA CE3 range B800 0000 – B8FF FFFF 0184 82E4 MAR185 Controls EMIFA CE3 range B900 0000 – B9FF FFFF 0184 82E8 MAR186 Controls EMIFA CE3 range BA00 0000 – BAFF FFFF 0184 82EC MAR187 Controls EMIFA CE3 range BB00 0000 – BBFF FFFF 0184 82F0 MAR188 Controls EMIFA CE3 range BC00 0000 – BCFF FFFF 0184 82F4 MAR189 Controls EMIFA CE3 range BD00 0000 – BDFF FFFF 0184 82F8 MAR190 Controls EMIFA CE3 range BE00 0000 – BEFF FFFF 0184 82FC MAR191 Controls EMIFA CE3 range BF00 0000 – BFFF FFFF 0184 8300 –0184 83FC MAR192 to MAR255 Reserved 0184 8400 –0187 FFFF – Reserved COMMENTS PRODUCT PREVIEW HEX ADDRESS RANGE Table 1–7. Quick DMA (QDMA) and Pseudo Registers HEX ADDRESS RANGE ACRONYM 0200 0000 QOPT QDMA options parameter register REGISTER NAME 0200 0004 QSRC QDMA source address register 0200 0008 QCNT QDMA frame count register 0200 000C QDST QDMA destination address register 0200 0010 QIDX QDMA index register 0200 0014 – 0200 001C Reserved 0200 0020 QSOPT QDMA pseudo options register 0200 0024 QSSRC QDMA psuedo source address register 0200 0028 QSCNT QDMA psuedo frame count register 0200 002C QSDST QDMA destination address register 0200 0030 QSIDX QDMA psuedo index register June 2003 SPRS222 29 Peripheral Register Descriptions PRODUCT PREVIEW Table 1–8. EDMA Registers (C64x) HEX ADDRESS RANGE ACRONYM 01A0 0800 – 01A0 FF98 – REGISTER NAME Reserved 01A0 FF9C EPRH Event polarity high register 01A0 FFA4 CIPRH Channel interrupt pending high register 01A0 FFA8 CIERH Channel interrupt enable high register 01A0 FFAC CCERH Channel chain enable high register 01A0 FFB0 ERH Event high register 01A0 FFB4 EERH Event enable high register 01A0 FFB8 ECRH Event clear high register 01A0 FFBC ESRH Event set high register 01A0 FFC0 PQAR0 Priority queue allocation register 0 01A0 FFC4 PQAR1 Priority queue allocation register 1 01A0 FFC8 PQAR2 Priority queue allocation register 2 01A0 FFCC PQAR3 Priority queue allocation register 3 01A0 FFDC EPRL Event polarity low register 01A0 FFE0 PQSR Priority queue status register 01A0 FFE4 CIPRL Channel interrupt pending low register 01A0 FFE8 CIERL Channel interrupt enable low register 01A0 FFEC CCERL Channel chain enable low register 01A0 FFF0 ERL Event low register 01A0 FFF4 EERL Event enable low register 01A0 FFF8 ECRL Event clear low register 01A0 FFFC ESRL Event set low register 01A1 0000 – 01A3 FFFF – Reserved Table 1–9. EDMA Parameter RAM (C64x)† HEX ADDRESS RANGE ACRONYM REGISTER NAME 01A0 0000 – 01A0 0017 – Parameters for Event 0 (6 words) 01A0 0018 – 01A0 002F – Parameters for Event 1 (6 words) 01A0 0030 – 01A0 0047 – Parameters for Event 2 (6 words) 01A0 0048 – 01A0 005F – Parameters for Event 3 (6 words) 01A0 0060 – 01A0 0077 – Parameters for Event 4 (6 words) 01A0 0078 – 01A0 008F – Parameters for Event 5 (6 words) 01A0 0090 – 01A0 00A7 – Parameters for Event 6 (6 words) 01A0 00A8 – 01A0 00BF – Parameters for Event 7 (6 words) 01A0 00C0 – 01A0 00D7 – Parameters for Event 8 (6 words) 01A0 00D8 – 01A0 00EF – Parameters for Event 9 (6 words) 01A0 00F0 – 01A0 00107 – Parameters for Event 10 (6 words) 01A0 0108 – 01A0 011F – Parameters for Event 11 (6 words) 01A0 0120 – 01A0 0137 – Parameters for Event 12 (6 words) 01A0 0138 – 01A0 014F – COMMENTS Parameters for Event 0 (6 words) or Reload/Link Parameters for other Event Parameters for Event 13 (6 words) † The DM64x device has 213 EDMA parameters total: 64-Event/Reload channels and 149-Reload only parameter sets [six (6) words each] that can be used to reload/link EDMA transfers. 30 SPRS222 June 2003 Peripheral Register Descriptions Table 1–9. EDMA Parameter RAM (C64x)† (Continued) HEX ADDRESS RANGE ACRONYM 01A0 0150 – 01A0 0167 – Parameters for Event 14 (6 words) REGISTER NAME 01A0 0168 – 01A0 017F – Parameters for Event 15 (6 words) 01A0 0150 – 01A0 0167 – Parameters for Event 16 (6 words) 01A0 0168 – 01A0 017F – Parameters for Event 17 (6 words) ... COMMENTS ... 01A0 05D0 – 01A0 05E7 – Parameters for Event 62 (6 words) 01A0 05E8 – 01A0 05FF – Parameters for Event 63 (6 words) 01A0 0600 – 01A0 0617 – Reload/link parameters for Event 0 (6 words) 01A0 0618 – 01A0 062F – Reload/link parameters for Event 1 (6 words) ... 01A0 07E0 – 01A0 07F7 – Reload/link parameters for Event 20 (6 words) 01A0 07F8 – 01A0 07FF – Reload/link parameters for Event 21 (6 words) 01A0 0800 – 01A0 0817 – Reload/link parameters for Event 22 (6 words) ... ... 01A0 13C8 – 01A0 13DF – Reload/link parameters for Event 147 (6 words) 01A0 13E0 – 01A0 13F7 – Reload/link parameters for Event 148 (6 words) 01A0 13F8 – 01A0 13FF – Scratch pad area (2 words) 01A0 1400 – 01A3 FFFF – Reserved † The DM64x device has 213 EDMA parameters total: 64-Event/Reload channels and 149-Reload only parameter sets [six (6) words each] that can be used to reload/link EDMA transfers. Table 1–10. Interrupt Selector Registers (C64x) HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS 019C 0000 MUXH Interrupt multiplexer high Selects which interrupts drive CPU interrupts 10–15 (INT10–INT15) 019C 0004 MUXL Interrupt multiplexer low Selects which interrupts drive CPU interrupts 4–9 (INT04–INT09) 019C 0008 EXTPOL External interrupt polarity Sets the polarity of the external interrupts (EXT_INT4–EXT_INT7) 019C 000C – 019C 01FF – 019C 0200 PDCTL 019C 0204 – 019F FFFF – Reserved Peripheral power-down control register (see Table 1–11) Reserved Table 1–11. Peripheral Power-Down Control Register HEX ADDRESS RANGE ACRONYM 019C 0200 PDCTL REGISTER NAME Peripheral power-down control register Table 1–12. Ethernet MAC (EMAC) Registers HEX ADDRESS RANGE ACRONYM 01C8 0000 TXIDVER 01C8 0004 TXCONTROL 01C8 0008 TXTEARDOWN 01C8 000F – 01C8 0010 RXIDVER June 2003 REGISTER NAME Transmit Identification and Version Register Transmit Control Register Transmit Teardown Register Reserved Receive Identification and Version Register SPRS222 31 PRODUCT PREVIEW ... Reload/Link Parameters for other Event 0–15 Peripheral Register Descriptions PRODUCT PREVIEW Table 1–12. Ethernet MAC (EMAC) Registers (Continued) 32 HEX ADDRESS RANGE ACRONYM 01C8 0014 RXCONTROL REGISTER NAME 01C8 0018 RXTEARDOWN 01C8 001C – 01C8 00FF – 01C8 0100 RXMBPENABLE Receive Multicast/Broadcast/Promiscuous Channel Enable Register 01C8 0104 RXUNICASTSET Receive Unicast Set Register 01C8 0108 RXUNICASTCLEAR 01C8 010C RXMAXLEN Receive Control Register Receive Teardown Register Reserved Receive Unicast Clear Register Receive Maximum Length Register 01C8 0110 RXBUFFEROFFSET 01C8 0114 RXFILTERLOWTHRESH Receive Buffer Offset Register 01C8 0118 – 01C8 011F – 01C8 0120 RX0FLOWTHRESH Receive Channel 0 Flow Control Threshold Register 01C8 0124 RX1FLOWTHRESH Receive Channel 1 Flow Control Threshold Register Receive Filter Low Priority Packets Threshold Register Reserved 01C8 0128 RX2FLOWTHRESH Receive Channel 2 Flow Control Threshold Register 01C8 012C RX3FLOWTHRESH Receive Channel 3 Flow Control Threshold Register 01C8 0130 RX4FLOWTHRESH Receive Channel 4 Flow Control Threshold Register 01C8 0134 RX5FLOWTHRESH Receive Channel 5 Flow Control Threshold Register 01C8 0138 RX6FLOWTHRESH Receive Channel 6 Flow Control Threshold Register 01C8 013C RX7FLOWTHRESH Receive Channel 7 Flow Control Threshold Register 01C8 0140 RX0FREEBUFFER Receive Channel 0 Free Buffer Count Register 01C8 0144 RX1FREEBUFFER Receive Channel 1 Free Buffer Count Register 01C8 0148 RX2FREEBUFFER Receive Channel 2 Free Buffer Count Register 01C8 014C RX3FREEBUFFER Receive Channel 3 Free Buffer Count Register 01C8 0150 RX4FREEBUFFER Receive Channel 4 Free Buffer Count Register 01C8 0154 RX5FREEBUFFER Receive Channel 5 Free Buffer Count Register 01C8 0158 RX6FREEBUFFER Receive Channel 6 Free Buffer Count Register 01C8 015C RX7FREEBUFFER Receive Channel 7 Free Buffer Count Register 01C8 0160 MACCONTROL MAC Control Register 01C8 0164 MACSTATUS MAC Status Register 01C8 0168 EMCONTROL Emulation Control Register 01C8 016C – 01C8 0170 TXINTSTATRAW 01C8 0174 TXINTSTATMASKED 01C8 0178 TXINTMASKSET 01C8 017C TXINTMASKCLEAR Reserved Transmit Interrupt Status (Unmasked) Register Transmit Interrupt Status (Masked) Register Transmit Interrupt Mask Set Register Transmit Interrupt Mask Clear Register 01C8 0180 MACINVECTOR MAC Input Vector Register 01C8 0184 MACEOIVECTOR MAC EOI Vector Register 01C8 0188 – 01C8 018F – 01C8 0190 RXINTSTATRAW 01C8 0194 RXINTSTATMASKED 01C8 0198 RXINTMASKSET 01C8 019C RXINTMASKCLEAR 01C8 01A0 MACINTSTATRAW 01C8 01A4 MACINTSTATMASKED SPRS222 Reserved Receive Interrupt Status (Unmasked) Register Receive Interrupt Status (Masked) Register Receive Interrupt Mask Set Register Receive Interrupt Mask Clear Register MAC Interrupt Status (Unmasked) Register MAC Interrupt Status (Masked) Register June 2003 Peripheral Register Descriptions Table 1–12. Ethernet MAC (EMAC) Registers (Continued) HEX ADDRESS RANGE ACRONYM 01C8 01A8 MACINTMASKSET REGISTER NAME 01C8 01AC MACINTMASKCLEAR 01C8 01B0 MACADDRL0 MAC Address Channel 0 Lower Byte Register 01C8 01B4 MACADDRL1 MAC Address Channel 1 Lower Byte Register MAC Interrupt Mask Set Register 01C8 01B8 MACADDRL2 MAC Address Channel 2 Lower Byte Register 01C8 01BC MACADDRL3 MAC Address Channel 3 Lower Byte Register 01C8 01C0 MACADDRL4 MAC Address Channel 4 Lower Byte Register 01C8 01C4 MACADDRL5 MAC Address Channel 5 Lower Byte Register 01C8 01C8 MACADDRL6 MAC Address Channel 6 Lower Byte Register 01C8 01CC MACADDRL7 MAC Address Channel 7 Lower Byte Register 01C8 01D0 MACADDRM MAC Address Middle Byte Register 01C8 01D4 MACADDRH MAC Address High Bytes Register 01C8 01D8 MACHASH1 MAC Address Hash 1 Register 01C8 01DC MACHASH2 MAC Address Hash 2 Register 01C8 01E0 BOFFTEST Backoff Test Register 01C8 01E4 TPACETEST Transmit Pacing Test Register 01C8 01E8 RXPAUSE Receive Pause Timer Register 01C8 01EC TXPAUSE Transmit Pause Timer Register 01C8 01F0 – 01C8 01FF – Reserved 01C8 0200 RXGOODFRAMES Good Receive Frames Register 01C8 0204 RXBCASTFRAMES Broadcast Receive Frames Register 01C8 0208 RXMCASTFRAMES Multicast Receive Frames Register 01C8 020C RXPAUSEFRAMES Pause Receive Frames Register 01C8 0210 RXCRCERRORS 01C8 0214 RXALIGNCODEERRORS Receive CRC Errors Register Receive Alignment/Code Errors Register 01C8 0218 RXOVERSIZED 01C8 021C RXJABBER 01C8 0220 RXUNDERSIZED Receive Undersized Frames Register 01C8 0224 RXFRAGMENTS Receive Frame Fragments Register 01C8 0228 RXFILTERED 01C8 022C RXQOSFILTERED 01C8 0230 RXOCTETS Receive Octet Frames Register 01C8 0234 TXGOODFRAMES Good Transmit Frames Register 01C8 0238 TXBCASTFRAMES Broadcast Transmit Frames Register 01C8 023C TXMCASTFRAMES Multicast Transmit Frames Register 01C8 0240 TXPAUSEFRAMES Pause Transmit Frames Register 01C8 0244 TXDEFERRED Deferred Transmit Frames Register Collision Register 01C8 0248 TXCOLLISION 01C8 024C TXSINGLECOLL 01C8 0250 TXMULTICOLL 01C8 0254 TXEXCESSIVECOLL 01C8 0258 TXLATECOLL 01C8 025C TXUNDERRUN 01C8 0260 TXCARRIERSLOSS June 2003 PRODUCT PREVIEW MAC Interrupt Mask Clear Register Receive Oversized Frames Register Receive Jabber Frames Register Filtered Receive Frames Register Receive QOS Filtered Frames Register Single Collision Transmit Frames Register Multiple Collision Transmit Frames Register Excessive Collisions Register Late Collisions Register Transmit Underrun Register Transmit Carrier Sense Errors Register SPRS222 33 Peripheral Register Descriptions PRODUCT PREVIEW Table 1–12. Ethernet MAC (EMAC) Registers (Continued) 34 HEX ADDRESS RANGE ACRONYM REGISTER NAME 01C8 0264 TXOCTETS Transmit Octet Frames Register 01C8 0268 FRAME64 01C8 026C FRAME65T127 Transmit and Receive 64 Octet Frames Register Transmit and Receive 65 to 127 Octet Frames Register 01C8 0270 FRAME128T255 Transmit and Receive 128 to 255 Octet Frames Register 01C8 0274 FRAME256T511 Transmit and Receive 256 to 511 Octet Frames Register 01C8 0278 FRAME512T1023 Transmit and Receive 512 to 1023 Octet Frames Register 01C8 027C FRAME1024TUP Transmit and Receive 1024 or Above Octet Frames Register 01C8 0280 NETOCTETS 01C8 0284 RXSOFOVERRUNS Network Octet Frames Register Receive Start of Frame Overruns Register 01C8 0288 RXMOFOVERRUNS Receive Middle of Frame Overruns Register 01C8 028C RXDMAOVERRUNS Receive DMA Overruns Register 01C8 0290 – 01C8 02FF – 01C8 0300 – 01C8 03FF RXFIFO Processor Test Access 01C8 0400 – 01C8 04FF TXFIFO Processor Test Access 01C8 0500 – 01C8 05FF – 01C8 0600 TX0HDP Transmit Channel 0 DMA Head Descriptor Pointer Register 01C8 0604 TX1HDP Transmit Channel 1 DMA Head Descriptor Pointer Register 01C8 0608 TX2HDP Transmit Channel 2 DMA Head Descriptor Pointer Register 01C8 060C TX3HDP Transmit Channel 3 DMA Head Descriptor Pointer Register 01C8 0610 TX4HDP Transmit Channel 4 DMA Head Descriptor Pointer Register 01C8 0614 TX5HDP Transmit Channel 5 DMA Head Descriptor Pointer Register 01C8 0618 TX6HDP Transmit Channel 6 DMA Head Descriptor Pointer Register 01C8 061C TX7HDP Transmit Channel 7 DMA Head Descriptor Pointer Register 01C8 0620 RX0HDP Receive Channel 0 DMA Head Descriptor Pointer Register 01C8 0624 RX1HDP Receive Channel 1 DMA Head Descriptor Pointer Register 01C8 0628 RX2HDP Receive Channel 2 DMA Head Descriptor Pointer Register 01C8 062C RX3HDP Receive Channel 3 DMA Head Descriptor Pointer Register 01C8 0630 RX4HDP Receive Channel 4 DMA Head Descriptor Pointer Register 01C8 0634 RX5HDP Receive Channel 5 DMA Head Descriptor Pointer Register 01C8 0638 RX6HDP Receive Channel 6 DMA Head Descriptor Pointer Register SPRS222 Reserved Reserved June 2003 Peripheral Register Descriptions Table 1–12. Ethernet MAC (EMAC) Registers (Continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 01C8 063C RX7HDP 01C8 0640 TX0INTACK Transmit Channel 0 Interrupt Acknowledge Register 01C8 0644 TX1INTACK Transmit Channel 1 Interrupt Acknowledge Register 01C8 0648 TX2INTACK Transmit Channel 2 Interrupt Acknowledge Register 01C8 064C TX3INTACK Transmit Channel 3 Interrupt Acknowledge Register 01C8 0650 TX4INTACK Transmit Channel 4 Interrupt Acknowledge Register 01C8 0654 TX5INTACK Transmit Channel 5 Interrupt Acknowledge Register 01C8 0658 TX6INTACK Transmit Channel 6 Interrupt Acknowledge Register 01C8 065C TX7INTACK Transmit Channel 7 Interrupt Acknowledge Register 01C8 0660 RX0INTACK Receive Channel 0 Interrupt Acknowledge Register 01C8 0664 RX1INTACK Receive Channel 1 Interrupt Acknowledge Register 01C8 0668 RX2INTACK Receive Channel 2 Interrupt Acknowledge Register 01C8 066C RX3INTACK Receive Channel 3 Interrupt Acknowledge Register 01C8 0670 RX4INTACK Receive Channel 4 Interrupt Acknowledge Register 01C8 0674 RX5INTACK Receive Channel 5 Interrupt Acknowledge Register 01C8 0678 RX6INTACK Receive Channel 6 Interrupt Acknowledge Register 01C8 067C RX7INTACK Receive Channel 7 Interrupt Acknowledge Register 01C8 0680 – 01C8 06FF – Reserved 01C8 0700 – 01C8 077F – State RAM Test Access – Processor read and write access to head descriptor pointers and interrupt acknowledge registers. 01C8 0780 – 01C8 0FFF – Reserved June 2003 PRODUCT PREVIEW Receive Channel 7 DMA Head Descriptor Pointer Register SPRS222 35 Peripheral Register Descriptions Table 1–13. EMAC Wrapper HEX ADDRESS RANGE ACRONYM 01C8 1000 – 01C8 1FFF REGISTER NAME EMAC Control Module Descriptor Memory 01C8 2000 – 01C8 2FFF – Reserved Table 1–14. EWRAP Registers HEX ADDRESS RANGE ACRONYM 01C8 3000 EWTRCTRL 01C8 3004 EWCTL 01C8 3008 EWINTTCNT 01C8 300C – 01C8 37FF – REGISTER NAME TR control Interrupt control register Interrupt timer count Reserved Table 1–15. Device Configuration Registers PRODUCT PREVIEW HEX ADDRESS RANGE 36 ACRONYM REGISTER NAME COMMENTS 01B3 F000 PERCFG Peripheral Configuration Register Enables or disables specific peripherals. This register is also used for power-down of disabled peripherals. 01B3 F004 DEVSTAT Device Status Register Read-only. Provides status of the User’s device configuration on reset. 01B3 F008 JTAGID JTAG Identification Register Read-only. Provides JTAG ID of the device. 01B3 F00C – 01B3 F014 – 01B3 F018 PCFGLOCK 01B3 F01C – 01B3 FFFF – SPRS222 32-bit Reserved Peripheral Configuration Lock Register Reserved June 2003 Peripheral Register Descriptions Table 1–16. McBSP 0 Registers ACRONYM REGISTER NAME 018C 0000 DRR0 McBSP0 data receive register via Configuration Bus 0x3000 0000 – 0x33FF FFFF DRR0 McBSP0 data receive register via Peripheral Bus 018C 0004 DXR0 McBSP0 data transmit register via Configuration Bus 0x3000 0000 – 0x33FF FFFF DXR0 McBSP0 data transmit register via Peripheral Bus 018C 0008 SPCR0 018C 000C RCR0 McBSP0 receive control register 018C 0010 XCR0 McBSP0 transmit control register 018C 0014 SRGR0 018C 0018 MCR0 018C 001C RCERE00 McBSP0 enhanced receive channel enable register 0 018C 0020 XCERE00 McBSP0 enhanced transmit channel enable register 0 COMMENTS The CPU and EDMA controller can only read this register; they cannot write to it. McBSP0 serial port control register McBSP0 sample rate generator register McBSP0 multichannel control register 018C 0024 PCR0 018C 0028 RCERE10 McBSP0 pin control register McBSP0 enhanced receive channel enable register 1 018C 002C XCERE10 McBSP0 enhanced transmit channel enable register 1 018C 0030 RCERE20 McBSP0 enhanced receive channel enable register 2 018C 0034 XCERE20 McBSP0 enhanced transmit channel enable register 2 018C 0038 RCERE30 McBSP0 enhanced receive channel enable register 3 018C 003C XCERE30 McBSP0 enhanced transmit channel enable register 3 018C 0040 – 018F FFFF – Reserved Table 1–17. McBSP 1 Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 0190 0000 DRR1 McBSP1 data receive register via Configuration Bus 0x3400 0000 – 0x37FF FFFF DRR1 McBSP1 data receive register via peripheral bus 0190 0004 DXR1 McBSP1 data transmit register via configuration bus 0x3400 0000 – 0x37FF FFFF DXR1 McBSP1 data transmit register via peripheral bus 0190 0008 SPCR1 0190 000C RCR1 McBSP1 receive control register 0190 0010 XCR1 McBSP1 transmit control register 0190 0014 SRGR1 The CPU and EDMA controller can only read this register; they cannot write to it. McBSP1 serial port control register McBSP1 sample rate generator register 0190 0018 MCR1 0190 001C RCERE01 McBSP1 enhanced receive channel enable register 0 0190 0020 XCERE01 McBSP1 enhanced transmit channel enable register 0 0190 0024 PCR1 0190 0028 RCERE11 McBSP1 enhanced receive channel enable register 1 0190 002C XCERE11 McBSP1 enhanced transmit channel enable register 1 0190 0030 RCERE21 McBSP1 enhanced receive channel enable register 2 0190 0034 XCERE21 McBSP1 enhanced transmit channel enable register 2 McBSP1 multichannel control register McBSP1 pin control register 0190 0038 RCERE31 McBSP1 enhanced receive channel enable register 3 0190 003C XCERE31 McBSP1 enhanced transmit channel enable register 3 0190 0040 – 0193 FFFF – June 2003 COMMENTS Reserved SPRS222 37 PRODUCT PREVIEW HEX ADDRESS RANGE Peripheral Register Descriptions Table 1–18. Timer 0 Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS 0194 0000 CTL0 Timer 0 control register Determines the operating mode of the timer, monitors the timer status, and controls the function of the TOUT pin. 0194 0004 PRD0 Timer 0 period register Contains the number of timer input clock cycles to count. This number controls the TSTAT signal frequency. 0194 0008 CNT0 Timer 0 counter register Contains the current value of the incrementing counter. 0194 000C – 0197 FFFF – Reserved Table 1–19. Timer 1 Registers PRODUCT PREVIEW HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS 0198 0000 CTL1 Timer 1 control register Determines the operating mode of the timer, monitors the timer status, and controls the function of the TOUT pin. 0198 0004 PRD1 Timer 1 period register Contains the number of timer input clock cycles to count. This number controls the TSTAT signal frequency. 0198 0008 CNT1 Timer 1 counter register Contains the current value of the incrementing counter. 0198 000C – 019B FFFF – Reserved Table 1–20. Timer 2 Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS 01AC 0000 CTL2 Timer 2 control register Determines the operating mode of the timer, monitors the timer status. 01AC 0004 PRD2 Timer 2 period register Contains the number of timer input clock cycles to count. This number controls the TSTAT signal frequency. 01AC 0008 CNT2 Timer 2 counter register Contains the current value of the incrementing counter. 01AC 000C – 01AF FFFF – Reserved Table 1–21. HPI Registers [DM641 Only] HEX ADDRESS RANGE ACRONYM – HPID HPI data register REGISTER NAME Host read/write access only COMMENTS 0188 0000 HPIC HPI control register HPIC has both Host/CPU read/write access 0188 0004 HPIA (HPIAW)† HPI address register (Write) 0188 0008 HPIA (HPIAR)† HPI address register (Read) HPIA has both Host/CPU read/write access 0188 0001 – 018B FFFF – Reserved † Host access to the HPIA register updates both the HPIAW and HPIAR registers. The CPU can access HPIAW and HPIAR independently. 38 SPRS222 June 2003 Peripheral Register Descriptions Table 1–22. GP0 Registers HEX ADDRESS RANGE ACRONYM 01B0 0000 GPEN GP0 enable register REGISTER NAME 01B0 0004 GPDIR GP0 direction register 01B0 0008 GPVAL GP0 value register 01B0 000C – Reserved 01B0 0010 GPDH GP0 delta high register 01B0 0014 GPHM GP0 high mask register 01B0 0018 GPDL GP0 delta low register 01B0 001C GPLM GP0 low mask register 01B0 0020 GPGC GP0 global control register 01B0 0024 GPPOL GP0 interrupt polarity register 01B0 0028 – 01B3 EFFF – Reserved Table 1–23. VCXO Interpolated Control (VIC) Port Registers ACRONYM REGISTER NAME 01C4 C000 VICCTL 01C4 C004 VICIN VIC input register 01C4 C008 VPDIV VIC clock divider register 01C4 C00C – 01C4 FFFF – PRODUCT PREVIEW HEX ADDRESS RANGE VIC control register Reserved Table 1–24. MDIO Registers HEX ADDRESS RANGE ACRONYM 01C8 3800 VERSION MDIO Version Register 01C8 3804 CONTROL MDIO Control Register 01C8 3808 ALIVE 01C8 380C LINK 01C8 3810 LINKINTRAW 01C8 3814 LINKINTMASKED REGISTER NAME MDIO PHY Alive Indication Register MDIO PHY Link Status Register MDIO Link Status Change Interrupt Register MDIO Link Status Change Interrupt (Masked) Register 01C8 3818 USERINTRAW 01C8 381C USERINTMASKED MDIO User Command Complete Interrupt (Masked) Register 01C8 3820 USERINTMASKSET MDIO User Command Complete Interrupt Mask Set Register 01C8 3824 USERINTMASKCLEAR 01C8 3828 USERACCESS0 MDIO User Access Register 0 01C8 382C USERACCESS1 MDIO User Access Register 1 01C8 3830 USERPHYSEL0 MDIO User PHY Select Register 0 01C8 3834 USERPHYSEL1 MDIO User PHY Select Register 1 01C8 3838 – 01C8 3FFF – June 2003 MDIO User Command Complete Interrupt Register MDIO User Command Complete Interrupt Mask Clear Register Reserved SPRS222 39 Peripheral Register Descriptions Table 1–25. Video Port 0 and 1 (VP0 and VP1) Control Registers PRODUCT PREVIEW HEX ADDRESS RANGE 40 ACRONYM DESCRIPTION VP0 VP1 [DM641 ONLY] 01C4 0000 01C4 4000 VP_PIDx Video Port Peripheral Identification Register 01C4 0004 01C4 4004 VP_PCRx Video Port Peripheral Control Register 01C4 01C4 Reserved 01C4 01C4 01C4 0020 01C4 4020 VP_PFUNCx Reserved Video Port Pin Function Register 01C4 0024 01C4 4024 VP_PDIRx Video Port Pin Direction Register 01C4 0028 01C4 4028 VP_PDINx Video Port Pin Data Input Register 01C4 002C 01C4 402C VP_PDOUTx Video Port Pin Data Output Register 01C4 0030 01C4 4030 VP_PDSETx Video Port Pin Data Set Register 01C4 0034 01C4 4034 VP_PDCLRx Video Port Pin Data Clear Register 01C4 0038 01C4 4038 VP_PIENx Video Port Pin Interrupt Enable Register 01C4 003C 01C4 403C VP_PIPOx Video Port Pin Interrupt Polarity Register 01C4 0040 01C4 4040 VP_PISTATx Video Port Pin Interrupt Status Register 01C4 0044 01C4 4044 VP_PICLRx Video Port Pin Interrupt Clear Register 01C4 00C0 01C4 40C0 VP_CTLx Video Port Control Register 01C4 00C4 01C4 40C4 VP_STATx Video Port Status Register 01C4 00C8 01C4 40C8 VP_IEx Video Port Interrupt Enable Register 01C4 00CC 01C4 40CC VP_ISx Video Port interrupt Status Register 01C4 0100 01C4 4100 VC_STATx Video Capture Channel A Status Register 01C4 0104 01C4 4104 VC_CTLx Video Capture Channel A Control Register 01C4 0108 01C4 4108 VC_ASTRTx Video Capture Channel A Field 1 Start Register 01C4 010C 01C4 410C VC_ASTOPx Video Capture Channel A Field 2 Stop Register 01C4 0110 01C4 4110 VC_ASTRTx Video Capture Channel A Field 2 Start Register 01C4 0114 01C4 4114 VC_ASTOPx Video Capture Channel A Field 1 Stop Register 01C4 0118 01C4 4118 VC_AVINTx Video Capture Channel A Vertical Interrupt Register 01C4 011C 01C4 411C VC_ATHRLDx Video Capture Channel A Threshold Register 01C4 0120 01C4 4120 VC_AEVTCTx Video Capture Channel A Event Count Register 01C4 0180 01C4 4180 TSI_CTLx 01C4 0184 01C4 4184 TSI_CLKINITLx TCI Clock Initialization LSB Register 01C4 0188 01C4 4188 TSI_CLKINITMx TCI Clock Initialization MSB Register 01C4 018C 01C4 418C TSI_STCLKLx TCI System Time Clock LSB Register 01C4 0190 01C4 4190 TSI_STCLKMx TCI System Time Clock MSB Register 01C4 0194 01C4 4194 TSI_STCMPLx TCI System Time Clock Compare LSB Register 01C4 0198 01C4 4198 TSI_STCMPMx TCI System Time Clock Compare MSB Register 01C4 019C 01C4 419C TSI_STMSKLx TCI System Time Clock Compare Mask LSB Register 01C4 01A0 01C4 41A0 TSI_STMSKMx TCI System Time Clock Compare Mask MSB Register 01C4 01A4 01C4 41A4 TSI_TICKSx 01C4 0200 01C4 4200 VD_STATx Video Display Status Register 01C4 0204 01C4 4204 VD_CTLx Video Display Control Register 01C4 0208 01C4 4208 VD_FRMSZx SPRS222 TCI Capture Control Register TCI System Time Clock Ticks Interrupt Register Video Display Frame Size Register June 2003 Peripheral Register Descriptions Table 1–25. Video Port 0 and 1 (VP0 and VP1) Control Registers (Continued) HEX ADDRESS RANGE VP0 VP1 [DM641 ONLY] ACRONYM DESCRIPTION 01C4 020C 01C4 420C VD_HBLNKx Video Display Horizontal Blanking Register 01C4 0210 01C4 4210 VD_VBLKS1x Video Display Field 1 Vertical Blanking Start Register 01C4 0214 01C4 4214 VD_VBLKE1x Video Display Field 1 Vertical Blanking End Register 01C4 0218 01C4 4218 VD_VBLKS2x Video Display Field 2 Vertical Blanking Start Register 01C4 021C 01C4 421C VD_VBLKE2x Video Display Field 2 Vertical Blanking End Register 01C4 0220 01C4 4220 VD_IMGOFF1x 01C4 0224 01C4 4224 VD_IMGSZ1x 01C4 0228 01C4 4228 VD_IMGOFF2x 01C4 022C 01C4 422C VD_IMGSZ2x 01C4 0230 01C4 4230 VD_FLDT1x Video Display Field 1 Timing Register 01C4 0234 01C4 4234 VD_FLDT2x Video Display Field 2 Timing Register Video Display Field 1 Image Offset Register Video Display Field 1 Image Size Register Video Display Field 2 Image Offset Register 01C4 0238 01C4 4238 VD_THRLDx Video Display Threshold Register 01C4 023C 01C4 423C VD_HSYNCx Video Display Horizontal Synchronization Register 01C4 0240 01C4 4240 VD_VSYNS1x Video Display Field 1 Vertical Synchronization Start Register 01C4 0244 01C4 4244 VD_VSYNE1x Video Display Field 1 Vertical Synchronization End Register 01C4 0248 01C4 4248 VD_VSYNS2x Video Display Field 2 Vertical Synchronization Start Register 01C4 024C 01C4 424C VD_VSYNE2x Video Display Field 2 Vertical Synchronization End Register 01C4 0250 01C4 4250 VD_RELOADx Video Display Counter Reload Register 01C4 0254 01C4 4254 VD_DISPEVTx Video Display Display Event Register 01C4 0258 01C4 4258 VD_CLIPx 01C4 025C 01C4 425C VD_DEFVALx 01C4 0260 01C4 4260 VD_VINTx Video Display Vertical Interrupt Register 01C4 0264 01C4 4264 VD_FBITx Video Display Field Bit Register 01C4 0268 01C4 4268 VD_VBIT1x Video Display Field 1Vertical Blanking Bit Register 01C4 026C 01C4 426C VD_VBIT2x Video Display Field 2Vertical Blanking Bit Register 7400 000 7800 0000 Y_RSCA 7400 0008 7800 0008 CB_SRCA CB FIFO Source Register A 7400 0010 7800 0010 CR_SRCA CR FIFO Source Register A 7400 0020 7800 0020 Y_DSTA Y FIFO Destination Register A 7400 0028 7800 0028 CB_DST CB FIFO Destination Register A 7400 0030 7800 0030 CR_DST CR FIFO Destination Register A June 2003 PRODUCT PREVIEW Video Display Field 2 Image Size Register Video Display Clipping Register Video Display Default Display Value Register Y FIFO Source Register A SPRS222 41 Peripheral Register Descriptions Table 1–26. McASP0 Control Registers PRODUCT PREVIEW HEX ADDRESS RANGE ACRONYM REGISTER NAME 01B4 C000 PID 01B4 C004 PWRDEMU Peripheral Identification register [Register value: 0x0010 0101] 01B4 C008 – Reserved 01B4 C00C – Reserved 01B4 C010 PFUNC Pin function register 01B4 C014 PDIR Pin direction register 01B4 C018 PDOUT Pin data out register 01B4 C01C PDIN/PDSET Power down and emulation management register Pin data in / data set register Read returns: PDIN Writes affect: PDSET 01B4 C020 PDCLR 01B4 C024 – 01B4 C040 – 01B4 C044 GBLCTL Global control register 01B4 C048 AMUTE Mute control register 01B4 C04C DLBCTL Digital Loop-back control register 01B4 C050 DITCTL DIT mode control register 01B4 C054 – 01B4 C05C – 01B4 C060 RGBLCTL 01B4 C064 RMASK 01B4 C068 RFMT 01B4 C06C AFSRCTL 01B4 C070 ACLKRCTL 01B4 C074 AHCLKRCTL 01B4 C078 RTDM 01B4 C07C RINTCTL Reserved Reserved Alias of GBLCTL containing only Receiver Reset bits, allows transmit to be reset independently from receive. Receiver format unit bit mask register Receive bit stream format register Receive frame sync control register Receive clock control register High-frequency receive clock control register Receive TDM slot 0–31 register Receiver interrupt control register 01B4 C080 RSTAT Status register – Receiver 01B4 C084 RSLOT Current receive TDM slot register 01B4 C088 RCLKCHK 01B4 C08C – 01B4 C09C – 01B4 C0A0 XGBLCTL 01B4 C0A4 XMASK 42 Pin data clear register 01B4 C0A8 XFMT 01B4 C0AC AFSXCTL 01B4 C0B0 ACLKXCTL 01B4 C0B4 AHCLKXCTL Receiver clock check control register Reserved Alias of GBLCTL containing only Transmitter Reset bits, allows transmit to be reset independently from receive. Transmit format unit bit mask register Transmit bit stream format register Transmit frame sync control register Transmit clock control register High-frequency Transmit clock control register 01B4 C0B8 XTDM Transmit TDM slot 0–31 register 01B4 C0BC XINTCTL Transmit interrupt control register 01B4 C0C0 XSTAT Status register – Transmitter 01B4 C0C4 XSLOT Current transmit TDM slot 01B4 C0C8 XCLKCHK Transmit clock check control register 01B4 C0CC XEVTCTL Transmitter DMA control register SPRS222 June 2003 Peripheral Register Descriptions Table 1–26. McASP0 Control Registers (Continued) HEX ADDRESS RANGE ACRONYM 01B4 C0D0 – 01B4 C0FC – REGISTER NAME 01B4 C100 DITCSRA0 Left (even TDM slot) channel status register file 01B4 C104 DITCSRA1 Left (even TDM slot) channel status register file 01B4 C108 DITCSRA2 Left (even TDM slot) channel status register file 01B4 C10C DITCSRA3 Left (even TDM slot) channel status register file 01B4 C110 DITCSRA4 Left (even TDM slot) channel status register file 01B4 C114 DITCSRA5 Left (even TDM slot) channel status register file 01B4 C118 DITCSRB0 Right (odd TDM slot) channel status register file 01B4 C11C DITCSRB1 Right (odd TDM slot) channel status register file 01B4 C120 DITCSRB2 Right (odd TDM slot) channel status register file 01B4 C124 DITCSRB3 Right (odd TDM slot) channel status register file 01B4 C128 DITCSRB4 Right (odd TDM slot) channel status register file 01B4 C12C DITCSRB5 Right (odd TDM slot) channel status register file 01B4 C130 DITUDRA0 Left (even TDM slot) user data register file 01B4 C134 DITUDRA1 Left (even TDM slot) user data register file 01B4 C138 DITUDRA2 Left (even TDM slot) user data register file 01B4 C13C DITUDRA3 Left (even TDM slot) user data register file 01B4 C140 DITUDRA4 Left (even TDM slot) user data register file 01B4 C144 DITUDRA5 Left (even TDM slot) user data register file 01B4 C148 DITUDRB0 Right (odd TDM slot) user data register file 01B4 C14C DITUDRB1 Right (odd TDM slot) user data register file 01B4 C150 DITUDRB2 Right (odd TDM slot) user data register file 01B4 C154 DITUDRB3 Right (odd TDM slot) user data register file 01B4 C158 DITUDRB4 Right (odd TDM slot) user data register file Right (odd TDM slot) user data register file 01B4 C15C DITUDRB5 01B4 C160 – 01B4 C17C – 01B4 C180 SRCTL0 Serializer 0 control register 01B4 C184 SRCTL1 Serializer 1 control register 01B4 C188 SRCTL2 Serializer 2 control register 01B4 C18C SRCTL3 Serializer 3 control register Reserved 01B4 C190 – 01B4 C1FC – 01B4 C200 XBUF0 Transmit Buffer for Serializer 0 01B4 C204 XBUF1 Transmit Buffer for Serializer 1 01B4 C208 XBUF2 Transmit Buffer for Serializer 2 Reserved Transmit Buffer for Serializer 3 01B4 C20C XBUF3 01B4 C210 – 01B4 C27C – 01B4 C280 RBUF0 Receive Buffer for Serializer 0 01B4 C284 RBUF1 Receive Buffer for Serializer 1 Reserved 01B4 C288 RBUF2 Receive Buffer for Serializer 2 01B4 C28C RBUF3 Receive Buffer for Serializer 3 01B4 C290 – 01B4 FFFF – June 2003 PRODUCT PREVIEW Reserved Reserved SPRS222 43 Peripheral Register Descriptions Table 1–27. McASP0 Data Registers HEX ADDRESS RANGE 3C00 0000 – 3C0F FFFF ACRONYM RBUF/XBUFx REGISTER NAME COMMENTS McASPx receive buffers or McASPx transmit buffers via the Peripheral Data Bus. (Used when RSEL or XSEL bits = 0 [these bits are located in the RFMT or XFMT registers, respectively].) PRODUCT PREVIEW Table 1–28. I2C0 Registers 44 HEX ADDRESS RANGE ACRONYM REGISTER NAME 01B4 0000 I2COAR0 I2C0 own address register 01B4 0004 I2CIER0 I2C0 interrupt enable register 01B4 0008 I2CSTR0 I2C0 interrupt status register 01B4 000C I2CCLKL0 I2C0 clock low-time divider register 01B4 0010 I2CCLKH0 I2C0 clock high-time divider register 01B4 0014 I2CCNT0 I2C0 data count register 01B4 0018 I2CDRR0 I2C0 data receive register 01B4 001C I2CSAR0 I2C0 slave address register 01B4 0020 I2CDXR0 I2C0 data transmit register 01B4 0024 I2CMDR0 I2C0 mode register 01B4 0028 I2CISRC0 I2C0 interrupt source register 01B4 002C – 01B4 0030 I2CPSC0 I2C0 prescaler register 01B4 0034 I2CPID10 I2C0 Peripheral Identification register 1 [Value: 0x0000 0101] 01B4 0038 I2CPID20 I2C0 Peripheral Identification register 2 [Value: 0x0000 0005] 01B4 003C – 01B4 3FFF – SPRS222 Reserved Reserved June 2003 EDMA Channel Synchronization Events 1.10 EDMA Channel Synchronization Events The C64x EDMA supports up to 64 EDMA channels which service peripheral devices and external memory. Table 1–29 lists the source of C64x EDMA synchronization events associated with each of the programmable EDMA channels. For the DM641/DM640 device, the association of an event to a channel is fixed; each of the EDMA channels has one specific event associated with it. These specific events are captured in the EDMA event registers (ERL, ERH) even if the events are disabled by the EDMA event enable registers (EERL, EERH). The priority of each event can be specified independently in the transfer parameters stored in the EDMA parameter RAM. For more detailed information on the EDMA module and how EDMA events are enabled, captured, processed, linked, chained, and cleared, etc., see the EDMA Controller chapter of the TMS320C6000 Peripherals Reference Guide (literature number SPRU190). Table 1–29. TMS320DM641/DM640 EDMA Channel Synchronization Events† EDMA CHANNEL EVENT NAME 0 DSP_INT 1 TINT0 Timer 0 interrupt 2 TINT1 Timer 1 interrupt EVENT DESCRIPTION 3 SD_INTA 4 GPINT4/EXT_INT4 GP0 event 4/External interrupt pin 4 5 GPINT5/EXT_INT5 GP0 event 5/External interrupt pin 5 6 GPINT6/EXT_INT6 GP0 event 6/External interrupt pin 6 7 GPINT7/EXT_INT7 GP0 event 7/External interrupt pin 7 8 GPINT0 GP0 event 0 9 GPINT1 GP0 event 1 10 GPINT2 GP0 event 2 11 GPINT3 GP0 event 3 12 XEVT0 McBSP0 transmit event 13 REVT0 McBSP0 receive event 14 XEVT1 McBSP1 transmit event 15 REVT1 McBSP1 receive event EMIFA SDRAM timer interrupt 16 VP0EVTYA VP0 Channel A Y event DMA request 17 VP0EVTUA VP0 Channel A Cb event DMA request 18 VP0EVTVA VP0 Channel A Cr event DMA request 19 TINT2 20–31 – Timer 2 interrupt None 32 AXEVTE0 McASP0 transmit even event 33 AXEVTO0 McASP0 transmit odd event 34 AXEVT0 35 AREVTE0 McASP0 receive even event 36 AREVTO0 McASP0 receive odd event 37 AREVT0 38 VP1EVTYB PRODUCT PREVIEW HPI-to-DSP interrupt [For DM641 Only; “None” for DM640] McASP0 transmit event McASP0 receive event VP1 Channel A Y event DMA request [For DM641 Only; “None” for DM640] 39 VP1EVTUB VP1 Channel A Cb event DMA request [For DM641 Only; “None” for DM640] † In addition to the events shown in this table, each of the 64 channels can also be synchronized with the transfer completion or alternate transfer completion events. For more detailed information on EDMA event-transfer chaining, see the EDMA Controller chapter of the TMS320C6000 Peripherals Reference Guide (literature number SPRU190). June 2003 SPRS222 45 EDMA Channel Synchronization Events PRODUCT PREVIEW Table 1–29. TMS320DM641/DM640 EDMA Channel Synchronization Events† (Continued) EDMA CHANNEL EVENT NAME EVENT DESCRIPTION 40 VP1EVTVB 41–43 – VP1 Channel A Cr event DMA request [For DM641 Only; “None” for DM640] 44 ICREVT0 I2C0 receive event I2C0 transmit event None 45 ICXEVT0 46–47 – 48 GPINT8 GP0 event 8 49 GPINT9 GP0 event 9 50 GPINT10 GP0 event 10 51 GPINT11 GP0 event 11 52 GPINT12 GP0 event 12 53 GPINT13 GP0 event 13 54 GPINT14 GP0 event 14 55 GPINT15 GP0 event 15 None 56–63 – None † In addition to the events shown in this table, each of the 64 channels can also be synchronized with the transfer completion or alternate transfer completion events. For more detailed information on EDMA event-transfer chaining, see the EDMA Controller chapter of the TMS320C6000 Peripherals Reference Guide (literature number SPRU190). 46 SPRS222 June 2003 Interrupt Sources and Interrupt Selector 1.11 Interrupt Sources and Interrupt Selector The C64x DSP core supports 16 prioritized interrupts, which are listed in Table 1–30. The highest-priority interrupt is INT_00 (dedicated to RESET) while the lowest-priority interrupt is INT_15. The first four interrupts (INT_00–INT_03) are non-maskable and fixed. The remaining interrupts (INT_04–INT_15) are maskable and default to the interrupt source specified in Table 1–30. The interrupt source for interrupts 4–15 can be programmed by modifying the selector value (binary value) in the corresponding fields of the Interrupt Selector Control registers: MUXH (address 0x019C0000) and MUXL (address 0x019C0004). Table 1–30. DM641/DM640 DSP Interrupts INTERRUPT SELECTOR CONTROL REGISTER SELECTOR VALUE (BINARY) INTERRUPT EVENT INT_00† INT_01† – – RESET – – NMI INT_02† INT_03† – – Reserved Reserved. Do not use. – – Reserved Reserved. Do not use. INT_04‡ INT_05‡ MUXL[4:0] 00100 GPINT4/EXT_INT4 GP0 interrupt 4/External interrupt pin 4 MUXL[9:5] 00101 GPINT5/EXT_INT5 GP0 interrupt 5/External interrupt pin 5 INT_06‡ INT_07‡ MUXL[14:10] 00110 GPINT6/EXT_INT6 GP0 interrupt 6/External interrupt pin 6 MUXL[20:16] 00111 GPINT7/EXT_INT7 GP0 interrupt 7/External interrupt pin 7 INT_08‡ INT_09‡ MUXL[25:21] 01000 EDMA_INT EDMA channel (0 through 63) interrupt MUXL[30:26] 01001 EMU_DTDMA INT_10‡ INT_11‡ MUXH[4:0] 00011 SD_INTA MUXH[9:5] 01010 EMU_RTDXRX EMU real-time data exchange (RTDX) receive INT_12‡ INT_13‡ MUXH[14:10] 01011 EMU_RTDXTX EMU RTDX transmit MUXH[20:16] 00000 DSP_INT INT_14‡ INT_15‡ MUXH[25:21] 00001 TINT0 Timer 0 interrupt MUXH[30:26] 00010 TINT1 Timer 1 interrupt – – 01100 XINT0 McBSP0 transmit interrupt – – 01101 RINT0 McBSP0 receive interrupt – – 01110 XINT1 McBSP1 transmit interrupt – – 01111 RINT1 McBSP1 receive interrupt – – 10000 GPINT0 – – 10001 Reserved Reserved. Do not use. – – 10010 Reserved Reserved. Do not use. – – 10011 TINT2 – – 10100 Reserved Reserved. Do not use. – – 10101 Reserved Reserved. Do not use. – – 10110 ICINT0 – – 10111 Reserved – – 11000 EMAC_MDIO_INT INTERRUPT SOURCE PRODUCT PREVIEW CPU INTERRUPT NUMBER EMU DTDMA EMIFA SDRAM timer interrupt HPI-to-DSP interrupt [DM641 Only] GP0 interrupt 0 Timer 2 interrupt I2C0 interrupt Reserved. Do not use. EMAC/MDIO interrupt † Interrupts INT_00 through INT_03 are non-maskable and fixed. ‡ Interrupts INT_04 through INT_15 are programmable by modifying the binary selector values in the Interrupt Selector Control registers fields. Table 1–30 shows the default interrupt sources for Interrupts INT_04 through INT_15. For more detailed information on interrupt sources and selection, see the Interrupt Selector and External Interrupts chapter of the TMS320C6000 Peripherals Reference Guide (literature number SPRU190). June 2003 SPRS222 47 Interrupt Sources and Interrupt Selector Table 1–30. DM641/DM640 DSP Interrupts (Continued) CPU INTERRUPT NUMBER INTERRUPT SELECTOR CONTROL REGISTER SELECTOR VALUE (BINARY) INTERRUPT EVENT – – 11001 VPINT0 VP0 interrupt – – 11010 VPINT1 VP1 interrupt [DM641 Only] – – 11011 Reserved – – 11100 AXINT0 McASP0 transmit interrupt – – 11101 ARINT0 McASP0 receive interrupt – – 11110 – 11111 Reserved INTERRUPT SOURCE Reserved. Do not use. PRODUCT PREVIEW Reserved. Do not use. † Interrupts INT_00 through INT_03 are non-maskable and fixed. ‡ Interrupts INT_04 through INT_15 are programmable by modifying the binary selector values in the Interrupt Selector Control registers fields. Table 1–30 shows the default interrupt sources for Interrupts INT_04 through INT_15. For more detailed information on interrupt sources and selection, see the Interrupt Selector and External Interrupts chapter of the TMS320C6000 Peripherals Reference Guide (literature number SPRU190). 48 SPRS222 June 2003 Signal Groups Description 1.12 Signal Groups Description CLKMODE1 CLKMODE0 PLLV TMS TDO TDI TCK TRST EMU0 EMU1 EMU2 EMU3 EMU4 EMU5 EMU6 EMU7 EMU8 EMU9 EMU10 EMU11 Reset and Interrupts Clock/PLL RESET NMI GP0[7]/EXT_INT7‡ GP0[6]/EXT_INT6‡ GP0[5]/EXT_INT5‡ GP0[4]/EXT_INT4‡ RSV RSV RSV Reserved RSV RSV RSV IEEE Standard 1149.1 (JTAG) Emulation Peripheral Control/Status PRODUCT PREVIEW CLKIN CLKOUT4/GP0[1]† CLKOUT6/GP0[2]† TOUT0/MAC_EN Control/Status GP0[7]/EXT_INT7‡ GP0[6]/EXT_INT6‡ GP0[5]/EXT_INT5‡ GP0[4]/EXT_INT4‡ GP0 (8-Bit) GP0[3] CLKOUT6/GP0[2]† CLKOUT4/GP0[1]† GP0[0] General-Purpose Input/Output 0 (GP0) Port † These pins are muxed with the GP0 pins and by default these signals function as clocks (CLKOUT4 or CLKOUT6). To use these muxed pins as GPIO signals, the appropriate GPIO register bits (GPxEN and GPxDIR) must be properly enabled and configured. For more details, see the Device Configurations section of this data sheet. ‡ These pins are GP0 pins that can also function as external interrupt sources (EXT_INT[7:4]). Default after reset is EXT_INTx or GPIO as input-only. Figure 1–5. CPU and Peripheral Signals June 2003 SPRS222 49 Signal Groups Description 32 Data AED[31:0] AECLKIN ACE3 ACE2 Memory Map Space Select ACE1 ACE0 20 AEA[22:3] ABE3 ABE2 ABE1 ABE0 External Memory I/F Control Address Byte Enables Bus Arbitration AECLKOUT1 AECLKOUT2 ASDCKE AARE/ASDCAS/ASADS/ASRE AAOE/ASDRAS/ASOE AAWE/ASDWE/ASWE AARDY ASOE3 APDT AHOLD AHOLDA ABUSREQ PRODUCT PREVIEW EMIFA (32-bit) Data VDAC VCXO Interpolated Control Port (VIC) 16 HD[15:0] HCNTL0 HCNTL1 Data HPI (Host-Port Interface) [DM641 only] Register Select Control HHWIL Half-Word Select HAS HR/W HCS HDS1 HDS2 HRDY HINT Figure 1–6. Peripheral Signals 50 SPRS222 June 2003 Signal Groups Description TOUT1/LENDIAN TINP1 TOUT0/MAC_EN TINP0 Timer 0 Timer 1 Timer 2 Timers SCL0 I2C0 SDA0 I2C0 DM641/DM640 McBSP0 Transmit VP0D[0]/CLKX0†‡ VP0D[1]/FSX0†‡ VP0D[2]/DX0†‡ Receive Receive VP0D[6]/CLKR0†‡ VP0D[5]/FSR0†‡ VP0D[4]/DR0†‡ Clock Clock VP0D[3]/CLKS0†‡ VP1D[0]/CLKX1†§ VP1D[1]/FSX1†§ VP1D[2]/DX1†§ Transmit VP1D[6]/CLKR1†§ VP1D[5]/FSR1†§ VP1D[4]/DR1†§ VP1D[3]/CLKS1†§ McBSPs (Multichannel Buffered Serial Ports) † For DM641, these McBSP1 and McBSP0 pins are muxed with the Video Port 1 (VP1) and Video Port 0 (VP0) peripherals, respectively. By default, these signals function as VP1 and VP0, respectively. For more details on these muxed pins, see the Device Configurations section of this data sheet. ‡ For DM640, these McBSP0 pins are muxed with the Video Port 0 (VP0) peripheral. By default, these signals function as VP0. For more details on these muxed pins, see the Device Configurations section of this data sheet. § The DM640 device does not support the VP1 peripheral; therefore, the McBSP1 peripheral pins are standalone perpheral functions, not muxed. Figure 1–6. Peripheral Signals (Continued) June 2003 SPRS222 51 PRODUCT PREVIEW McBSP1 Signal Groups Description EMAC MTXD0 MTXD1 MTXD2 MTXD3 Transmit MRXD0 MRXD1 MRXD2 MRXD3 Receive MDIO Input/Output MDIO MTXEN MRXER MRXDV MCOL MCRS PRODUCT PREVIEW MTCLK MRCLK Clock Error Detect and Control MDCLK Clocks Ethernet MAC (EMAC) and MDIO STCLK VP0CLK0 VP0CLK1 VP0CTL0 VP0CTL1 VP0CTL2 VP0D[0]/CLKX0 VP0D[1]/FSX0 VP0D[2]/DX0 VP0D[3]/CLKS0 Timing and Control Logic VP0D[4]/DR0 VP0D[5]/FSR0 VP0D[6]/CLKR0 VP0D[7] Capture/Display Buffer (2560 Bytes) Channel A† Video Port 0 (VP0) † Channel A supports: BT.656 (8-bit) and TSI (8-bit) capture pipeline modes and BT.656 (8-bit) display pipeline mode. Figure 1–6. Peripheral Signals (Continued) 52 SPRS222 June 2003 Signal Groups Description VP1D[0]/CLKX1 VP1D[1]/FSX1 VP1D[2]/DX1 VP1D[3]/CLKS1 Timing and Control Logic VP1D[4]/DR1 VP1D[5]/FSR1 VP1D[6]/CLKR1 VP1D[7] Capture/Display Buffer (2560 Bytes) PRODUCT PREVIEW STCLK‡ VP1CLK0 VP1CLK1 VP1CTL0 VP1CTL1 VP1CTL2 Channel A† Video Port 1 (VP1) [DM641 only] † Channel A supports: BT.656 (8-bit) and TSI (8-bit) capture pipeline modes and BT.656 (8-bit) display pipeline mode. ‡ For DM641, the same STCLK signal is used for both video ports (VP0 and VP1). Figure 1–6. Peripheral Signals (Continued) June 2003 SPRS222 53 Signal Groups Description (Transmit/Receive Data Pins) (Transmit/Receive Data Pins) 8-Serial Ports Flexible Partitioning Tx, Rx, OFF AXR0[0] AXR0[1] AXR0[2] AXR0[3] (Transmit Bit Clock) (Receive Bit Clock) ACLKR0 AHCLKR0 Receive Clock Generator Transmit Clock Generator PRODUCT PREVIEW (Receive Master Clock) AFSR0 (Receive Frame Sync or Left/Right Clock) ACLKX0 AHCLKX0 (Transmit Master Clock) Receive Clock Check Circuit Transmit Clock Check Circuit Receive Frame Sync Transmit Frame Sync Error Detect (see Note A ) Auto Mute Logic AFSX0 (Transmit Frame Sync or Left/Right Clock) AMUTE0 AMUTEIN0 McASP0 (Multichannel Audio Serial Port 0) NOTES: A. The McASPs’ Error Detect function detects underruns, overruns, early/late frame syncs, DMA errors, and external mute input. B. Bolded and italicized text within parentheses denotes the function of the pins in an audio system. Figure 1–6. Peripheral Signals (Continued) 54 SPRS222 June 2003 Device Configurations 2 Device Configurations On the DM641/DM640 device, bootmode and certain device configurations/peripheral selections are determined at device reset, while other device configurations/peripheral selections are software-configurable via the peripheral configurations register (PERCFG) [address location 0x01B3F000] after device reset. 2.1 Peripheral Selection at Device Reset On the DM641/DM640 devices there are NO peripherals sharing the same pins (internally muxed, yet mutually exclusive) that are controlled via external pins. • For proper DM641 device operation, the HD5 pin [Y1] at device reset must be pulled down via a 10-kΩ resistor. • For proper DM641/DM60 device operation, the reserved (RSV) [E2] pin at device reset must be pulled down via a 10-kΩ resistor. • EMAC and MDIO peripherals The MAC_EN pin is latched at reset. This pin determines specific peripheral selection, summarized in Table 2–1. Table 2–1. MAC_EN Peripheral Selection (EMAC and MDIO) PERIPHERAL SELECTION† June 2003 PERIPHERALS SELECTED MAC_EN Pin [C5] HPI Data (16-Bit) [DM641 Only] EMAC and MDIO 0 √ Disabled 1 √ √ SPRS222 55 PRODUCT PREVIEW However, for proper DM641/DM640 device operation; the following external pins must be configured correctly: Device Configurations 2.2 Device Configuration at Device Reset Table 2–2 describes the DM641/DM640 device configuration pins, which are set up via external pullup/pulldown resistors through the specified EMIFA address bus pins (AEA[22:19]) and the TOUT1/LENDIAN pin, all of which are latched during device reset. Table 2–2. DM641/DM640 Device Configuration Pins (TOUT1/LENDIAN, AEA[22:19], and HD5) CONFIGURATION PIN NO. TOUT1/LENDIAN B5 PRODUCT PREVIEW AEA[22:21] AEA[20:19] FUNCTIONAL DESCRIPTION Device Endian mode (LEND) 0 – System operates in Big Endian mode 1 – System operates in Little Endian mode (default) [U23, V24] Bootmode [1:0] – Boot mode (AEA[22:21]): 00 – No boot (default mode) 01 – HPI [DM641 only]; Reserved [For DM640 device] 10 – Reserved 11 – EMIFA boot [V25, V26] EMIFA input clock select Clock mode select for EMIFA (AECLKIN_SEL[1:0]) 00 – AECLKIN (default mode) 01 – CPU/4 Clock Rate 10 – CPU/6 Clock Rate 11 – Reserved Peripheral Selection TOUT0/MAC_EN 2.3 [C5] 1 – EMAC and MDIO enabled 0 – EMAC and MDIO disabled Peripheral Selection After Device Reset Video Ports, McBSP1, McBSP0, McASP0 and I2C0 The DM641/DM640 device has designated registers for peripheral configuration (PERCFG), device status (DEVSTAT), and JTAG identification (JTAGID). These registers are part of the Device Configuration module and are mapped to a 4K block memory starting at 0x01B3F000. The CPU accesses these registers via the CFGBUS. The peripheral configuration register (PERCFG), allows the user to control the peripheral selection of the Video Ports (VP0 and VP1 [DM641 only]) McBSP0, McBSP1, McASP0, and I2C0 peripherals. For more detailed information on the PERCFG register control bits, see Figure 2–1 and Table 2–3. 56 SPRS222 June 2003 Device Configurations 24 31 Reserved R-0 16 23 Reserved R-0 8 15 Reserved R-0 7 6 5 4 3 2 1 0 Reserved Reserved VP1EN† VP0EN I2C0EN MCBSP1EN MCBSP0EN MCASP0EN R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 Legend: R = Read only; R/W = Read/Write; -n = value after reset † The DM640 device does not support the VP1 peripheral; therefore, this bit is Reserved. PRODUCT PREVIEW Figure 2–1. Peripheral Configuration Register (PERCFG) [Address Location: 0x01B3F000 – 0x01B3F003] Table 2–3. Peripheral Configuration (PERCFG) Register Selection Bit Descriptions BIT NAME 31:6 Reserved 5 VP1EN DESCRIPTION Reserved. Read-only, writes have no effect. VP1 Enable bit [DM641 only]. Determines whether the VP1 peripheral is enabled or disabled. 0 = VP1 is disabled, and the module is powered down (default). (This feature allows power savings by disabling the peripheral when not in use.) 1 = VP1 is enabled. The DM640 device does not support the VP1 peripheral; therefore, this bit is Reserved. 4 3 2 1 0 June 2003 VP0EN VP0 Enable bit. Determines whether the VP0 peripheral is enabled or disabled. 0 = VP0 is disabled, and the module is powered down (default). (This feature allows power savings by disabling the peripheral when not in use.) 1 = VP0 is enabled. I2C0EN Inter-integrated circuit 0 (I2C0) enable bit. Selects whether I2C0 peripheral is enabled or disabled (default). 0 = I2C0 is disabled, and the module is powered down (default). 1 = I2C0 is enabled. MCBSP1EN Video Port 1 (VP1) lower data pins vs. McBSP1 enable bit. Selects whether VP1 peripheral lower-data pins or the McBSP1 peripheral is enabled. 0 = VP1 lower-data pins are enabled and function (if VP1EN=1), McBSP1 is disabled; the remaining VP1 upper-data pins are dependent on the MCASP0EN bit and the VP1EN bit settings. 1 = McBSP1 is enabled, VP1 lower-data pin functions are disabled (default). MCBSP0EN Video Port 0 (VP0) lower data pins vs. McBSP0 enable bit. Selects whether VP0 peripheral lower-data pins or the McBSP1 peripheral is enabled. 0 = VP0 lower-data pins are enabled and function (if VP0EN=1), McBSP0 is disabled; the remaining VP0 upper-data pins are dependent on the MCASP0EN bit and the VP1EN bit settings. 1 = McBSP0 is enabled, VP0 lower-data pin functions are disabled (default). MCASP0EN McASP0 select bit. Selects whether the McASP0 peripheral or the VP0 and VP1 upper-data pins are enabled. 0 = Reserved [default]. 1 = McASP0 is enabled. For proper DM641/DM640 device operation, the pin must be set to a “1”. SPRS222 57 Device Configurations 2.3.1 Peripheral Configuration Lock By default, the McASP0, VP0, VP1[DM641 only], and I2C peripherals are disabled on power up. In order to use these peripherals on the DM641/DM640 device, the peripheral must first be enabled in the Peripheral Configuration register (PERCFG). Software muxed pins should not be programmed to switch functionalities during run-time. Care should also be taken to ensure that no accesses are being performed before disabling the peripherals. To help minimize power consumption in the DM641/DM640 device, unused peripherals may be disabled. Figure 2–2 shows the flow needed to enable (or disable) a given peripheral on the DM641/DM640 devices. PRODUCT PREVIEW Unlock the PERCFG Register Using the PCFGLOCK Register Write to PERCFG Register to Enable/Disable Peripherals Read from PERCFG Register Wait 128 CPU Cycles Before Accessing Enabled Peripherals Figure 2–2. Peripheral Enable/Disable Flow Diagram A 32-bit key (value = 0x10C0010C) must be written to the Peripheral Configuration Lock register (PCFGLOCK) in order to unlock access to the PERCFG register. Reading the PCFGLOCK register determines whether the PERCFG register is currently locked (LOCKSTAT bit = 1) or unlocked (LOCKSTAT bit = 0), see Figure 2–3. A peripheral can only be enabled when the PERCFG register is “unlocked” (LOCKSTAT bit = 0). 58 SPRS222 June 2003 Device Configurations Read Accesses 31 1 0 Reserved LOCKSTAT R-0 R-1 Write Accesses 31 0 LOCK W-0 Legend: R = Read only; R/W = Read/Write; -n = value after reset Figure 2–3. PCFGLOCK Register Diagram [Address Location: 0x01B3 F018] – Read/Write Accesses Table 2–4. PCFGLOCK Register Selection Bit Descriptions – Read Accesses NAME Reserved 0 LOCKSTAT DESCRIPTION PRODUCT PREVIEW BIT 31:1 Reserved. Read-only, writes have no effect. Lock status bit. Determines whether the PERCFG register is locked or unlocked. 0 = Unlocked, read accesses to the PERCFG register allowed. 1 = Locked, write accesses to the PERCFG register do not modify the register state [default]. Reads are unaffected by Lock Status. Table 2–5. PCFGLOCK Register Selection Bit Descriptions – Write Accesses BIT NAME 31:0 LOCK DESCRIPTION Lock bits. 0x10C0010C = Unlocks PERCFG register accesses. Any write to the PERCFG register will automatically relock the register. In order to avoid the unnecessary overhead of multiple unlock/enable sequences, all peripherals should be enabled with a single write to the PERCFG register with the necessary enable bits set. Prior to waiting 128 CPU cycles, the PERCFG register should be read. There is no direct correlation between the CPU issuing a write to the PERCFG register and the write actually occurring. Reading the PERCFG register after the write is issued forces the CPU to wait for the write to the PERCFG register to occur. Once a peripheral is enabled, the DSP (or other peripherals such as the McBSP) must wait a minimum of 128 CPU cycles before accessing the enabled peripheral. The user must ensure that no accesses are performed to a peripheral while it is disabled. June 2003 SPRS222 59 Device Configurations 2.3.2 Device Status Register Description The device status register depicts the status of the device peripheral selection. For the actual register bit names and their associated bit field descriptions, see Figure 2–4 and Table 2–6. 31 24 Reserved R-0 16 23 Reserved R-0 PRODUCT PREVIEW 15 11 10 9 8 Reserved MAC_EN Reserved Reserved Reserved R-0 R-x R-0 R-x R-0 14 13 12 7 6 5 4 3 2 1 0 Reserved CLKMODE1 CLKMODE0 LENDIAN BOOTMODE1 BOOTMODE0 AECLKINSEL1 AECLKINSEL0 R-x R-x R-x R-x R-x R-x R-x R-x Legend: R = Read only; R/W = Read/Write; -n = value after reset Figure 2–4. Device Status Register (DEVSTAT) Description – 0x01B3 F004 Table 2–6. Device Status (DEVSTAT) Register Selection Bit Descriptions BIT NAME 31:12 Reserved Reserved. Read-only, writes have no effect. 11 MAC_EN EMAC enable bit. Shows the status of whether EMAC peripheral is enabled or disabled (default). 0 = EMAC is disabled, and the module is powered down (default). 1 = EMAC is enabled. 10:7 Reserved Reserved. Read-only, writes have no effect. 60 6 CLKMODE1 5 CLKMODE0 4 LENDIAN 3 BOOTMODE1 2 BOOTMODE0 SPRS222 DESCRIPTION Clock mode select bits Shows the status of whether the CPU clock frequency equals the input clock frequency X1 (Bypass), x6, or x12. Clock mode select for CPU clock frequency (CLKMODE[1:0]) 00 – Bypass (x1) (default mode) 01 – x6 10 – x12 11 – Reserved For more details on the CLKMODE pins and the PLL multiply factors, see the Clock PLL section of this data sheet. Device Endian mode (LEND) Shows the status of whether the system is operating in Big Endian mode or Little Endian mode (default). 0 – System is operating in Big Endian mode 1 – System is operating in Little Endian mode (default) Bootmode configuration bits Shows the status of what device bootmode configuration is operational. Bootmode [1:0] 00 – No boot (default mode) 01 – HPI [DM641 only]; Reserved [For DM640 device] 10 – Reserved 11 – EMIFA boot June 2003 Device Configurations Table 2–6. Device Status (DEVSTAT) Register Selection Bit Descriptions (Continued) BIT NAME 1 AECLKINSEL1 0 AECLKINSEL0 DESCRIPTION EMIFA input clock select Shows the status of what clock mode is enabled or disabled for the EMIF. Clock mode select for EMIFA (AECLKIN_SEL[1:0]) 00 – AECLKIN (default mode) 01 – CPU/4 Clock Rate 10 – CPU/6 Clock Rate 11 – Reserved 2.3.3 JTAG ID Register Description 31–28 27–12 11–1 0 VARIANT (4-Bit) PART NUMBER (16-Bit) MANUFACTURER (11-Bit) LSB R-0000 R-0000 0000 0111 1001 R-0000 0010 111 R-1 PRODUCT PREVIEW The JTAG ID register is a read-only register that identifies to the customer the JTAG/Device ID. For the DM641/DM640 device, the JTAG ID register resides at address location 0x01B3 F004. The register hex value for the DM641/DM640 device is: 0x0007 902F. For the actual register bit names and their associated bit field descriptions, see Figure 2–5 and Table 2–7. Legend: R = Read only; -n = value after reset Figure 2–5. JTAG ID Register Description – TMS320DM641/DM640 Register Value – 0x0007 902F Table 2–7. JTAG ID Register Selection Bit Descriptions BIT NAME 31:28 VARIANT 27:12 PART NUMBER 11–1 MANUFACTURER 0 LSB 2.4 DESCRIPTION Variant (4-Bit) value. DM641/DM640 value: 0000. Part Number (16-Bit) value. DM641/DM640 value: 0000 0000 0111 1001. Manufacturer (11-Bit) value. DM641/DM640 value: 0000 0010 111. LSB. This bit is read as a “1” for DM641/DM640. Multiplexed Pins Multiplexed pins are pins that are shared by more than one peripheral and are internally multiplexed. Some of these pins are configured by software, and the others are configured by external pullup/pulldown resistors only at reset. Those muxed pins that are configured by software should not be programmed to switch functionalities during run-time. Those muxed pins that are configured by external pullup/pulldown resistors are mutually exclusive; only one peripheral has primary control of the function of these pins after reset. Table 2–8 identifies the multiplexed pins on the DM641/DM640 device; shows the default (primary) function and the default settings after reset; and describes the pins, registers, etc. necessary to configure specific multiplexed functions. June 2003 SPRS222 61 Configuration Examples 2.5 Debugging Considerations It is recommended that external connections be provided to device configuration pins, including AEA[22:19] and TOUT0/MAC_EN. Although internal pullup/pulldown resistors exist on these pins, providing external connectivity adds convenience to the user in debugging and flexibility in switching operating modes. Internal pullup/pulldown resistors also exist on the non-configuration pins on the AEA bus (AEA[18:0]). Do not oppose the internal pullup/pulldown resistors on these non-configuration pins with external pullup/pulldown resistors. If an external controller provides signals to these non-configuration pins, these signals must be driven to the default state of the pins at reset, or not be driven at all. For the internal pullup/pulldown resistors for all device pins, see the terminal functions table. Table 2–8. DM641/DM640 Device Multiplexed Pins MULTIPLEXED PINS PRODUCT PREVIEW NAME NO. DEFAULT FUNCTION DEFAULT SETTING CLKOUT4/GP0[1] D6 CLKOUT4 GP1EN = 0 (disabled) CLKOUT6/GP0[2] C6 CLKOUT6 GP2EN = 0 (disabled) VP1D[6]/CLKR1 AD8 VP1D[5]/FSR1 AC7 VP1D[4]/DR1 AD7 VP1D[3]/CLKS1 AE7 VP1D[2]/DX1 AC6 VP1D[1]/FSX1 AD6 VP1D[0]/CLKX1 AE6 VP0D[6]/CLKR0 AE15 VP0D[5]/FSR0 AB16 VP0D[4]/DR0 AC16 VP0D[3]/CLKS0 AD16 VP0D[2]/DX0 AE16 VP0D[1]/FSX0 AF16 VP0D[0]/CLKX0 AF17 2.6 McBSP1 functions VP1EN bit = 0 (disabled) MCBSP1EN bit = 1 (enabled) None VP0EN bit = 0 (disabled) MCBSP0EN bit = 1 (enabled) DESCRIPTION These pins are software-configurable. To use these pins as GPIO pins, the GPxEN bits in the GPIO Enable Register and the GPxDIR bits in the GPIO Direction Register must be properly configured. GPxEN = 1: GPx pin enabled GPxDIR = 0: GPx pin is an input GPxDIR = 1: GPx pin is an output Muxed on the DM641 device only [The DM640 device does not support the VP1 peripheral; therefore, the McBSP1 peripheral pins are standalone peripheral functions, not muxed.] By default, the McBSP1 peripheral, function is enabled upon reset (MCBSP1EN bit = 1). To enable the Video Port 1 data pins, the VP1EN bit in the PERCFG register must be set to a 1. By default, the McBSP0 peripheral function is enabled upon reset (MCBSP0EN bit = 1). To enable the Video Port 0 data pins, the VP0EN bit in the PERCFG register must be set to a 1. Configuration Examples Figure 2–6 through Figure 2–9 illustrate some examples of peripheral selections that are configurable on the DM641 and DM640 devices. 62 SPRS222 June 2003 Configuration Examples 32 AED[31:0] EMIFA HD[15:0] 16 HPI (16-Bit) HRDY, HINT HCNTL0, HCNTL1, HHWIL, HAS, HR/W, HCS, HDS1, HDS2 Clock and System AECLKIN, AARDY, AHOLD AEA[22:3], ACE[3:0], ABE[3:0], AECLKOUT1, AECLKOUT2, ASDCKE, ASOE3, APDT, AHOLDA, ABUSREQ, AARE/ASDCAS/ASADS/ASRE, AAOE/ASDRAS/ASOE, AAWE/ASDWE/ASWE CLKIN, CLKMODE0, CLKMODE1 MTXD[3:0], MTXEN EMAC TIMER2 MDIO TIMER1 MRXD[3:0], MRXER, MRXDV, MCOL, MCRS, MTCLK, MRCLK CLKOUT4, CLKOUT6, PLLV TINP1 MDIO, MDCLK STCLK† VP0CLK0 VP0CLK1, VP0CTL[2:0], VP0D[7:0] AHCLKX0, AFSX0, ACLKX0, AMUTE0, AMUTEIN0, AHCLKR0, AFSR0, ACLKR0 PRODUCT PREVIEW TOUT1/LENDIAN TINP0 VP0 (8-Bit) TIMER0 McBSP0 GP0 and EXT_INT TOUT0/MAC_EN McASP0 Control GP0[3:0] GP0[7:4] SCL0 I2C0 SDA0 McASP0 Data AXR0[3:0] McBSP1 VIC VDAC STCLK† VP1 (8-Bit) VP1CLK0 VP1CLK1, VP1CTL[2:0], VP1D[7:0] Shading denotes a peripheral module not available for this configuration. † STCLK supports both video ports (VP1 and VP0). PERCFG Register Value: Extenal Pins: 0x0000 0039 TOUT0/MAC_EN = 1 Figure 2–6. Configuration Example A for DM641 (2 8-Bit Video Ports + 1 McASP0 + VIC + I2C0 + EMIF) [TBD Application] June 2003 SPRS222 63 Configuration Examples 32 AED[31:0] EMIFA HD[15:0] 16 HPI (16-Bit) HRDY, HINT HCNTL0, HCNTL1, HHWIL, HAS, HR/W, HCS, HDS1, HDS2 Clock and System AECLKIN, AARDY, AHOLD AEA[22:3], ACE[3:0], ABE[3:0], AECLKOUT1, AECLKOUT2, ASDCKE, ASOE3, APDT, AHOLDA, ABUSREQ, AARE/ASDCAS/ASADS/ASRE, AAOE/ASDRAS/ASOE, AAWE/ASDWE/ASWE CLKIN, CLKMODE0, CLKMODE1 MTXD[3:0], MTXEN EMAC TIMER2 MDIO TIMER1 MRXD[3:0], MRXER, MRXDV, MCOL, MCRS, MTCLK, MRCLK CLKOUT4, CLKOUT6, PLLV TINP1 MDIO, MDCLK PRODUCT PREVIEW TOUT1/LENDIAN CLKR0, FSR0, DR0, CLKS0, DX0, FSX0, CLKX0 AHCLKX0, AFSX0, ACLKX0, AMUTE0, AMUTEIN0, AHCLKR0, AFSR0, ACLKR0 AXR0[3:0] TINP0 VP0 (8-Bit) TIMER0 McBSP0 GP0 and EXT_INT TOUT0/MAC_EN McASP0 Control GP0[3:0] GP0[7:4] SCL0 I2C0 SDA0 McASP0 Data CLKR1, FSR1, DR1, CLKS1, DX1, FSX1, CLKX1 McBSP1 VIC VDAC VP1 (8-Bit) Shading denotes a peripheral module not available for this configuration. PERCFG Register Value: Extenal Pins: 0x0000 000F TOUT0/MAC_EN = 1 Figure 2–7. Configuration Example B for DM641 (1 McASP0 + 2 McBSPs + VIC + I2C0 + EMIF) [TBD Application] 64 SPRS222 June 2003 Configuration Examples 32 AED[31:0] EMIFA Clock and System AECLKIN, AARDY, AHOLD AEA[22:3], ACE[3:0], ABE[3:0], AECLKOUT1, AECLKOUT2, ASDCKE, ASOE3, APDT, AHOLDA, ABUSREQ, AARE/ASDCAS/ASADS/ASRE, AAOE/ASDRAS/ASOE, AAWE/ASDWE/ASWE CLKIN, CLKMODE0, CLKMODE1 MTXD[3:0], MTXEN EMAC TIMER2 MDIO TIMER1 MRXD[3:0], MRXER, MRXDV, MCOL, MCRS, MTCLK, MRCLK CLKOUT4, CLKOUT6, PLLV TINP1 MDIO, MDCLK STCLK VP0CLK0 VP0CLK1, VP0CTL[2:0], VP0D[7:0] AHCLKX0, AFSX0, ACLKX0, AMUTE0, AMUTEIN0, AHCLKR0, AFSR0, ACLKR0 PRODUCT PREVIEW TOUT1/LENDIAN TINP0 VP0 (8-Bit) TIMER0 McBSP0 GP0 and EXT_INT TOUT0/MAC_EN McASP0 Control GP0[3:0] GP0[7:4] SCL0 I2C0 SDA0 McASP0 Data AXR0[3:0] McBSP1 VIC VDAC Shading denotes a peripheral module not available for this configuration. PERCFG Register Value: Extenal Pins: 0x0000 0019 TOUT0/MAC_EN = 1 Figure 2–8. Configuration Example A for DM640 (1 8-Bit Video Port + 1 McASP0 + VIC + I2C0 + EMIF) [TBD Application] June 2003 SPRS222 65 Configuration Examples 32 AED[31:0] EMIFA Clock and System AECLKIN, AARDY, AHOLD AEA[22:3], ACE[3:0], ABE[3:0], AECLKOUT1, AECLKOUT2, ASDCKE, ASOE3, APDT, AHOLDA, ABUSREQ, AARE/ASDCAS/ASADS/ASRE, AAOE/ASDRAS/ASOE, AAWE/ASDWE/ASWE CLKIN, CLKMODE0, CLKMODE1 MTXD[3:0], MTXEN EMAC TIMER2 MDIO TIMER1 MRXD[3:0], MRXER, MRXDV, MCOL, MCRS, MTCLK, MRCLK CLKOUT4, CLKOUT6, PLLV TINP1 MDIO, MDCLK PRODUCT PREVIEW TOUT1/LENDIAN CLKR0, FSR0, DR0, CLKS0, DX0, FSX0, CLKX0 AHCLKX0, AFSX0, ACLKX0, AMUTE0, AMUTEIN0, AHCLKR0, AFSR0, ACLKR0 AXR0[3:0] TINP0 VP0 (8-Bit) TIMER0 McBSP0 GP0 and EXT_INT TOUT0/MAC_EN McASP0 Control GP0[3:0] GP0[7:4] SCL0 I2C0 SDA0 McASP0 Data CLKR1, FSR1, DR1, CLKS1, DX1, FSX1, CLKX1 McBSP1 VIC VDAC Shading denotes a peripheral module not available for this configuration. PERCFG Register Value: Extenal Pins: 0x0000 000F TOUT0/MAC_EN = 1 Figure 2–9. Configuration Example B for DM640 (1 McASP0 + 2 McBSPs + VIC + I2C0 + EMIF) [TBD Application] 66 SPRS222 June 2003 Terminal Functions 2.7 Terminal Functions PRODUCT PREVIEW The terminal functions table (Table 2–9) identifies the external signal names, the associated pin (ball) numbers along with the mechanical package designator, the pin type (I, O/Z, or I/O/Z), whether the pin has any internal pullup/pulldown resistors and a functional pin description. For more detailed information on device configuration, peripheral selection, multiplexed/shared pins, and debugging considerations, see the Device Configurations section of this data sheet. June 2003 SPRS222 67 Terminal Functions Table 2–9. Terminal Functions NAME SIGNAL DM641 DM640 TYPE† IPD/ IPU‡ DESCRIPTION CLOCK/PLL CONFIGURATION CLKIN AC2 AC2 I IPD Clock Input. This clock is the input to the on-chip PLL. CLKOUT4/GP0[1]§ D6 D6 I/O/Z IPD Clock output at 1/4 of the device speed (O/Z) [default] or this pin can be programmed as a GP0 1 pin (I/O/Z). CLKOUT6/GP0[2]§ C6 C6 I/O/Z IPD Clock output at 1/6 of the device speed (O/Z) [default] or this pin can be programmed as a GP0 2 pin (I/O/Z). CLKMODE1 AE4 AE4 I IPD CLKMODE0 AA2 AA2 I IPD PLLV¶ V6 V6 A# TMS E15 E15 I IPU JTAG test-port mode select TDO B18 B18 O/Z IPU JTAG test-port data out TDI A18 A18 I IPU JTAG test-port data in TCK A16 A16 I IPU JTAG test-port clock TRST D14 D14 I IPD JTAG test-port reset. For IEEE 1149.1 JTAG compatibility, see the IEEE 1149.1 JTAG compatibility statement portion of this data sheet. EMU11 D17 D17 I/O/Z IPU Emulation pin 11. Reserved for future use, leave unconnected. EMU10 C17 C17 I/O/Z IPU Emulation pin 10. Reserved for future use, leave unconnected. EMU9 B17 B17 I/O/Z IPU Emulation pin 9. Reserved for future use, leave unconnected. EMU8 D16 D16 I/O/Z IPU Emulation pin 8. Reserved for future use, leave unconnected. EMU7 A17 A17 I/O/Z IPU Emulation pin 7. Reserved for future use, leave unconnected. EMU6 C16 C16 I/O/Z IPU Emulation pin 6. Reserved for future use, leave unconnected. EMU5 B16 B16 I/O/Z IPU Emulation pin 5. Reserved for future use, leave unconnected. EMU4 D15 D15 I/O/Z IPU Emulation pin 4. Reserved for future use, leave unconnected. EMU3 C15 C15 I/O/Z IPU Emulation pin 3. Reserved for future use, leave unconnected. EMU2 B15 B15 I/O/Z IPU EMU1 C14 C14 I/O/Z IPU Emulation pin 2. Reserved for future use, leave unconnected. Emulation pin 1|| Clock mode select • Selects whether the CPU clock frequency = input clock frequency x1 (Bypass), x6, or x12. For more details on the CLKMODE pins and the PLL multiply factors, see the Clock PLL section of this data sheet. PLL voltage supply PRODUCT PREVIEW JTAG EMULATION EMU0 A15 A15 I/O/Z IPU Emulation pin 0|| † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground ‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-kΩ resistor should be used.) § These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet. ¶ PLLV is not part of external voltage supply. See the Clock PLL section for information on how to connect this pin. # A = Analog signal (PLL Filter) || The EMU0 and EMU1 pins are internally pulled up with 30-kΩ resistors; therefore, for emulation and normal operation, no external pullup/pulldown resistors are necessary. However, for boundary scan operation, pull down the EMU1 and EMU0 pins with a dedicated 1-kΩ resistor. 68 SPRS222 June 2003 Terminal Functions Table 2–9. Terminal Functions NAME SIGNAL DM641 DM640 TYPE† IPD/ IPU‡ DESCRIPTION RESETS, INTERRUPTS, AND GENERAL-PURPOSE INPUT/OUTPUTS P4 P4 I NMI B4 B4 I IPD Device reset Nonmaskable interrupt, edge-driven (rising edge) GP0[7]/EXT_INT7 E1 E1 I/O/Z IPU GP0[6]/EXT_INT6 F2 F2 I/O/Z IPU GP0[5]/EXT_INT5 F3 F3 I/O/Z IPU GP0[4]/EXT_INT4 F4 F4 I/O/Z IPU General-purpose input/output (GPIO) pins (I/O/Z) or external interrupts (input only). The default after reset setting is GPIO enabled as input-only. • When these pins function as External Interrupts [by selecting the corresponding interrupt enable register bit (IER.[7:4])], they are edge-driven and the polarity can be independently selected via the External Interrupt Polarity Register bits (EXTPOL.[3:0]). GP0[3] L5 L5 I/O/Z IPD GP0 3 pin (I/O/Z). GP0[0] M5 M5 I/O/Z IPD GP0 0 pin (I/O/Z) [default] The general-purpose 0 pin (GP0[0]) (I/O/Z) can be programmed as GPIO 0 (input only) [default] or as GP0[0] (output only) pin or output as a general-purpose interrupt (GP0INT) signal (output only). This pin must remain low during device reset. CLKOUT6/ GP0[2]§ C6 C6 I/O/Z IPD Clock output at 1/6 of the device speed (O/Z) [default] or this pin can be programmed as a GP0 2 pin (I/O/Z). CLKOUT4/ GP0[1]§ D6 D6 I/O/Z IPD Clock output at 1/4 of the device speed (O/Z) [default] or this pin can be programmed as a GP0 1 pin (I/O/Z). † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground ‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-kΩ resistor should be used.) § These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet. June 2003 SPRS222 69 PRODUCT PREVIEW RESET Terminal Functions Table 2–9. Terminal Functions (Continued) NAME SIGNAL DM641 DM640 TYPE† IPD/ IPU‡ DESCRIPTION PRODUCT PREVIEW HOST-PORT INTERFACE (HPI) [DM641 ONLY] HINT N4 — I/O/Z Host interrupt from DSP to host (O) [default] HCNTL1 P1 — I/O/Z Host control – selects between control, address, or data registers (I) [default] HCNTL0 R3 — I/O/Z Host control – selects between control, address, or data registers (I) [default] HHWIL N3 — I/O/Z Host half-word select – first or second half-word (not necessarily high or low order) [For HPI16 bus width selection only] (I) [default] HR/W M1 — I/O/Z Host read or write select (I) [default] HAS P3 — I/O/Z Host address strobe (I) [default] HCS R1 — I/O/Z Host chip select (I) [default] HDS1 R2 — I/O/Z Host data strobe 1 (I) [default] HDS2 T2 — I/O/Z Host data strobe 2 (I) [default] HRDY N1 — I/O/Z Host ready from DSP to host (O) [default] HD15 T3 — HD14 U1 — HD13 U3 — HD12 U2 — HD11 U4 — HD10 V1 — HD9 V3 — HD8 V2 — HD7 W2 — HD6/ W4 — HD5 Y1 — HD4 W3 — HD3 Y2 — HD2 Y4 — HD1 AA1 — HD0 Y3 — Host-port data (I/O/Z) [DM641 Only] As HPI data bus • Used for transfer of data, address, and control I/O/Z For proper DM641 device operation, the HD5 pin at device reset must be pulldown via a 10-kΩ resistor. EMIFA (32-BIT) – CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY ACE3 L26 L26 O/Z IPU ACE2 K23 K23 O/Z IPU ACE1 K24 K24 O/Z IPU ACE0 K25 K25 O/Z IPU ABE3 M25 M25 O/Z IPU ABE2 M26 M26 O/Z IPU ABE1 L23 L23 O/Z IPU ABE0 L24 L24 O/Z IPU APDT M22 M22 O/Z IPU EMIFA memory space enables • Enabled by bits 28 through 31 of the word address • Only one pin is asserted during any external data access EMIFA byte-enable control • Decoded from the low-order address bits. The number of address bits or byte enables used depends on the width of external memory. • Byte-write enables for most types of memory • Can be directly connected to SDRAM read and write mask signal (SDQM) EMIFA peripheral data transfer, allows direct transfer between external peripherals † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground ‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-kΩ resistor should be used.) § These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet. 70 SPRS222 June 2003 Terminal Functions Table 2–9. Terminal Functions (Continued) NAME SIGNAL DM641 DM640 TYPE† IPD/ IPU‡ DESCRIPTION EMIFA (32-BIT) – BUS ARBITRATION AHOLDA N22 N22 O IPU EMIFA hold-request-acknowledge to the host AHOLD W24 W24 I IPU EMIFA hold request from the host ABUSREQ P22 P22 O IPU EMIFA bus request output AECLKIN H25 H25 I IPD EMIFA external input clock. The EMIFA input clock (AECLKIN, CPU/4 clock, or CPU/6 clock) is selected at reset via the pullup/pulldown resistors on the AEA[20:19] pins. AECLKIN is the default for the EMIFA input clock. AECLKOUT2 J23 J23 O/Z IPD EMIFA output clock 2. Programmable to be EMIFA input clock (AECLKIN, CPU/4 clock, or CPU/6 clock) frequency divided-by-1, -2, or -4. AECLKOUT1 J26 J26 O/Z IPD EMIFA output clock 1 [at EMIFA input clock (AECLKIN, CPU/4 clock, or CPU/6 clock) frequency]. AARE/ ASDCAS/ ASADS/ASRE J25 J25 O/Z IPU EMIFA asynchronous memory read-enable/SDRAM column-address strobe/programmable synchronous interface-address strobe or read-enable • For programmable synchronous interface, the RENEN field in the CE Space Secondary Control Register (CExSEC) selects between ASADS and ASRE: If RENEN = 0, then the ASADS/ASRE signal functions as the ASADS signal. If RENEN = 1, then the ASADS/ASRE signal functions as the ASRE signal. AAOE/ ASDRAS/ ASOE J24 J24 O/Z IPU EMIFA asynchronous memory output-enable/SDRAM strobe/programmable synchronous interface output-enable AAWE/ ASDWE/ ASWE K26 K26 O/Z IPU EMIFA asynchronous memory write-enable/SDRAM write-enable/programmable synchronous interface write-enable ASDCKE L25 L25 O/Z IPU EMIFA SDRAM clock-enable (used for self-refresh mode). • If SDRAM is not in system, ASDCKE can be used as a general-purpose output. ASOE3 R22 R22 O/Z IPU EMIFA synchronous memory output-enable for ACE3 (for glueless FIFO interface) row-address AARDY L22 L22 I IPU Asynchronous memory ready input † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground ‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-kΩ resistor should be used.) § These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet. June 2003 SPRS222 71 PRODUCT PREVIEW EMIFA (32-BIT) – ASYNCHRONOUS/SYNCHRONOUS MEMORY CONTROL Terminal Functions Table 2–9. Terminal Functions (Continued) NAME SIGNAL DM641 DM640 TYPE† IPD/ IPU‡ DESCRIPTION PRODUCT PREVIEW EMIFA (32-BIT) – ADDRESS AEA22 U23 U23 AEA21 V24 V24 AEA20 V25 V25 AEA19 V26 V26 AEA18 V23 V23 AEA17 U24 U24 AEA16 U25 U25 AEA15 U26 U26 AEA14 T24 T24 AEA13 T25 T25 AEA12 R23 R23 AEA11 R24 R24 AEA10 P23 P23 AEA9 P24 P24 AEA8 P26 P26 AEA7 N23 N23 AEA6 N24 N24 AEA5 N26 N26 AEA4 M23 M23 AEA3 M24 M24 EMIFA external address (doubleword address) • Also controls initialization of DSP modes at reset (I) via pullup/pulldown resistors – Boot mode (AEA[22:21]): 00 – No boot (default mode) 01 – HPI [DM641 only]; Reserved [For DM640 device] 10 – Reserved 11 – EMIFA boot O/Z IPD – EMIF clock select – AEA[20:19]: Clock mode select for EMIFA (AECLKIN_SEL[1:0]) 00 – AECLKIN (default mode) 01 – CPU/4 Clock Rate 10 – CPU/6 Clock Rate 11 – Reserved For more details, see the Device Configurations section of this data sheet. EMIFA (32-BIT) – DATA AED31 C26 C26 AED30 C25 C25 AED29 D26 D26 AED28 D25 D25 AED27 E24 E24 AED26 E25 E25 AED25 F24 F24 AED24 F25 F25 AED23 F23 F23 AED22 F26 F26 AED21 G24 G24 AED20 G25 G25 AED19 G23 G23 AED18 G26 G26 AED17 H23 H23 AED16 H24 H24 AED15 C19 C19 I/O/Z IPU EMIFA external data AED14 D19 D19 † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground ‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-kΩ resistor should be used.) § These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet. 72 SPRS222 June 2003 Terminal Functions Table 2–9. Terminal Functions (Continued) NAME SIGNAL DM641 DM640 TYPE† IPD/ IPU‡ DESCRIPTION EMIFA (32-BIT) – DATA (CONTINUED) A20 A20 AED12 D20 D20 AED11 B20 B20 AED10 C20 C20 AED9 A21 A21 AED8 D21 D21 AED7 B21 B21 AED6 C21 C21 AED5 A23 A23 AED4 C22 C22 AED3 B22 B22 AED2 B23 B23 AED1 A24 A24 AED0 B24 B24 MDCLK R5 R5 I/O/Z IPD MDIO serial clock input/output (I/O/Z). MDIO P5 P5 I/O/Z IPU MDIO serial data input/output (I/O/Z). I/O/Z IPU EMIFA external data MANAGEMENT DATA INPUT/OUTPUT (MDIO) VCX0 INTERPOLATED CONTROL PORT (VIC) VDAC AD1 AD1 O/Z IPD VCXO Interpolated Control Port (VIC) single-bit digital-to-analog converter (VDAC) output [output only]. VIDEO PORTS (VP0 [DM641/DM640] AND VP1 [DM641 ONLY]) STCLK AC1 AC1 I IPD The STCLK signal drives the hardware counter on the video ports. 8-BIT VIDEO PORT 1 (VP1) [DM641 ONLY] VP1D[7] AC8 — VP1D[6]/CLKR1§ VP1D[5]/FSR1§ AD8 *** AC7 *** VP1D[4]/DR1§ AD7 *** VP1D[3]/CLKS1§ VP1D[2]/DX1§ AE7 *** AC6 *** VP1D[1]/FSX1§ AD6 *** VP1D[0]/CLKX1§ AE6 *** VP1CLK1 AF10 — VP1CLK0 AF8 — VP1CTL2 AD5 — VP1CTL1 AE5 — Video port 1 (VP1) data input/output (I/O/Z) [default] or McBSP1 data input/ output (I/O/Z) [DM641 only] I/O/Z IPD ***The DM640 device does not support the VP1 peripheral; therefore, the McBSP1 peripheral pins are standalone peripheral functions, not muxed. For more details on the McBSP1 pin functions [for both the DM641 and DM640 devices], see McBSP1 section of this table. VP1 clock 1 (I/O/Z) I VP1 clock 0 (I) VP1 control 2 (I/O/Z) I/O/Z IPD VP1 control 1 (I/O/Z) VP1CTL0 AF4 — VP1 control 0 (I/O/Z) † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground ‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-kΩ resistor should be used.) § These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet. June 2003 SPRS222 73 PRODUCT PREVIEW AED13 Terminal Functions Table 2–9. Terminal Functions (Continued) NAME SIGNAL DM641 DM640 TYPE† IPD/ IPU‡ DESCRIPTION PRODUCT PREVIEW 8-BIT VIDEO PORT 0 (VP0) [DM641 AND DM640] VP0D[7] AD15 AD15 VP0D[6]/CLKR0§ VP0D[5]/FSR0§ AE15 AE15 AB16 AB16 VP0D[4]/DR0§ AC16 AC16 VP0D[3]/CLKS0§ VP0D[2]/DX0§ AD16 AD16 AE16 AE16 VP0D[1]/FSX0§ AF16 AF16 VP0D[0]/CLKX0§ AF17 AF17 VP0CLK1 AF12 AF12 I/O/Z I VP0CLK0 AF14 AF14 VP0CTL2 AD17 AD17 VP0CTL1 AC17 AC17 VP0CTL0 AE17 AE17 Video port 0 (VP0) data input/output (I/O/Z) [default] or McBSP0 data input/ output (I/O/Z) I/O/Z IPD For more details on the McBSP0 pin functions, see McBSP0 section of this table. VP0 clock 1 (I/O/Z) VP0 clock 0 (I) IPD VP0 control 2 (I/O/Z) VP0 control 1 (I/O/Z) I/O/Z VP0control 0 (I/O/Z) TIMER 2 — No external pins. The timer 2 peripheral pins are not pinned out as external pins. — TIMER 1 TOUT1/LENDIAN B5 B5 O/Z IPU TINP1 A5 A5 I IPD Timer 1 output (O/Z) or device endian mode (I). Also controls initialization of DSP modes at reset via pullup/pulldown resistors – Device Endian mode 0 – Big Endian 1 – Little Endian (default) For more details on LENDIAN, see the Device Configurations section of this data sheet. Timer 1 or general-purpose input TIMER 0 TOUT0/MAC_EN C5 C5 O/Z IPD Timer 0 output (O/Z) or MAC enable select bit (I) MAC enable pin. The MAC_EN pin controls the selection (enable/disable) of the EMAC and MDIO peripherals. TINP0 A4 A4 I IPD Timer 0 or general-purpose input SCL0 E4 E4 I/O/Z For more details, see the Device Configurations section of this data sheet. INTER-INTEGRATED CIRCUIT 0 (I2C0) — I2C0 clock. SDA0 D3 D3 I/O/Z — I2C0 data. † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground ‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-kΩ resistor should be used.) § These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet. 74 SPRS222 June 2003 Terminal Functions Table 2–9. Terminal Functions (Continued) NAME SIGNAL DM641 DM640 TYPE† IPD/ IPU‡ DESCRIPTION MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1) [DM641 ONLY] VP1D[6]/CLKR1§ AD8 — I/O/Z IPD Video Port 1 (VP1) input/output data 6 pin (I/O/Z) [default] or McBSP1 receive clock (I/O/Z) VP1D[5]/FSR1§ AC7 — I/O/Z IPD VP1 input/output data 5 pin (I/O/Z) [default] or McBSP1 receive frame sync (I/O/Z) VP1D[4]/DR1§ AD7 — I IPD VP1 input/output data 4 pin (I/O/Z) [default] or McBSP1 receive data (I) VP1D[3]/CLKS1§ AE7 — I IPD VP1 input/output data 3 pin (I/O/Z) [default] or McBSP1 external clock source (I) (as opposed to internal) VP1D[2]/DX1§ AC6 — I/O/Z IPD VP1 input/output data 2 pin (I/O/Z) [default] or McBSP1 transmit data (O/Z) VP1D[1]/FSX1§ AD6 — I/O/Z IPD VP1 input/output data 1 pin (I/O/Z) [default] or McBSP1 transmit frame sync (I/O/Z) VP1D[0]/CLKX1§ AE6 — I/O/Z IPD VP1 input/output data 0 pin (I/O/Z) [default] or McBSP1 transmit clock (I/O/Z) — AD8 I/O/Z IPD McBSP1 receive clock (I/O/Z) FSR1 — AC7 I/O/Z IPD McBSP1 receive frame sync (I/O/Z) DR1 — AD7 I IPD McBSP1 receive data (I) CLKS1 — AE7 I IPD McBSP1 external clock source (I) (as opposed to internal) DX1 — AC6 I/O/Z IPD McBSP1 transmit data (O/Z) FSX1 — AD6 I/O/Z IPD McBSP1 transmit frame sync (I/O/Z) CLKX1 — AE6 I/O/Z IPD McBSP1 transmit clock (I/O/Z) MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0) VP0D[6]/CLKR0§ AE15 AE15 I/O/Z IPD Video Port 0 (VP0) input/output data 6 pin (I/O/Z) [default] or McBSP0 receive clock (I/O/Z) VP0D[5]/FSR0§ AB16 AB16 I/O/Z IPD VP0 input/output data 5 pin (I/O/Z) [default] or McBSP0 receive frame sync (I/O/Z) VP0D[4]/DR0§ AC16 AC16 I IPU VP0 input/output data 4 pin (I/O/Z) [default] or McBSP0 receive data (I) VP0D[3]/CLKS0§ AD16 AD16 I IPD VP0 input/output data 3 pin (I/O/Z) [default] or McBSP0 external clock source (I) (as opposed to internal) VP0D[2]/DX0§ AE16 AE16 O/Z IPU VP0 input/output data 2 pin (I/O/Z) [default] or McBSP0 transmit data (O/Z) VP0D[1]/FSX0§ AF16 AF16 I/O/Z IPD VP0 input/output data 1 pin (I/O/Z) [default] or McBSP0 transmit frame sync (I/O/Z) VP0D[0]/CLKX0§ AF17 AF17 I/O/Z IPD VP0 input/output data 0 pin (I/O/Z) [default] or McBSP0 transmit clock (I/O/Z) † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground ‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-kΩ resistor should be used.) § These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet. June 2003 SPRS222 75 PRODUCT PREVIEW MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1) [DM640 ONLY] CLKR1 Terminal Functions Table 2–9. Terminal Functions (Continued) NAME SIGNAL DM641 DM640 TYPE† IPD/ IPU‡ DESCRIPTION PRODUCT PREVIEW ETHERNET MAC (EMAC) MRCLK G1 G1 I MCR H3 H3 I MRXER G2 G2 I MRXDV J4 J4 I MRXD3 H2 H2 I MRXD2 J3 J3 I MRXD1 J1 J1 I MRXD0 K4 K4 I MTCLK L4 L4 I MCOL K2 K2 I MTXEN L3 L3 O/Z MTXD3 L2 L2 O/Z MTXD2 M4 M4 O/Z MTXD1 M2 M2 O/Z MTXD0 M3 M3 O/Z EMAC Media Independent I/F (MII) data, clocks, and control pins for Transmit/Receive. MII transmit clock (MTCLK), Transmit clock source from the attached PHY. MII transmit data (MTXD[3:0]), Transmit data nibble synchronous with transmit clock (MTCLK). MII transmit enable (MTXEN), This signal indicates a valid transmit data on the transmit data pins (MTDX[3:0]). MII collision sense (MCOL) Assertion of this signal during half-duplex operation indicates network collision. During full-duplex operation, transmission of new frames will not begin if this pin is asserted. MII carrier sense (MCRS) Indicates a frame carrier signal is being received. MII receive data (MRXD[3:0]), Receive data nibble synchronous with receive clock (MRCLK). MII receive clock (MRCLK), Receive clock source from the attached PHY. MII receive data valid (MRXDV), This signal indicates a valid data nibble on the receive data pins (MRDX[3:0]). MII receive error (MRXER), Indicates reception of a coding error on the receive data. MULTICHANNEL AUDIO SERIAL PORT 0 (McASP0) CONTROL AHCLKX0 AC12 AC12 I/O/Z IPD McASP0 transmit high-frequency master clock (I/O/Z). AFSX0 AD12 AD12 I/O/Z IPD McASP0 transmit frame sync or left/right clock (LRCLK) (I/O/Z). ACLKX0 AB13 AB13 I/O/Z IPD McASP0 transmit bit clock (I/O/Z). AMUTE0 AC13 AC13 O/Z IPD McASP0 mute output (O/Z). AMUTEIN0 AD13 AD13 I/O/Z IPD McASP0 mute input (I/O/Z). AHCLKR0 AB14 AB14 I/O/Z IPD McASP0 receive high-frequency master clock (I/O/Z). AFSR0 AC14 AC14 I/O/Z IPD McASP0 receive frame sync or left/right clock (LRCLK) (I/O/Z). ACLKR0 AD14 AD14 I/O/Z IPD McASP0 receive bit clock (I/O/Z). MULTICHANNEL AUDIO SERIAL PORT 0 (McASP0) DATA AXR0[3] AE11 AE11 AXR0[2] AC10 AC10 AXR0[1] AD10 AD10 I/O/Z IPD McASP0 TX/RX data pins [3:0] (I/O/Z). AXR0[0] AC9 AC9 † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground ‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-kΩ resistor should be used.) § These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet. 76 SPRS222 June 2003 Terminal Functions Table 2–9. Terminal Functions NAME SIGNAL DM641 DM640 TYPE† IPD/ IPU‡ DESCRIPTION RESERVED FOR TEST RSV E2 E2 I IPD Reserved. For proper DM641/DM640 device operation, this pin at device reset must be pulled down via a 10-kΩ resistor. RSV — Y1 I/O/Z — Reserved [for DM640 Only]. For proper DM640 device operation, this pin at device reset must be pulled down via a 10-kΩ resistor. RSV H7 H7 Reserved. This pin must be connected directly to CVDD for proper device operation. RSV R6 R6 Reserved. This pin must be connected directly to DVDD for proper device operation. RSV A7 A7 I IPD A9 A9 I/O/Z IPD A10 A10 I/O/Z IPD A11 A11 I/O/Z IPD A13 A13 I/O/Z IPD B8 B8 I/O/Z IPD B9 B9 I/O/Z IPD B10 B10 I/O/Z IPD B11 B11 I/O/Z IPD B12 B12 I/O/Z IPD C1 C1 I/O/Z — C7 C7 I/O/Z IPD C8 C8 I/O/Z IPD C9 C9 I/O/Z IPD C10 C10 I/O/Z IPD C11 C11 I/O/Z IPD C12 C12 I/O/Z IPD D7 D7 I/O/Z IPD D8 D8 I/O/Z IPD D9 D9 I/O/Z IPD D10 D10 I/O/Z IPD D11 D11 I/O/Z IPD D12 D12 I/O/Z IPD E11 E11 I/O/Z IPD E12 E12 I/O/Z IPD E13 E13 I/O/Z IPD E14 E14 — — F1 F1 I/O/Z — G3 G3 I/O/Z — G4 G4 I/O/Z — PRODUCT PREVIEW ADDITIONAL RESERVED FOR TEST Reserved (leave unconnected, do not connect to power or ground) Pull down via a 10-kΩ resistor Reserved (leave unconnected, do not connect to power or ground) Pull down via a 10-kΩ Ω resistor H4 H4 I/O/Z — † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground ‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-kΩ resistor should be used.) June 2003 SPRS222 77 Terminal Functions Table 2–9. Terminal Functions (Continued) PRODUCT PREVIEW NAME RSV SIGNAL DM641 DM640 TYPE† IPD/ IPU‡ J2 J2 I/O/Z — K1 K1 I/O/Z — K3 K3 I/O/Z — R4 R4 I IPU R25 R25 O/Z IPU R26 R26 O/Z IPU T4 T4 O IPD T22 T22 O/Z IPU T23 T23 O/Z IPU V4 V4 I/O/Z — W7 W7 — — W23 W23 I/O/Z IPU Y23 Y23 I/O/Z IPU Y24 Y24 I/O/Z IPU Y25 Y25 I/O/Z IPU IPU Y26 Y26 I/O/Z AA3 AA3 — — AA23 AA23 I/O/Z IPU AA24 AA24 I/O/Z IPU AA25 AA25 I/O/Z IPU AA26 AA26 I/O/Z IPU AB3 AB3 — — AB11 AB11 I/O/Z IPD AB12 AB12 I/O/Z IPD AB15 AB15 I/O/Z IPD AB23 AB23 I/O/Z IPU AB24 AB24 I/O/Z IPU AB25 AB25 I/O/Z IPU AC4 AC4 — — AC11 AC11 I/O/Z IPD AC15 AC15 I/O/Z IPD AC19 AC19 I/O/Z IPU AC20 AC20 I/O/Z IPU AC21 AC21 I/O/Z IPU AC25 AC25 I/O/Z IPU AC26 AC26 I/O/Z IPU AD3 AD3 — — AD9 AD9 I/O/Z IPD AD11 AD11 I/O/Z IPD AD19 AD19 I/O/Z IPU DESCRIPTION Pull down via a 10-kΩ resistor Reserved (leave unconnected, do not connect to power or ground) Pull down via a 10-kΩ resistor Reserved (leave unconnected, do not connect to power or ground) † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground ‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-kΩ resistor should be used.) 78 SPRS222 June 2003 Terminal Functions Table 2–9. Terminal Functions (Continued) RSV SIGNAL DM641 DM640 TYPE† IPD/ IPU‡ DESCRIPTION AD20 AD20 I/O/Z IPU AD21 AD21 I/O/Z IPU AD22 AD22 I/O/Z IPU AD23 AD23 I/O/Z IPU AD25 AD25 I/O/Z IPU AD26 AD26 I/O/Z IPU AE9 AE9 I/O/Z IPD AE18 AE18 I/O/Z IPD AE20 AE20 I/O/Z IPU AE21 AE21 I/O/Z IPU AE22 AE22 I/O/Z IPU AE23 AE23 I/O/Z IPU AF3 AF3 — — AF5 AF5 I/O/Z IPD AF6 AF6 I/O/Z IPD AF18 AF18 I/O/Z IPD AF20 AF20 I/O/Z IPU AF21 AF21 I/O/Z IPU AF23 AF23 I/O/Z IPU AF24 AF24 I/O/Z IPU — M1 I/O/Z — Pull up via a 10-kΩ resistor — N1 I/O/Z — Pull down via a 10-kΩ resistor — N3 I/O/Z — — N4 I/O/Z — — P1 I/O/Z — — P3 I/O/Z — — R1 I/O/Z — — R2 I/O/Z — — R3 I/O/Z — — T2 I/O/Z — — T3 I/O/Z — — U1 I/O/Z — — U2 I/O/Z — — U3 I/O/Z — — U4 I/O/Z — — V1 I/O/Z — — V2 I/O/Z — — V3 I/O/Z — — W2 I/O/Z — — W3 I/O/Z — Reserved (leave unconnected, do not connect to power or ground) PRODUCT PREVIEW NAME Pull up via a 10-kΩ Ω resistor Ω resistor Pull down via a 10-kΩ † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground ‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-kΩ resistor should be used.) June 2003 SPRS222 79 Terminal Functions Table 2–9. Terminal Functions (Continued) NAME SIGNAL DM641 — DM640 W4 — RSV TYPE† IPD/ IPU‡ I/O/Z — I/O/Z — — Y2 I/O/Z — — Y3 I/O/Z — — Y4 I/O/Z — — AA1 I/O/Z — — AC8 I/O/Z IPD — AD5 I/O/Z IPD — AE5 I/O/Z IPD — AF4 I/O/Z IPD — AF8 I IPD — AF10 I/O/Z IPD A2 A2 A25 A25 B1 B1 B2 B2 B14 B14 B25 B25 B26 B26 DESCRIPTION Pull down via a 10-kΩ Ω resistor Reserved (leave unconnected, do not connect to power or ground) PRODUCT PREVIEW SUPPLY VOLTAGE PINS DVDD C3 C3 C24 C24 D4 D4 D23 D23 E5 E5 E7 E7 E8 E8 E10 E10 E17 E17 E19 E19 E20 E20 E22 E22 F9 F9 F12 F12 F15 F15 S 3.3-V supply voltage F18 F18 † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground ‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-kΩ resistor should be used.) 80 SPRS222 June 2003 Terminal Functions Table 2–9. Terminal Functions (Continued) NAME SIGNAL DM641 DM640 TYPE† IPD/ IPU‡ DESCRIPTION DVDD G5 G5 G22 G22 H5 H5 H22 H22 J6 J6 J21 J21 K5 K5 K22 K22 M6 M6 M21 M21 N2 N2 P25 P25 R21 R21 U5 U5 U22 U22 V21 V21 W5 W5 W22 W22 W25 W25 Y5 Y5 Y22 Y22 AA9 AA9 AA12 AA12 AA15 AA15 AA18 AA18 AB5 AB5 AB7 AB7 AB8 AB8 AB10 AB10 AB17 AB17 AB19 AB19 AB20 AB20 S PRODUCT PREVIEW SUPPLY VOLTAGE PINS (CONTINUED) 3.3-V supply voltage † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground ‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-kΩ resistor should be used.) June 2003 SPRS222 81 Terminal Functions Table 2–9. Terminal Functions (Continued) NAME SIGNAL DM641 DM640 TYPE† IPD/ IPU‡ DESCRIPTION SUPPLY VOLTAGE PINS (CONTINUED) PRODUCT PREVIEW DVDD CVDD AB22 AB22 AC23 AC23 AD24 AD24 AE1 AE1 AE2 AE2 AE13 AE13 AE25 AE25 AE26 AE26 AF2 AF2 AF25 AF25 F6 F6 F7 F7 F20 F20 F21 F21 G6 G6 G7 G7 G8 G8 G10 G10 G11 G11 G13 G13 G14 G14 G16 G16 G17 G17 G19 G19 G20 G20 G21 G21 H20 H20 K7 K7 K20 K20 L7 L7 L20 L20 M12 M12 M14 M14 N7 N7 S 3.3-V supply voltage S 1.2-V supply voltage (-400, -500 devices) 1.4-V supply voltage (-600 device) † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground ‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-kΩ resistor should be used.) 82 SPRS222 June 2003 Terminal Functions Table 2–9. Terminal Functions (Continued) NAME SIGNAL DM641 DM640 TYPE† IPD/ IPU‡ DESCRIPTION CVDD N13 N13 N15 N15 N20 N20 P7 P7 P12 P12 P14 P14 P20 P20 R13 R13 R15 R15 T7 T7 T20 T20 U7 U7 U20 U20 W20 W20 Y6 Y6 Y7 Y7 Y8 Y8 Y10 Y10 Y11 Y11 Y13 Y13 Y14 Y14 Y16 Y16 Y17 Y17 Y19 Y19 Y20 Y20 Y21 Y21 AA6 AA6 AA7 AA7 AA20 AA20 AA21 AA21 S PRODUCT PREVIEW SUPPLY VOLTAGE PINS (CONTINUED) 1.2-V supply voltage (-400, -500 devices) 1.4-V supply voltage (-600 device) † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground ‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-kΩ resistor should be used.) June 2003 SPRS222 83 Terminal Functions Table 2–9. Terminal Functions (Continued) NAME SIGNAL DM641 DM640 TYPE† IPD/ IPU‡ DESCRIPTION PRODUCT PREVIEW GROUND PINS VSS A1 A1 A3 A3 A6 A6 A8 A8 A12 A12 A14 A14 A19 A19 A22 A22 A26 A26 B3 B3 B6 B6 B7 B7 B13 B13 B19 B19 C2 C2 C4 C4 C13 C13 C18 C18 C23 C23 D1 D1 D2 D2 D5 D5 D13 D13 D18 D18 D22 D22 D24 D24 E3 E3 E6 E6 E9 E9 E16 E16 E18 E18 E21 E21 E23 E23 E26 E26 GND Ground pins † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground ‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-kΩ resistor should be used.) 84 SPRS222 June 2003 Terminal Functions Table 2–9. Terminal Functions (Continued) NAME SIGNAL DM641 DM640 TYPE† IPD/ IPU‡ DESCRIPTION VSS F5 F5 F8 F8 F10 F10 F11 F11 F13 F13 F14 F14 F16 F16 F17 F17 F19 F19 F22 F22 G9 G9 G12 G12 G15 G15 G18 G18 H1 H1 H6 H6 H21 H21 H26 H26 J5 J5 J7 J7 J20 J20 J22 J22 K6 K6 K21 K21 L1 L1 L6 L6 L21 L21 M7 M7 M13 M13 M15 M15 M20 M20 N5 N5 N6 N6 N12 N12 GND PRODUCT PREVIEW GROUND PINS (CONTINUED) Ground pins † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground ‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-kΩ resistor should be used.) June 2003 SPRS222 85 Terminal Functions Table 2–9. Terminal Functions (Continued) NAME SIGNAL DM641 DM640 TYPE† IPD/ IPU‡ DESCRIPTION PRODUCT PREVIEW GROUND PINS (CONTINUED) VSS N14 N14 N21 N21 N25 N25 P2 P2 P6 P6 P13 P13 P15 P15 P21 P21 R7 R7 R12 R12 R14 R14 R20 R20 T1 T1 T5 T5 T6 T6 T21 T21 T26 T26 U6 U6 U21 U21 V5 V5 V7 V7 V20 V20 V22 V22 W1 W1 W6 W6 W21 W21 W26 W26 Y9 Y9 Y12 Y12 Y15 Y15 Y18 Y18 AA4 AA4 AA5 AA5 AA8 AA8 GND Ground pins † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground ‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-kΩ resistor should be used.) 86 SPRS222 June 2003 Terminal Functions Table 2–9. Terminal Functions (Continued) NAME SIGNAL DM641 DM640 TYPE† IPD/ IPU‡ DESCRIPTION GROUND PINS (CONTINUED) VSS AA10 AA11 AA11 AA13 AA13 AA14 AA14 AA16 AA16 AA17 AA17 AA19 AA19 AA22 AA22 AB1 AB1 AB2 AB2 AB4 AB4 AB6 AB6 AB9 AB9 AB18 AB18 AB21 AB21 AB26 AB26 AC3 AC3 AC5 AC5 AC18 AC18 AC22 AC22 AC24 AC24 AD2 AD2 AD4 AD4 AD18 AD18 AE3 AE3 AE8 AE8 AE10 AE10 AE12 AE12 AE14 AE14 AE19 AE19 AE24 AE24 AF1 AF1 GND PRODUCT PREVIEW AA10 Ground pins AF7 AF7 † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground ‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-kΩ resistor should be used.) June 2003 SPRS222 87 Terminal Functions Table 2–9. Terminal Functions (Continued) NAME SIGNAL DM641 DM640 TYPE† IPD/ IPU‡ DESCRIPTION GROUND PINS (CONTINUED) AF9 VSS AF9 AF11 AF11 AF13 AF13 AF15 AF15 AF19 AF19 AF22 AF22 AF26 AF26 GND Ground pins PRODUCT PREVIEW † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground ‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-kΩ resistor should be used.) 88 SPRS222 June 2003 Development Support 2.8 Development Support TI offers an extensive line of development tools for the TMS320C6000 DSP platform, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. The following products support development of C6000 DSP-based applications: Software Development Tools: Code Composer Studio Integrated Development Environment (IDE): including Editor C/C++/Assembly Code Generation, and Debug plus additional development tools Scalable, Real-Time Foundation Software (DSP/BIOS), which provides the basic run-time target software needed to support any DSP application. For a complete listing of development-support tools for the TMS320C6000 DSP platform, visit the Texas Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL). For information on pricing and availability, contact the nearest TI field sales office or authorized distributor. Code Composer Studio, DSP/BIOS, XDS, and TMS320 are trademarks of Texas Instruments. June 2003 SPRS222 89 PRODUCT PREVIEW Hardware Development Tools: Extended Development System (XDS) Emulator (supports C6000 DSP multiprocessor system debug) EVM (Evaluation Module) Device and Development-Support Tool Nomenclature 2.9 Device and Development-Support Tool Nomenclature To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all TMS320 DSP devices and support tools. Each TMS320 DSP commercial family member has one of three prefixes: TMX, TMP, or TMS. Texas Instruments recommends two of three possible prefix designators for support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS). Device development evolutionary flow: TMX Experimental device that is not necessarily representative of the final device’s electrical specifications TMP Final silicon die that conforms to the device’s electrical specifications but has not completed quality and reliability verification TMS Fully qualified production device PRODUCT PREVIEW Support tool development evolutionary flow: TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing. TMDS Fully qualified development-support product TMX and TMP devices and TMDX development-support tools are shipped with appropriate disclaimers describing their limitations and intended uses. Experimental devices (TMX) may not be representative of a final product and Texas Instruments reserves the right to change or discontinue these products without notice. TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI’s standard warranty applies. Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used. TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, GDK), the temperature range (for example, blank is the default commercial temperature range), and the device speed range in megahertz (for example, -600 is 600 MHz). Figure 2–10 provides a legend for reading the complete device name for any TMS320C6000 DSP platform member. TMS320 is a trademark of Texas Instruments. 90 SPRS222 June 2003 Device and Development-Support Tool Nomenclature TMX 320 DM641 GDK PREFIX TMX = Experimental device TMP = Prototype device TMS = Qualified device SMX= Experimental device, MIL SMJ = MIL-PRF-38535, QML SM = High Rel (non-38535) DEVICE FAMILY 320 = TMS320t DSP family ( ) 600 DEVICE SPEED RANGE 400 (400-MHz CPU, 100-MHz EMIF) 500 (500-MHz CPU, 100-MHz EMIF) 600 (600-MHz CPU, 133-MHz EMIF) TEMPERATURE RANGE (DEFAULT: 0°C TO 90°C)† Blank = 0°C to 90°C, commercial temperature A = –40°C to 105°C, extended temperature PACKAGE TYPE‡ GDK = 548-pin plastic BGA GNZ = 548-pin plastic BGA DEVICE DM64x DSP: 642 641 640 PRODUCT PREVIEW † For more details, see the recommended operating conditions portion of this data sheet. ‡ BGA = Ball Grid Array Figure 2–10. TMS320DM64x DSP Device Nomenclature (Including the DM641 and DM640 Devices) June 2003 SPRS222 91 Documentation Support 2.10 Documentation Support Extensive documentation supports all TMS320 DSP family generations of devices from product announcement through applications development. The types of documentation available include: data sheets, such as this document, with design specifications; complete user’s reference guides for all devices and tools; technical briefs; development-support tools; on-line help; and hardware and software applications. The following is a brief, descriptive list of support documentation specific to the C6000 DSP devices: The TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189) describes the C6000 DSP CPU (core) architecture, instruction set, pipeline, and associated interrupts. PRODUCT PREVIEW The TMS320C6000 Peripherals Reference Guide (literature number SPRU190) describes the functionality of the peripherals available on the C6000 DSP platform of devices, such as the 64-/32-/16-bit external memory interfaces (EMIFs), enhanced direct-memory-access (EDMA) controller, multichannel buffered serial ports (McBSPs), 32-/16-bit host-port interfaces (HPIs), a peripheral component interconnect (PCI), clocking and phase-locked loop (PLL); general-purpose timers, general-purpose input/output port (GP0), and power-down modes. This guide also includes information on internal data and program memories. The TMS320C64x Technical Overview (literature number SPRU395) gives an introduction to the C64x digital signal processor, and discusses the application areas that are enhanced by the C64x DSP VelociTI.2 VLIW architecture. The TMS320C64x DSP Video Port/VCXO Interpolated Control (VIC) Port Reference Guide (literature number SPRU629) describes the functionality of the Video Port and VIC Port peripherals. The TMS320C6000 DSP Multichannel Audio Serial Port (McASP) Reference Guide (literature number SPRU041) describes the functionality of the McASP peripheral. TMS320C6000 DSP Inter-Integrated Circuit (I2C) Module Peripheral Reference Guide (literature number SPRU175) describes the functionality of the I2C peripheral. TMS320C6000 DSP Ethernet Media Access Controller (EMAC)/ Management Data Input/Output (MDIO) Module Reference Guide (literature number SPRU628) describes the functionality of the EMAC and MDIO peripherals. The Using IBIS Models for Timing Analysis application report (literature number SPRA839) describes how to properly use IBIS models to attain accurate timing analysis for a given system. The tools support documentation is electronically available within the Code Composer Studio Integrated Development Environment (IDE). For a complete listing of C6000 DSP latest documentation, visit the Texas Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL). 92 SPRS222 June 2003 Clock PLL 2.11 Clock PLL Most of the internal C64x DSP clocks are generated from a single source through the CLKIN pin. This source clock either drives the PLL, which multiplies the source clock frequency to generate the internal CPU clock, or bypasses the PLL to become the internal CPU clock. To use the PLL to generate the CPU clock, the external PLL filter circuit must be properly designed. Figure 2–11 shows the external PLL circuitry for either x1 (PLL bypass) or other PLL multiply modes. To minimize the clock jitter, a single clean power supply should power both the C64x DSP device and the external clock oscillator circuit. The minimum CLKIN rise and fall times should also be observed. For the input clock timing requirements, see the input and output clocks electricals section. June 2003 SPRS222 PRODUCT PREVIEW Rise/fall times, duty cycles (high/low pulse durations), and the load capacitance of the external clock source must meet the DSP requirements in this data sheet (see the electrical characteristics over recommended ranges of supply voltage and operating case temperature table and the input and output clocks electricals section). 93 Clock PLL 3.3 V CPU Clock EMI filter C1 C2 10 µF 0.1 µF /2 Peripheral Bus, EDMA Clock, L2 Clock /8 Timer Internal Clock PLLV CLKMODE0 CLKMODE1 PLLMULT /4 CLKOUT4, Peripheral Clock (AUXCLK for McASP), McBSP Internal Clock /6 CLKOUT6 PLL x6, x12 CLKIN PLLCLK 1 00 01 10 /4 PRODUCT PREVIEW 0 /2 ECLKIN AEA[20:19] Internal to DM641/DM640 (For the PLL Options, CLKMODE Pins Setup, and PLL Clock Frequency Ranges, see Table 9.) EMIF 00 01 10 ECLKOUT1 ECLKOUT2 EK2RATE (GBLCTL.[19,18]) NOTES: A. Place all PLL external components (C1, C2, and the EMI Filter) as close to the C6000 DSP device as possible. For the best performance, TI recommends that all the PLL external components be on a single side of the board without jumpers, switches, or components other than the ones shown. B. For reduced PLL jitter, maximize the spacing between switching signals and the PLL external components (C1, C2, and the EMI Filter). C. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DVDD. D. EMI filter manufacturer TDK part number ACF451832-333, -223, -153, -103. Panasonic part number EXCCET103U. Figure 2–11. External PLL Circuitry for Either PLL Multiply Modes or x1 (Bypass) Mode 94 SPRS222 June 2003 Clock PLL Table 2–10. TMS320DM641/DM640 PLL Multiply Factor Options, Clock Frequency Ranges, and Typical Lock Time†‡ GDK PACKAGE – 23 x 23 mm BGA, GNZ PACKAGE – 27 x 27 mm BGA CLKMODE1 CLKMODE0 CLKMODE (PLL MULTIPLY FACTORS) CLKIN RANGE (MHz) CPU CLOCK FREQUENCY RANGE (MHz) CLKOUT4 RANGE (MHz) CLKOUT6 RANGE (MHz) TYPICAL LOCK TIME (µs)§ N/A 0 0 Bypass (x1) 30–75 30–75 7.5–18.8 5–12.5 0 1 x6 30–75 180–450 45–112.5 30–75 1 0 x12 30–50 360–600 90–150 60–100 75 PRODUCT PREVIEW 1 1 Reserved – – – – – † These clock frequency range values are applicable to a DM641–600 speed device. For –400, –500 device speed values, see the CLKIN timing requirements table for the specific device speed. ‡ Use external pullup resistors on the CLKMODE pins (CLKMODE1 and CLKMODE0) to set the DM641/DM640 device to one of the valid PLL multiply clock modes (x6 or x12). With internal pulldown resistors on the CLKMODE pins (CLKMODE1, CLKMODE0), the default clock mode is x1 (bypass). § Under some operating conditions, the maximum PLL lock time may vary by as much as 150% from the specified typical value. For example, if the typical lock time is specified as 100 µs, the maximum value may be as long as 250 µs. June 2003 SPRS222 95 Multichannel Audio Serial Port (McASP0) Peripheral 2.12 Multichannel Audio Serial Port (McASP0) Peripheral The TMS320DM641/DM640 device includes one multichannel audio serial port (McASP) interface peripheral (McASP0). The McASP is a serial port optimized for the needs of multi-channel audio applications. The McASP consists of a transmit and receive section. These sections can operate completely independently with different data formats, separate master clocks, bit clocks, and frame syncs or alternatively, the transmit and receive sections may be synchronized. The McASP module also includes a pool of 16 shift registers that may be configured to operate as either transmit data, receive data, or general-purpose I/O (GPIO). PRODUCT PREVIEW The transmit section of the McASP can transmit data in either a time-division-multiplexed (TDM) synchronous serial format or in a digital audio interface (DIT) format where the bit stream is encoded for S/PDIF, AES-3, IEC-60958, CP-430 transmission. The receive section of the McASP supports the TDM synchronous serial format. The McASP can support one transmit data format (either a TDM format or DIT format) and one receive format at a time. All transmit shift registers use the same format and all receive shift registers use the same format. However, the transmit and receive formats need not be the same. Both the transmit and receive sections of the McASP also support burst mode which is useful for non-audio data (for example, passing control information between two DSPs). The McASP peripheral has additional capability for flexible clock generation, and error detection/handling, as well as error management. For more detailed information on and the functionality of the McASP peripheral, see the TMS320C6000 DSP Multichannel Audio Serial Port (McASP) Reference Guide (literature number SPRU041). 2.12.1 McASP Block Diagram Figure 2–12 illustrates the major blocks along with external signals of the DM641/DM640 McASP0 peripheral; and shows the 4 serial data [AXR] pins. The McASP also includes full general-purpose I/O (GPIO) control, so any pins not needed for serial transfers can be used for general-purpose I/O. 96 SPRS222 June 2003 Multichannel Audio Serial Port (McASP0) Peripheral McASP0 DIT RAM Transmit Frame Sync Generator Transmit Clock Check (HighFrequency) Transmit Clock Generator Receive Clock Generator Transmit Data Formatter Receive Frame Sync Generator AHCLKR0 ACLKR0 AFSR0 Serializer 0 AXR0[0] Serializer 1 AXR0[1] Serializer 2 AXR0[2] Serializer 3 AXR0[3] PRODUCT PREVIEW Receive Clock Check (HighFrequency) INDIVIDUALLY PROGRAMMABLE TX/RX/GPIO DMA Transmit DMA Receive AHCLKX0 ACLKX0 AMUTE0 AMUTEIN0 Error Detect Receive Data Formatter AFSX0 Serializer 4 Serializer 5 Serializer 6 Serializer 7 GPIO Control Figure 2–12. McASP0 Configuration June 2003 SPRS222 97 I2C 2.13 I2C The I2C module on the TMS320DM641/DM640 may be used by the DSP to control local peripherals ICs (DACs, ADCs, etc.) while the other may be used to communicate with other controllers in a system or to implement a user interface. The I2C port supports: • Compatible with Philips I2C Specification Revision 2.1 (January 2000) • Fast Mode up to 400 Kbps (no fail-safe I/O buffers) • Noise Filter to Remove Noise 50 ns or less • Seven- and Ten-Bit Device Addressing Modes • Master (Transmit/Receive) and Slave (Transmit/Receive) Functionality • Events: DMA, Interrupt, or Polling • Slew-Rate Limited Open-Drain Output Buffers PRODUCT PREVIEW Figure 2–13 is a block diagram of the I2C0 module. I2C0 Module Clock Prescale Peripheral Clock (CPU/4) I2CPSCx SCL Noise Filter I2C Clock Bit Clock Generator Control I2CCLKHx I2COARx Own Address I2CSARx Slave Address I2CMDRx Mode I2CCNTx Data Count I2CCLKLx Transmit I2CXSRx Transmit Shift I2CDXRx Transmit Buffer Interrupt/DMA SDA I2C Data Noise Filter Receive I2CIERx Interrupt Enable I2CDRRx Receive Buffer I2CSTRx Interrupt Status I2CRSRx Receive Shift I2CISRCx Interrupt Source NOTE A: Shading denotes control/status registers. Figure 2–13. I2C0 Module Block Diagram 98 SPRS222 June 2003 Video Port 2.14 Video Port The TMS320DM641 device has two video port peripherals [VP0 and VP1]. The TMS320DM640 device only supports one video port peripheral [VP0]. The video port peripheral can operate as a video capture port, video display port, or as a transport stream interface (TSI) capture port. The port consists of a single channel A. A 2460-byte capture/display buffer is utilized on this channel. The port is always configured for either video capture or display only. Separate data pipelines control the parsing and formatting of video capture or display data for each of the BT.656, raw video, and TSI modes. For video capture operation, the video port may operate as a single channel of 8-bit BT.656, 8-bit raw video, or 8-bit TSI. PRODUCT PREVIEW For video display operation, the video port may operate as 8-bit BT.656 or 8-bit raw video. June 2003 SPRS222 99 VIC 2.15 VIC The VCXO interpolated control (VIC) port provides digital-to-analog conversation with resolution from 9-bits to up to 16-bits. The output of the VIC is a single bit interpolated D/A output (VDAC pin). Typical D/A converters provide a discrete output level for every value of the digital word that is being converted. This is a problem for digital words that are long. This is avoided in a Sigma Delta type D/A converter by choosing a few widely spaced output levels and interpolating values between them. The interpolating mechanism causes the output to oscillate rapidly between the levels in such a manner that the average output represents the value of input code. In the VIC, two output levels are chosen (0 and 1), and Sigma Delta interpolation scheme is implemented to interpolate between these levels with a rapidly changing signal. The frequency of interpolation is dependent on the resolution needed. PRODUCT PREVIEW When the video port is used in transport stream interface (TSI) mode, the VIC port is used to control the system clock, VCXO, for MPEG transport stream. The VIC supports the following features: • • • 100 Single interpolation for D/A conversion Programmable precision from 9-to-16 bits Interface for register accesses SPRS222 June 2003 EMAC 2.16 EMAC The ethernet media access controller (EMAC) provides an efficient interface between the DM641/DM640 DSP core processor and the network. The DM641/DM640 EMAC support both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex, with hardware flow control and quality of service (QOS) support. The DM641/DM640 EMAC makes use of a custom interface to the DSP core that allows efficient data transmission and reception. The EMAC controls the flow of packet data from the DSP to the PHY. The MDIO module controls PHY configuration and status monitoring. PRODUCT PREVIEW Both the EMAC and the MDIO modules interface to the DSP through a custom interface that allows efficient data transmission and reception. This custom interface is referred to as the EMAC control module, and is considered integral to the EMAC/MDIO peripheral. The control module is also used to control device reset, interrupts, and system priority. June 2003 SPRS222 101 MDIO 2.17 MDIO The management data input/output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system. PRODUCT PREVIEW The management data input/output (MDIO) module implements the 802.3 serial management interface to interrogate and control Ethernet PHY(s) using a shared two-wire bus. Host software uses the MDIO module to configure the auto-negotiation parameters of each PHY attached to the EMAC, retrieve the negotiation results, and configure required parameters in the EMAC module for correct operation. The module is designed to allow almost transparent operation of the MDIO interface, with very little maintenance from the core processor. 102 SPRS222 June 2003 Power-Supply Sequencing 2.18 Power-Supply Sequencing TI DSPs do not require specific power sequencing between the core supply and the I/O supply. However, systems should be designed to ensure that neither supply is powered up for extended periods of time (>1 second) if the other supply is below the proper operating voltage. 2.18.1 Power-Supply Design Considerations A dual-power supply with simultaneous sequencing can be used to eliminate the delay between core and I/O power up. A Schottky diode can also be used to tie the core rail to the I/O rail (see Figure 2–14). I/O Supply DVDD C6000 DSP Core Supply CVDD VSS GND Figure 2–14. Schottky Diode Diagram Core and I/O supply voltage regulators should be located close to the DSP (or DSP array) to minimize inductance and resistance in the power delivery path. Additionally, when designing for high-performance applications utilizing the C6000 platform of DSPs, the PC board should include separate power planes for core, I/O, and ground, all bypassed with high-quality low-ESL/ESR capacitors. TI DSPs do not require specific power sequencing between the core supply and the I/O supply. However, systems should be designed to ensure that neither supply is powered up for extended periods of time if the other supply is below the proper operating voltage. 2.19 Power-Supply Decoupling In order to properly decouple the supply planes from system noise, place as many capacitors (caps) as possible close to the DSP. Assuming 0603 caps, the user should be able to fit a total of 60 caps, 30 for the core supply and 30 for the I/O supply. These caps need to be close to the DSP, no more than 1.25 cm maximum distance to be effective. Physically smaller caps are better, such as 0402, but need to be evaluated from a yield/manufacturing point-of-view. Parasitic inductance limits the effectiveness of the decoupling capacitors, therefore physically smaller capacitors should be used while maintaining the largest available capacitance value. As with the selection of any component, verification of capacitor availability over the product’s production lifetime should be considered. June 2003 SPRS222 103 PRODUCT PREVIEW Schottky Diode Power-Down Operation 2.20 Power-Down Operation The DM641/DM640 device can be powered down in three ways: • • • Power-down due to pin configuration Power-down due to software configuration – relates to the default state of the peripheral configuration bits in the PERCFG register. Power-down during run-time via software configuration On the DM641/DM640 device, the EMAC and MDIO peripherals are controlled (selected) at the pin level during chip reset (e.g., using the MAC_EN pin). The McASP0, McBSP0, McBSP1, VP0, VP1 [DM641 only], and I2C0 peripheral functions are selected via the peripheral configuration (PERCFG) register bits. For more detailed information on the peripheral configuration pins and the PERCFG register bits, see the Device Configurations section of this document. 2.21 IEEE 1149.1 JTAG Compatibility Statement PRODUCT PREVIEW The TMS320DM641/DM640 DSP requires that both TRST and RESET be asserted upon power up to be properly initialized. While RESET initializes the DSP core, TRST initializes the DSP’s emulation logic. Both resets are required for proper operation. While both TRST and RESET need to be asserted upon power up, only RESET needs to be released for the DSP to boot properly. TRST may be asserted indefinitely for normal operation, keeping the JTAG port interface and DSP’s emulation logic in the reset state. TRST only needs to be released when it is necessary to use a JTAG controller to debug the DSP or exercise the DSP’s boundary scan functionality. For maximum reliability, the TMS320DM641/DM640 DSP includes an internal pulldown (IPD) on the TRST pin to ensure that TRST will always be asserted upon power up and the DSP’s internal emulation logic will always be properly initialized. JTAG controllers from Texas Instruments actively drive TRST high. However, some third-party JTAG controllers may not drive TRST high but expect the use of a pullup resistor on TRST. When using this type of JTAG controller, assert TRST to intialize the DSP after powerup and externally drive TRST high before attempting any emulation or boundary scan operations. Following the release of RESET, the low-to-high transition of TRST must be “seen” to latch the state of EMU1 and EMU0. The EMU[1:0] pins configure the device for either Boundary Scan mode or Emulation mode. For more detailed information, see the terminal functions section of this data sheet. 104 SPRS222 June 2003 EMIF Device Speed 2.22 EMIF Device Speed The rated EMIF speed of these devices only applies to the SDRAM interface when in a system that meets the following requirements: • • • • • 1 bank (maximum of 2 chips) of SDRAM connected to EMIF up to 1 bank of buffers connected to EMIF EMIF trace lengths between 1 and 3 inches 183-MHz SDRAM for 133-MHz operation 143-MHz SDRAM for 100-MHz operation Other configurations may be possible, but timing analysis must be done to verify all AC timings are met. Verification of AC timings is mandatory when using configurations other than those specified above. TI recommends utilizing I/O buffer information specification (IBIS) to analyze all AC timings. To properly use IBIS models to attain accurate timing analysis for a given system, see the Using IBIS Models for Timing Analysis application report (literature number SPRA839). June 2003 SPRS222 PRODUCT PREVIEW To maintain signal integrity, serial termination resistors should be inserted into all EMIF output signal lines (see the Terminal Functions table for the EMIF output signals). 105 Bootmode 2.23 Bootmode The DM641/DM640 device resets using the active-low signal RESET. While RESET is low, the device is held in reset and is initialized to the prescribed reset state. Refer to reset timing for reset timing characteristics and states of device pins during reset. The release of RESET starts the processor running with the prescribed device configuration and boot mode. The DM641 has three types of boot modes while the DM641 has only two types of boot modes: • Host boot [DM641 only] PRODUCT PREVIEW If host boot is selected, upon release of RESET, the CPU is internally “stalled” while the remainder of the device is released. During this period, an external host can initialize the CPU’s memory space as necessary through the host interface, including internal configuration registers, such as those that control the EMIF or other peripherals. For the DM641 device, the HPI peripheral is used for host boot. Once the host is finished with all necessary initialization, it must set the DSPINT bit in the HPIC register to complete the boot process. This transition causes the boot configuration logic to bring the CPU out of the “stalled” state. The CPU then begins execution from address 0. The DSPINT condition is not latched by the CPU, because it occurs while the CPU is still internally “stalled”. Also, DSPINT brings the CPU out of the “stalled” state only if the host boot process is selected. All memory may be written to and read by the host. This allows for the host to verify what it sends to the DSP if required. After the CPU is out of the “stalled” state, the CPU needs to clear the DSPINT, otherwise, no more DSPINTs can be received. • EMIF boot (using default ROM timings) Upon the release of RESET, the 1K-Byte ROM code located in the beginning of CE1 is copied to address 0 by the EDMA using the default ROM timings, while the CPU is internally “stalled”. The data should be stored in the endian format that the system is using. In this case, the EMIF automatically assembles consecutive 8-bit bytes to form the 32-bit instruction words to be copied. The transfer is automatically done by the EDMA as a single-frame block transfer from the ROM to address 0. After completion of the block transfer, the CPU is released from the “stalled” state and starts running from address 0. • No boot With no boot, the CPU begins direct execution from the memory located at address 0. If SDRAM is used in the system, the CPU is internally “stalled” until the SDRAM initialization is complete. Note: operation is undefined if invalid code is located at address 0. 106 SPRS222 June 2003 Electrical Specifications 3 Electrical Specifications 3.1 Absolute Maximum Ratings Over Operating Case Temperature Range (Unless Otherwise Noted)† Supply voltage ranges: CVDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 1.8 V DVDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4 V Input voltage ranges: VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4 V Output voltage ranges: VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4 V Operating case temperature ranges, TC: (default) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0_C to 90_C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65_C to 150_C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS. Recommended Operating Conditions MIN NOM MAX UNIT CVDD Supply voltage, Core (-400 and -500 devices)‡ 1.14 1.2 1.26 V CVDD Supply voltage, Core (-600 device)‡ 1.36 1.4 1.44 V DVDD Supply voltage, I/O 3.14 3.3 3.46 V VSS VIH Supply ground 0 0 0 V High-level input voltage 2 V VIL Low-level input voltage 0.8 V TC Operating case temperature 0 90 _C ‡ Future variants of the C64x DSPs may operate at voltages ranging from 1.2 V to 1.4 V to provide a range of system power/performance options. TI highly recommends that users design-in a supply that can handle multiple voltages within this range (i.e., 1.2 V, 1.25 V, 1.3 V, 1.35 V, 1.4 V with ± 3% tolerances) by implementing simple board changes such as reference resistor values or input pin configuration modifications. Examples of such supplies include the PT4660, PT5500, PT5520, PT6440, and PT6930 series from Power Trends, a subsidiary of Texas Instruments. Not incorporating a flexible supply may limit the system’s ability to easily adapt to future versions of C64x devices. June 2003 SPRS222 107 PRODUCT PREVIEW 3.2 Electrical Specifications 3.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Case Temperature (Unless Otherwise Noted) PARAMETER VOH VOL High-level output voltage Low-level output voltage TEST CONDITIONS† DVDD = MIN, DVDD = MIN, IOH = MAX IOL = MAX MIN TYP 2.4 Input current High-level output current V ±10 uA 50 100 150 uA VI = VSS to DVDD opposing internal pulldown resistor‡ –150 –100 –50 uA –16 mA –8 mA –0.5 mA 16 mA 8 mA Timer, TDO, GPIO (Excluding GP[2,1]), McBSP HPI [DM641] EMIF, CLKOUT4, CLKOUT6, EMUx PRODUCT PREVIEW 0.4 VI = VSS to DVDD opposing internal pullup resistor‡ EMIF, CLKOUT4, CLKOUT6, EMUx IOH UNIT V VI = VSS to DVDD no opposing internal resistor II MAX Timer, TDO, GPIO (Excluding GP[2,1]), McBSP IOL Low-level output current HPI [DM641] 1.5 mA IOZ Off-state output current VO = DVDD or 0 V CVDD = 1.4 V, CPU clock = 600 MHz ±10 uA TBD mA ICDD Core supply current§ CVDD = 1.2 V, CPU clock = 500 MHz CVDD = 1.2 V, CPU clock = 400 MHz TBD mA TBD mA DVDD = 3.3 V, CPU clock = 600 MHz TBD IDDD Ci I/O supply current§ Input capacitance mA 10 pF Co Output capacitance 10 pF † For test conditions shown as MIN, MAX, or NOM, use the appropriate value specified in the recommended operating conditions table. ‡ Applies only to pins with an internal pullup (IPU) or pulldown (IPD) resistor. § Measured with average activity (50% high/50% low power). The actual current draw is highly application-dependent. For more details on core and I/O activity, refer to the TMS320C6414/5/6 Power Consumption Summary application report (literature number SPRA811). 108 SPRS222 June 2003 Electrical Specifications 3.4 Parameter Information Tester Pin Electronics 42 Ω Data Sheet Timing Reference Point Output Under Test 3.5 nH Transmission Line Z0 = 50 Ω (see note) 4.0 pF Device Pin (see note) 1.85 pF Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin. Figure 3–1. Test Load Circuit for AC Timing Measurements The load capacitance value stated is only for characterization and measurement of AC timing signals. This load capacitance value does not indicate the maximum load the device is capable of driving. 3.4.1 Signal Transition Levels All input and output timing parameters are referenced to 1.5 V for both “0” and “1” logic levels. Vref = 1.5 V Figure 3–2. Input and Output Voltage Reference Levels for AC Timing Measurements All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks, VOL MAX and VOH MIN for output clocks. Vref = VIH MIN (or VOH MIN) Vref = VIL MAX (or VOL MAX) Figure 3–3. Rise and Fall Transition Time Voltage Reference Levels 3.4.2 Signal Transition Rates All timings are tested with an input edge rate of 4 Volts per nanosecond (4 V/ns). June 2003 SPRS222 109 PRODUCT PREVIEW NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer) from the data sheet timings. Electrical Specifications 3.5 Timing Parameters and Board Routing Analysis The timing parameter values specified in this data sheet do not include delays by board routings. As a good board design practice, such delays must always be taken into account. Timing values may be adjusted by increasing/decreasing such delays. TI recommends utilizing the available I/O buffer information specification (IBIS) models to analyze the timing characteristics correctly. If needed, external logic hardware such as buffers may be used to compensate any timing differences. For inputs, timing is most impacted by the round-trip propagation delay from the DSP to the external device and from the external device to the DSP. This round-trip delay tends to negatively impact the input setup time margin, but also tends to improve the input hold time margins (see Table 3–1 and Figure 3–4). Figure 3–4 represents a general transfer between the DSP and an external device. The figure also represents board route delays and how they are perceived by the DSP and the external device. Table 3–1. Board-Level Timing Example (see Figure 3–4) PRODUCT PREVIEW NO. DESCRIPTION 1 Clock route delay 2 Minimum DSP hold time 3 Minimum DSP setup time 4 External device hold time requirement 5 External device setup time requirement 6 Control signal route delay 7 External device hold time 8 External device access time 9 DSP hold time requirement 10 DSP setup time requirement 11 Data route delay ECLKOUTx (Output from DSP) 1 ECLKOUTx (Input to External Device) Control Signals† (Output from DSP) 2 3 4 5 Control Signals (Input to External Device) 6 7 Data Signals‡ (Output from External Device) 8 10 Data Signals‡ (Input to DSP) 9 11 † Control signals include data for Writes. ‡ Data signals are generated during Reads from an external device. Figure 3–4. Board-Level Input/Output Timings 110 SPRS222 June 2003 Input and Output Clocks 4 Input and Output Clocks Table 4–1. Timing Requirements for CLKIN for –400 Devices†‡§ (see Figure 4–1) –400 PLL MODE x12 NO. 1 2 3 4 MIN MAX 30 33.3 tc(CLKIN) tw(CLKINH) Cycle time, CLKIN Pulse duration, CLKIN high 0.4C tw(CLKINL) tt(CLKIN) Pulse duration, CLKIN low 0.4C PLL MODE x6 x1 (BYPASS) MIN MAX 13.3 33.3 0.4C MAX 13.3 33.3 0.45C 0.4C Transition time, CLKIN UNIT MIN ns 0.45C 5 ns ns 5 1 ns † The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN. ‡ For more details on the PLL multiplier factors (x6, x12), see the Clock PLL section of this data sheet. § C = CLKIN cycle time in ns. For example, when CLKIN frequency is 50 MHz, use C = 20 ns. Table 4–2. Timing Requirements for CLKIN for –500 Devices†‡§ (see Figure 4–1) 1 2 3 4 MIN MAX 24 33.3 PLL MODE x6 x1 (BYPASS) MIN MAX 13.3 33.3 UNIT MIN MAX 13.3 33.3 tc(CLKIN) tw(CLKINH) Cycle time, CLKIN Pulse duration, CLKIN high 0.4C 0.4C 0.45C ns tw(CLKINL) tt(CLKIN) Pulse duration, CLKIN low 0.4C 0.4C 0.45C ns Transition time, CLKIN 5 5 1 ns ns † The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN. ‡ For more details on the PLL multiplier factors (x6, x12), see the Clock PLL section of this data sheet. § C = CLKIN cycle time in ns. For example, when CLKIN frequency is 50 MHz, use C = 20 ns. Table 4–3. Timing Requirements for CLKIN for –600 Devices†‡§ (see Figure 4–1) –600 PLL MODE x12 NO. 1 2 3 4 PLL MODE x6 x1 (BYPASS) UNIT MIN MAX MIN MAX MIN MAX 20 33.3 13.3 33.3 13.3 33.3 tc(CLKIN) tw(CLKINH) Cycle time, CLKIN Pulse duration, CLKIN high 0.4C 0.4C 0.45C tw(CLKINL) tt(CLKIN) Pulse duration, CLKIN low 0.4C 0.4C 0.45C Transition time, CLKIN 5 5 ns ns ns 1 ns † The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN. ‡ For more details on the PLL multiplier factors (x6, x12), see the Clock PLL section of this data sheet. § C = CLKIN cycle time in ns. For example, when CLKIN frequency is 50 MHz, use C = 20 ns. 1 4 2 CLKIN 3 4 Figure 4–1. CLKIN Timing June 2003 SPRS222 111 PRODUCT PREVIEW –500 PLL MODE x12 NO. Input and Output Clocks Table 4–4. Switching Characteristics Over Recommended Operating Conditions for CLKOUT4†‡ (see Figure 4–2) NO. –400 –500 –600 PARAMETER UNIT CLKMODE = x1, x6, x12 MIN 1 2 3 4 MAX tc(CKO4) tw(CKO4H) Cycle time, CLKOUT4 4P – 0.7 4P + 0.7 ns Pulse duration, CLKOUT4 high 2P – 0.7 2P + 0.7 ns tw(CKO4L) tt(CKO4) Pulse duration, CLKOUT4 low 2P – 0.7 2P + 0.7 ns 1 ns Transition time, CLKOUT4 † The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN. ‡ P = 1/CPU clock frequency in nanoseconds (ns) 1 4 PRODUCT PREVIEW 2 CLKOUT4 3 4 Figure 4–2. CLKOUT4 Timing Table 4–5. Switching Characteristics Over Recommended Operating Conditions for CLKOUT6†‡ (see Figure 4–3) NO. –400 –500 –600 PARAMETER UNIT CLKMODE = x1, x6, x12 MIN 1 2 3 4 MAX tc(CKO6) tw(CKO6H) Cycle time, CLKOUT6 6P – 0.7 6P + 0.7 ns Pulse duration, CLKOUT6 high 3P – 0.7 3P + 0.7 ns tw(CKO6L) tt(CKO6) Pulse duration, CLKOUT6 low 3P – 0.7 3P + 0.7 ns 1 ns Transition time, CLKOUT6 † The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN. ‡ P = 1/CPU clock frequency in nanoseconds (ns) 1 4 2 CLKOUT6 3 4 Figure 4–3. CLKOUT6 Timing 112 SPRS222 June 2003 Input and Output Clocks Table 4–6. Timing Requirements for AECLKIN for EMIFA†‡ (see Figure 4–4) –400 –500 –600 NO. 1 2 3 4 tc(EKI) tw(EKIH) Cycle time, AECLKIN MIN 6§ Pulse duration, AECLKIN high 3.38 tw(EKIL) tt(EKI) Pulse duration, AECLKIN low 3.38 Transition time, AECLKIN UNIT MAX 16P ns ns ns 2 ns † P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. ‡ The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN. § Minimum AECLKIN times are based on internal logic speed; the maximum useable speed of the EMIF may be lower due to AC timing requirements. On the 600 devices, 133-MHz operation is achievable if the requirements of the EMIF Device Speed section are met. On the 500 and 400 devices, 100-MHz operation is achievable if the requirements of the EMIF Device Speed section are met. 1 AECLKIN 3 4 Figure 4–4. ECLKIN Timing for EMIFA Table 4–7. Switching Characteristics Over Recommended Operating Conditions for AECLKOUT1 for the EMIFA Module¶#|| (see Figure 4–5) NO. 1 2 3 4 5 6 –400 –500 –600 PARAMETER UNIT MIN MAX E – 0.7 E + 0.7 ns Pulse duration, AECLKOUT1 high EH – 0.7 EH + 0.7 ns Pulse duration, AECLKOUT1 low EL – 0.7 EL + 0.7 ns 1 ns 8 ns 8 ns tc(EKO1) tw(EKO1H) Cycle time, AECLKOUT1 tw(EKO1L) tt(EKO1) td(EKIH-EKO1H) td(EKIL-EKO1L) Delay time, AECLKIN high to AECLKOUT1 high 1 Delay time, AECLKIN low to AECLKOUT1 low 1 Transition time, AECLKOUT1 ¶ The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN. # E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA. || EH is the high period of E (EMIF input clock period) in ns and EL is the low period of E (EMIF input clock period) in ns for EMIFA. AECLKIN 6 5 1 2 3 4 4 AECLKOUT1 Figure 4–5. AECLKOUT1 Timing for the EMIFA Module June 2003 SPRS222 113 PRODUCT PREVIEW 4 2 Input and Output Clocks Table 4–8. Switching Characteristics Over Recommended Operating Conditions for AECLKOUT2 for the EMIFA Module†‡ (see Figure 4–6) NO. 1 2 3 4 5 6 –400 –500 –600 PARAMETER UNIT MIN MAX NE – 0.7 NE + 0.7 ns Pulse duration, AECLKOUT2 high 0.5NE – 0.7 0.5NE + 0.7 ns tw(EKO2L) tt(EKO2) Pulse duration, AECLKOUT2 low 0.5NE – 0.7 0.5NE + 0.7 ns td(EKIH-EKO2H) td(EKIH-EKO2L) Delay time, AECLKIN high to AECLKOUT2 high Delay time, AECLKIN high to AECLKOUT2 low tc(EKO2) tw(EKO2H) Cycle time, AECLKOUT2 Transition time, AECLKOUT2 1 ns 3 8 ns 3 8 ns † The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN. ‡ E = the EMIF input clock (AECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA. N = the EMIF input clock divider; N = 1, 2, or 4. PRODUCT PREVIEW 5 6 AECLKIN 1 2 3 4 4 AECLKOUT2 Figure 4–6. AECLKOUT2 Timing for the EMIFA Module 114 SPRS222 June 2003 Asynchronous Memory Timing 5 Asynchronous Memory Timing Table 5–1. Timing Requirements for Asynchronous Memory Cycles for EMIFA Module† (see Figure 5–1 and Figure 5–2) –400 –500 –600 NO. MIN 3 4 6 UNIT MAX tsu(EDV-AREH) th(AREH-EDV) Setup time, AEDx valid before AARE high 6.5 ns Hold time, AEDx valid after AARE high 1 ns tsu(ARDY-EKO1H) th(EKO1H-ARDY) Setup time, AARDY valid before AECLKOUT1 high 3 ns 7 Hold time, AARDY valid after AECLKOUT1 high 1 ns † To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. The ARDY signal is recognized in the cycle for which the setup and hold time is met. To use ARDY as an asynchronous input, the pulse width of the ARDY signal should be wide enough (e.g., pulse width = 2E) to ensure setup and hold time is met. NO. PARAMETER –400 –500 –600 MIN 1 2 5 8 9 UNIT MAX tosu(SELV-AREL) toh(AREH-SELIV) Output setup time, select signals valid to AARE low RS * E – 1.5 Output hold time, AARE high to select signals invalid RH * E – 1.9 td(EKO1H-AREV) tosu(SELV-AWEL) Delay time, AECLKOUT1 high to AARE valid Output setup time, select signals valid to AAWE low WS * E – 1.7 ns toh(AWEH-SELIV) td(EKO1H-AWEV) Output hold time, AAWE high to select signals invalid WH * E – 1.8 ns 1 ns ns 7 ns 10 Delay time, AECLKOUT1 high to AAWE valid 1.3 7.1 ns ‡ RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are programmed via the EMIF CE space control registers. § E = AECLKOUT1 period in ns for EMIFA ¶ Select signals for EMIFA include: ACEx, ABE[3:0], AEA[22:3], AAOE; and for EMIFA writes, include AED[31:0]. June 2003 SPRS222 115 PRODUCT PREVIEW Table 5–2. Switching Characteristics Over Recommended Operating Conditions for Asynchronous Memory Cycles for EMIFA Module‡§¶ (see Figure 5–1 and Figure 5–2) Asynchronous Memory Timing Setup = 2 Strobe = 3 Not Ready Hold = 2 AECLKOUT1 1 2 1 2 ACEx ABE[3:0] BE 2 1 AEA[22:3] Address 3 4 AED[31:0] 1 2 Read Data AAOE/ASDRAS/ASOE† PRODUCT PREVIEW 5 5 AARE/ASDCAS/ASADS/ASRE† AAWE/ASDWE/ASWE† 7 7 6 6 AARDY † AAOE/ASDRAS/ASOE, AARE/ASDCAS/ASADS/ASRE, and AAWE/ASDWE/ASWE operate as AAOE (identified under select signals), AARE, and AAWE, respectively, during asynchronous memory accesses. Figure 5–1. Asynchronous Memory Read Timing for EMIFA 116 SPRS222 June 2003 Asynchronous Memory Timing Setup = 2 Strobe = 3 Hold = 2 Not Ready AECLKOUT1 9 8 ACEx 9 8 ABE[3:0] BE 9 8 AEA[22:3] Address 9 8 AED[31:0] Write Data AAOE/ASDRAS/ASOE† AARE/ASDCAS/ASADS/ASRE† AAWE/ASDWE/ASWE† 7 6 7 6 AARDY † AAOE/ASDRAS/ASOE, AARE/ASDCAS/ASADS/ASRE, and AAWE/ASDWE/ASWE operate as AAOE (identified under select signals), AARE, and AAWE, respectively, during asynchronous memory accesses. Figure 5–2. Asynchronous Memory Write Timing for EMIFA June 2003 SPRS222 117 PRODUCT PREVIEW 10 10 Programmable Synchronous Interface Timing 6 Programmable Synchronous Interface Timing Table 6–1. Timing Requirements for Programmable Synchronous Interface Cycles for EMIFA Module† (see Figure 6–1) –400 NO. MIN –500 MAX MIN –600 MAX MIN MAX UNIT 6 tsu(EDV-EKOxH) Setup time, read AEDx valid before AECLKOUTx high 3.1 3.1 2 ns 7 th(EKOxH-EDV) Hold time, read AEDx valid after AECLKOUTx high 1.5 1.5 1.5 ns PRODUCT PREVIEW † The following parameters are programmable via the EMIF CE Space Secondary Control register (CExSEC): – Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency – Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency – ACEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, ACEx goes inactive after the final command has been issued (CEEXT = 0). For synchronous FIFO interface with glue, ACEx is active when ASOE is active (CEEXT = 1). – Function of ASADS/ASRE (RENEN): For standard SBSRAM or ZBT SRAM interface, ASADS/ASRE acts as ASADS with deselect cycles (RENEN = 0). For FIFO interface, ASADS/ASRE acts as ASRE with NO deselect cycles (RENEN = 1). – Synchronization clock (SNCCLK): Synchronized to AECLKOUT1 or AECLKOUT2 Table 6–2. Switching Characteristics Over Recommended Operating Conditions for Programmable Synchronous Interface Cycles for EMIFA Module† (see Figure 6–1–Figure 6–3) –400 NO. 1 PARAMETER –500 –600 UNIT MIN MAX MIN MAX MIN MAX 1.3 6.4 1.3 6.4 1.3 4.9 ns 4.9 ns td(EKOxH-CEV) td(EKOxH-BEV) Delay time, AECLKOUTx high to ACEx valid td(EKOxH-BEIV) td(EKOxH-EAV) Delay time, AECLKOUTx high to ABEx invalid 4 5 td(EKOxH-EAIV) Delay time, AECLKOUTx high to AEAx invalid 1.3 8 td(EKOxH-ADSV) Delay time, AECLKOUTx high to ASADS/ASRE valid 1.3 6.4 1.3 6.4 1.3 4.9 ns 9 td(EKOxH-OEV) td(EKOxH-EDV) Delay time, AECLKOUTx high to, ASOE valid 1.3 6.4 1.3 6.4 1.3 4.9 ns 4.9 ns td(EKOxH-EDIV) td(EKOxH-WEV) Delay time, AECLKOUTx high to AEDx invalid 1.3 Delay time, AECLKOUTx high to ASWE valid 1.3 2 3 10 11 12 Delay time, AECLKOUTx high to ABEx valid 6.4 1.3 Delay time, AECLKOUTx high to AEAx valid 6.4 1.3 6.4 Delay time, AECLKOUTx high to AEDx valid 1.3 6.4 1.3 6.4 1.3 6.4 1.3 SPRS222 1.3 ns 1.3 6.4 1.3 ns ns ns † The following parameters are programmable via the EMIF CE Space Secondary Control register (CExSEC): – Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency – Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency – ACEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, ACEx goes inactive after the final command has been issued (CEEXT = 0). For synchronous FIFO interface with glue, ACEx is active when ASOE is active (CEEXT = 1). – Function of ASADS/ASRE (RENEN): For standard SBSRAM or ZBT SRAM interface, ASADS/ASRE acts as ASADS with deselect cycles (RENEN = 0). For FIFO interface, ASADS/ASRE acts as ASRE with NO deselect cycles (RENEN = 1). – Synchronization clock (SNCCLK): Synchronized to AECLKOUT1 or AECLKOUT2 118 6.4 ns 4.9 4.9 June 2003 Programmable Synchronous Interface Timing READ latency = 2 AECLKOUTx 1 1 ACEx ABE[3:0] 2 BE1 3 BE2 BE3 BE4 4 AEA[22:3] EA1 5 EA3 EA2 6 AED[31:0] EA4 7 Q1 Q2 Q3 Q4 8 8 AARE/ASDCAS/ASADS/ ASRE§ 9 9 AAOE/ASDRAS/ASOE§ † The read latency and the length of ACEx assertion are programmable via the SYNCRL and CEEXT fields, respectively, in the EMIFA CE Space Secondary Control register (CExSEC). In this figure, SYNCRL = 2 and CEEXT = 0. ‡ The following parameters are programmable via the EMIF CE Space Secondary Control register (CExSEC): – Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency – Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency – ACEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, ACEx goes inactive after the final command has been issued (CEEXT = 0). For synchronous FIFO interface with glue, ACEx is active when ASOE is active (CEEXT = 1). – Function of ASADS/ASRE (RENEN): For standard SBSRAM or ZBT SRAM interface, ASADS/ASRE acts as ASADS with deselect cycles (RENEN = 0). For FIFO interface, ASADS/ASRE acts as ASRE with NO deselect cycles (RENEN = 1). – Synchronization clock (SNCCLK): Synchronized to AECLKOUT1 or AECLKOUT2 § AARE/ASDCAS/ASADS/ASRE, AAOE/ASDRAS/ASOE, and AAWE/ASDWE/ASWE operate as ASADS/ASRE, ASOE, and ASWE, respectively, during programmable synchronous interface accesses. Figure 6–1. Programmable Synchronous Interface Read Timing for EMIFA (With Read Latency = 2)†‡ June 2003 SPRS222 119 PRODUCT PREVIEW AAWE/ASDWE/ASWE§ Programmable Synchronous Interface Timing AECLKOUTx 1 1 ACEx ABE[3:0] 2 BE1 AEA[22:3] 4 EA1 EA2 EA3 EA4 10 Q1 Q2 Q3 Q4 10 AED[31:0] AARE/ASDCAS/ASADS/ASRE§ 3 BE2 BE3 BE4 5 11 8 8 AAOE/ASDRAS/ASOE§ 12 12 PRODUCT PREVIEW AAWE/ASDWE/ASWE§ † The write latency and the length of ACEx assertion are programmable via the SYNCWL and CEEXT fields, respectively, in the EMIFA CE Space Secondary Control register (CExSEC). In this figure, SYNCWL = 0 and CEEXT = 0. ‡ The following parameters are programmable via the EMIF CE Space Secondary Control register (CExSEC): – Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency – Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency – ACEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, ACEx goes inactive after the final command has been issued (CEEXT = 0). For synchronous FIFO interface with glue, ACEx is active when ASOE is active (CEEXT = 1). – Function of ASADS/ASRE (RENEN): For standard SBSRAM or ZBT SRAM interface, ASADS/ASRE acts as ASADS with deselect cycles (RENEN = 0). For FIFO interface, ASADS/ASRE acts as ASRE with NO deselect cycles (RENEN = 1). – Synchronization clock (SNCCLK): Synchronized to AECLKOUT1 or AECLKOUT2 § AARE/ASDCAS/ASADS/ASRE, AAOE/ASDRAS/ASOE, and AAWE/ASDWE/ASWE operate as ASADS/ASRE, ASOE, and ASWE, respectively, during programmable synchronous interface accesses. Figure 6–2. Programmable Synchronous Interface Write Timing for EMIFA (With Write Latency = 0)†‡§ 120 SPRS222 June 2003 Programmable Synchronous Interface Timing Write Latency = 1‡ AECLKOUTx 1 1 ACEx ABE[3:0] 2 BE1 3 BE2 BE3 BE4 EA2 10 EA3 EA4 Q1 Q2 Q3 5 4 AEA[22:3] EA1 10 AED[31:0] 11 Q4 8 8 AARE/ASDCAS/ASADS/ ASRE§ AAOE/ASDRAS/ASOE§ 12 12 † The write latency and the length of ACEx assertion are programmable via the SYNCWL and CEEXT fields, respectively, in the EMIFA CE Space Secondary Control register (CExSEC). In this figure, SYNCWL = 1 and CEEXT = 0. ‡ The following parameters are programmable via the EMIF CE Space Secondary Control register (CExSEC): – Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency – Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency – ACEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, ACEx goes inactive after the final command has been issued (CEEXT = 0). For synchronous FIFO interface with glue, ACEx is active when ASOE is active (CEEXT = 1). – Function of ASADS/ASRE (RENEN): For standard SBSRAM or ZBT SRAM interface, ASADS/ASRE acts as ASADS with deselect cycles (RENEN = 0). For FIFO interface, ASADS/ASRE acts as ASRE with NO deselect cycles (RENEN = 1). – Synchronization clock (SNCCLK): Synchronized to AECLKOUT1 or AECLKOUT2 § AARE/ASDCAS/ASADS/ASRE, AAOE/ASDRAS/ASOE, and AAWE/ASDWE/ASWE operate as ASADS/ASRE, ASOE, and ASWE, respectively, during programmable synchronous interface accesses. Figure 6–3. Programmable Synchronous Interface Write Timing for EMIFA (With Write Latency = 1)†‡ June 2003 SPRS222 121 PRODUCT PREVIEW AAWE/ASDWE/ASWE§ Synchronous DRAM Timing 7 Synchronous DRAM Timing Table 7–1. Timing Requirements for Synchronous DRAM Cycles for EMIFA Module (see Figure 7–1) –400 NO. MIN –500 MAX MIN –600 MAX MIN UNIT MAX 6 tsu(EDV-EKO1H) Setup time, read AEDx valid before AECLKOUT1 high 2.1 2.1 0.6 ns 7 th(EKO1H-EDV) Hold time, read AEDx valid after AECLKOUT1 high 2.5 2.5 1.8 ns Table 7–2. Switching Characteristics Over Recommended Operating Conditions for Synchronous DRAM Cycles for EMIFA Module (see Figure 7–1–Figure 7–8) –400 NO. 1 UNIT MIN MAX MIN MAX 1.3 6.4 1.3 6.4 1.3 4.9 ns 4.9 ns Delay time, AECLKOUT1 high to ABEx invalid 4 td(EKO1H-BEIV) td(EKO1H-EAV) 5 td(EKO1H-EAIV) Delay time, AECLKOUT1 high to AEAx invalid 1.3 8 td(EKO1H-CASV) Delay time, AECLKOUT1 high to ASDCAS valid 1.3 9 td(EKO1H-EDV) td(EKO1H-EDIV) 10 –600 MAX Delay time, AECLKOUT1 high to ACEx valid 3 –500 MIN td(EKO1H-CEV) td(EKO1H-BEV) 2 PRODUCT PREVIEW PARAMETER Delay time, AECLKOUT1 high to ABEx valid 6.4 1.3 Delay time, AECLKOUT1 high to AEAx valid 6.4 1.3 6.4 Delay time, AECLKOUT1 high to AEDx valid 1.3 6.4 1.3 6.4 1.3 6.4 ns 4.9 1.3 6.4 1.3 6.4 1.3 ns ns 4.9 ns 4.9 ns Delay time, AECLKOUT1 high to AEDx invalid 1.3 1.3 ns 1.3 6.4 1.3 6.4 1.3 4.9 ns 11 td(EKO1H-WEV) Delay time, AECLKOUT1 high to ASDWE valid 12 td(EKO1H-RAS) Delay time, AECLKOUT1 high to ASDRAS valid 1.3 6.4 1.3 6.4 1.3 4.9 ns 13 td(EKO1H-ACKEV) Delay time, AECLKOUT1 high to ASDCKE valid 1.3 6.4 1.3 6.4 1.3 4.9 ns 14 td(EKO1H-PDTV) Delay time, AECLKOUT1 high to APDT valid 1.3 6.4 1.3 6.4 1.3 4.9 ns 122 SPRS222 June 2003 Synchronous DRAM Timing READ AECLKOUT1 1 1 ACEx 2 BE1 ABE[3:0] 4 Bank 5 AEA[22:14] 4 Column 5 AEA[12:3] 4 3 BE2 BE3 BE4 5 AEA13 6 AED[31:0] D1 7 D2 D3 D4 AARE/ASDCAS/ASADS/ ASRE† 8 8 AAWE/ASDWE/ASWE† 14 14 APDT‡ † AARE/ASDCAS/ASADS/ASRE, AAWE/ASDWE/ASWE, and AAOE/ASDRAS/ASOE operate as ASDCAS, ASDWE, and ASDRAS, respectively, during SDRAM accesses. ‡ APDT signal is only asserted when the EDMA is in PDT mode (set the PDTS bit to 1 in the EDMA options parameter RAM). For APDT read, data is not latched into EMIF. The PDTRL field in the PDT control register (PDTCTL) configures the latency of the APDT signal with respect to the data phase of a read transaction. The latency of the APDT signal for a read can be programmed to 0, 1, 2, or 3 by setting PDTRL to 00, 01, 10, or 11, respectively. PDTRL equals 00 (zero latency) in Figure 7–1. Figure 7–1. SDRAM Read Command (CAS Latency 3) for EMIFA June 2003 SPRS222 123 PRODUCT PREVIEW AAOE/ASDRAS/ASOE† Synchronous DRAM Timing WRITE AECLKOUT1 1 2 2 4 ACEx ABE[3:0] BE1 4 3 BE2 BE3 BE4 D2 D3 D4 5 Bank AEA[22:14] 5 4 Column AEA[12:3] 4 5 AEA13 9 AED[31:0] 10 9 D1 PRODUCT PREVIEW AAOE/ASDRAS/ASOE† 8 8 11 11 AARE/ASDCAS/ASADS/ ASRE† AAWE/ASDWE/ASWE† 14 14 APDT‡ † AARE/ASDCAS/ASADS/ASRE, AAWE/ASDWE/ASWE, and AAOE/ASDRAS/ASOE operate as ASDCAS, ASDWE, and ASDRAS, respectively, during SDRAM accesses. ‡ APDT signal is only asserted when the EDMA is in PDT mode (set the PDTD bit to 1 in the EDMA options parameter RAM). For APDT write, data is not driven (in High-Z). The PDTWL field in the PDT control register (PDTCTL) configures the latency of the APDT signal with respect to the data phase of a write transaction. The latency of the APDT signal for a write transaction can be programmed to 0, 1, 2, or 3 by setting PDTWL to 00, 01, 10, or 11, respectively. PDTWL equals 00 (zero latency) in Figure 7–2. Figure 7–2. SDRAM Write Command for EMIFA 124 SPRS222 June 2003 Synchronous DRAM Timing ACTV AECLKOUT1 1 1 ACEx ABE[3:0] 4 Bank Activate 5 AEA[22:14] 4 Row Address 5 AEA[12:3] 4 Row Address 5 AEA13 AED[31:0] 12 12 AARE/ASDCAS/ASADS/ ASRE† AAWE/ASDWE/ASWE† † AARE/ASDCAS/ASADS/ASRE, AAWE/ASDWE/ASWE, and AAOE/ASDRAS/ASOE operate as ASDCAS, ASDWE, and ASDRAS, respectively, during SDRAM accesses. Figure 7–3. SDRAM ACTV Command for EMIFA DCAB AECLKOUT1 1 1 4 5 12 12 11 11 ACEx ABE[3:0] AEA[22:14, 12:3] AEA13 AED[31:0] AAOE/ASDRAS/ASOE† AARE/ASDCAS/ASADS/ ASRE† AAWE/ASDWE/ASWE† † AARE/ASDCAS/ASADS/ASRE, AAWE/ASDWE/ASWE, and AAOE/ASDRAS/ASOE operate as ASDCAS, ASDWE, and ASDRAS, respectively, during SDRAM accesses. Figure 7–4. SDRAM DCAB Command for EMIFA June 2003 SPRS222 125 PRODUCT PREVIEW AAOE/ASDRAS/ASOE† Synchronous DRAM Timing DEAC AECLKOUT1 1 1 ACEx ABE[3:0] 4 AEA[22:14] 5 Bank AEA[12:3] 4 5 12 12 11 11 AEA13 AED[31:0] AAOE/ASDRAS/ASOE† PRODUCT PREVIEW AARE/ASDCAS/ASADS/ ASRE† AAWE/ASDWE/ASWE† † AARE/ASDCAS/ASADS/ASRE, AAWE/ASDWE/ASWE, and AAOE/ASDRAS/ASOE operate as ASDCAS, ASDWE, and ASDRAS, respectively, during SDRAM accesses. Figure 7–5. SDRAM DEAC Command for EMIFA REFR AECLKOUT1 1 1 12 12 8 8 ACEx ABE[3:0] AEA[22:14, 12:3] AEA13 AED[31:0] AAOE/ASDRAS/ASOE† AARE/ASDCAS/ASADS/ ASRE† AAWE/ASDWE/ASWE† † AARE/ASDCAS/ASADS/ASRE, AAWE/ASDWE/ASWE, and AAOE/ASDRAS/ASOE operate as ASDCAS, ASDWE, and ASDRAS, respectively, during SDRAM accesses. Figure 7–6. SDRAM REFR Command for EMIFA 126 SPRS222 June 2003 Synchronous DRAM Timing MRS AECLKOUT1 1 1 4 MRS value 5 12 12 8 8 11 11 ACEx ABE[3:0] AEA[22:3] AED[31:0] AAOE/ASDRAS/ ASOE† AARE/ASDCAS/ASADS/ ASRE† † AARE/ASDCAS/ASADS/ASRE, AAWE/ASDWE/ASWE, and AAOE/ASDRAS/ASOE operate as ASDCAS, ASDWE, and ASDRAS, respectively, during SDRAM accesses. Figure 7–7. SDRAM MRS Command for EMIFA ≥ TRAS cycles End Self-Refresh Self Refresh AECLKOUT1 ACEx ABE[3:0] AEA[22:14, 12:3] AEA13 AED[31:0] AAOE/ASDRAS/ASOE† AARE/ASDCAS/ASADS/ ASRE† AAWE/ASDWE/ASWE† 13 13 ASDCKE † AARE/ASDCAS/ASADS/ASRE, AAWE/ASDWE/ASWE, and AAOE/ASDRAS/ASOE operate as ASDCAS, ASDWE, and ASDRAS, respectively, during SDRAM accesses. Figure 7–8. SDRAM Self-Refresh Timing for EMIFA June 2003 SPRS222 127 PRODUCT PREVIEW AAWE/ASDWE/ASWE† AHOLD/AHOLDA Timing 8 AHOLD/AHOLDA Timing Table 8–1. Timing Requirements for the AHOLD/AHOLDA Cycles for EMIFA Module† (see Figure 8–1) –400 NO. 3 MIN toh(HOLDAL-HOLDL) Hold time, AHOLD low after AHOLDA low –500 MAX MIN E –600 MAX E MIN UNIT MAX E ns † E = the EMIF input clock (AECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA. Table 8–2. Switching Characteristics Over Recommended Operating Conditions for the AHOLD/AHOLDA Cycles for EMIFA Module†‡§ (see Figure 8–1) –400 PRODUCT PREVIEW NO. PARAMETER –500 –600 UNIT MIN MAX MIN MAX MIN MAX 2E ¶ 2E ¶ 2E ¶ ns 0 2E 0 2E 0 2E ns 1 td(HOLDL-EMHZ) Delay time, AHOLD low to EMIFA Bus high impedance 2 td(EMHZ-HOLDAL) Delay time, EMIF Bus high impedance to AHOLDA low 4 td(HOLDH-EMLZ) Delay time, AHOLD high to EMIF Bus low impedance 2E 7E 2E 7E 2E 7E ns 5 td(EMLZ-HOLDAH) Delay time, EMIFA Bus low impedance to AHOLDA high 0 2E 0 2E 0 2E ns 6 td(HOLDL-EKOHZ) Delay time, AHOLD low to AECLKOUTx high impedance 2E ¶ 2E ¶ 2E ¶ ns 7 td(HOLDH-EKOLZ) Delay time, AHOLD high to AECLKOUTx low impedance 2E 7E 2E 7E 2E 7E ns † E = the EMIF input clock (AECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA. ‡ EMIFA Bus consists of: ACE[3:0], ABE[3:0], AED[31:0], AEA[22:3], AARE/ASDCAS/ASADS/ASRE, AAOE/ASDRAS/ASOE, and AAWE/ASDWE/ASWE , ASDCKE, ASOE3, and APDT. § The EKxHZ bits in the EMIF Global Control register (GBLCTL) determine the state of the AECLKOUTx signals during AHOLDA. If EKxHZ = 0, AECLKOUTx continues clocking during Hold mode. If EKxHZ = 1, AECLKOUTx goes to high impedance during Hold mode, as shown in Figure 8–1. ¶ All pending EMIF transactions are allowed to complete before HOLDA is asserted. If no bus transactions are occurring, then the minimum delay time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1. External Requestor Owns Bus DSP Owns Bus DSP Owns Bus 3 AHOLD 2 5 AHOLDA EMIFA Bus† 1 4 C64x C64x AECLKOUTx 6 7 AECLKOUTx † EMIFA Bus consists of: ACE[3:0], ABE[3:0], AED[31:0], AEA[22:3], AARE/ASDCAS/ASADS/ASRE, AAOE/ASDRAS/ASOE, and AAWE/ASDWE/ASWE, ASDCKE, ASOE3, and APDT. Figure 8–1. AHOLD/AHOLDA Timing for EMIFA 128 SPRS222 June 2003 ABUSREQ Timing 9 ABUSREQ Timing Table 9–1. Switching Characteristics Over Recommended Operating Conditions for the ABUSREQ Cycles for EMIFA Module (see Figure 9–1) –400 NO. 1 PARAMETER td(AEKO1H-ABUSRV) Delay time, AECLKOUT1 high to ABUSREQ valid –500 –600 MIN MAX MIN MAX MIN MAX 0.6 7.1 0.6 7.1 1 5.5 UNIT ns AECLKOUT1 1 1 ABUSREQ PRODUCT PREVIEW Figure 9–1. ABUSREQ Timing for EMIFA June 2003 SPRS222 129 Reset Timing 10 Reset Timing Table 10–1. Timing Requirements for Reset (see Figure 10–1) –400 –500 –600 NO. MIN 1 16 tw(RST) tsu(boot) 17 Width of the RESET pulse Setup time, boot configuration bits valid before RESET high† Hold time, boot configuration bits valid after RESET high† UNIT MAX 250 µs 4E or 4C‡ 4E or 4C‡ ns th(boot) † AEA[22:19], LEND, BOOTMODE[1:0], ECLKIN_SEL[1:0], and HD5 are the boot configuration pins during device reset. ‡ E = 1/AECLKIN clock frequency in ns. C = 1/CLKIN clock frequency in ns. Select the MIN parameter value, whichever value is larger. ns Table 10–2. Switching Characteristics Over Recommended Operating Conditions During Reset§¶# (see Figure 10–1) PRODUCT PREVIEW NO. 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PARAMETER –400 –500 –600 UNIT MIN MAX td(RSTL-ECKI) td(RSTH-ECKI) Delay time, RESET low to AECLKIN synchronized internally 2E 3P + 20E ns Delay time, RESET high to AECLKIN synchronized internally 2E 8P + 20E ns td(RSTL-ECKO1HZ) td(RSTH-ECKO1V) Delay time, RESET low to AECLKOUT1 high impedance 2E td(RSTL-EMIFZHZ) td(RSTH-EMIFZV) Delay time, RESET low to EMIF Z high impedance td(RSTL-EMIFHIV) td(RSTH-EMIFHV) Delay time, RESET low to EMIF high group invalid td(RSTL-EMIFLIV) td(RSTH-EMIFLV) Delay time, RESET low to EMIF low group invalid td(RSTL-LOWIV) td(RSTH-LOWV) Delay time, RESET low to low group invalid td(RSTL-ZHZ) td(RSTH-ZV) Delay time, RESET low to Z group high impedance Delay time, RESET high to AECLKOUT1 valid Delay time, RESET high to EMIF Z valid ns 2E 3P + 4E ns 16E 8P + 20E ns 2E Delay time, RESET high to EMIF high group valid ns 8P + 20E 2E Delay time, RESET high to EMIF low group valid 8P + 20E ns ns 11P 0 2P ns ns 0 Delay time, RESET high to low group valid Delay time, RESET high to Z group valid ns 8P + 20E ns ns 8P ns § P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. ¶ E = the EMIF input clock (AECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA. # EMIF Z group consists of: AEA[22:3], AED[31:0], ACE[3:0], ABE[3:0], AARE/ASDCAS/ASADS/ASRE,AAWE/ASDWE/ASWE, AAOE/ASDRAS/ASOE, ASOE3, ASDCKE, and APDT. EMIF high group consists of: AHOLDA (when the corresponding AHOLD input is high) EMIF low group consists of: ABUSREQ; AHOLDA (when the corresponding AHOLD input is low) Low group consists of: Z group consists of: HD[15:0], VP0D[0]/CLKX0, VP0D[1]/FSX0, VP0D[2]/DX0, CLKR0, VP0D[5]/FSR0, TOUT0, TOUT1, VDAC, GP0[7:0], HR/W, HDS2, HDS1, HCS, HCNTL1, HAS, HCNTL0, HHWIL (16-bit HPI mode only), HRDY, HINT, and VP0D[4,3]. VP1 signals apply to DM641 only: VP1D[0]/CLKX1, VP1D[1]/FSX1, VP1D[2]/DX1, VP1D[6]/CLKR1, VP1D[5]/FSR1, and VP1D[4,3]. 130 SPRS222 June 2003 Reset Timing CLKOUT4 CLKOUT6 1 RESET 2 3 4 5 6 7 AECLKIN AECLKOUT1 AECLKOUT2 EMIF Z Group†‡ 8 9 10 11 EMIF Low Group† 12 13 14 15 Low Group† Z Group†‡ 17 Boot and Device Configuration Inputs§ 16 † EMIF Z group consists of: AEA[22:3], AED[31:0], ACE[3:0], ABE[3:0], AARE/ASDCAS/ASADS/ASRE,AAWE/ASDWE/ASWE, AAOE/ASDRAS/ASOE, ASOE3, ASDCKE, and APDT. EMIF high group consists of: AHOLDA (when the corresponding AHOLD input is high) EMIF low group consists of: ABUSREQ; AHOLDA (when the corresponding AHOLD input is low) Low group consists of: Z group consists of: HD[15:0], VP0D[0]/CLKX0, VP0D[1]/FSX0, VP0D[2]/DX0, CLKR0, VP0D[5]/FSR0, TOUT0, TOUT1, VDAC, GP0[7:0], HR/W, HDS2, HDS1, HCS, HCNTL1, HAS, HCNTL0, HHWIL (16-bit HPI mode only), HRDY, HINT, and VP0D[4,3]. VP1 signals apply to DM641 only: VP1D[0]/CLKX1, VP1D[1]/FSX1, VP1D[2]/DX1, VP1D[6]/CLKR1, VP1D[5]/FSR1, and VP1D[4,3]. ‡ If AEA[22:19], LEND, BOOTMODE[1:0], ECLKIN_SEL[1:0], and HD5 pins are actively driven, care must be taken to ensure no timing contention between parameters 6, 7, 14, 15, 16, and 17. § Boot and Device Configurations Inputs (during reset) include: AEA[22:19],LEND, BOOTMODE[1:0], ECLKIN_SEL[1:0], and HD5. Figure 10–1. Reset Timing† June 2003 SPRS222 131 PRODUCT PREVIEW EMIF High Group† External Interrupt Timing 11 External Interrupt Timing Table 11–1. Timing Requirements for External Interrupts† (see Figure 11–1) –400 –500 –600 NO. MIN 1 2 tw(ILOW) tw(IHIGH) UNIT MAX Width of the interrupt pulse low 4P ns Width of the interrupt pulse high 4P ns † P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. 1 2 EXT_INTx, NMI PRODUCT PREVIEW Figure 11–1. External/NMI Interrupt Timing 132 SPRS222 June 2003 Multichannel Audio Serial Port (McASP) Timing 12 Multichannel Audio Serial Port (McASP) Timing Table 12–1. Timing Requirements for McASP†‡ (see Figure 12–1 and Figure 12–2) –400 –500 –600 MIN 1 2 3 4 5 MAX tc(AHCKRX) tw(AHCKRX) Cycle time, AHCLKR/X 20 ns Pulse duration, AHCLKR/X high or low 10 ns tc(CKRX) tw(CKRX) Cycle time, ACLKR/X ACLKR/X ext 33 ns Pulse duration, ACLKR/X high or low ACLKR/X ext 16.5 ns ACLKR/X int 5 ns ACLKR/X ext 5 ns ACLKR/X int 5 ns ACLKR/X ext 5 ns tsu(FRXC-KRX) Setup time, AFSR/X input valid before ACLKR/X latches data 6 th(CKRX-FRX) Hold time, AFSR/X input valid after ACLKR/X latches data 7 tsu(AXR-CKRX) Setup time, AXR input valid before ACLKR/X latches data 8 UNIT th(CKRX-AXR) Hold time, AXR input valid after ACLKR/X latches data ACLKR/X int 5 ns ACLKR/X ext 5 ns ACLKR/X int 5 ns ACLKR/X ext 5 ns Table 12–2. Switching Characteristics Over Recommended Operating Conditions for McASP (see Figure 12–1 and Figure 12–2) NO. –400 –500 –600 PARAMETER MIN 9 10 11 12 13 UNIT MAX tc(AHCKRX) tw(AHCKRX) Cycle time, AHCLKR/X 20 ns Pulse duration, AHCLKR/X high or low 10 ns tc(CKRX) tw(CKRX) Cycle time, ACLKR/X ACLKR/X int 33 ns Pulse duration, ACLKR/X high or low ACLKR/X int 16.5 ACLKR/X int 0 10 ns ACLKR/X ext 0 10 ns ACLKR/X int 0 10 ns ACLKR/X ext 0 10 ns ACLKR/X int 0 10 ns ACLKR/X ext 0 10 ns td(CKRX-FRX) Delay time, ACLKR/X transmit edge to AFSX/R output valid 14 td(CKRX-AXRV) Delay time, ACLKR/X transmit edge to AXR output valid 15 tdis(CKRX–AXRHZ) Disable time, AXR high impedance following last data bit from ACLKR/X transmit edge June 2003 ns SPRS222 133 PRODUCT PREVIEW NO. Multichannel Audio Serial Port (McASP) Timing 2 1 2 AHCLKR/X (Falling Edge Polarity) AHCLKR/X (Rising Edge Polarity) 4 3 4 ACLKR/X (Falling Edge Polarity) ACLKR/X (Rising Edge Polarity) 6 5 AFSR/X (Bit Width, 0 Bit Delay) PRODUCT PREVIEW AFSR/X (Bit Width, 1 Bit Delay) AFSR/X (Bit Width, 2 Bit Delay) AFSR/X (Slot Width, 0 Bit Delay) AFSR/X (Slot Width, 1 Bit Delay) AFSR/X (Slot Width, 2 Bit Delay) 8 7 AXR[n] (Data In/Receive) A0 A1 A30 A31 B0 B1 B30 B31 C0 C1 C2 C3 C31 Figure 12–1. McASP Input Timings 134 SPRS222 June 2003 Multichannel Audio Serial Port (McASP) Timing 10 10 9 AHCLKR/X (Falling Edge Polarity) AHCLKR/X (Rising Edge Polarity) 12 11 12 ACLKR/X (Falling Edge Polarity) ACLKR/X (Rising Edge Polarity) 13 13 13 13 AFSR/X (Bit Width, 0 Bit Delay) PRODUCT PREVIEW AFSR/X (Bit Width, 1 Bit Delay) AFSR/X (Bit Width, 2 Bit Delay) 13 13 13 AFSR/X (Slot Width, 0 Bit Delay) AFSR/X (Slot Width, 1 Bit Delay) 14 AFSR/X (Slot Width, 2 Bit Delay) 14 14 14 15 14 14 AXR[n] (Data Out/Transmit) A0 A1 A30 A31 B0 B1 B30 B31 C0 C1 C2 C3 C31 Figure 12–2. McASP Output Timings June 2003 SPRS222 135 Inter-Integrated Circuits (I2C) Timing 13 Inter-Integrated Circuits (I2C) Timing Table 13–1. Timing Requirements for I2C Timings† (see Figure 13–1) –400 –500 –600 NO. STANDARD MODE MIN 1 tc(SCL) 2 Setup time, SCL high before SDA low (for a repeated START tsu(SCLH-SDAL) condition) 3 Hold time, SCL low after SDA low (for a START and a repeated th(SCLL-SDAL) START condition) 4 tw(SCLL) tw(SCLH) 5 6 PRODUCT PREVIEW 7 8 9 10 12 Pulse duration, SCL low Pulse duration, SCL high 14 15 4.7 0.6 µs 4 0.6 µs 4.7 1.3 µs 4 0.6 100‡ 0§ µs 0.9¶ 1.3 20 + 0.1Cb# 300 ns 300 ns 300 ns 300 ns 4.7 tw(SP) Cb# MAX µs tw(SDAH) tr(SDA) Rise time, SDA 1000 Rise time, SCL 1000 Fall time, SDA 300 20 + 0.1Cb# 20 + 0.1Cb# 300 20 + 0.1Cb# tf(SCL) Fall time, SCL tsu(SCLH-SDAH) Setup time, SCL high before SDA high (for STOP condition) 13 MIN 2.5 250 0§ Pulse duration, SDA high between STOP and START conditions MAX 10 tsu(SDAV-SDLH) Setup time, SDA valid before SCL high th(SDA-SDLL) Hold time, SDA valid after SCL low (For I2C bus devices) tr(SCL) tf(SDA) 11 Cycle time, SCL UNIT FAST MODE 4 ns µs µs 0.6 Pulse duration, spike (must be suppressed) 0 Capacitive load for each bus line µs 400 50 ns 400 pF † The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered down. ‡ A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tsu(SDA–SCLH) ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDA–SCLH) = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-Bus Specification) before the SCL line is released. § A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL. ¶ The maximum th(SDA–SCLL) has only to be met if the device does not stretch the low period [tw(SCLL)] of the SCL signal. # Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed. 11 9 SDA 6 8 14 4 13 5 10 SCL 1 12 3 2 7 3 Stop Start Repeated Start Stop Figure 13–1. I2C Receive Timings 136 SPRS222 June 2003 Inter-Integrated Circuits (I2C) Timing Table 13–2. Switching Characteristics for I2C Timings† (see Figure 13–2) –400 –500 –600 PARAMETER 16 tc(SCL) Cycle time, SCL td(SCLH-SDAL) Delay time, SCL high to SDA low (for a repeated START condition) STANDARD MODE MIN 17 18 19 20 21 22 23 24 25 26 27 28 MAX UNIT FAST MODE MIN MAX 10 2.5 µs 4.7 0.6 µs 4 0.6 µs 4.7 1.3 µs 4 0.6 µs td(SDAV-SDLH) Delay time, SDA valid to SCL high tv(SDLL-SDAV) Valid time, SDA valid after SCL low (For I2C bus devices) 250 100 0 0 tw(SDAH) tr(SDA) Pulse duration, SDA high between STOP and START conditions 4.7 Rise time, SDA 1000 1.3 20 + 0.1Cb† tr(SCL) tf(SDA) Rise time, SCL 1000 Fall time, SDA Delay time, SDA low to SCL low (for a START and a repeated td(SDAL-SCLL) START condition) tw(SCLL) tw(SCLH) Pulse duration, SCL low Pulse duration, SCL high tf(SCL) Fall time, SCL td(SCLH-SDAH) Delay time, SCL high to SDA high (for STOP condition) ns 0.9 µs µs 300 ns 300 ns 300 20 + 0.1Cb† 20 + 0.1Cb† 300 ns 300 20 + 0.1Cb† 300 4 29 Cp Capacitance for each I2C pin 10 † Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed. 10 26 ns µs 0.6 pF 24 SDA 21 23 19 28 20 25 SCL 16 27 18 17 22 18 Stop Start Repeated Start Stop Figure 13–2. I2C Transmit Timings June 2003 SPRS222 137 PRODUCT PREVIEW NO. Host-Port Interface (HPI) Timing 14 Host-Port Interface (HPI) Timing Table 14–1. Timing Requirements for Host-Port Interface Cycles†‡ (see Figure 14–1 through Figure 14–4) –400 –500 –600 NO. MIN 1 2 3 4 10 11 PRODUCT PREVIEW 12 tsu(SELV-HSTBL) th(HSTBL-SELV) Setup time, select signals§ valid before HSTROBE low Hold time, select signals§ valid after HSTROBE low tw(HSTBL) tw(HSTBH) Pulse duration, HSTROBE low tsu(SELV-HASL) th(HASL-SELV) 13 tsu(HDV-HSTBH) th(HSTBH-HDV) 14 th(HRDYL-HSTBL) 18 tsu(HASL-HSTBL) th(HSTBL-HASL) 19 UNIT MAX 5 ns 2.4 4P¶ ns 4P ns 5 ns Hold time, select signals§ valid after HAS low 2 ns Setup time, host data valid before HSTROBE high 5 ns 2.8 ns Hold time, HSTROBE low after HRDY low. HSTROBE should not be inactivated until HRDY is active (low); otherwise, HPI writes will not complete properly. 2 ns Setup time, HAS low before HSTROBE low 2 ns 2.1 ns Pulse duration, HSTROBE high between consecutive accesses Setup time, select signals§ valid before HAS low Hold time, host data valid after HSTROBE high Hold time, HAS low after HSTROBE low ns † HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. ‡ P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. § Select signals include: HCNTL[1:0] and HR/W. For HPI16 mode only, select signals also include HHWIL. ¶ Select the parameter value of 4P or 12.5 ns, whichever is larger. Table 14–2. Switching Characteristics Over Recommended Operating Conditions During Host-Port Interface Cycles†‡ (see Figure 14–1 through Figure 14–4) –400 –500 –600 NO. PARAMETER UNIT 6 td(HSTBL-HRDYH) Delay time, HSTROBE low to HRDY high# 7 td(HSTBL-HDLZ) Delay time, HSTROBE low to HD low impedance for an HPI read 8 9 td(HDV-HRDYL) toh(HSTBH-HDV) 15 td(HSTBH-HDHZ) Delay time, HSTROBE high to HD high impedance 12 ns 16 td(HSTBL-HDV) Delay time, HSTROBE low to HD valid (HPI16 only) 4P + 8 ns MIN MAX 1.3 4P + 8 ns 2 ns Delay time, HD valid to HRDY low –3 ns Output hold time, HD valid after HSTROBE high 1.5 ns † HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. ‡ P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. # This parameter is used during HPID reads and writes. For reads, at the beginning of the first half-word transfer (HPI16) on the falling edge of HSTROBE, the HPI sends the request to the EDMA internal address generation hardware, and HRDY remains high until the EDMA internal address generation hardware loads the requested data into HPID. For writes, HRDY goes high if the internal write buffer is full. 138 SPRS222 June 2003 Host-Port Interface (HPI) Timing HAS 1 1 2 2 HCNTL[1:0] 1 1 2 2 HR/W 1 1 2 2 HHWIL 4 3 HSTROBE† 3 HCS 15 9 7 15 9 16 HD[15:0] (output) 1st half-word 6 2nd half-word 8 HRDY † HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. PRODUCT PREVIEW Figure 14–1. HPI16 Read Timing (HAS Not Used, Tied High) [for DM641 Only] HAS† 19 11 19 10 11 10 HCNTL[1:0] 11 11 10 10 HR/W 11 11 10 10 HHWIL 4 3 HSTROBE‡ 18 18 HCS 15 7 9 15 16 9 HD[15:0] (output) 6 1st half-word 8 2nd half-word HRDY † For correct operation, strobe the HAS signal only once per HSTROBE active cycle. ‡ HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. Figure 14–2. HPI16 Read Timing (HAS Used) [for DM641 Only] June 2003 SPRS222 139 Host-Port Interface (HPI) Timing HAS 1 1 2 2 HCNTL[1:0] 1 1 2 2 HR/W 1 1 2 2 HHWIL 3 3 4 HSTROBE† HCS 12 12 13 13 HD[15:0] (input) 1st half-word 2nd half-word 6 14 HRDY PRODUCT PREVIEW † HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. Figure 14–3. HPI16 Write Timing (HAS Not Used, Tied High) [for DM641 Only] 19 HAS† 19 11 11 10 10 HCNTL[1:0] 11 11 10 10 HR/W 11 11 10 10 HHWIL 3 4 HSTROBE‡ 18 18 HCS 12 13 12 13 HD[15:0] (input) 1st half-word 6 2nd half-word 14 HRDY † For correct operation, strobe the HAS signal only once per HSTROBE active cycle. ‡ HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. Figure 14–4. HPI16 Write Timing (HAS Used) [for DM641 Only] 140 SPRS222 June 2003 Multichannel Buffered Serial Port (McBSP) Timing 15 Multichannel Buffered Serial Port (McBSP) Timing Table 15–1. Timing Requirements for McBSP†‡ (see Figure 15–1) –400 –500 –600 2 3 tc(CKRX) tw(CKRX) Cycle time, CLKR/X CLKR/X ext Pulse duration, CLKR/X high or CLKR/X low CLKR/X ext CLKR int 5 tsu(FRH-CKRL) Setup time, external FSR high before CLKR low 6 th(CKRL-FRH) Hold time, external FSR high after CLKR low 7 tsu(DRV-CKRL) Setup time, DR valid before CLKR low 8 th(CKRL-DRV) Hold time, DR valid after CLKR low 10 tsu(FXH-CKXL) Setup time, external FSX high before CLKX low 11 th(CKXL-FXH) Hold time, external FSX high after CLKX low MIN 4P§ UNIT MAX ns 0.5tc(CKRX) – 1¶ 9 CLKR ext 1.3 CLKR int 6 CLKR ext 3 CLKR int 8 CLKR ext 0.9 CLKR int 3 CLKR ext 3.1 CLKX int 9 CLKX ext 1.3 CLKX int 6 CLKX ext 3 ns ns ns ns ns ns ns † CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted. ‡ P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. § The maximum bit rate for McBSP-to-McBSP communications is 75 MHz for –600 devices and 66 MHz for –500, –400 devices; therefore, the minimum CLKR/X clock cycle is either four times the CPU cycle time (4P), or 13.3 ns (75 MHz) for –600 devices [or 15 ns (66 MHz) for –500, –400 devices], whichever value is larger. For example, when running parts at 600 MHz (P = 1.67 ns), use 13.3 ns as the minimum CLKR/X clock cycle (by setting the appropriate CLKGDV ratio or external clock source). When running parts at 500 MHz (P = 2 ns), use 15 ns as the minimum CLKR/X clock cycle. The maximum bit rate for McBSP-to-McBSP communications applies to the following hardware configuration: the serial port is a Master of the clock and frame syncs (with CLKR connected to CLKX, FSR connected to FSX, CLKXM = FSXM = 1, and CLKRM = FSRM = 0) in data delay 1 or 2 mode (R/XDATDLY = 01b or 10b) and the other device the McBSP communicates to is a Slave. ¶ This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle. June 2003 SPRS222 141 PRODUCT PREVIEW NO. Multichannel Buffered Serial Port (McBSP) Timing Table 15–2. Switching Characteristics Over Recommended Operating Conditions for McBSP†‡ (see Figure 15–1) PRODUCT PREVIEW NO. –400 –500 –600 PARAMETER Delay time, CLKS high to CLKR/X high for internal CLKR/X generated from CLKS input UNIT MIN MAX 1.4 10 4P§¶ C – 1# C + 1# ns ns 1 td(CKSH-CKRXH) 2 Cycle time, CLKR/X CLKR/X int 3 tc(CKRX) tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X int 4 td(CKRH-FRV) Delay time, CLKR high to internal FSR valid CLKR int –2.1 3 CLKX int –1.7 3 CLKX ext 1.7 9 CLKX int –3.9 4 CLKX ext CLKX int –2.1 –3.9 + D1|| 9 4 + D2|| CLKX ext –2.1 + D1|| 9 + D2|| 9 td(CKXH-FXV) Delay time, CLKX high to internal FSX valid 12 tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit from CLKX high 13 td(CKXH-DXV) Delay time, CLKX high to DX valid 14 td(FXH-DXV) ns ns Delay time, FSX high to DX valid FSX int –2.3 5.6 ONLY applies when in data delay 0 (XDATDLY = 00b) mode FSX ext 1.9 9 ns ns ns ns † CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted. ‡ Minimum delay times also represent minimum output hold times. § P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. ¶ The maximum bit rate for McBSP-to-McBSP communications is 75 MHz for –600 devices and 66 MHz for –500, –400 devices; therefore, the minimum CLKR/X clock cycle is either four times the CPU cycle time (4P), or 13.3 ns (75 MHz) for –600 devices [or 15 ns (66 MHz) for –500, –400 devices], whichever value is larger. For example, when running parts at 600 MHz (P = 1.67 ns), use 13.3 ns as the minimum CLKR/X clock cycle (by setting the appropriate CLKGDV ratio or external clock source). When running parts at 500 MHz (P = 2 ns), use 15 ns as the minimum CLKR/X clock cycle. The maximum bit rate for McBSP-to-McBSP communications applies to the following hardware configuration: the serial port is a Master of the clock and frame syncs (with CLKR connected to CLKX, FSR connected to FSX, CLKXM = FSXM = 1, and CLKRM = FSRM = 0) in data delay 1 or 2 mode (R/XDATDLY = 01b or 10b) and the other device the McBSP communicates to is a Slave. # C = H or L S = sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency) = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit (see ¶ footnote above). || Extra delay from CLKX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR. if DXENA = 0, then D1 = D2 = 0 if DXENA = 1, then D1 = 4P, D2 = 8P 142 SPRS222 June 2003 Multichannel Buffered Serial Port (McBSP) Timing CLKS 1 2 3 3 CLKR 4 4 FSR (int) 5 6 FSR (ext) 7 DR 8 Bit(n-1) (n-2) (n-3) 2 3 3 CLKX 9 FSX (int) FSX (ext) FSX (XDATDLY=00b) 14 13 Bit(n-1) 12 DX Bit 0 13 (n-2) (n-3) Figure 15–1. McBSP Timing Table 15–3. Timing Requirements for FSR When GSYNC = 1 (see Figure 15–2) –400 –500 –600 NO. MIN 1 2 tsu(FRH-CKSH) th(CKSH-FRH) UNIT MAX Setup time, FSR high before CLKS high 4 ns Hold time, FSR high after CLKS high 4 ns CLKS 1 2 FSR external CLKR/X (no need to resync) CLKR/X (needs resync) Figure 15–2. FSR Timing When GSYNC = 1 June 2003 SPRS222 143 PRODUCT PREVIEW 11 10 Multichannel Buffered Serial Port (McBSP) Timing Table 15–4. Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0†‡ (see Figure 15–3) –400 –500 –600 NO. MASTER MIN 4 5 tsu(DRV-CKXL) th(CKXL-DRV) Setup time, DR valid before CLKX low UNIT SLAVE MAX MIN MAX 12 2 – 12P ns 4 5 + 24P ns Hold time, DR valid after CLKX low † P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. ‡ For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1. Table 15–5. Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0†‡ (see Figure 15–3) NO. –400 –500 –600 PARAMETER PRODUCT PREVIEW MASTER§ 2 th(CKXL-FXL) td(FXL-CKXH) Hold time, FSX low after CLKX low¶ Delay time, FSX low to CLKX high# 3 td(CKXH-DXV) Delay time, CLKX high to DX valid 6 tdis(CKXL-DXHZ) Disable time, DX high impedance following last data bit from CLKX low 7 tdis(FXH-DXHZ) Disable time, DX high impedance following last data bit from FSX high 8 td(FXL-DXV) Delay time, FSX low to DX valid 1 UNIT SLAVE MIN MAX T–2 T+3 L–2 L+3 –2 4 L–2 L+3 MIN MAX ns ns 12P + 2.8 20P + 17 ns ns 4P + 3 12P + 17 ns 8P + 1.8 16P + 17 ns † P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. ‡ For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1. § S = Sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency) = Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero ¶ FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP # FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master clock (CLKX). CLKX 1 2 FSX 7 6 DX 8 3 Bit 0 Bit(n-1) 4 DR Bit 0 (n-2) (n-3) (n-4) 5 Bit(n-1) (n-2) (n-3) (n-4) Figure 15–3. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 144 SPRS222 June 2003 Multichannel Buffered Serial Port (McBSP) Timing Table 15–6. Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0†‡ (see Figure 15–4) –400 –500 –600 NO. MASTER MIN 4 5 tsu(DRV-CKXH) th(CKXH-DRV) Setup time, DR valid before CLKX high UNIT SLAVE MAX MIN MAX 12 2 – 12P ns 4 5 + 24P ns Hold time, DR valid after CLKX high † P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. ‡ For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1. Table 15–7. Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0†‡ (see Figure 15–4) PARAMETER MASTER§ MIN UNIT SLAVE MAX MIN MAX 2 th(CKXL-FXL) td(FXL-CKXH) Hold time, FSX low after CLKX low¶ Delay time, FSX low to CLKX high# 3 td(CKXL-DXV) Delay time, CLKX low to DX valid –2 4 12P + 4 20P + 17 ns 6 tdis(CKXL-DXHZ) Disable time, DX high impedance following last data bit from CLKX low –2 4 12P + 3 20P + 17 ns 7 td(FXL-DXV) Delay time, FSX low to DX valid 16P + 17 ns 1 L–2 L+3 ns T–2 T+3 ns H–2 H+4 8P + 2 † P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. ‡ For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1. § S = Sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency) = Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero ¶ FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP # FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master clock (CLKX). CLKX 1 2 6 Bit 0 7 FSX DX 3 Bit(n-1) 4 DR Bit 0 (n-2) (n-3) (n-4) 5 Bit(n-1) (n-2) (n-3) (n-4) Figure 15–4. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 June 2003 SPRS222 145 PRODUCT PREVIEW NO. –400 –500 –600 Multichannel Buffered Serial Port (McBSP) Timing Table 15–8. Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1†‡ (see Figure 15–5) –400 –500 –600 NO. MASTER MIN 4 5 tsu(DRV-CKXH) th(CKXH-DRV) Setup time, DR valid before CLKX high UNIT SLAVE MAX MIN MAX 12 2 – 12P ns 4 5 + 24P ns Hold time, DR valid after CLKX high † P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. ‡ For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1. Table 15–9. Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1†‡ (see Figure 15–5) NO. –400 –500 –600 PARAMETER PRODUCT PREVIEW MASTER§ MIN UNIT SLAVE MAX MIN MAX 2 th(CKXH-FXL) td(FXL-CKXL) Hold time, FSX low after CLKX high¶ 3 td(CKXL-DXV) Delay time, CLKX low to DX valid 6 tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit from CLKX high 7 tdis(FXH-DXHZ) Disable time, DX high impedance following last data bit from FSX high 4P + 3 12P + 17 ns 8 td(FXL-DXV) Delay time, FSX low to DX valid 8P + 2 16P + 17 ns 1 T–2 T+3 ns Delay time, FSX low to CLKX low# H–2 H+3 ns –2 H–2 4 12P + 4 20P + 17 H+3 ns ns † P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. ‡ For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1. § S = Sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency) = Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero ¶ FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP # FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master clock (CLKX). CLKX 1 2 FSX 7 6 DX 8 3 Bit 0 Bit(n-1) 4 DR Bit 0 (n-2) (n-3) (n-4) 5 Bit(n-1) (n-2) (n-3) (n-4) Figure 15–5. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 146 SPRS222 June 2003 Multichannel Buffered Serial Port (McBSP) Timing Table 15–10. Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1†‡ (see Figure 15–6) –400 –500 –600 NO. MASTER MIN 4 tsu(DRV-CKXH) th(CKXH-DRV) 5 Setup time, DR valid before CLKX high UNIT SLAVE MAX MIN MAX 12 2 – 12P ns 4 5 + 24P ns Hold time, DR valid after CLKX high † P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. ‡ For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1. Table 15–11. Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1†‡ (see Figure 15–6) PARAMETER MASTER§ UNIT SLAVE MIN MAX H–2 H+3 MIN MAX ns T–2 T+1 ns 2 th(CKXH-FXL) td(FXL-CKXL) Hold time, FSX low after CLKX high¶ Delay time, FSX low to CLKX low# 3 td(CKXH-DXV) Delay time, CLKX high to DX valid –2 4 12P + 4 20P + 17 ns 6 tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit from CLKX high –2 4 12P + 3 20P + 17 ns 7 td(FXL-DXV) Delay time, FSX low to DX valid 16P + 17 ns 1 L–2 L+4 8P + 2 † P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. ‡ For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1. § S = Sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency) = Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero ¶ FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP # FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master clock (CLKX). CLKX 1 2 FSX 6 DX 7 3 Bit 0 Bit(n-1) 4 DR Bit 0 (n-2) (n-3) (n-4) 5 Bit(n-1) (n-2) (n-3) (n-4) Figure 15–6. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 June 2003 SPRS222 147 PRODUCT PREVIEW NO. –400 –500 –600 Video Port Timing (VP0 [DM641/DM640] and VP1 [DM641 Only]) 16 Video Port Timing (VP0 [DM641/DM640] and VP1 [DM641 Only]) VCLKIN timing (Video Capture Mode) Table 16–1. Timing Requirements for Video Capture Mode for VPxCLKINx† (see Figure 16–1) –400 –500 –600 NO. MIN 1 2 3 4 tc(VKI) tw(VKIH) Cycle time, VPxCLKINx tw(VKIL) tt(VKI) UNIT MAX 12.5 ns Pulse duration, VPxCLKINx high 5.4 ns Pulse duration, VPxCLKINx low 5.4 ns Transition time, VPxCLKINx 2 ns † The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN. 4 PRODUCT PREVIEW 1 3 2 VPxCLKINx 4 Figure 16–1. Video Port Capture VPxCLKINx TIming 16.1 STCLK Timing Table 16–2. Timing Requirments for STCLK† (see Figure 16–2) –400 –500 –600 NO. MIN 1 2 3 4 tc(STCLK) tw(STCLKH) Cycle time, STCLK tw(STCLKL) tt(STCLK) UNIT MAX 33.3 ns Pulse duration, STCLK high 16 ns Pulse duration, STCLK low 16 ns Transition time, STCLK 2 ns † The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN. 4 1 2 3 STCLK 4 Figure 16–2. STCLK Timing 148 SPRS222 June 2003 Video Port Timing (VP0 [DM641/DM640] and VP1 [DM641 Only]) 16.2 Video Data and Control Timing (Video Capture Mode) Table 16–3. Timing Requirements in Video Capture Mode for Video Data and Control Inputs (see Figure 16–3) –400 –500 –600 NO. MIN 1 2 3 4 UNIT MAX tsu(VDATV-VKIH) Setup time, VPxDx valid before VPxCLKINx high th(VDATV-VKIH) Hold time, VPxDx valid after VPxCLKINx high 2.4 ns 0.5 ns tsu(VCTLV-VKIH) Setup time, VPxCTLx valid before VPxCLKINx high th(VCTLV-VKIH) Hold time, VPxCTLx valid after VPxCLKINx high 2.4 ns 0.5 ns VPxCLKINx 1 PRODUCT PREVIEW 2 VPxD[7:0] (Input) 3 4 VPxCTLx (Input) Figure 16–3. Video Port Capture Data and Control Input Timing June 2003 SPRS222 149 Video Port Timing (VP0 [DM641/DM640] and VP1 [DM641 Only]) 16.3 VCLKIN Timing (Video Display Mode) Table 16–4. Timing Requirements for Video Display Mode for VPxCLKINx† (see Figure 16–4) –400 –500 –600 NO. MIN 1 2 3 4 tc(VKI) tw(VKIH) Cycle time, VPxCLKINx tw(VKIL) tt(VKI) UNIT MAX 9 ns Pulse duration, VPxCLKINx high 4.1 ns Pulse duration, VPxCLKINx low 4.1 Transition time, VPxCLKINx ns 2 ns † The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN. 4 1 2 3 PRODUCT PREVIEW VPxCLKINx 4 Figure 16–4. Video Port Display VPxCLKINx Timing 16.4 Video Control Input/Output and Video Display Data Output Timing With Respect to VPxCLKINx and VPxCLKOUTx (Video Display Mode) Table 16–5. Timing Requirements in Video Display Mode for Video Control Input Shown With Respect to VPxCLKINx and VPxCLKOUTx (see Figure 16–5) –400 –500 –600 NO. MIN 13 14 15 MAX tsu(VCTLV-VKIH) th(VCTLV-VKIH) Setup time, VPxCTLx valid before VPxCLKINx high 2.4 ns Hold time, VPxCTLx valid after VPxCLKINx high 0.5 ns tsu(VCTLV-VKOH) th(VCTLV-VKOH) Setup time, VPxCTLx valid before VPxCLKOUTx high‡ Hold time, VPxCTLx valid after VPxCLKOUTx high‡ 7.4 ns –0.9 ns 16 ‡ Assuming non-inverted VPxCLKOUTx signal. 150 UNIT SPRS222 June 2003 Video Port Timing (VP0 [DM641/DM640] and VP1 [DM641 Only]) Table 16–6. Switching Characteristics Over Recommended Operating Conditions in Video Display Mode for Video Data and Control Output Shown With Respect to VPxCLKINx and VPxCLKOUTx†‡ (see Figure 16–5) 1 2 3 4 5 6 7 8 9 10 11 12 PARAMETER MIN MAX V – 0.7 V + 0.7 ns Pulse duration, VPxCLKOUTx high VH – 0.7 VH + 0.7 ns Pulse duration, VPxCLKOUTx low VL – 0.7 VL + 0.7 ns 1 ns 1.4 5 ns 1.4 5 ns Delay time, VPxCLKINx high to VPxCLKOUTx low 1.4 5 ns Delay time, VPxCLKINx low to VPxCLKOUTx high 1.4 5 ns 9 ns tc(VKO) tw(VKOH) Cycle time, VPxCLKOUTx tw(VKOL) tt(VKO) td(VKIH-VKOH) td(VKIL-VKOL) Delay time, VPxCLKINx high to VPxCLKOUTx high§ Delay time, VPxCLKINx low to VPxCLKOUTx low§ td(VKIH-VKOL) td(VKIL-VKOH) td(VKIH-VPOUTV) td(VKIH-VPOUTIV) Delay time, VPxCLKINx high to VPxOUT valid¶ td(VKOH-VPOUTV) td(VKOH-VPOUTIV) UNIT Transition time, VPxCLKOUTx Delay time, VPxCLKINx high to VPxOUT invalid¶ Delay time, VPxCLKOUTx high to VPxOUT valid†¶ 1.7 ns 4 Delay time, VPxCLKOUTx high to VPxOUT invalid†¶ ns –0.2 ns † V = the video input clock (VPxCLKINx) period in ns. ‡ VH is the high period of V (video input clock period) in ns and VL is the low period of V (video input clock period) in ns. § Assuming non-inverted VPxCLKOUTx signal. ¶ VPxOUT consists of VPxCTLx and VPxD[7:0] VPxCLKINx 5 2 1 VPxCLKOUTx [VCLK2P = 0] VPxCLKOUTx (Inverted) [VCLK2P = 1] 4 4 7 8 12 11 VPxCTLx,VPxD[7:0] (Outputs) 6 3 10 9 15 16 14 13 VPxCTLx (Input) Figure 16–5. Video Port Display Data Output Timing and Control Input/Output Timing With Respect to VPxCLKINx and VPxCLKOUTx June 2003 SPRS222 151 PRODUCT PREVIEW NO. –400 –500 –600 Video Port Timing (VP0 [DM641/DM640] and VP1 [DM641 Only]) 16.5 Video Dual-Display Sync Mode Timing (With Respect to VPxCLKINx) Table 16–7. Timing Requirements for Dual-Display Sync Mode for VPxCLKINx (see Figure 16–6) –400 –500 –600 NO. MIN 1 tskr(VKI) Skew rate, VPxCLKINx before VPyCLKINy UNIT MAX ±500 ps VPxCLKINx 1 VPyCLKINy PRODUCT PREVIEW Figure 16–6. Video Port Dual-Display Sync Timing 152 SPRS222 June 2003 Ethernet Media Access Controller (EMAC) Timing 17 Ethernet Media Access Controller (EMAC) Timing Table 17–1. Timing Requirements for MRCLK† (see Figure 17–1) –400 –500 –600 NO. MIN 1 2 3 4 UNIT MAX tc(MRCLK) tw(MRCLKH) Cycle time, MRCLK 25 ns Pulse duration, MRCLK high 11 ns tw(MRCLKL) tt(MRCLK) Pulse duration, MRCLK low 11 ns Transition time, MRCLK 3 ns † The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN. 4 1 MRCLK 4 Figure 17–1. MRCLK Timing (EMAC – Receive) Table 17–2. Timing Requirements for MTCLK† (see Figure 17–2) –400 –500 –600 NO. MIN 1 2 3 UNIT MAX tc(MTCLK) tw(MTCLKH) Cycle time, MTCLK 400 ns Pulse duration, MTCLK high 180 ns tw(MTCLKL) tt(MTCLK) Pulse duration, MTCLK low 180 ns 4 Transition time, MTCLK † The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN. 5 4 1 2 ns 3 MTCLK 4 Figure 17–2. MTCLK Timing (EMAC – Transmit) June 2003 SPRS222 153 PRODUCT PREVIEW 3 2 Ethernet Media Access Controller (EMAC) Timing Table 17–3. Timing Requirements for EMAC MII Receive 10/100 Mbit/s† (see Figure 17–3) –400 –500 –600 NO. MIN 1 tsu(MRXD-MRCLKH) Setup time, receive selected signals valid before MRCLK high 2 th(MRCLKH-MRXD) Hold time, receive selected signals valid after MRCLK high † Receive selected signals include: MRXD3–MRXD0, MRXDV, and MRXER. UNIT MAX 8 ns 8 ns MRXD3–MRXD0 is driven by the PHY on the falling edge of MRCLK. MRXD3–MRXD0 timing must be met during clock periods when MRXDV is asserted. MRXDV is asserted and deasserted by the PHY on the falling edge of MRCLK. MRXER is driven by the PHY on the falling edge of MRCLK (xx = 00–01). 1 2 PRODUCT PREVIEW MRCLK (Input) MRXD3–MRXD0, MRXDV, MRXER (Inputs) Figure 17–3. EMAC Receive Interface Timing Table 17–4. Switching Characteristics Over Recommended Operating Conditions for EMAC MII Transmit 10/100 Mbit/s‡ (see Figure 17–4) NO. –400 –500 –600 PARAMETER 1 td(MTCLKH-MTXD) Delay time, MTCLK high to transmit selected signals valid ‡ Transmit selected signals include: MTXD3–MTXD0, and MTXEN. UNIT MIN MAX 5 25 ns MTXD3–MTXD0 is driven by the reconciliation sublayer synchronous to the MTCLK. MTXEN is asserted and deasserted by the reconciliation sublayer synchronous to the MTCLK rising edge. 1 MTCLK (Input) MTXD3–MTXD0, MTXEN (Outputs) Figure 17–4. EMAC Transmit Interface Timing 154 SPRS222 June 2003 Management Data Input/Output (MDIO) Timing 18 Management Data Input/Output (MDIO) Timing Table 18–1. Timing Requirements for MDIO Input (see Figure 18–1) –400 –500 –600 NO. MIN 1 UNIT MAX Cycle time, MDCLK 400 ns 2 tc(MDCLK) tw(MDCLK) Pulse duration, MDCLK high/low 180 ns 3 tt(MDCLK) Transition time, MDCLK 4 tsu(MDIO-MDCLKH) Setup time, MDIO data input valid before MDCLK high 10 ns 5 th(MDCLKH-MDIO) Hold time, MDIO data input valid after MDCLK high 10 ns 5 ns 1 4 5 MDIO (input) Figure 18–1. MDIO Input Timing Table 18–2. Switching Characteristics Over Recommended Operating Conditions for MDIO Output (see Figure 18–2) NO. –400 –500 –600 PARAMETER MIN 7 td(MDCLKL-MDIO) Delay time, MDCLK low to MDIO data output valid UNIT MAX 100 ns 1 MDCLK 7 MDIO (output) Figure 18–2. MDIO Output Timing June 2003 SPRS222 155 PRODUCT PREVIEW MDCLK Timer Timing 19 Timer Timing Table 19–1. Timing Requirements for Timer Inputs† (see Figure 19–1) –400 –500 –600 NO. MIN 1 2 tw(TINPH) tw(TINPL) UNIT MAX Pulse duration, TINP high 8P ns Pulse duration, TINP low 8P ns † P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. Table 19–2. Switching Characteristics Over Recommended Operating Conditions for Timer Outputs† (see Figure 19–1) NO. –400 –500 –600 PARAMETER MIN PRODUCT PREVIEW 3 4 tw(TOUTH) tw(TOUTL) UNIT MAX Pulse duration, TOUT high 8P – 3 ns Pulse duration, TOUT low 8P – 3 ns † P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. 2 1 TINPx 4 3 TOUTx Figure 19–1. Timer Timing 156 SPRS222 June 2003 General-Purpose Input/Output (GPIO) Port Timing 20 General-Purpose Input/Output (GPIO) Port Timing Table 20–1. Timing Requirements for GPIO Inputs†‡ (see Figure 20–1) –400 –500 –600 NO. MIN 1 2 tw(GPIH) tw(GPIL) UNIT MAX Pulse duration, GPIx high 8P ns Pulse duration, GPIx low 8P ns † P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. ‡ The pulse width given is sufficient to generate a CPU interrupt or an EDMA event. However, if a user wants to have the DSP recognize the GPIx changes through software polling of the GPIO register, the GPIx duration must be extended to at least 12P to allow the DSP enough time to access the GPIO register through the CFGBUS. Table 20–2. Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs† (see Figure 20–1) PARAMETER MIN 3 4 tw(GPOH) tw(GPOL) UNIT MAX Pulse duration, GPOx high 32P ns Pulse duration, GPOx low 32P ns † P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. 2 1 GPIx 4 3 GPOx Figure 20–1. GPIO Port Timing June 2003 SPRS222 157 PRODUCT PREVIEW NO. –400 –500 –600 JTAG Test-Port Timing 21 JTAG Test-Port Timing Table 21–1. Timing Requirements for JTAG Test Port (see Figure 21–1) –400 –500 –600 NO. MIN 1 UNIT MAX tc(TCK) tsu(TDIV-TCKH) Cycle time, TCK 35 ns 3 Setup time, TDI/TMS/TRST valid before TCK high 10 ns 4 th(TCKH-TDIV) Hold time, TDI/TMS/TRST valid after TCK high 9 ns Table 21–2. Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port (see Figure 21–1) NO. PRODUCT PREVIEW 2 –400 –500 –600 PARAMETER td(TCKL-TDOV) Delay time, TCK low to TDO valid UNIT MIN MAX –3 18 ns 1 TCK 2 2 TDO 4 3 TDI/TMS/TRST Figure 21–1. JTAG Test-Port Timing 158 SPRS222 June 2003 Mechanical Data 22 Mechanical Data 22.1 Ball Grid Array Mechanical Data Drawing (GDK) GDK (S–PBGA–N548) PLASTIC BALL GRID ARRAY 23,10 SQ 22,90 20,00 TYP 21,10 SQ 20,90 0,80 0,40 AF AE AD AC AB AA Y W V U 0,80 T R PRODUCT PREVIEW P N M L 0,40 K A1 Corner J H G F E D C B A 1 3 2 5 4 7 6 9 8 11 13 15 17 19 21 23 25 10 12 14 16 18 20 22 24 26 Bottom View 2,80 MAX 0,50 NOM Seating Plane 0,55 0,45 0,10 0,45 0,35 0,12 4203481-3/B 07/02 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Flip chip application only. June 2003 SPRS222 159 Mechanical Data Table 22–1. Thermal Resistance Characteristics (S-PBGA Package) [GDK] °C/W Air Flow (m/s†) Junction-to-case 3.3 N/A Junction-to-board 7.92 N/A 18.2 0.00 15.3 0.5 NO 1 2 RΘJC RΘJB 3 4 5 RΘ ΘJA Junction-to-free air 6 7 PRODUCT PREVIEW 8 PsiJT PsiJB Junction-to-package top Junction-to-board 13.7 1.0 12.2 2.00 0.37 0.00 0.47 0.5 0.57 1.0 0.7 2.00 11.4 0.00 11 0.5 10.7 1.0 10.2 2.00 † m/s = meters per second 160 SPRS222 June 2003 Mechanical Data 22.2 Ball Grid Array Mechanical Data Drawing (GNZ) GNZ (S–PBGA–N548) PLASTIC BALL GRID ARRAY 27,20 SQ 26,80 25,00 TYP 1,00 25,20 SQ 24,80 0,50 AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A PRODUCT PREVIEW A1 Corner 1,00 0,50 1 3 2 5 4 7 6 9 8 11 13 15 17 19 21 23 25 10 12 14 16 18 20 22 24 26 Bottom View 2,80 MAX 0,50 NOM Seating Plane 0,70 0,50 0,10 0,60 0,40 0,15 4202595-5/E 12/02 NOTES: A. B. C. D. June 2003 All linear dimensions are in millimeters. This drawing is subject to change without notice. Flip chip application only. Substrate color may vary. SPRS222 161 Mechanical Data Table 22–2. Thermal Resistance Characteristics (S-PBGA Package) [GNZ] °C/W Air Flow (m/s†) Junction-to-case 3.3 N/A Junction-to-board 7.46 N/A 17.4 0.00 14.0 0.5 NO 1 2 RΘJC RΘJB 3 4 5 RΘ ΘJA Junction-to-free air 6 7 PRODUCT PREVIEW 8 PsiJT PsiJB Junction-to-package top Junction-to-board 12.3 1.0 10.8 2.00 0.37 0.00 0.47 0.5 0.57 1.0 0.7 2.00 11.4 0.00 11 0.5 10.7 1.0 10.2 2.00 † m/s = meters per second 162 SPRS222 June 2003