A42U2604 Series Preliminary 4M X 4 CMOS DYNAMIC RAM WITH EDO PAGE MODE Document Title 4M X 4 CMOS DYNAMIC RAM WITH EDO PAGE MODE Revision History Rev. No. 0.0 Preliminary History Issue Date Remark Initial issue June 13, 2001 Preliminary (June, 2001, Version 0.0) AMIC Technology, Inc. A42U2604 Series Preliminary 4M X 4 CMOS DYNAMIC RAM WITH EDO PAGE MODE Features n Organization: 4,194,304 words X 4 bits n Part Identification - A42U2604 (2K Ref.) n Single 2.5V power supply/built-in VBB generator n Low power consumption - Operating: 120mA (-50 max) - Standby: 1mA (TTL), 0.2mA (CMOS), 250µA (Self-refresh current) n High speed - 50/60/80 ns RAS access time - 25/30/40 ns column address access time - 13/15/20 ns CAS access time - 20/25/35 ns EDO Page Mode Cycle Time n Fast Page Mode with Extended Data Out n Read-modify-write, RAS -only, CAS -before- RAS , Hidden refresh capability n TTL-compatible, three-state I/O n JEDEC standard packages - 300mil, 24/26-pin SOJ - 300mil, 24/26-pin TSOP type II package General Description This allow random access of up to 2048(2K Ref.) words within a row at a 50/40/28 MHz EDO cycle, making the A42U2604 ideally suited for graphics, digital signal processing and high performance computing systems. The A42U2604 is a new generation randomly accessed memory for graphics, organized in a 4,194,304-word by 4-bit configuration. This product can execute Write and Read operation via CAS pin. The A42U2604 offers an accelerated Fast Page Mode cycle with a feature called Extended Data Out (EDO). Pin Configuration n SOJ n TSOP VCC 1 26 I/O 0 2 25 I/O 1 3 24 23 CAS 22 OE 21 A9 NC 6 19 A8 A10 8 Pin Descriptions VCC 1 26 I/O 3 I/O0 2 25 I/O 3 I/O 2 I/O1 3 24 I/O 2 WE 4 23 CAS RAS 5 22 OE 21 VSS Address Inputs (2K product) I/O0 - I/O3 Data Input/Output A9 RAS Row Address Strobe A8 CAS Column Address Strobe 19 WE Write Enable OE Output Enable VCC 2.5V Power Supply VSS Ground NC No Connection 5 NC 6 A10 8 A0 9 18 A7 A0 9 18 A7 A1 10 17 A6 A1 10 17 A6 A2 11 16 A5 A2 11 16 A5 A3 12 15 A4 A3 12 15 A4 VCC 13 14 VSS VCC 13 14 VSS A42U2604V 4 A42U2604S WE (June, 2001, Version 0.0) Description A0 - A10 RAS PRELIMINARY Symbol VSS 1 AMIC Technology, Inc. A42U2604 Series Selection Guide Symbol Description -50 -60 -80 Unit tRAC Maximum RAS Access Time 50 60 80 ns tAA Maximum Column Address Access Time 25 30 40 ns tCAC Maximum CAS Access Time 13 15 20 ns tOEA Maximum Output Enable ( OE ) Access Time 13 15 20 ns tRC Minimum Read or Write Cycle Time 84 104 134 ns tPC Minimum EDO Cycle Time 20 25 35 ns Functional Description The A42U2604 reads and writes data by multiplexing an 22-bit address into a 11-bit(2K) row and column address. RAS and CAS are used to strobe the row address and the column address, respectively. valid as long as RAS and OE are low, and WE is high; this is the only characteristic which differentiates Extended Data Out operation from a standard Read or Fast Page Read. A Read cycle is performed by holding the WE signal high during RAS / CAS operation. A Write cycle is executed by A memory cycle is terminated by returning both RAS and CAS high. Memory cell data will retain its correct state by maintaining power and accessing all 2048(2K) combinations of the 11-bit(2K) row addresses, regardless of sequence, at least once every 32ms through any RAS cycle (Read, Write) or RAS Refresh cycle ( RAS -only, CBR, or Hidden). The CBR Refresh cycle automatically controls the row addresses by invoking the refresh counter and controller. holding the WE signal low during RAS / CAS operation; the input data is latched by the falling edge of WE or CAS , whichever occurs later. The data inputs and outputs are routed through 4 common I/O pins, with RAS , CAS , WE and OE controlling the in direction. EDO Page Mode operation all 2048(2K) columns within a selected row to be randomly accessed at a high data rate. A EDO Page Mode cycle is initiated with a row address latched by RAS followed by a column address latched by CAS . While holding RAS low, CAS can be toggled to strobe changing column addresses, thus achieving shorter cycle times. The A42U2604 offers an accelerated Fast Page Mode cycle through a feature called Extended Data Out, which keeps the output drivers on during the CAS precharge time (tcp). Since data can be output after CAS goes high, the user is not required to wait for valid data to appear before starting the next access cycle. Data-out will remain PRELIMINARY (June, 2001, Version 0.0) Power-On The initial application of the VCC supply requires a 200 µs wait followed by a minimum of any eight initialization cycles containing a RAS clock. During Power-On, the VCC current is dependent on the input levels of RAS and CAS . It is recommended that RAS and CAS track with VCC or be held at a valid VIH during Power-On to avoid current surges. 2 AMIC Technology, Inc. A42U2604 Series Block Diagram Vcc RAS CAS Control Clocks Vss VBB Generator WE Refresh Timer Row Decoder Data in Buffer Refresh Counter A0~A10 A0~A10 Memory Array 4,194,304 X 4 Cells Row Address Buffer Col. Address Buffer Recommended Operating Conditions Symbol Sense Amps & I/O Refresh control Description I/O0 to I/O3 Data out Buffer OE Column Decoder (Ta = 0°C to +70°C) Min. Typ. Max. Unit 2.25 2.5 2.75 V VCC Power Supply VSS Input High Voltage 0 0 0 V VIH Input High Voltage 1.8 - VCC + 0.2 V VIL Input Low Voltage -1.0 - 0.8 V PRELIMINARY (June, 2001, Version 0.0) 3 AMIC Technology, Inc. A42U2604 Series Truth Table Function RAS CAS Standby H Read: Word L Read L Address I/Os WE OE H X X X High-Z L H L Row/Col. Data Out L H L Row/Col. Data Out Write: Word (Early) L L L X Row/Col. Data In Write (Early) L L L X Row/Col. Data In Read-Write L L H→L L→H Row/Col. Data Out → Data In EDO-Page-Mode Read: Hi-Z -First cycle -Subsequent Cycles L L H→L H H H→L H→L Row/Col. Col. Data Out Data Out EDO-Page-Mode Write(Early) -First cycle -Subsequent Cycles L L H→L H→L L L X X Row/Col. Col. Data In Data In EDO-Page-Mode Read-Write -First cycle -Subsequent Cycles L L H→L H→L L→H Data Out → Data In H→L H→L L→H Row/Col. Col. Hidden Refresh Read L→H→L L H L Row/Col. Data Out Hidden Refresh Write L→H→L L L X Row/Col. Data In → High-Z L H X X Row High-Z RAS -Only Refresh CBR Refresh Self Refresh PRELIMINARY H→L Data Out → Data In H→L L X X X High-Z H→L L H X X High-Z (June, 2001, Version 0.0) 4 AMIC Technology, Inc. A42U2604 Series Absolute Maximum Ratings* *Comments Input Voltage (Vin) . . . . . . . . . . . . . . . -0.5V to VCC+0.5V Output Voltage (Vout) . . . . . . . . . . . . . -0.5V to VCC+0.5V Power Supply Voltage (VCC) . . . . . . . -0.5V to VCC+0.5V Operating Temperature (TOPR) . . . . . . . . . . 0°C to +70°C Storage Temperature (TSTG) . . . . . . . . . -55°C to +150°C Soldering Temperature X Time (TSOLDER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C X 10sec Power Dissipation (PD) . . . . . . . . . . . . . . . . . . . . . . . . 1W Short Circuit Output Current (Iout) . . . . . . . . . . . . . . 50mA Latch-up Current . . . . . . . . . . . . . . . . . . . . . . . . . . 200mA Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of these specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. DC Electrical Characteristics (VCC = 2.5V ± 10%, VSS = 0V, Ta = 0°C to +70°C) -50 Symbol -60 -80 Parameter Unit Min. Max. Min. Max. Min. Max. Test Conditions IIL Input Leakage Current -5 +5 -5 +5 -5 +5 µA 0V ≤ Vin ≤ Vin + 0.2V Pins not under Test = 0V IOL Output Leakage Current -5 +5 -5 +5 -5 +5 µA DOUT disabled, 0V ≤ Vout ≤ + VCC ICC1 Operating Power Supply Current - 120 - 110 - 100 mA ICC2 TTL Standby Power Supply Current - 1 - 1 - 1 mA ICC3 Average Power Supply Current, RAS Refresh Mode - 120 - 110 - 100 mA ICC4 EDO Page Mode Average Power Supply Current - 100 - 90 - 80 mA ICC5 CAS -before- RAS Refresh Power Supply Current - 110 - 100 - 90 mA ICC6 CMOS Standby Power Supply Current - 0.2 - 0.2 - 0.2 mA RAS = UCAS = LCAS = VCC - 0.2V ICC7 Self Refresh Mode Current - 250 - 250 - 250 µA RAS = CAS ≤ VSS+0.2V All other input high levels are VCC-0.2V or input low levels are VSS +0.2V 2.0 - 2.0 - 2.0 - V IOUT = -2mA - 0.4 - 0.4 - 0.4 V IOUT = 2mA VOH RAS , UCAS , LCAS = min. Notes 1, 2 Address cycling; tRC RAS = UCAS = LCAS =VIH RAS cycling, 1 UCAS = LCAS = VIH, tRC = min. RAS = VIL, UCAS , LCAS Address cycling; tPC = min. RAS , UCAS , LCAS = min. 1, 2 1 cycling; tRC Output Voltage VOL PRELIMINARY (June, 2001, Version 0.0) 5 AMIC Technology, Inc. A42U2604 Series AC Characteristics (VCC = 2.5V ±10%, VSS = 0V, Ta = 0°C to +70°C) Test Conditions: Input timing reference level: VIH/VIL=1.8V/0.8V Output reference level: VOH/VOL=1.6V/0.8V Output Load: 1TTL gate + CL (100pF) Assumed tT=2ns # Std Symbol tT tREF -50 -60 -80 Unit Notes 50 ns 4, 5 - 32 ms 3 128 - 128 ms 3 Parameter Min. Max. Min. Max. Min . Max. 1 50 1 50 1 2K - 32 - 32 Self-REF - 128 - Transition Time (Rise and Fall) Refresh Period 1 tRC Random Read or Write Cycle Time 84 - 104 - 134 - ns 2 tRP RAS Precharge Time 30 - 40 - 50 - ns 3 tRAS RAS Pulse Width 50 10K 60 10K 80 10K ns 4 tCAS CAS Pulse Width 7 10K 10 10K 15 10K ns 5 tRCD RAS to CAS Delay Time 11 37 14 45 20 60 ns 6 6 tRAD RAS to Column Address Delay Time 9 25 12 30 15 40 ns 7 7 tRSH CAS to RAS Hold Time 7 - 10 - 10 - ns 8 tCSH CAS Hold Time 37 - 40 - 50 - ns 9 tCRP CAS to RAS Precharge Time 5 - 5 - 5 - ns 10 tASR Row Address Setup Time 0 - 0 - 0 - ns 11 tRAH Row Address Hold Time 7 - 10 - 10 - ns 12 tCLZ CAS to Output in Low Z 0 - 0 - 0 - ns 8 13 tRAC Access Time from RAS - 50 - 60 - 80 ns 6,7 14 tCAC Access Time from CAS - 13 - 15 - 20 ns 6, 12 15 tAA Access Time from Column Address - 25 - 30 - 40 ns 7, 12 16 tAR Column Address Hold Time from RAS 44 - 55 - 70 - ns 17 tRCS Read Command Setup Time 0 - 0 - 0 - ns 18 tRCH Read Command Hold Time 0 - 0 - 0 - ns PRELIMINARY (June, 2001, Version 0.0) 6 9 AMIC Technology, Inc. A42U2604 Series AC Characteristics (continued) (VCC = 2.5V ±10%, VSS = 0V, Ta = 0°C to +70°C) Test Conditions: Input timing reference level: VIH/VIL=1.8V/0.8V Output reference level: VOH/VOL=1.6V/0.8V Output Load: 1TTL gate + CL (100pF) Assumed tT=2ns # Std Symbol -50 -60 -80 Parameter Min. Max. Min. Max. Min . Max. Unit Notes 9 19 tRRH Read Command Hold Time Reference to RAS 0 - 0 - 0 - ns 20 tRAL Column Address to RAS Lead Time 25 - 30 - 40 - ns 21 tCOH Output Hold After CAS Low 5 - 5 - 3 - ns 22 tODS Output Disable Setup Time 0 - 0 - 0 - ns 23 tOFF Output Buffer Turn-Off Delay Time 0 13 0 15 0 20 ns 24 tASC Column Address Setup Time 0 - 0 - 0 - ns 25 tCAH Column Address Hold Time 7 - 10 - 10 - ns 26 tOES OE Low to CAS High Set Up 5 - 5 - 10 - ns 27 tWCS Write Command Setup Time 0 - 0 - 0 - ns 11 28 tWCH Write Command Hold Time 7 - 10 - 10 - ns 11 29 tWCR Write Command Hold Time to RAS 44 - 55 - 70 - ns 30 tWP Write Command Pulse Width 7 - 10 - 10 - ns 31 tRWL Write Command to RAS Lead Time 13 - 15 - 20 - ns 32 tCWL Write Command to CAS Lead Time 7 - 10 - 10 - ns 33 tDS Data-in setup Time 0 - 0 - 0 - ns 34 tDH Data-in Hold Time 7 - 10 - 15 - ns 35 tDHR Data-in Hold Time to RAS 44 - 55 - 70 - ns 36 tRWC Read-Modify-Write Cycle Time 110 - 135 - 180 - ns 37 tRWD RAS to WE Delay Time (Read-ModifyWrite) 67 - 79 - 107 - ns 11 38 tCWD CAS to WE Modify-Write) 30 - 34 - 47 - ns 11 PRELIMINARY Delay (June, 2001, Version 0.0) Time (Read- 7 8, 10 AMIC Technology, Inc. A42U2604 Series AC Characteristics (continued) (VCC = 2.5V ± 10%, VSS = 0V, Ta = 0°C to +70°C) Test Conditions: Input timing reference level: VIH/VIL=1.8V/0.8V Output reference level: VOH/VOL=1.6V/0.8V Output Load: 1TTL gate + CL (100pF) Assumed tT=2ns # 39 -50 Std Symbol tAWD -60 -80 Parameter Unit Notes - ns 11 Min. Max. Min. Max. Min. Max. 42 - 49 - 67 Column Address to WE Delay Time (Read-Modify-Write) 40 tOEH OE Hold Time from WE 7 - 10 - 20 - ns 41 tOEP OE High Pulse Width 2 - 2 - 5 - ns 42 tPC Read or Write Cycle Time (EDO Page) 20 - 25 - 35 - ns 13 43 tCPA - 28 - 33 - 45 ns 12 Access Time from CAS Precharge (EDO Page) 44 tCP CAS Precharge Time (EDO Page) 7 - 10 - 10 - ns 45 tPCM EDO Page Mode RMW Cycle Time 58 - 68 - 80 - ns 46 tCRW EDO Page Mode CAS Pulse Width (RMW) 34 - 38 - 42 - ns 47 tRASP RAS Pulse Width 50 100K 60 100K 80 100K ns 48 tCSR CAS Setup Time ( CAS -before- RAS ) 5 - 5 - 5 - ns 3 49 tCHR CAS Hold Time 10 - 10 - 15 - ns 3 50 tRPC 5 - 5 - 5 - ns (EDO Page) ( CAS -before- RAS ) RAS to CAS Precharge Time ( CAS -before- RAS ) 51 tROH RAS Hold Time Reference to OE 5 - 5 - 5 - ns 52 tOEA OE Access Time - 13 - 15 - 20 ns 53 tOED OE to Data Delay 13 - 15 - 20 - ns 54 tOEZ Output Buffer Turn-off Delay from OE 0 13 0 15 0 20 ns 55 tRASS RAS pulse width ( C -B- R self-refresh) 100 - 100 - 100 - µs 56 tRPS 84 - 104 - 134 - ns - 50 - 50 - 50 ns RAS precharge time 8 ( C -B- R self-refresh) 57 tCHS PRELIMINARY CAS hold time ( C -B- R self-refresh) (June, 2001, Version 0.0) 8 AMIC Technology, Inc. A42U2604 Series Notes: 1. ICC1, ICC3, ICC4, and ICC5 depend on cycle rate. 2. ICC1 and ICC4 depend on output loading. Specified values are obtained with the outputs open. 3. An initial pause of 200µs is required after power-up followed by any 8 RAS cycles before proper device operation is achieved. In the case of an internal refresh counter, a minimum of 8 CAS -before- RAS initialization cycles instead of 8 RAS cycles are required. 8 initialization cycles are required after extended periods of bias without. 4. AC Characteristics assume tT = 2ns. All AC parameters are measured with a load equivalent to one TTL load and 100pF, VIL (min.) ≥ GND and VIH (max.) ≤ VCC. 5. VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL. 6. Operation within the tRCD (max.) limit insures that tRAC (max.) can be met. tRCD (max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled exclusively by tCAC. 7. Operation within the tRAD (max.) limit insures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled exclusively by tAA. 8. Assumes three state test load (5pF and a 500Ω Thevenin equivalent). 9. Either tRCH or tRRH must be satisfied for a read cycle. 10. tOFF (max.) defines the time at which the output achieves the open circuit condition; it is not referenced to output voltage levels. 11. tWCS, tWCH, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS ≥ tWCS (min.) and tWCH ≥ tWCH (min.), the cycle is an early write cycle and data-out pins will remain open circuit, high impedance, throughout the entire cycle. If tRWD ≥ tRWD (min.) , tCWD ≥ tCWD (min.) and tAWD ≥ tAWD (min.), the cycle is a read-modify-write cycle and the data out will contain data read from the selected cell. If neither of the above conditions is satisfied, the condition of the data out at access time is indeterminate. 12. Access time is determined by the longer of tAA or tCAC or tCPA. 13. tASC ≥ tCP to achieve tPC (min.) and tCPA (max.) values. PRELIMINARY (June, 2001, Version 0.0) 9 AMIC Technology, Inc. A42U2604 Series Word Read Cycle tRC(1) tRAS(3) tRP(2) RAS tCSH(8) tCRP(9) tRCD(5) tRSH(7) tCRP(9) tCAS(4) CAS tRAD(6) tASR(10) Address tRAL(20) tRAH(11) tASC(24) Row Address tCAH(25) Column Address tAR(16) tRCH(18) tRCS(17) tRRH(19) WE tROH(51) tOEA(52) OE tCAC(14) tAA(15) tRAC(13) I/O 0 ~ I/O 3 tOFF(23) tOEZ(54) High-Z Valid Data-out tCLZ(12) : High or Low PRELIMINARY (June, 2001, Version 0.0) 10 AMIC Technology, Inc. A42U2604 Series Word Write Cycle (Early Write) tRC(1) tRAS(3) tRP(2) RAS tCSH(8) tCRP(9) tRCD(5) tRSH(7) tCRP(9) tCAS(4) CAS tAR(16) tRAD(6) tASR(10) tRAL(20) tRAH(11) tCAH(25) tASC(24) Address Row Address Column Address tWCR(29) tCWL(32) tRWL(31) tWP(30) WE tWCS(27) tWCH(28) OE tDHR(35) tDS(33) I/O 0 ~ I/O 3 tDH(34) Valid Data-in : High or Low PRELIMINARY (June, 2001, Version 0.0) 11 AMIC Technology, Inc. A42U2604 Series Word Write Cycle (Late Write) tRC(1) t RAS(3) tRP(2) RAS t CSH(8) t CRP(9) t RCD(5) tRSH(7) tCRP(9) tCAS(4) CAS tAR(16) tRAD(6) tASR(10) t RAL(20) tRAH(11) tCAH(25) t ASC(24) Address Row Address Column Address tCWL(32) tRWL(31) t WCR(29) tWP(30) WE t OEH(40) t OED(53) OE tDHR(35) t DS(33) I/O 0 ~ I/O 3 t DH(34) High-Z Vaild Data-in : High or Low PRELIMINARY (June, 2001, Version 0.0) 12 AMIC Technology, Inc. A42U2604 Series Word Read-Modify-Write Cycle tRWC(36) tRAS(3) tRP(2) RAS tCSH(8) tCRP(9) tRCD(5) tRSH(7) tCRP(9) tCAS(4) CAS tAR(16) tRAD(6) tASR(10) Address tASC(24) tRAH(11) Row Address tCAH(25) Column Address tAWD(39) tCWL(32) tCWD38) tRCS(17) tRWD(37) tRWL(31) WE tWP(30) tOED(53) tOEA(52) tOEZ(54) OE tOEH(40) tCAC(14) tAA(15) tDS(33) tDH(34) tRAC(13) I/O 0 ~ I/O 3 High-Z Data-out Data-in tCLZ(12) : High or Low PRELIMINARY (June, 2001, Version 0.0) 13 AMIC Technology, Inc. A42U2604 Series EDO Page Mode Word Read Cycle tRASP(47) tRP(2) RAS tCSH(8) tCRP(9) tPC(42) tRSH(7) tCRP(9) tRCD(5) tCP(44) tCAS(4) tCAS(4) tCAS(4) CAS tCSH(8) tAR(16) tASR(10) Address tRAD(6) tRAH(11) tRAL(20) tCAH(25) tCAH(25) tASC(24) tASC(24) Row Column Column tCAH(25) Column tRCS(17) tRCS(17) tRCH(25) tRCH(25) tRCS(17) WE tAA(15) tAA(15) tRRH(19) tCPA(43) tOEA(52) tOEA(52) tOES(26) OE tCAC(14) tRAC(13) tCAC(14) tOEP(41) tCOH(21) tCLZ(12) I/O 0 ~ I/O 3 Data-out tOFF(23) tCAC(14) tOEZ(54) tOEZ(54) Data-out Data-out tCLZ(12) : High or Low PRELIMINARY (June, 2001, Version 0.0) 14 AMIC Technology, Inc. A42U2604 Series EDO Page Mode Early Word Write Cycle tRASP(47) tRP(2) RAS tCSH(8) tCRP(9) tPC(42) tRSH(7) tCRP(9) tRCD(5) tCAS(4) tCP(44) tCAS(4) tCP(44) tCAS(4) CAS tRAL(20) tRAD(6) tASR(10) Address tCAH(25) tRAH(11) tASC(24) tCAH(25) tASC(24) Row tCAH(25) tASC(24) Column Column tCWL(32) tCWL(32) Column tCWL(32) tRWL(31) tWCS(27) tWCS(27) tWCS(27) tWCH(28) tWCH(28) tWCH(28) WE tWP(30) tWP(30) tWP(30) OE tDH(34) tDS(33) I/O 0 ~ I/O 3 tDH(34) tDS(33) Data-in tDH(34) tDS(33) Data-in Data-in : High or Low PRELIMINARY (June, 2001, Version 0.0) 15 AMIC Technology, Inc. A42U2604 Series EDO Page Mode Word Read-Modify-Write Cycle tRP(2) tRASP(47) RAS tCSH(8) tCRP(9) tPCM(45) tRSH(7) tCRP(9) tRCD(5) tCAS(4) tCP(44) tCP(44) tCAS(4) tCAS(4) CAS tRAL(20) tRAD(6) tASR(10) tCAH(25) tRAH(11) Address Row tCAH(25) tCAH(25) tASC(24) tASC(24) Column tASC(24) Column Column tCWL(32) tCWL(32) tCWL(32) tRWD(37) tRWL(31) tRCS(17) tCWD(38) tCWD(38) tCWD(38) WE tWP(30) tAWD(39) tWP(30) tAWD(39) t WP(30) tAWD(39) tROH(51) tOEA(52) tOEA(52) t OEA(52) OE tOEH(40) tOED(53) tCAC(14) tOED(53) tCPA(43) tAA(15) t CPA(43) tAA(15) t OEZ(54) tAA(15) tOEZ(54) tDH(34) tRAC(13) tOEZ(54) tDH(34) tDH(34) t DS(33) tDS(33) tDS(33) I/O0 ~ I/O3 tOED(53) High-Z tCLZ(12) tCLZ(12) tCLZ(12) Data-in Data-out Data-in Data-out Data-in Data-out : High or Low PRELIMINARY (June, 2001, Version 0.0) 16 AMIC Technology, Inc. A42U2604 Series RAS Only Refresh Cycle tRC(1) tRAS(3) tRP(2) RAS t RPC(50) t CRP(9) CAS t ASR(10) tRAH(11) Row Address Note: WE, OE = Don't care. : High or Low CAS Before RAS Refresh Cycle tRC(1) tRP(2) tRAS(3) tRP(2) RAS tRPC(50) tCHR(49) tCSR(48) tPC(42) CAS tOFF(23) High-Z I/O 0 ~ I/O 3 Note: WE, OE, Address = Don't care. PRELIMINARY (June, 2001, Version 0.0) : High or Low 17 AMIC Technology, Inc. A42U2604 Series Hidden Refresh Cycle (Word Read) t RC(1) t RC(1) tRAS(3) tRP(2) tRAS(3) tRP(2) RAS tAR(16) t CRP(9) tRSH(7) tRCD(5) tCHR(49) tCRP(9) CAS tRAD(6) t ASR(10) t RAL(20) t CAH(25) t RAH(11) t ASC(24) Address Row Column t RCS(17) tRRH(19) WE t AA(15) OE t CAC(14) t OFF(23) tCLZ(12) t RAC(13) I/O 0 ~ I/O 3 High-Z Valid Data-out : High or Low PRELIMINARY (June, 2001, Version 0.0) 18 AMIC Technology, Inc. A42U2604 Series Hidden Refresh Cycle (Early Word Write) tRC(1) t RC(1) t RAS(3) t RP(2) tRAS(3) t RP(2) RAS t AR(16) tCRP(9) t RCD(5) tRSH(7) tCHR(49) t CRP(9) CAS t RAD(6) t ASR(10) t RAH(11) tRAL(20) t CAH(25) tASC(24) Address Row Column t WCS(27) t WCH(28) tWP(30) WE OE t DS(33) I/O 0 ~ I/O 3 t DH(34) Valid Data-in : High or Low PRELIMINARY (June, 2001, Version 0.0) 19 AMIC Technology, Inc. A42U2604 Series EDO Page Mode Read-Early-Write Cycle (Pseudo Read-Modify-Write) tRP(2) tRASP(47) RAS tCSH(8) tPC(42) tRCD(5) t CRP(9) tCAS(4) t PC(42) tCP(44) tCAS(4) tRSH(7) tCP(44) tCAS(4) t CPR(9) CAS tRAD(6) tRAL(20) tRAD(6) tASR(10) Address t ASC(24) tRAH(11) t ASC(24) Row t CAH(25) tASC(24) tCAH(25) Column Column t CAH(25) Column tRCH(18) t RCS(17) tWCS(27) WE tWCH(28) tAA(15) tAA(15) tCAP(43) tDS(33) tDH(34) tRAC(13) tCAC(14) tCAC(14) tOEA(52) OE tCOH(21) I/O 0 ~ I/O 3 Data-out Data-out Data-in : High or Low PRELIMINARY (June, 2001, Version 0.0) 20 AMIC Technology, Inc. A42U2604 Series Self Refresh Mode tRP(2) tRASS(55) tRPS(56) RAS tCHS(57) tCSR(48) tRPC(50) tCRP(9) UCAS LCAS tCPN(42) tASR(10) ROW A0 ~ A10 COL tOFF(23) High-Z I/O 0 ~ I/O 3 : High or Low Note: WE, OE = Don't care. n Self Refresh Mode. a. Entering the Self Refresh Mode: The A42U2604 Self Refresh Mode is entered by using CAS before RAS cycle and holding RAS and CAS signal "low" longer than 100µs. b. Continuing the Self Refresh Mode: The Self Refresh Mode is continued by holding RAS "low" after entering the Self Refresh Mode. It does not depend on CAS being "high" or "low" after entering the Self Refresh Mode continue the Self Refresh Mode. c. Exiting the Self Refresh Mode: The A42U2604 exits the Self Refresh Mode when the RAS signal is brought "high". PRELIMINARY (June, 2001, Version 0.0) 21 AMIC Technology, Inc. A42U2604 Series Capacitance (Ta = Room Temperature, VCC = 2.5V ± 10%) Symbol Signals CIN1 A0 - A10 CIN2 RAS , CAS , Parameter Max. Unit Test Conditions 5 pF Vin = 0V Input Capacitance 7 pF Vin = 0V I/O Capacitance 10 pF Vin = Vout = 0V WE , OE CI/O I/O0 - I/O3 Ordering Codes Package\ RAS Access Time 50ns 60ns 80ns Refresh Cycle SelfRefresh 24/26L SOJ (300mil) A42U2604S-50 A42U2604S-60 A42U2604S-80 2K Yes 24/26L TSOP type II (300mil) A42U2604V-50 A42U2604V-60 A42U2604V-80 2K Yes PRELIMINARY (June, 2001, Version 0.0) 22 AMIC Technology, Inc. A42U2604 Series Package Information SOJ 24L/26L (300mil) Outline Dimensions unit: inches/mm 18 13 6 7 12 E1 19 1 E D 24 -yS b b2 A A A1 A2 C Pin 1 Identifier θ e Seating Plane 0.004 E2 y Dimensions in inches Symbol A Dimensions in mm Min Nom Max Min Nom Max A - - 0.140 - - 3.56 A1 0.070 0.080 0.090 1.78 2.03 2.29 A2 0.095 0.100 0.105 2.41 2.54 2.67 b 0.016 0.018 0.022 0.41 0.46 0.56 b2 0.026 0.028 0.032 0.66 0.71 0.81 C 0.008 0.010 0.014 0.20 0.25 0.36 D - 0.675 0.686 - 17.15 17.42 E 0.327 0.337 0.347 8.31 8.56 8.81 E1 0.295 0.300 0.305 7.49 7.62 7.75 E2 e 0.245 0.265 0.285 6.22 6.73 7.24 0.044 0.050 0.056 1.12 1.27 1.42 S - - 0.048 - - 1.22 θ 0° - 10° 0° - 10° Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E1 does not include resin fins. 3. Dimension E2 is for PC Board surface mount pad pitch design reference only. 4. Dimension S includes end flash. PRELIMINARY (June, 2001, Version 0.0) 23 AMIC Technology, Inc. A42U2604 Series Package Information TSOP 24/26L (TYPE II) Outline Dimensions 13 E HE 0.010 24 unit: inches/mm θ L1 1 12 e B A A1 S D A2 c D y L1 Dimensions in inches Symbol Min Nom Max A - - A1 0.002 - A2 0.037 B 0.012 L Dimensions in mm Min Nom Max 0.047 - - 1.20 - 0.05 - - 0.039 0.041 0.95 1.00 1.05 0.016 0.020 0.30 0.40 0.50 c - 0.005 - - 0.127 - D 0.671 0.675 0.679 17.04 17.14 17.24 E 0.298 0.300 0.302 7.57 7.62 7.67 e - 0.050 - - 1.27 - HE 0.359 0.363 0.367 9.12 9.22 9.32 L - 0.031 - - 0.80 - L1 0.016 0.020 0.024 0.40 0.50 0.60 S - 0.037 - - 0.95 - y - - 0.004 - - 0.10 θ 0° - 5° 0° - 5° Notes: 1. Dimension D&E do not included interiead flash. 2. Dimension B does not included dambar protrusion / intrusion. 3. Dimension S includes end flash. PRELIMINARY (June, 2001, Version 0.0) 24 AMIC Technology, Inc.