ETC AHA4540

comtech aha corporation
Product Specification
AHA4540 TPC EVB
TPC Evaluation Board
This product is covered under multiple patents held or licensed by Comtech AHA Corporation.
This product is covered by a Turbo Code Patent LIcense from France Telecom - TDF - Groupe des ecoles des
telecommunications.
PS4540evb_0802
A subsidiary of Comtech Telecommunications Corporation
2345 NE Hopkins Court
Pullman WA 99163
tel: 509.334.1000
fax: 509.334.9000
www.aha.com
comtech aha corporation
Table of Contents
1.0 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Conventions, Notations and Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.3 System Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.4 Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.0 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1 Encoding Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1.1 Encode Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1.2 Encode Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2 Decoding Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2.1 Decode Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2.2 Decode Data Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.3 Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.3.1 Crystal Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.3.2 Frequency Synthesizers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.4 Synchronization Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.4.1 Led Status Definitions (D1-D8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.4.2 Switch Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.4.3 Jumper Clock Configuration (JP7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.4.4 Jumper Clock Configuration (JP8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.5 Loopback - Test 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.6 Loopback - Test 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.7 Loopback - Test 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.8 Loopback Test 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.9 Loopback - Test 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.10 EVB configuration for Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.11 Mode 1 Script Writing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.12 Software Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.13 Quick Start. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.0 Hardware Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.0 FPGA Controller Toplevel Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.0 AHA4540 EVB Communication Software. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.1 Operation of AHAESB Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.1.1 Connect Button. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.1.2 Configure Button. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.1.3 Interactive Mode Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.1.4 Log Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.1.5 Reset Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.1.6 User Test Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.1.7 Test Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.1.8 AHAESB Script Syntax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.2 ESB Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6.0 REFERENCE GUIDE TO PROGRAMMING EVB REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6.1 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
7.0 Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7.1 AHA4540 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7.2 Frequency Synthesizers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7.3 AHA4540 EVB FPGA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
8.0 Signals In/Out of EVB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
8.1 EVB Main Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
9.0 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
9.1 Board Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
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A subsidiary of Comtech Telecommunications Corporation
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9.2 Signal Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
10.0 Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
11.0 Board Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
12.0 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
13.0 Related Publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Appendix A: Board Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
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A subsidiary of Comtech Telecommunications Corporation
PS4540evb_0802
comtech aha corporation
Figures
Figure 1:
Figure 2:
Figure 3:
Figure 4:
Figure 5:
Figure 6:
Figure 7:
AHA4540 EVB Photo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
AHA4540 EVB Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Encode/Decode Loopback - Test 1 Datapath. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
AHA4540 EVB Major Component Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
FPGA Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Data Input Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Data Output Timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
PS4540evb_0802
A subsidiary of Comtech Telecommunications Corporation
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comtech aha corporation
Tables
Table 1:
Table 2:
Table 3:
Table 4:
Table 5:
Table 6:
iv
LED Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Switch Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Jumper Clock Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Jumper Clock Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
List of EVB Registers with Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Data Input/Output Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
A subsidiary of Comtech Telecommunications Corporation
PS4540evb_0802
comtech aha corporation
1.0
INTRODUCTION
The AHA4540 EVB is a hardware evaluation
board that allows incorporation of the AHA4540
Turbo Product Codes (TPC) device in a prototype
communications system or laboratory test
environment. It can be used to demonstrate the
forward error correction (FEC) performance gain
that TPCs offer over other available solutions. The
EVB supports simultaneous encoding and decoding
of a serial or parallel data stream. The board can be
programmed and configured via an RS232 interface
connected to a PC running the included
configuration software to support a wide variety of
code configurations.
The AHA4540 EVB can be interfaced with a
standard Bit Error Rate Tester (BERT) for data
source and data sink or other communications
hardware connected to the uncoded side of the EVB.
On the channel side of the EVB, coded data is
output from the encoder and connected to a modem
or other hardware channel model and then input
back into the EVB after demodulation.
The AHA4540 device is a single-chip Turbo
Product Code (TPC) Forward Error Correction
(FEC) Encoder/Decoder. This device integrates
independent TPC encoder and decoder functions,
and configurable for full or half duplex operation. In
addition to TPC coding, the device includes helical
interleaving, CRC computation and detection,
digital modlation/ demodulation (8PSK, QPSK, 16/
64/256 QAM), LLR mapping and pseudo random
bit stream scrambling. Each of these functional
blocks can be independently bypassed. When
connected with a PC for configuration via the
RS232 interface the AHA4540 EVB is fully
programmable for a wide range of coding
configurations and allows all registers in the
AHA4540 device to be accessed for configuration.
Figure 1:
1.1
CONVENTIONS, NOTATIONS AND
DEFINITIONS
– Active low signals have an “N” appended to the
end of the signal name. For example, MCSN and
RESETN.
– Channel Rate - The rate at which encoded data is
output from the device when encoding or input to
the device when decoding. Note that system
channel rate may be different due to external
synchronization marks or other overhead.
– Code block - A data stream to be encoded or
decoded is segmented into blocks for processing
by the AHA4540. Data in a code block is
configured as either a 2D or a 3D array.
– Code rate - Ratio of the number of data bits to the
number of data and ECC bits.
– Data rate - The rate at which unencoded data is
input to the device when encoding or output from
the device when decoding.
– Full iteration - Decoding all axes of an array (all
rows and columns).
– Hard Decision Array (HDA) - The hard decision
output. Data is stored as one bit per location.
– Hex values are represented with a prefix of “0x”,
such as register “0x00”. Binary values do not
contain a prefix.
– Latency - The time from the first bit of an incoming
block till the first bit of the same block out.
– (n1,k1)x(n2,k2) - A general representation of a
2D block code for use in the descriptions to follow
in this specification. For example, in a
(64,57)x(64,57) code; n1,n2=64 represents the
length of the data + ECC bits, and k1,k2=57
represents the length of only the data bits. 3D
codes are represented as (n1,k1)x(n2,k2)x(n3,k3)
– Soft value - Input to the decoder from either an
Analog/Digital Converter (ADC) or digital
demodulator.
AHA4540 EVB Photo
PS4540evb_0802
A subsidiary of Comtech Telecommunications Corporation
Page 1 of 37
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1.2
FEATURES
1.4
PERFORMANCE:
• 160 MHz maximum clock input (S_UCLK,
S_CCLK)
• 160 Mbits/sec maximum serial data rate
• Simultaneous independent TPC encoding and
decoding
• Access to registers in the AHA4540 device
• Up to 4 bit soft decision input to TPC decoder
• On-board synchronization in the AHA4540
• On-board AHA4540 includes CRC insertion and
detection
INTERFACE:
• SMA connectors for all clock and data signals on/
off board
• 2 frequency synthesizers on board generate
payload side clocks at frequencies up to 60 MHz
• User can supply payload and channel side bit
clocks up to 160 MHz max frequency
• RS232 control interface for board configuration
and monitoring
GENERAL:
• PCB form factor (5.30” x 8.80”)
• On board LED status indicators
• Requires 5V power supply @ 2.0 A
• Requires Windows PC for configuration control
via RS232 port
• SMA connectors are used for inputs and outputs
for all high speed serial interfaces
1.3
•
•
MODES
Mode 1: SERIAL
Uses RS232 w/ AHAESB windows software for
configuration. This mode allows the user
to easily switch between codes using an
AHAESB script. Data is transfered to
and from the device through serial SMA
connectors. This mode is selected when
internal control register (0x08) bit 0 and
bit 1 are cleared, and the CDATA MAP
register (0x20) is set to 0x00.
Mode 2: PARALLEL
Uses RS232 w/ AHAESB windows software for
configuration. This mode allows the user
to easily switch between codes using an
AHAESB script. Data is transfered to
and from the device through parallel flat
cable connectors. This mode is selected
when internal control register (0x08) bit
1 is asserted and register 0x20, CDATA
MAP register is programmed to 0x01.
USER_EDATA is always enabled and
active. It must always be configured as 8
bits wide. USER_DDATA is always
enabled. Bits 2 and 5 of Internal Control
register (0x08) should be set to enable
the USER_DACPT signal.
SYSTEM REQUIREMENTS
5.0V Power is supplied to the AHA4540 EVB
by the user’s power supply. (2.0 Amps
maximum)
Programming of the EVB requires a Pentium
class PC running Windows® 95, 98 or NT with
an RS232 port.
Page 2 of 37
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2.0
FUNCTIONAL OVERVIEW
The AHA4540 simultaneously encodes and
decodes user provided data using Turbo Product
Codes (TPCs). User provided data is clocked into
the EVB serially using signals S-UCLK and
S_UDATA from coaxial SMA connectors, or with
parallel 8-bit transfers using USER_UDATA from
the parallel connector JP3 and ready/accept
handshake signals. In Figure 2, CPLD_1 contains
the multiplexor that selects either serial data with
clock, or parallel data from the USER_UDATA bus.
Control of this multiplexor is via the AHAESB
Windows software provided. The TPC encoder in
the AHA4540 device encodes the data, adds FEC
bits, then outputs the data to CPLD_3 where the
data gets serialized and transmitted to the channel
along with the clock, S_EDATA and S_ECLK, and
also driven out in 8-bit wide format to the
USER_EDATA bus on JP4.
Once the data is output from the evalutation
board on either the serial or parallel encoded data
interfaces, it is transmitted through an external
channel where the data is corrupted by the addition
Figure 2:
of noise resulting in data bit errors. This corrupted
data is clocked into the evaluation board serially
using S_CCLK and S_CDATA or using the
USER_CDATA 16-bit wide parallel input bus on
JP5.
The S_CDATA signal is useful for wrapping
around hard decision channel data back into the
AHA4540 TPC decoder. For soft decision data the
16-bit parallel port must be used. The CDATA port
of the AHA4540 accepts up to 16-bits per clock
transfers of received channel data. This data may be
I,Q data or soft metrics. The chip can accept up to
four I,Q pairs or four soft metrics per transfer. In
serial streaming mode the received serial channel
data is deserialized into four soft metrics with the
lower 3 bits of each metric forced to zero in the
FPGA. The TPC decoder in the AHA4540 corrects
the data errors and outputs the corrected blocks
through CPLD_2 in both serialized clock and data
format, S_DDATA, S_DCLK, and parallel format
to the USER_DDATA bus on JP2.
AHA4540 EVB Block Diagram
Encoder Payload Clock
70Mhz
BERT
TRX
(SMA)
Frequency
Control
CLK_SYNC
USER_UDATA
PAR
PAR
I/O
I/O
Frequency
Synthesizer
1
USER_URDY
CPLD1
Deserializer and
2:1 MUX
8
UCLK
UD
URDY
USER_UCLK
UACPT
AHA4540
Encoder
CPLD3
Serializer
ECLK
ED
8
EPCLK
CPLD4
Deserializer
(43M)
PAR
I/O
USER_DDATA
USER_DACPT
FPGA_DACPT
8
DD
Decoder
DCLK
DPCLK
70Mhz
LCHCLK
UPI
CD
Oscillator
86 MHz
16
16
FPGA
PAR
I/O
PC I/O
RS232
LEDs
Frequency
Control
Encoder Channel Clock
Encoder Payload Clock
D1
GOUT_0
Decoder Channel Clock
D2
GOUT_1
Decoder Payload Clock
D3
Unused
D4
Unused
D5
SW1
D6
SW2
D7
SW3
FPGA RDY
D8
ENCODING OPERATION
The AHA4540 (U1) performs TPC encoding
one block at a time. For example, a 2D block with a
(n1,k1)x(n2,k2) code, would correspond to an input
block size of k1 x k2 bits. Once an entire block of
data has been input to the AHA4540, it is encoded.
The encoder would compute the extra ECC bits and
output n1 x n2 bits. On board Serializers and
PS4540evb_0802
SERIAL
I/O
(SMA)
CLK_86M
Frequency
Synthesizer
2
2.1
CLK_86M
SERIAL
I/O
(SMA)
CCLK
CPLD2
Serializer
and Buffer
BERT
REC
(SMA)
CLK_86M
HCHCLK
NOTES:
1. SMA connectors to BERT and channel Serial I/O
2. USER I/O Conn is through two 50-pin flat cables
Deserializers allow the user to accept a continuous
data stream.
2.1.1
ENCODE DATA INPUT
The AHA4540 EVB takes serial data on the
S_UDATA SMA connector. The input data is
clocked into the EVB using the S_UCLK signal.
Input data is latched on the rising edge of the
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S_UCLK signal. An output signal CLK_SYNC
may be used as a clock request signal for S_UCLK.
Parallel input data mode is supported via the
USER_UDATA bus on JP3. The data gets passed
through CPLD_1 to the AHA4540. To select
parallel mode operation the Internal Control register
0x08 bit-6 must be set by writing the register in a
user software script. The scripts are either
interactively loaded or named USERTESTx.AHA
which allows them to connect to one of the buttons
on the AHAESB control software window.
2.1.2
ENCODE DATA OUTPUT
Encoded data is output from the AHA4540
EVB encoder serially on the S_EDATA signal.
Output data is strobed out of the EVB on the falling
edge of the S_ECLK signal. This signal is the
inverted user supplied clock (CSCLK, J9. Encoded
data can be strobed out from the EVB at data rates
up to 160 Mbits/sec.
Parallel encoded data is available on the
USER_EDATA bus on connector JP4. The Internal
Control register 0x08 bits 0,1 must be set to 0x02 to
enable the USER_EACPT signal. USER_ERDY
and USER_ECLK are always driven on JP4.
2.2
DECODING OPERATION
The AHA4540 device on the EVB also operates
as a TPC decoder, operating on a single block at a
time. For a 2D block with a (n1,k1)x(n2,k2) code, n1
x n2 symbols are input for each block. Once an entire
block of data is received by the AHA4540 decoder,
it is iteratively decoded, corrupted bits are corrected
and then the block of k1 x k2 data bits is output from
the decoder.
2.2.1
DECODE DATA INPUT
The input data to the AHA4540 decoder device
on the EVB can be either hard decision data (1 bit)
or soft decision data (up to 4 bit soft decision via
USER_CDATA on the parallel connector JP5).
Hard decision serialized data can use the S_CDATA
SMA connector for data input. The rising edge of
S_CCLK is used to clock in the data when the
serialized channel input is used.
Parallel received data from the channel may be
used by enabling the USER_CDATA port on JP5.
This is a 16-bit bus that gets passed straight through
to the AHA4540 TPC decoder. Enabling this
requires writing the Internal Control register 0x08
bits 0,1 to 0x02. USER_CCLK is passed through to
Page 4 of 37
the AHA4540 CCLK signal in this mode of
operation.
2.2.2
DECODE DATA OUTPUT
The AHA4540 decoder outputs the decoded data
stream serially from the EVB on the S_DDATA SMA
connector J4. Decode data is clocked out using the
rising edge of S_DCLK output signal on SMA
connector J6. Decoded data is output from the EVB at
the programmed data rate at rates up to 160 Mbit/sec.
Maximum data rate if using an on-board synthesizer
to generate the payload bit clock is 60 Mbit/sec.
Parallel decoded data output is available on
connector JP3. The data bus and USER-DRDY are
always driven. Enabling USER_DACPT requires
setting USER_SEL and PSEL2 (bits, 2,5) in the
Internal Control register (0x08).
2.3
CLOCK SOURCES
2.3.1
CRYSTAL OSCILLATORS
There are a total of three crystal oscillators on
the EVB. Crystal (Y1) at 86.0 MHz is used for the
AHA4540 processing clocks DPCLK and EPCLK
(86 Mhz / 2). Crystal (Y2) at 3.6864 MHz is a
reference for the RS232 interface in the FPGA.
Crystal (Y3) at 30.0 MHz is the reference clock for
the frequency synthesizers (U20,U21). The
frequency synthesizers multiply this clock by six
and use an internal reference clock of 180 Mhz.
2.3.2
FREQUENCY SYNTHESIZERS
The frequency synthesizers defines the uncoded
data rates through SMA connector (J2)
CLK_SYNC and (J6) S_DCLK. Interactive
feedback control inside the FPGA automatically
adjusts the uncoded data rate frequency to prevent
data underflows or overflows, thus frequency
locking the payload side data rate to the channel side
data rate.
Maximum frequency for the two synthesizers is
60 MHz. They are programmable by writing the 4Byte control value in a user script, or selecting the
Clock Synth Tab in the Configure window, typing in
the frequencies in MHz and selecting the set button.
To determine the 4-Byte value use the equations
below. The first equation determines the code rate
including frame sync bits, and the next one
calculates the 4-Byte value that gets programmed
via the user script.
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SYNTH_CLK_FREQ = Payload Data Rage = [Message_data_bits / (Message_data_bits + ECC_bits +
Synchronization_bits)]*CHANNEL_CLCK_FREQ
[1]
4-Byte value = [Synth Byte 1, Synth Byte 2, Synth Byte 3, Synth Byte 4] = B1,B2,B3,B4
[2]
B1,B2,B3,B4 = [SYNTH_CLK_FREQ * 232] / 180
Programming Synthesizer 1, Encoder Payload Clock, requires writing this value to registers 0x0C,
0x0D, 0x0E, and 0x0F.
2.4
SYNCHRONIZATION SUPPORT
All synchroniztion support is performed by the AHA4540. See AHA4540 Product Specification for
more infomation.
2.4.1
LED STATUS DEFINITIONS (D1-D8)
Table 1:
LED Definition
LEDS
D1
D2
D3
D4
D5
D6
D7
D8
2.4.2
LED DEFINITION
GOUT_0
GOUT_1
Unused
Unused
SW1
SW2
SW3
FPGA Programmed
SWITCH DEFINITIONS
Table 2:
Switch Definition
PUSH
BUTTON
SWITCH DEFITION
SW0
SW1
SW2
SW3
Reprogram FPGA
Undefined
Undefined
Reset AHA4540, AD9851 and FPGA
2.4.3
JUMPER CLOCK CONFIGURATION (JP7)
Table 3:
Jumper Clock Configuration
JP7 PINS
1,2,3
1-2
2-3
PS4540evb_0802
ENCODER CLKSYNC SOURCE
VCO1
Frequency Synthesizer 1
2.4.4
JUMPER CLOCK CONFIGURATION (JP8)
Table 4:
Jumper Clock Configuration
JP8 PINS
1,2,3
1-2
3-4
5-6
2.5
DECODER CLKSYNC SOURCE
VCO2
User Supplied S_DCLK_IN SMA
(J13)
Frequency Synthesizer 2
LOOPBACK - TEST 1
Test 1 routes the uncoded input data to the
output data through the entire data path of the EVB
including the output connections for the user
channel. The encoder and decoder are configured
for a (128,120)2 code and the channel rate is 50
MHz. Connect the cables to the BERT as specified.
Connect an additional SMA to SMA jumper
between S_EDATA to S_CDATA and S_ECLK to
S_CCLK.
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Connect appropriate cables as specified below
for proper operation.
2.6
BERT transmitter connections:
Same system configuration as TEST 1. This
loopback test uses the (16,11)3 TPC code.
– S_UDATA (SMA J1): Data input from BERT
transmitter
– S_UCLK (SMA J3): Clock input from BERT
transmitter
– CLK_SYNC (SMA J2): Optional clock request to
BERT transmitter
BERT receiver connections:
– S_DDATA (SMA J4): Data output to BERT
receiver
– S_DCLK (SMA J6): Clock output to BERT
receiver
Note:
Cable lengths for S_UDATA and S_UCLK
should be approximately the same length
shielded coax (recommended RG58c/u or
equivalent, Zo=50ohms). Cables for S_DDATA
and S_DCLK should be approximately the same
length. (Max length 4ft.)
Channel Clock source:
CSCLK (SMA J9): Connect to external clock
source with frequency = 50.06 MHz.
• Frequency other than this will require changing
the 4-Byte value for the encoder payload clock
synthesizer in the software script named
TEST1.AHA.
Channel Loopback cables
– Connect S_ECLK (SMA J10) to S_CCLK (SMA
J7)
– Connect S_EDATA (SMA J8) to S_CDATA
(SMA J5)
– Connect CLK_SYNC (J2) to S_DCLK_IN (J13).
This allows the the Encoder synthesizer to be used
for both payload rate clock sources.
Figure 3:
BERT
TX
LOOPBACK - TEST 3
This test implements the (128, 120)2 code, at
50.06 Mb/s channel rate, and allows two separate
channel clocks and payload clocks. Both on board
synthesizers are used and locked to their appropriate
channel rate bit clock.
Same system configuration as TEST 1 except
the following:
1) Disconnect cable to S_DCLK_IN(J13)
2) Move jumper JP8 to pins 5,6
2.8
LOOPBACK TEST 4
This is a pass through test requiring one clock
source for all channel clocks and payload side
clocks and runs at any frequency up to 160 MHz.
Same system configuration as TEST 1 except
the following:
1) CLK_SYNC (SMA J2) is not used. Connect
the clock request on the BERT Transmitter
to the channel bit clock source.
2.9
LOOPBACK - TEST 5
This test uses the same system configuration as
TEST 1. It is a high speed, 160 Mb/s channel rate
test with the (16,11)3 TPC code and a payload data
rate of 51.75 Mb/s. Decoder iterations are set to 3.
Encode/Decode Loopback - Test 1
Datapath
Encoder
8
8
Payload
BERT
RX
2.7
LOOPBACK - TEST 2
Channel
8
Decoder
Loopback
Cables
8
AHA4540 - EVB
JP7 Jumper Settings: (2-3)
JP8 Jumper Settings: (2-3)
Page 6 of 37
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2.10
EVB CONFIGURATION FOR MODE 1
1)
2)
3)
4)
Connect 5V power supply to JP9 pins 1 and 2.
Connect RS232 cable to EVB and Host PC
Start AHAESB software on Host PC.
Connect to board by pressing Connect button
(Set serial port parameters correctly).
5) Connect SMA-BNC cables to EVB, Data
Source/Sink, and Channel Source/Sink as
described in Section 2.5.
6) Run AHAESB script to setup the board and
program the AHA4540 device to desired
configuration.
7) EVB should start encoding, decoding, and
passing data.
2.11 MODE 1 SCRIPT WRITING
1)
2)
3)
4)
5)
Board reset.
Program payload frequency.
Program block sizes.
Program Sync Word Length
Program the encoder/decoder configuration
into the AHA4540 device
5.1) Assign the AHA4540 address byte into
register 0x04
5.2) Assign the AHA4540 data byte into
register 0x05
5.3) Send a write strobe to the AHA4540
device by using the following line, “inc
pluto_write_strobe.aha”
5.4) (optional) You may read back your
written value with the following line, “inc
pluto_read_strobe.aha”, this will verify
that the correct value was written to the
AHA4540 device
5.5) Repeat these three or four steps for all
registers in the TPC encoder/decoder that
need to be written after a reset.
6) (Optional) The script may be tied directly to a
user test button and executed by selecting the
button on the AHAESB software window. This
requries naming the script usertest1.AHA,
usertest2.AHA, ... usertest5.AHA and locating
it in the same directory as the AHAESB.EXE
executable software.
2.13 QUICK START
This section briefly describes the steps necessary
to power-up the EVB and get Loopback Test1
running, using a standard Bit Error Rate Transmitter/
Receiver (BERT).
1) Install the AHAESB per instructions for Mode
1 above
2) Provide correct voltage to the EVB 5.0V/GND
Power Connector.
3) Connect SMA cables as shown below:
BERT transmitter connections:
– S_UDATA to BERT data output
– S_UCLK to BERT clock output
– CLK_SYNC to BERT external clock input
BERT receiver connections:
– S_DDATA to BERT data input
– S_DCLK to BERT clock input
Encode out to Decode in bypass cable:
– S_EDATA to S_CDATA on EVB
– S_ECLK to S_CCLK on EVB
4) Confirm jumpers are connected (2-3), (2-3) for
JP7 and JP8.
5) Connect external clock source to CSCLK (J9)
for the channel bit-rate clock.
6) Connect loopback cable
S_EDATA→S_CDATA.
S_ECLK→S_CCLK.
7) Run Loopback Test 1 by clicking on the
appropriate button in the AHAESB SW.
8) Set up BERT transmitter for TTL signal levels.
Verify these levels with an oscilloscope.
9) Set up BERT transmitter for external clock
sync.
10) BERT receiver should show zero bit errors, and
frequency is 43 MHz.
11) The signal monitors in the right side of the
software window should show alternating zeros
and ones indicating data is flowing from data
source to data sink through the EVB.
2.12 SOFTWARE INSTALLATION
The AHAESB software (AHAESB.exe) is used
to configure and monitor the EVB. This software is
shipped with the EVB.
PS4540evb_0802
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HARDWARE DESCRIPTION
AHA4540 EVB Major Component Diagram
JDR1
REG4
REG3
JP9
JP5
JP4
Y2
J7
Y1
V15
J9
J8
U14
V20
V9
SW0-SW3
JP6
J5
v18
Figure 4:
v12
3.0
J10
V6
J18
J2
D1D8
V21
V13
Y3
V6
V19
REG1
J4
V11
V1
J3
V10
J6
J13
J1
REG2
J11/J12
JP3
JP2
Discrete Components
AHA4540 TPC Encoder / Decoder
Xilinx Virtex E FPGA, XCV200E-PQ240
SPROM to program FPGA Controller
Altera 7032 CPLD
Altera 7032 CPLD
Altera 7032 CPLD
Altera 7032 CPLD
Line Driver (Tristatable)
Line Driver (Tristatable)
Line Driver (Tristatable)
Line Driver (Tristatable)
Line Driver (Tristatable)
Frequency Synthesizer for Payload Data Side
Clock
U21: Frequency Synthesizer for Payload Data Side
Clock
U1:
U9:
U10:
U11:
U13:
U14:
U15:
U5:
U6:
U12:
U18:
U19:
U20:
J1:
J2:
J3:
J4:
J5:
J6:
J7:
J8:
J9:
J10:
J13:
Unencoded Data (Input)
Clock Sync for BERT (Output)
Unencoded Clock (Input)
Decoded Data (Output)
Channel Data (Input)
Decoded Clock (Output)
Channel Clock (Input)
Encoded Data (Output)
Encoder Side Channel Clock (Input)
Encoded Clock (Output)
Decoder Side Channel Clock (Input)
JP6:
JP7:
JP8:
JP9:
J11:
J12:
JP2: Decoder Parallel Input:
JP3: Unencoded Parallel Input
JP4: Encoded Parallel Input
JP5: Channel Parallel Input
SW0 - SW1:
Resets
SW2 - SW3: Push Buttons
REG1: 5.0V to 2.5V Regulator
REG2: 5.0V to 12V Regulator
REG3: 5.0V to 1.8V Regulator
REG4: 5.0V to 3.3V Regulator
JDR1:RS232 Connector
Y1:
Y3:
Y2:
Page 8 of 37
JTAG Port for Altera CPLD’s
Encoder Side Payload Clock Jumper
Decoder Side Payload Clock Jumper
Power Connector
Serial Program Port for FPGA
JTAG Program Port for FPGA
86.0 Mhz Clock for AHA4540 EPCLK and
DPCLK (EPCLK = DPCLK/2)
30 MHz Crystal for Frequency Synthesizer
Reference Clock
3.6864 MHz Crystal for Serial Port
Communication base frequency
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4.0
FPGA CONTROLLER TOPLEVEL DESCRIPTION
Hierarchical FPGA VHDL Flow
Ra_pipe - Ready / Accept handshaking pipe stage
UART - Communication with the PC via RS232
port. The UART block can read and
write registers.
RS232con - Takes in Serial RS232 data and
converts it to byte wide data
CZX - Clock Zone crossing boundary
Figure 5:
UCON - Microcontroller interface. Manages
reads and writes to the register stack.
Programs the Frequency Synthesizer.
Freq_ctrl_r5 - This block determines if the
payload date frequency should be
increased or decreased to avoid an
underflow or overflow.
Micro_reg - 8-bit microcontroller register
FPGA Block Diagram
CLK_SYNC FREQUENCY CSCLK
S_DCLK
CONTROL
S_UCLK
FREQUENCY S_CCLK
CONTROL
S_DCLK_IN
MICROCONTROLLER
(UCON)
RS232
UART
Tx
Rx
EVB REGISTERS
PS4540evb_0802
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5.0
AHA4540 EVB COMMUNICATION SOFTWARE
Communication and control of the AHA4540EVB is via the RS232 interface to a host PC. The
AHAESB.exe software is provided for this purpose.
The AHAESB software operates under Windows®
95, 98, 2000, or NT. The AHAESB software allows
the user to configure the AHA4540 device on the
EVB as well as the clock synthesizers and FPGA
registers.
5.1
OPERATION OF AHAESB
SOFTWARE
To operate the AHAESB software, click on the
AHA4540 EVB icon on the Windows® desktop or
alternatively execute the program AHA4540
EVB.exe from either a DOS window or the
Windows® RUN menu. An application window for
AHA4540 EVB should open.
5.1.1
CONNECT BUTTON
This button enables connection from the PC to the
AHA4540 EVB via the RS232 cable. A pop-up menu
will appear allowing the user to configure the
communication link between host PC and the
AHA4540 EVB. Configuration parameters are: Comm
Port (COM1,2,3 or 4), Number of Stop Bits (defaults to
1), and Data Rate (defaults to 115,200 Baud).
5.1.2
CONFIGURE BUTTON
This menu allows configuration of the clock
synthesizers. Registers in the AHA4540 device can
be accessed. See the AHA4540 Product
Specification for a complete list of AHA4540
registers. The clock synthesizers are also
programmable in the configure menu. Data rate can
be controlled from this menu.
5.1.3
INTERACTIVE MODE WINDOW
The interactive mode window allows the user to
control signals with the FPGA to allow customized
control of the EVB. Script files containing
instructions for the EVB can be loaded and saved
from this window.
5.1.4
LOG WINDOW
The Log Window records all communication
transactions between the PC and the EVB.
If an error were encountered while communicating
with the EVB it would be recorded here.
5.1.5
5.1.6
USER TEST MODES
These buttons can be linked to user scripts
created by the customer. These buttons provide an
easy and quick way to access/run user defined
scripts. They must be named usertestX.aha, where X
is the button number and reside in the same directory
as the executable file for the software. The self test
bit must be off and the number of soft bits set.
5.1.7
TEST MODES
These buttons are linked to test scripts created
by AHA. These buttons provide an easy and quick
way to access/run AHA defined board functionality
tests. They must be named testX.aha, where X is the
appropriate button number.
5.1.8
AHAESB SCRIPT SYNTAX
The syntax is similar to standard assembly with
only a few operations.
WRA – Command used to write to a register in the
FPGA.
i.e., WRA 1E 0F
This would write a 0F (15-bit sync word
length) to register 1E
RDA – Command used to read a register in the
FPGA
i.e., RDA 1E
If the above write was executed first, the
response from the interactive window
would yield “0F”.
inc – Command used to include another
AHAESB script in the current script. Useful
for hierarchical script programming.
i.e., inc reset.aha
SLP – Command used to make the AHAESB SW
wait a period of time before the next
command is issued.
i.e. SLP 3E8
Sleep for 1ms
RST – Generates a board reset
5.2
ESB STATUS
The EVB status window displays the
frequencies of the two on-board frequency
synthesizers, Encoder Synthesizer and Decoder
Synthesizer. It also includes data monitors that
monitor some of the signals on the board indicating
whether the signals are changing or not.
RESET STATUS
Indicates whether or not the board is in reset.
Page 10 of 37
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6.0
REFERENCE GUIDE TO PROGRAMMING EVB REGISTERS
This guide describes all user accessible registers on the evaluation Board.
Table 5:
List of EVB Registers with Address
ADDRESS (HEX)
00
01
02
03
04
05
06
07
08
09
0B
0C
0D
0E
0F
10
11
12
13
20
28
29
2A
2B
2C
2D
2E
30
31
32
33
34
35
36
37
38
39
43
PS4540evb_0802
NAME
LOCAL_UART_ADDRESS
RESETS
CHIIP_SELECTS
CONTROL_SIGNALS
ADDRESS
OUTPUT_DATA
INPUT_DATA
INTERRUPT_STATUS
INTERNAL_CONTROL
OUTPUT_PULSE
BITFILE_VERSION_REGISTER
ENCODE_FREQUENCY_SYNTH_BYTE_1
ENCODE_FREQUENCY_SYNTH_BYTE_2
ENCODE_FREQUENCY_SYNTH_BYTE_3
ENCODE_FREQUENCY_SYNTH_BYTE_4
DECODE_FREQUENCY_SYNTH_BYTE_1
DECODE_FREQUENCY_SYNTH_BYTE_2
DECODE_FREQUENCY_SYNTH_BYTE_3
DECODE_FREQUENCY_SYNTH_BYTE_4
CDATA_MAP
SYNTHESIZERS_CONTROL
ENCODE_SYNTH_DELTA_BYTE_2
ENCODE_SYNTH_DELTA_BYTE_3
ENCODE_SYNTH_DELTA_BYTE_4
DECODE_SYNTH_DELTA_BYTE_2
DECODE_SYNTH_DELTA_BYTE_3
DECODE_SYNTH_DELTA_BYTE_4
ENC_PAYLOAD_BITS_LSB
ENC_PAYLOAD_BITS_MSB
ENC_CHANNEL_BITS_LSB
ENC_CHANNEL_BITS_MSB
ENCODE_SYNC_LENGTH
DEC_PAYLOAD_BITS_LSB
DEC_PAYLOAD_BITS_MSB
DEC_CHANNEL_BITS_LSB
DEC_CHANNEL_BITS_MSB
DECODE_SYNC_LENGTH
SIGNAL_ACTIVITY
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6.1
REGISTER DESCRIPTION
0x00 LOCAL UART ADDRESS
reset value [0x00]
Local storage of register address for UART “RDA” and “WRA” commands
0x01 RESETS
Reset signals to devices on board.
reset value [0x00]
0x02 CHIP SELECTS
bit 0 : AHA4540 chip select, MCSN
reset value [0x00]
0x03 CONTROL SIGNALS
Control signals to on board devices.
reset value [0x00]
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
:
:
:
:
:
:
:
:
Unused, always asserted low
Unused, always asserted low
Unused, always asserted low
Unused, always asserted low
Unused, always asserted low
Unused, always asserted low
AHA4540 read strobe, MRDN_DSN
AHA4540 write strobe, MWRN_RWN1
0.04
ADDRESS
Address bus to AHA4540 device, MA[5:0}
reset value [0x00]
0x05 OUTPUT DATA
Data bus to AHA4540 device, MDATA[7:0]
reset value [0x00]
0x06 INPUT DATA
Data bus from AHA4540 device, MDATA[7:0]
reset value [0x00]
0x07 INTERRUPT STATUS
Interupts from AHA4540 and GOUTx signals
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
:
:
:
:
:
:
:
:
Unused, always asserted low
Unused, always asserted low
Unused, always asserted low
Unused, always asserted low
Unused, always asserted low
AHA4540 GOUT[1] signal
AHA4540 GOUT[0] signal
AHA4540 Interrupt, MINTN
0x08 INTERNAL CONTROL
Controls mode of board.
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
:
:
:
:
:
:
:
:
Page 12 of 37
reset value [undefined]
reset value [0x00]
unused, always asserted low
Psel_1, enables USER_UDATA and USER_UCLK
Psel_2, when set along with User_sel enables USER_DACPT
Psel_4, not used
Chsel, not used
User_sel, when set along with Psel_2 enables USER_DACPT
Loopback select_1
Loopback select_0
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comtech aha corporation
Loopback select bits 1,0
0x00
0x01
0x02
0x03
:
:
:
:
Serial Streaming
Edata to Cdata internal loopback
USER_EDATA, USER_CDATA parallel ports, and USER_CCLK enabled
CRDY and EACPT always asserted high
0x09
OUTPUT PULSE
Output Control Pulses.
reset value [0x00]
0x0B BIT FILE VERSION
reset value [0x0B]
Returns the bit file version. The upper 4 bits represent the whole number part and the lower 4 bits represent
the fractional part.
0X0C ENCODE FREQUENCY SYNTH BYTE 1
reset value [0x00]
0x0D ENCODE FREQUENCY SYNTH BYTE 2
reset value [0x00]
0x0E ENCODE FREQUENCY SYNTH BYTE 3
reset value [0x00]
0x0F ENCODE FREQUENCY SYNTH BYTE 4
reset value [0x00]
These registers set the output frequency of U20, the eoncoder path synthesizer according to the following
equation:
[ BYTE_1, BYTE_2, BYTE_3, BYTE_4 ] × 180
FREQ = ------------------------------------------------------------------------------------------------------------------- MHz
32
2
0x10
0X11
0X12
0X13
DECODE FREQUENCY SYNTH BYTE 1
DECODE FREQUENCY SYNTH BYTE 2
DECODE FREQUENCY SYNTH BYTE 3
DECODE FREQUENCY SYNTH BYTE 4
reset value [0X00]
reset value [0x00]
reset value [0x00]
reset value [0x00]
These register set the output frequency of U21 the encoder path synthesizer according to the following
equation:
[ BYTE_1, BYTE_2, BYTE_3, BYTE_4 ] × 100
FREQ = ------------------------------------------------------------------------------------------------------------------- MHz
32
2
0x20 CDATA MAP
Maps CDATA port into the AHA4540 as follows
Register Value
Mapping
0x00
0x01
0x02
0x03
Others
reset value [0x00]
Deserialized Hard decision data from SMA (S_CDATA) 4 soft metrics per
transfer
16-bit USER_CDATA mapped straight through
EDAT to CDATA internal loopback
USER-EDATA to USER_CDATA external loopback (requires external
wire jumpers).
16-bit USER_CDATA mapped straight through
0x28 SYNTHESIZERS CONTROL
bits 7-2: Unused
bit 1 : When set the decoder synthesizer uses the fixed register programmed value for the frequency
delta set in registers 0x2C, 0x2D, and 0x2E as follows:
NEW_SYNTH_VALUE = [SYNTH_BYTE 1, 2, 3, 4] +/- [0,00, DELTA_BYTE 2, 3, 4]
Byte 4 is the least significant Byte of the 4-Byte value
bit 0 : When set the encoder synthesizer uses the fixed register programmed value for the frequency
delta set in registers 0x29, 0x2A, and 0x2B as follows:
NEW_SYNTH_VALUE = [SYNTH_BTE 1, 2, 3, 4] +/- [0,00, DELTA_BYTE 2, 3, 4]
Byte 4 is the least significant Byte of the 4-Byte value
PS4540evb_0802
A subsidiary of Comtech Telecommunications Corporation
Page 13 of 37
comtech aha corporation
0x29
ENCODE SYNTH DELTA BYTE 2
reset value [0x00]
0x2A
0X2B
ENCODE SYNTH DELTA BYTE 3
ENCODE SYNTH DELTA BYTE 4
reset value [0x00]
reset value [0x00]
These register values are added or subtracted to the Encoder frequency synthesizer base value in registers
0x0C, 0x0D, 0x0E, 0x0F when enabled in register 0x28
NEW_SYNTH_VALUE = [SYNTH_BYTE 1, 2, 3, 4] +/- [0x00, DELTA_BYTE 2, 3, 4]
Byte 4 is the least significant Byte of the 4-Byte value.
0x2C
0x2D
0x2E
DECODE SYNTH DELTA BYTE 2
DECODE SYNTH DELTA BYTE 3
DECODE SYNTH DELTA BYTE 4
reset value [0x00]
reset value [0x00]
reset value [0x00]
These register values are added or subtracted to the decoder frequency synthesizer base value in registers
0x10, 0x11, 0x12, 0x13 when enabled in register 0x28.
NEW_SYNTH_VALUE = [SYNTH_BYTE 1, 2, 3, 4] +/- [0x00, DELTA_BYTE 2, 3, 4]
Byte 4 is the least significant Byte of teh 4-Byte value.
0x30
0x31
ENCODE PAYLOAD BITS LSB
ENCODE PAYLOAD BITS MSB
reset value [0x00]
reset value [0x00]
Set equal to the block size of the encoder TPC unencoded block.
0x32
0x33
ENCODE CHANNEL BITS LSB
ENCODE CHANNEL BITS MSB
reset value [0x00]
reset value [0x00]
Set equal to the encoder encoded block including the FEC Bits, but not including frame sync bits.
0x34
ENCODE SYNC BITS PER FEC BLK
reset value [0x00]
Set equal to (EFSyncLength x EFSyncFreq) as programmed into the AHA4540
0x35
0x36
DECODE PAYLOAD BITS LSB
DECODE PAYLOAD BITS MSB
reset value [0x00]
reset value [0x00]
Set equal to the block size of the decoder TPC unencoded block
0x37
0x38
DECODE CHANNEL BITS LSB
DECODE CHANNEL BITS MSB
reset value [0x00]
reset value [0x00]
Set equal to the TPC decoder encoded block size including the FEC bits, but not including frame sync bits.
0x39
DECODE SYNC BITS PER FEC BLK
reset value [0x00]
Set equal to (DFSyncLength x DFSync Freq) as programmed into the AHA4540
0x43
SIGNAL ACTIVITY
Indicates activity of selected signal ports by showing current value (multiple reads need to see changes)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
:
:
:
:
:
:
:
:
Page 14 of 37
decoder payload clk
encoder payload clk
E_CLK
E_DATA (0)
C_CLK
C_DATA
D_CLK
D_DATA (0)
A subsidiary of Comtech Telecommunications Corporation
PS4540evb_0802
comtech aha corporation
7.0
REGISTER PROGRAMMING
7.1
AHA4540 REGISTERS
The AHA4540 device on the board is accessible
for programming and status information through the
AH4540AEVB software. From the program select
the interactive button. Here you can read and write
7.2
to registers in the FPGA or AHA4540. Refer to the
AHA4540 product specification for a complete
description of all registers in the AHA4540 device.
FREQUENCY SYNTHESIZERS
Two on board synthesizers are programmed via
the AHAESB software. From the program select the
Clock Synth tab in the configure window. The value
entered for Encoder Synth controls the clock
synthesizer U21. Clock synthesizer U20 is
controled by the entry Decoder Synth. Synthesizer
U21 can also be programmed via user scripts by
writing the desired values to registers 0x0C, 0x0D,
0x0E, 0x0F as outlined in Section 5.1.8 AHAESB
Script Syntax. Synthesizer U20 can be written to
using register 0x10, 0x11, 0x12, 0x13.
The ratio of the values entered for clock
synthesizers should exactly match the code rate of
the code (including synchronization bits) as shown
in the following equation:
Data Rate
Data Bits
-------------------------------- = ------------------------------------------------------------------------------------------------Channel Rate Data Bits + ECC Bits + Sync_word_bits
7.3
AHA4540 EVB FPGA REGISTERS
See Section 6.0 REFERENCE GUIDE TO
PROGRAMMING EVB REGISTERS and Section
6.1 Register Description.
PS4540evb_0802
A subsidiary of Comtech Telecommunications Corporation
Page 15 of 37
comtech aha corporation
8.0
SIGNALS IN/OUT OF EVB
8.1
EVB MAIN BOARD
PIN
CONNECTOR
J1
J3
J2
J8
J10
J9
J4
J6
J13
J7
J5
JDR1
J11
J12
JP6
JP7
JP8
JP9
SMA
SMA
SMA
SMA
SMA
SMA
SMA
SMA
SMA
SMA
SMA
9 pin DSUB
.1" Header
.1" Header
.1" Header
1x3
2x3
2x3
FUNCTION
S_UDATA
S_UCLK
CLK_SYNC
S_EDATA
S_ECLK
CSCLK
S_DDATA
S_DCLK
S_DCLK_IN
S_CCLK
S_CDATA
RS232 Serial Data Connector
FPGA Serial Program Header
FPGA JTAG Connector
CPLD JTAG Connector
Encoder Payload Clock Selector
Deocder Payload Clock Selector
DC Power Connector
9.0
ELECTRICAL SPECIFICATIONS
9.1
BOARD POWER
TYPE
Input
Input
Output
Output
Output
Input
Output
Input
Input
Input
Input
I/O
Input
I/O
I/O
Control
Control
I/O, Pwr
Power is provided from the users power supply.
5 Volts DC at 2.0 Amps JP9 pins 1 and 2.
Power consumption varies depending on customer configuration, but a minimum of 2A is required for
factory configuration.
9.2
SIGNAL REQUIREMENTS
BERT signals at SMA connectors should be TTL levels. Program BERT for threshold levels of
approximately 1.5V. Validate TTL levels using an oscilloscope.
Page 16 of 37
A subsidiary of Comtech Telecommunications Corporation
PS4540evb_0802
comtech aha corporation
10.0 TIMING SPECIFICATIONS
Figure 6:
Data Input Timings
CLOCK
1
2
DATA
Figure 7:
Data Output Timings
CLOCK
3
DATA
Table 6:
Data Input/Output Timings
NUMBER
1
2
3
PARAMETER
MIN
DATA to CLK rising edge
DATA from CLK rising edge
DATA delay from CLK rising edge
11.0 BOARD DIMENSIONS
PCB board
Overall dimensions are 5.3" x 8.8".
MAX
4
4
8
ns
ns
ns
12.0 ORDERING INFORMATION
of:
AHA4540 EVB evaluation system kit consists
QUANTITY
1
1
1
6
1
1
PS4540evb_0802
UNITS NOTES
DESCRIPTION
Evaluation board w/AHA4540
encoder/decoder
RS232 interface cable for host PC
CD ROM containing software and
pdf files of documentss
SMA to SMA interconnecting cables
(122 cm), with optional BNC
adapters
Product Specification AHA4540
Product Specification AHA4540
EVB
A subsidiary of Comtech Telecommunications Corporation
Page 17 of 37
comtech aha corporation
13.0 RELATED PUBLICATIONS
DOCUMENT #
PB4522
PB4524
PS4522
PS4524
ANTPC01
ANTPC02
ANTPC03
ANTPC04
ANTPC05
ANTPC06
ANTPC07
ANTPC08
ANTPC10
ANTPC12
ANTPC13
TPCEVAL
Page 18 of 37
DESCRIPTION
AHA Product Brief – AHA4522 Astro LE 2K Block Turbo Product Code
Encoder/Decoder
AHA Product Brief – AHA4540 Astro LE 4K Block Turbo Product Code
Encoder/Decoder
AHA Product Specification – AHA4522 Astro LE 2K Block Turbo Product
Code Encoder/Decoder
AHA Product Specification – AHA4540 Astro LE 4K Block Turbo Product
Code Encoder/Decoder
AHA Application Note – Primer: Turbo Product Codes
AHA Application Note – Use and Performance of Shortened Codes with the
AHA4501 TPC Encoder/Decoder)
AHA Application Note – Turbo Product Code Encoder/Decoder with
Quadrature Amplitude Modulation (QAM)
AHA Application Note – Use and Performance of the AHA4501 TPC Encoder/
Decoder with Differential Phase Shift Keying (DPSK)
AHA Application Note – AHA4501 Turbo Product Code Encoder/Decoder
Designers Guide
AHA Application Note – AHA4501 Turbo Product Code Encoder/Decoder
Frequently Asked Questions (FAQ)
AHA Application Note – Turbo Product Codes for LMDS
AHA Application Note – Using Multiple AHA4501 Devices in Parallel for
Higher Data Rates
AHA Application Note – Shannon Limit vs. Constellation Constrained
Capacity
AHA Application Note – “enhanced” Turbo Product Codes (eTPCs)
AHA Application Note - AHA4540 with ARIB Standard
AHA Evaluation Software – Turbo Product Codes - Windows Evaluation
Software
A subsidiary of Comtech Telecommunications Corporation
PS4540evb_0802
PS4540evb_0802
A
B
C
D
A subsidiary of Comtech Telecommunications Corporation
TDO
TDI
TMS
TCK
USER_EDATA[7:0]
USER_ESTART
USER_EEND
USER_EACPT
USER_ERDY
ECLK
USER_CDATA[15:0]
USER_ROTATE
USER_CACPT
USER_CPCLK
USER_CRDY
USER_CSTART
USER_CLSB
TEST10
TEST[7:0]
CSCLK
S_EDATA
S_ECLK
BUFOEN3
S_CDATA
S_CCLK
USER_DRDY
USER_DACPT
DCLK
BUFOEN2
USER_DDATA[7:0]
S_DDATA
S_DCLK
DSTART
DEND
DERR
S_DCLK_IN
USER_CDATA[15:0]
TEST[7:0]
5
USER_EDATA[7:0]
USER_ESTART
USER_EEND
USER_EACPT
USER_ERDY
ECLK
USER_CPCLK
TEST10
RESET_CPLD
FPGA_DACPT
USERSEL
TDO1
TMS
TCK
FPGA_PSEL2
CPLD2
RESETN
S_DDATA
DCLK
S_DCLK
DRDY
SCLK
DACPT
BUFOEN2
DDATA_[7:0]
USER_DDATA[7:0]
FPGA_PSEL2
TDO
USER_DRDY
USER_DACPT
FPGA_DACPT
USERSEL
TDI
TMS
TCK
CPLD2
FREQ_SYNTH_DECODER
CLK_30M0
DEC_PAYLOAD_CLK
DCA_1
DCA_0
DCA_2
(FPGA)
TDO1
VCO_OUT
TDO2
VCO2
PC_IO_POWER
TXOUT
PC_IO_POWER
4
RIN
SWITCHES
SW0
SW1
SW2
SW3
switches1
3
MDATA[7:0]
RESETN
MA[6:0]
DSTART
DEND
DERR
DDATA[7:0]
DRDY
DCLK
RESET_AD9851
ENC_PAYLOAD_CLK
ENC_CHANNEL_CLK
DEC_PAYLOAD_CLK
S_CCLK
FSDATA[7:0]
FQ_UD_ENC
WLOAD_ENC
FQ_UD_DEC
WLOAD_DEC
USER_EACPT
3
LOAD_PGMN
SW1
SW2
SW3
DEC_CHANNEL_CLK
DCA_[2:0]
Channel Rate (172 MHz max)
UCA_[2:0]
DDATA[7:0]
VCO_OUT
CLKADJ[1]
CLKADJ[0]
VCO2
Pay Load
Rate (285
MHz max)
VCO1
CLKADJ[1]
CLKADJ[0]
VCO1
UDATA[7:0]
UCA_1
UCA_0
4
Put Decoupling Caps,
Terminating Resistors
(RES_TERM block) and
Regulators on bottom side
of board if necessary.
USER_DRDY
USER_DDATA[7:0]
CSCLK
S_EDATA
S_ECLK
BUFOEN3
S_CDATA
S_CCLK
CLK_SYNC_OUT
BUFOEN1
UECZERO
CHSEL
FPGA_PSEL
RESETN
CPLD1
FREQ_SYNTH_DECODER
FSDATA[7:0]
D[7:0]
S_DCLK_IN
VSCLK
DEC_PAYLOAD_CLK
FQ_UD_DEC
CLK_30M0
WLOAD_DEC FQ_UD
RESET_AD9851 WLOAD
RESET_AD9851
CLK_SYNC
UECZERO
CHSEL
FPGA_PSEL1
RESET_CPLD
DSTART
DEND
DERR
TDI
TMS
TCK
TDO4
TDI
TMS
TCK
USER_UDATA[7:0]
UCA_2
(FPGA)
CLK_SYNC
S_UDATA
URDY
S_UCLK
UACPT
USER_UCLK
UDATA[7:0]
USER_URDY
USER_UDATA[7:0]
UCLK
USER_UACPT
TDI
TDO
TMS
TCK
CPLD1
FREQ_SYNTH_ENCODER
CLK_SYNC
ENC_PAYLOAD_CLK
CLK_30M0
FREQ_SYNTH_ENCODER
RESET_AD9851
CLK_SYNC_OUT
BUFOEN1
IO_CONN
5
D[7:0]
VSCLK
FQ_UD
ENC_PAYLOAD_CLK
WLOAD
CLK_30M0
S_UDATA
S_UCLK
USER_UCLK
USER_URDY
USER_UDATA[7:0]
USER_UACPT
I/O_CONN
RESET_AD9851
FSDATA[7:0]
FQ_UD_ENC
WLOAD_ENC
TEST[7:0]
FPGA
LOAD_PGMN
SW1
SW2
SW3
UCLKADJ2
DCLKADJ2
CPCLK_SER
CLK_43M0
EDATA[7:0]
ESTART
EEND
ECLK
ERDY
2
UCA_2
DCA_2
CPCLK_SER
CLK_43M0
CCLK
RESET_CPLD
FPGA_PSEL1
FPGA_PSEL2
FPGA_PSEL4
CHSEL
FPGA_DACPT
USERSEL
ECLK
UECZERO
EDATA[7:0]
ERDY
EACPT
CPLD3_EACPT
CSDATA[7:0]
LEDN[7:0]
CDATA[15:0]
CCLK
EACPT
TEST[7:0]
CRDY
CACPT
CSTART
CLSB
CDATA[15:0]
ROTATE
GOUT1
GOUT0
EPCLK
CCLK
DPCLK
EACPT
EDATA[7:0]
ESTART
EEND
ECLK
ERDY
GOUT0
GOUT1
ROTATE
CDATA[15:0]
CLSB
CSTART
CACPT
CRDY
EDATA[7:0]
DDATA[7:0]
ERDY
DRDY
EACPT
DCLK
CPLD3_EACPT
RESET_AD9851
CSDATA[7:0]
ENC_PAYLOAD_CLK LEDN[7:0]
ENC_CHANNEL_CLK
DEC_PAYLOAD_CLK INVALIDN
DEC_CHANNEL_CLK
ROUT
FSDATA[7:0]
TXIN
FQ_UD_ENC
ECLK
WLOAD_ENC
UECZERO
FQ_UD_DEC
RS232EN
WLOAD_DEC
PSEL1
USER_EACPT
PSEL2
USER_CDATA[15:0]
PSEL4
USER_ROTATE
CHSEL
USER_CACPT
FPGA_DACPT
USER_CPCLK
USERSEL
USER_CRDY
USER_CSTART
CCLK
USER_CLSB
RESET_CPLD
MRDY_DTACKN
MINTN
MALE
MWRN_RWN
MRDN_DSN
MA[6:0]
MCSN
PROCMODE
MUXMODE
MDATA[7:0]
RESETN
FPGA
AHA4540
MDATA[7:0]
MUXMODE
PROCMODE
MCSN
MA[6:0]
MRDN_DSN
MWRN_RWN
MALE
MINTN
MRDY_DTACKN
RESETN
DSTART
DEND
DERR
DCLKADJ[2:0]
DCLK
DRDY
DACPT
DDATA[7:0]
UCLK
UCLKADJ[2:0]
URDY
UACPT
UDATA[7:0]
AHA4540
2
Date:
Size
B
Title
Friday, March 29, 2002
Document Number
AHA4540_EVB
RIN
RS232_IO
TDO
CLK_43M0
TXOUT
1
1
of
DECOUPLING
INVALIDN
Sheet
19
FPGA_PSEL4
RESET_CPLD
TDO4
CLK_43M0
S_CDATA
S_CCLK
CHSEL
RESET_CPLD
Rev
A
ENC_CHANNEL_CLK
S_EDATA
S_ECLK
BUFOEN3
TDO3
CSCLK
USER_EDATA[7:0]
USER_ESTART
USER_EEND
USER_ERDY
DECOUPLING
ROUT
FPGA_PSEL4
RESETN
RS232EN
TXIN
RS232_IO
LEDS
LEDN[7:0]
LEDS
CPLD4
TDI
TMS
TCK
CSDATA[7:0]
S_CDATA
S_CCLK
CHSEL
RESETN
ENC_CHANNEL_CLK
EPCLK
CPCLK_SER
DPCLK
AHA4540_EVB
TDO3
TMS
TCK
CPLD3
TDI
TMS
TCK
CPLD4
CPCLK_SER
TDO2
TMS
TCK
TEST10
CPLD3_EACPT
CSCLK
USER_EDATA[7:0]
USER_ESTART
USER_EEND
EDATA[7:0]
USER_ERDY
ESTART
EEND
S_EDATA
EACPT
S_ECLK
BUFOEN3
TEST10
TDO
VSCLK
ECLK
ERDY
CPLD3
1
A
B
C
D
comtech aha corporation
APPENDIX A: BOARD SCHEMATICS
Page 19 of 37
A
B
C
D
DPCLK
MRDN_DSN
MWRN_RWN
MALE
MINTN
MRDY_DTACKN
MA[6:0]
MUXMODE
PROCMODE
MCSN
MDATA[7:0]
VDD_3_3
RESETN
DSTART
DEND
DERR
DDATA[7:0]
R1
5
MA[6:0]
MDATA[7:0]
3.3K
DDATA[7:0]
DCLKADJ[2:0]
MA6
MA5
MA4
MA3
MA2
MA1
MA0
MDATA7
MDATA6
MDATA5
MDATA4
MDATA3
MDATA2
MDATA1
MDATA0
DDATA7
DDATA6
DDATA5
DDATA4
DDATA3
DDATA2
DDATA1
DDATA0
DCLKADJ2
DCLKADJ1
DCLKADJ0
171
33
32
35
57
56
29
28
27
26
25
22
21
15
16
34
53
52
47
46
45
42
41
40
5
6
189
190
191
207
206
205
202
201
200
195
194
183
182
181
188
165
DCLKADJ[2:0]
81
168
94
91
90
89
88
85
84
83
UDATA7
UDATA6
UDATA5
UDATA4
UDATA3
UDATA2
UDATA1
UDATA0
UDATA[7:0]
DRDY
DACPT
71
68
67
UCLKADJ2
UCLKADJ1
UCLKADJ0
UCLKADJ[2:0]
82
64
UCLK
DCLK
UDATA[7:0]
UCLKADJ[2:0]
URDY
UACPT
DPCLK
MRDN_DSN
MWRN_RWN
MALE
MINTN
MRDY_DTACKN
MA[6]
MA[5]
MA[4]
MA[3]
MA[2]
MA[1]
MA[0]
MUXMODE
PROCMODE
MCSN
MDATA[7]
MDATA[6]
MDATA[5]
MDATA[4]
MDATA[3]
MDATA[2]
MDATA[1]
MDATA[0]
RESETN
TRISTATEN
DSTART
DEND
DERR
DDATA[7]
DDATA[6]
DDATA[5]
DDATA[4]
DDATA[3]
DDATA[2]
DDATA[1]
DDATA[0]
DCLKADJ[2]
DCLKADJ[1]
DCLKADJ[0]
DRDY
DACPT
UCLK
DCLK
UDATA[7]
UDATA[6]
UDATA[5]
UDATA[4]
UDATA[3]
UDATA[2]
UDATA[1]
UDATA[0]
UCLKADJ[2]
UCLKADJ[1]
UCLKADJ[0]
URDY
UACPT
U1
VDD_1_8
4
4
11
18
24
31
37
44
49
55
61
70
74
80
87
93
100
106
112
119
126
132
138
143
147
154
160
167
173
180
187
193
199
204
AHA4540
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
A subsidiary of Comtech Telecommunications Corporation
4
3
10
17
23
30
36
43
48
54
60
69
73
79
86
92
99
105
111
118
125
131
137
142
146
153
159
166
172
179
186
192
198
203
208
3
2
20
39
51
63
66
78
98
103
114
124
130
152
170
178
185
197
3
ERDY
EACPT
ESTART
EEND
EPCLK
AGND
AVDD
ECLK
CCLK
59
58
76
75
72
176
14
13
12
9
8
7
127
162
161
158
157
156
155
149
148
145
144
141
140
139
136
135
134
163
128
164
150
96
133
AHA4540
Package = PQ150
GOUT[1]
GOUT[0]
TESTO[2]
TESTO[1]
TESTO[0]
TESTI[6]
TESTI[5]
TESTI[4]
TESTI[3]
TESTI[2]
TESTI[1]
TESTI[0]
ROTATE
CDATA[15]
CDATA[14]
CDATA[13]
CDATA[12]
CDATA[11]
CDATA[10]
CDATA[9]
CDATA[8]
CDATA[7]
CDATA[6]
CDATA[5]
CDATA[4]
CDATA[3]
CDATA[2]
CDATA[1]
CDATA[0]
CRDY
CACPT
CSTART
CLSB
122
121
120
117
116
115
110
109
104
95
107
108
101
174
175
VDD_3_3
EDATA[7]
EDATA[6]
EDATA[5]
EDATA[4]
EDATA[3]
EDATA[2]
EDATA[1]
EDATA[0]
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
Page 20 of 37
1
19
38
50
62
65
77
97
102
113
123
129
151
169
177
184
196
5
2
Date:
Size
B
Title
GOUT1
GOUT0
ROTATE
CDATA[15:0]
CRDY
CACPT
CSTART
CLSB
ECLK
CCLK
EDATA[7:0]
ERDY
EACPT
ESTART
EEND
EPCLK
Friday, March 29, 2002
Document Number
AHA4540_EVB
AHA4540 Device
CDATA[15:0]
EDATA[7:0]
Leave test output pins unconnected
CDATA15
CDATA14
CDATA13
CDATA12
CDATA11
CDATA10
CDATA9
CDATA8
CDATA7
CDATA6
CDATA5
CDATA4
CDATA3
CDATA2
CDATA1
CDATA0
EDATA7
EDATA6
EDATA5
EDATA4
EDATA3
EDATA2
EDATA1
EDATA0
VDD_1_8
2
1
Sheet
1
2
of
19
Rev
A
A
B
C
D
comtech aha corporation
PS4540evb_0802
PS4540evb_0802
A subsidiary of Comtech Telecommunications Corporation
A
B
C
D
5
USER_UDATA[7:0]
UACPT
USER_UCLK
CHSEL
FPGA_PSEL
5
USER_URDY
S_UDATA
TMS
TDI
TCK
UECZERO
CLK_SYNC
S_UCLK
RESETN
VDD_3_3
VDD_2_5
4
4
USER_UDATA0
USER_UDATA1
USER_UDATA2
USER_UDATA3
USER_UDATA4
10
22
30
42
3
15
23
35
1
44
2
43
4
5
6
8
9
11
12
14
CPLD1
3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O(TCK)
I/O(TDI)
I/O(TDO)
I/O(TMS)
EPM7032V
Package = PLCC44
GND
GND
GND
GND
VCCINT
VCCIO1
VCCINT
VCCIO2
INPUT/GCLRN
INPUT/OE1
INPUT/OE2/GCLK2
INPUT/GCLK1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
U11
USER_UDATA[7:0]
3
32
7
38
13
27
26
25
24
39
37
36
34
33
31
29
28
16
17
18
19
20
21
41
40
Date:
Size
A
Title
UDATA3
UDATA2
UDATA4
UDATA7
UDATA6
UDATA5
UDATA0
UDATA1
UDATA[7:0]
2
Friday, March 29, 2002
Document Number
AHA4540_EVM
Sheet
3
UCLK
URDY
CPLD1, Deserializer, SMA or USER Port to UDATA
USER_UDATA5
USER_UDATA6
USER_UDATA7
2
UDATA[7:0]
1
of
TDO
19
USER_UACPT
Rev
A
BUFOEN1
CLK_SYNC_OUT
1
A
B
C
D
comtech aha corporation
Page 21 of 37
Page 22 of 37
A subsidiary of Comtech Telecommunications Corporation
A
B
C
D
5
TMS
TDI
TCK
USERSEL
USER_DACPT
FPGA_DACPT
SCLK
RESETN
FPGA_PSEL2
DDATA_[7:0]
DRDY
5
VDD_3_3
VDD_2_5
4
USER_DDATA0
USER_DDATA1
4
10
22
30
42
3
15
23
35
1
44
2
43
4
5
6
8
9
11
12
14
CPLD2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O(TCK)
I/O(TDI)
I/O(TDO)
I/O(TMS)
EPM7032V
Package = PLCC44
GND
GND
GND
GND
VCCINT
VCCIO1
VCCINT
VCCIO2
INPUT/GCLRN
INPUT/OE1
INPUT/OE2/GCLK2
INPUT/GCLK1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
U13
DDATA[7:0]
3
32
7
38
13
27
26
25
24
39
37
36
34
33
31
29
28
16
17
18
19
20
21
41
40
3
DDATA7
DDATA6
DDATA5
DDATA4
DDATA3
DDATA2
DDATA1
DDATA0
USER_DDATA2
USER_DDATA3
USER_DDATA4
USER_DDATA5
USER_DDATA6
USER_DDATA7
Date:
Size
A
Title
2
Friday, March 29, 2002
Document Number
<Doc>
1
Sheet
TDO
DCLK
DACPT
4
1
USER_DDATA[7:0]
S_DDATA
S_DCLK
BUFOEN2
USER_DRDY
CPLD2, Serializer, DDATA to SMA
USER_DDATA[7:0]
2
of
19
Rev
A
A
B
C
D
comtech aha corporation
PS4540evb_0802
PS4540evb_0802
A subsidiary of Comtech Telecommunications Corporation
A
B
C
D
TMS
TDI
TCK
VSCLK
CSCLK
5
RESETN
ESTART
EEND
CHSEL
EDATA[7:0]
ERDY
5
VDD_3_3
VDD_2_5
EDATA0
EDATA1
EDATA2
EDATA3
EDATA4
4
4
10
22
30
42
3
15
23
35
1
44
2
43
4
5
6
8
9
11
12
14
CPLD3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
3
I/O(TCK)
I/O(TDI)
I/O(TDO)
I/O(TMS)
EPM7032V
Package = PLCC44
GND
GND
GND
GND
VCCINT
VCCIO1
VCCINT
VCCIO2
INPUT/GCLRN
INPUT/OE1
INPUT/OE2/GCLK2
INPUT/GCLK1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
U14
3
32
7
38
13
27
26
25
24
39
37
36
34
33
31
29
28
16
17
18
19
20
21
41
40
Date:
Size
A
Title
USER_EDATA1
USER_EDATA0
USER_EDATA2
USER_EDATA3
USER_EDATA5
USER_EDATA4
USER_EDATA7
USER_EDATA6
EDATA5
EDATA6
EDATA7
USER_EDATA[7:0]
2
Friday, March 29, 2002
Document Number
<Doc>
CPLD3, Serializer, EDATA to SMA
2
Sheet
5
1
of
USER_ESTART
USER_EEND
TDO
19
Rev
A
ENC_CHANNEL_CLK
TEST10
USER_ERDY
BUFOEN3
S_ECLK
S_EDATA
ECLK
EACPT
USER_EDATA[7:0]
1
A
B
C
D
comtech aha corporation
Page 23 of 37
A subsidiary of Comtech Telecommunications Corporation
A
B
C
OSC86M0
1
EN OUT
Y1
5
3
TMS
TDI
TCK
S_CCLK
RESETN
S_CDATA
VDD_3_3
Package = HG-8002JA
FPGA_PSEL4
4
GND
VCC
Page 24 of 37
2
D
5
VDD_3_3
VDD_2_5
4
4
10
22
30
42
3
15
23
35
1
44
2
43
4
5
6
8
9
11
12
14
CPLD4
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
3
I/O(TCK)
I/O(TDI)
I/O(TDO)
I/O(TMS)
EPM7032V
Package = PLCC44
GND
GND
GND
GND
VCCINT
VCCIO1
VCCINT
VCCIO2
INPUT/GCLRN
INPUT/OE1
INPUT/OE2/GCLK2
INPUT/GCLK1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
U15
3
32
7
38
13
27
26
25
24
39
37
36
34
33
31
29
28
16
17
18
19
20
21
41
40
CSDATA7
CSDATA6
Date:
Size
A
Title
R44 70
R42 70
R41 70
TDO
CPCLK_SER
CSDATA[7:0]
2
Friday, March 29, 2002
Document Number
<Doc>
Sheet
CPLD4, Deserializer, Serial input to 8-bit data
CSDATA5
CSDATA4
CSDATA3
CSDATA2
R40 70 CSDATA1
CSDATA0
R43 70
1
6
1
of
19
Rev
A
CLK_43M0
EPCLK
DPCLK
CSDATA[7:0]
Place all 70 ohm resistors
near CPLD4 on the appropriate
pin.
2
A
B
C
D
comtech aha corporation
PS4540evb_0802
PS4540evb_0802
A
B
C
D
VDD_3_3
VDD_3_3
VDD_1_8
VDD_1_8
VDD_1_8
VDD_3_3
C96
0.1uF
C74
0.1uF
C64
0.1uF
C47
0.1uF
C30
0.1uF
C9
0.1uF
A subsidiary of Comtech Telecommunications Corporation
CPLD1
5
C97
0.1uF
C75
0.1uF
C65
0.1uF
C48
0.1uF
C31
0.1uF
C10
0.1uF
5
C98
0.1uF
C76
0.1uF
C66
0.1uF
C49
0.1uF
C32
0.1uF
C11
0.1uF
C68
0.1uF
C51
0.1uF
C34
0.1uF
C13
0.1uF
C99
0.1uF
VDD_2_5
C77
0.1uF
C79
0.1uF
C69
0.1uF
C52
0.1uF
C35
0.1uF
C14
0.1uF
VDD_3_3
C78
0.1uF
XILINX FPGA
Device
C67
0.1uF
C50
0.1uF
C33
0.1uF
C12
0.1uF
C100
0.1uF
4
C81
0.1uF
C71
0.1uF
C54
0.1uF
C37
0.1uF
C16
0.1uF
C101
0.1uF
CPLD2
C80
0.1uF
C70
0.1uF
C53
0.1uF
C36
0.1uF
C15
0.1uF
4
C102
0.1uF
C82
0.1uF
C72
0.1uF
C55
0.1uF
C38
0.1uF
C17
0.1uF
C103
0.1uF
VDD_2_5
C83
0.1uF
C73
0.1uF
C56
0.1uF
C39
0.1uF
C18
0.1uF
VDD_3_3
C84
0.1uF
VDD_5_0
C57
0.1uF
C40
0.1uF
C19
0.1uF
C59
0.1uF
C42
0.1uF
C21
0.1uF
CPLD3
C105
0.1uF
C86
0.1uF
C183
0.1uF
AD9851, U20
C104
0.1uF
C85
0.1uF
C182
0.1uF
C58
0.1uF
C41
0.1uF
C20
0.1uF
3
C106
0.1uF
C87
0.1uF
C184
0.1uF
C60
0.1uF
C43
0.1uF
C22
0.1uF
3
C89
0.1uF
C107
0.1uF
VDD_3_3
C90
0.1uF
C186
0.1uF
C63
0.1uF
C46
0.1uF
C25
0.1uF
VDD_5_0
C62
0.1uF
C45
0.1uF
C24
0.1uF
VDD_2_5
C88
0.1uF
C185
0.1uF
C61
0.1uF
C44
0.1uF
C23
0.1uF
C108
0.1uF
C91
0.1uF
C187
0.1uF
C188
0.1uF
C189
0.1uF
2
C110
0.1uF
C93
0.1uF
CPLD4
C109
0.1uF
C92
0.1uF
AD9851, U21
2
C111
0.1uF
Date:
Size
B
Title
U6
C138
0.1uF
C143
0.1uF
C147
0.1uF
Friday, March 29, 2002
Document Number
<Doc>
Decoupling Caps
C146
0.1uF
VDD_3_3
C140
0.1uF
AGND
U10
1
7
C149
0.1uF
U16
of
19
Rev
A
C151
0.1uF
MAX3221
C150
0.1uF
C145
0.1uF
VDD_3_3
C141
0.1uF
BOTH
MAX997
U4 & U8
C142
0.1uF
VDD_3_3
C29
0.1uF
VDD_1_8
C136
0.1uF
U18
Sheet
C148
0.1uF
SPROM 18V04
BOTH
JTOS-300
1
C28
0.1uF
C135
0.1uF
U19
C144
0.1uF
C139
0.1uF
SN74LVT125
C134
0.1uF
C27
0.1uF
Miscellaneous
U12
AGND
ANALOG_12
U2 & U7
C95
0.1uF
VDD_2_5
C94
0.1uF
U5
C137
0.1uF
VDD_3_3
C133
0.1uF
C26
0.1uF
BOTH
OP283
ANALOG_16
VDD_3_3
U3A & U17A
DECOUPLING
CAPS
AHA4540 Device
A
B
C
D
comtech aha corporation
Page 25 of 37
A
B
C
JTAG for
SPROM and
FPGA
VDD_3_3
4.7K
26
28
29
30
31
33
35
36
38
9
11
19
13
LOAD PROGRAM FROM
PROM
LOAD PROGRAM FROM PC
PARALLEL PORT CABLE
18V0 4
Package = PLCC44
NC
NC
NC
NC
NC
NC
NC
NC
NC
TDI
TMS
RESETN
TCK
U10
VDD_3_3
5
Note: U7 (SPROM) is socketed, surface mount
socket with locating pins.
R27
VDD_3_3
Package = TH_STP_HDR_6
CON6
1
2
3
4
5
6
J12
PGM_CCLK
DONE
DIN
LOAD_PGMN
VDD_3_3
CON6
Package = TH_STP_HDR_6
1
2
3
4
5
6
J11
FPGA PGM CABLE
1
2
3
VDD_3_3
MDATA[7:0]
NC
NC
NC
TDO
D0
CLK
CEN
CEON
CFN
39
40
43
37
2
5
21
27
16
MALE
USER_ROTATE
MWRN_RWN
MRDN_DSN
MCSN
PROCMODE
MUXMODE
MRDY_DTACKN
MINTN
UCLKADJ2
UECZERO
RS232EN
GOUT0
GOUT1
INVALIDN
TXIN
ROUT
CSDATA[7:0]
MA[6:0]
ERDY
PSEL2
RESETN
CHSEL
PSEL1
CRDY
CACPT
CSTART
EACPT
ECLK
PSEL4
CLSB
USER_EACPT
USERSEL
CPLD3_EACPT
ROTATE
EDATA[7:0]
CDATA[15:0]
HEADER_3
Package = TH_STP_HDR_3
JP1
MDATA[7:0]
MA[6:0]
CSDATA[7:0]
EDATA[7:0]
CDATA[15:0]
4
24
26
27
28
31
33
34
35
36
38
39
40
41
42
46
47
CDATA13
CDATA14
CDATA15
EDATA1
EDATA2
EDATA3
EDATA4
EDATA5
EDATA6
EDATA7
R25
LOAD_PGMN
DIN
PROGRAM
TMS
TDI
TDO
TCK
D0/DIN(I/O)
I/O_INIT
M0
M1
M2
I/O
I/O
I/O
I/O_VREF
I/O
I/O
I/O_VREF
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O_VREF
I/O
I/O_VREF
I/O
I/O
I/O
I/O
I/O
I/O
I/O_VREF
I/O
I/O_VREF
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O_VREF
I/O
I/O
I/O_VREF
I/O
I/O
I/O
I/O_VREF
I/O
I/O
I/O
I/O
I/O
I/O_VREF
I/O
I/O
I/O
I/O
I/O
I/O
I/O_VREF
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O_VREF
I/O
I/O
I/O
I/O
I/O
I/O
I/O_VREF
I/O
I/O
I/O_VREF
I/O
I/O
I/O_VREF
I/O_
I/O
U9
XCV200E-8PQ24 0C
Package = PQ240
122
2
183
181
239
177
123
60
58
62
124
125
110
111
113
114
115
117
118
MDATA1
MDATA2
MDATA3
MDATA4
MDATA5
MDATA6
MDATA7
84
86
87
93
94
95
96
97
72
73
74
78
79
80
81
82
63
64
65
66
67
68
70
71
99
100
101
102
103
107
108
109
3.3K
CSDATA0
CSDATA1
CSDATA2
CSDATA3
CSDATA4
CSDATA5
CSDATA6
CSDATA7
48
49
50
52
53
54
56
57
12
13
17
18
19
20
21
23
CDATA5
CDATA6
CDATA7
CDATA8
CDATA9
CDATA10
CDATA11
CDATA12
EDATA0
3
4
5
6
7
9
10
11
CDATA0
CDATA1
CDATA2
CDATA3
CDATA4
3
FPGA
15
25
30
44
55
61
76
85
90
105
116
121
136
146
150
165
176
180
197
207
212
226
232
240
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VDD_3_3
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MDATA0
LOAD_PGMN
4
16
32
43
77
88
104
137
148
164
198
214
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
D
23
41
44
14
22
32
42
VCC
VCC
VCC
VCCO
VCCO
VCCO
VCCO
3
12
24
34
GND
GND
GND
GND
1
4
6
7
10
15
17
18
20
25
A subsidiary of Comtech Telecommunications Corporation
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
3
I/O_DOUT_BUSY
DONE
CCLK
GCK3
GCK2
GCK1
GCK0
I/O
I/O
I/O
I/O
I/O_VREF
I/O
I/O_VREF
I/O
I/O
I/O_VREF
I/O
I/O_VREF
I/O
I/O_VREF
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O_VREF
I/O
I/O
I/O
I/O
I/O
I/O_VREF
I/O
I/O
I/O_VREF
I/O
I/O
I/O_VREF
I/O
I/O
I/O_VREF
I/O_CS
I/O_WRITE
I/O
I/O_VREF
I/O
I/O
I/O
I/O
I/O
I/O_VREF
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O_VREF
I/O
I/O
I/O
I/O
I/O
I/O
I/O_VREF
I/O
I/O_VREF
I/O_VREF
I/O
I/O
I/O
I/O
I/O
I/O_VREF
I/O
USER_CDATA[15:0]
178
120
179
213
210
89
92
237
238
224
228
229
230
231
234
235
236
215
216
217
218
220
221
222
223
DONE
PGM_CCLK
2
DDATA3
DDATA4
DDATA5
DDATA6
DDATA7
DDATA0
DDATA1
DDATA2
LEDN4
LEDN5
LEDN6
LEDN7
R26
390
DDATA[7:0]
VDD_3_3
CPCLK_SER
Date:
Size
C
Title
ENC_CHANNEL_CLK
ENC_PAYLOAD_CLK
CCLK
DRDY
DCLKADJ2
FPGA_DACPT
DCLK
LEDN0
LEDN1
LEDN2
LEDN3
200
201
202
203
205
206
208
209
DDATA[7:0]
LEDN[7:0]
TEST[7:0]
FSDATA[7:0]
1
CLK_3M686 4
OSC3M686 4
Friday, March 29, 2002
EN
Y2
1
Sheet
OUT
3
VDD_3_3
USER_CDATA[15:0]
1
Package = HG-8002JA
Document Number
<Doc>
FPGA
LEDN[7:0]
TEST[7:0]
TEST0
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
TEST7
188
189
191
192
193
194
195
199
RESET_CPLD
SW2
SW3
FSDATA[7:0]
DEC_CHANNEL_CLK
DEC_PAYLOAD_CLK
FQ_UD_ENC
WLOAD_ENC
FQ_UD_DEC
WLOAD_DEC
SW1
RESET_AD9851
USER_CLSB
USER_CSTART
USER_CACPT
USER_CRDY
USER_CPCLK
CLK_43M0
USER_ROTATE
FSDATA0
FSDATA1
FSDATA2
FSDATA3
FSDATA4
FSDATA5
FSDATA6
FSDATA7
USER_CDATA15
USER_CDATA7
USER_CDATA8
USER_CDATA9
USER_CDATA10
USER_CDATA11
USER_CDATA12
USER_CDATA13
USER_CDATA14
USER_ROTATE
USER_CDATA0
USER_CDATA1
USER_CDATA2
USER_CDATA3
USER_CDATA4
USER_CDATA5
USER_CDATA6
171
173
174
175
184
185
186
187
160
161
162
163
167
168
169
170
149
152
153
154
155
156
157
159
138
139
140
141
142
144
145
147
126
127
128
130
131
132
133
134
VDD_1_8
2
4
GND
VCC
2
Page 26 of 37
1
8
14
22
29
37
45
51
59
69
75
83
91
98
106
112
119
129
135
143
151
158
166
172
182
190
196
204
211
219
227
233
5
8
of
19
Rev
<RevCode>
A
B
C
D
comtech aha corporation
PS4540evb_0802
A
B
C
D
CLK_30M0
5
RESET_AD9851
WLOAD
FQ_UD
D[7:0]
VSCLK
S_DCLK_IN
4
4
D7
D6
D5
D4
D3
D2
D1
D0
R95
3.9K
22
12
8
9
7
25
26
27
28
1
2
3
4
AD9851
RESET
RSET
FQ_UD
CLKIN
W_CLK
D7
D6
D5
D4
D3
D2
D1
D0
U20
VDD_5_0
3
6
23
11
18
VINP
DACBL(NC)
IOUTB
VINN
IOUT
QOUT
QOUTB
DVDD
DVDD
AVDD
AVDD
AGND
AGND
DGND
DGND
PS4540evb_0802
3
19
10
24
5
5
16
17
20
15
21
14
13
470pF
C167
33
R50
R94
100
R93
100K
R90
100K
R91
200
R51
70
2
4
6
2
C163
22pF
1pF
C160
L1
470nH
HEADER 3X2
1
3
5
JP8
2
A subsidiary of Comtech Telecommunications Corporation
Date:
Size
B
Friday, March 29, 2002
Document Number
AHA4524_EVB
FREQUENCY SYNTH DECODER
22pF
33pF
Title
C165 4.7pF
C162
L3
390nH
R53
70
C164 5.6pF
C161
L2
390nH
33
R52
1
9
of
R92
200
19
DEC_PAYLOAD_CLK
CLK_SYNC
C166
22pF
Sheet
1
Rev
D
A
B
C
D
comtech aha corporation
Page 27 of 37
A
B
C
D
5
RESET_AD9851
FQ_UD
CLK_30M0
WLOAD
D[7:0]
VSCLK
OSC30M0
1
EN OUT
Y3
4
R102
3.9K
22
12
25
26
27
28
1
2
3
4
51
D7
D6
D5
D4
D3
D2
D1
D0
8
9
7
Place resistor
near
U21.9.
4
R47
Place Oscillator
near
U21.9.
3
VDD_5_0
4
GND
VCC
2
AD9851
RESET
RSET
FQ_UD
CLKIN
W_CLK
D7
D6
D5
D4
D3
D2
D1
D0
U21
3
6
23
11
18
VINP
DACBL(NC)
IOUTB
VINN
IOUT
3
16
17
20
15
21
14
13
VDD_5_0
QOUT
QOUTB
DVDD
DVDD
AVDD
AVDD
AGND
AGND
DGND
DGND
Page 28 of 37
19
10
24
5
5
470pF
C176
R101
100
R100
100K
R97
100K
33
R48
R98
200
33
R54
R49
70
1
2
3
2
C172
22pF
1pF
C169
L5
470nH
R55
70
HEADER_3
Package = TH_STP_HDR_3
JP7
2
A subsidiary of Comtech Telecommunications Corporation
Date:
Size
B
Friday, March 29, 2002
Document Number
AHA4524_EVB
FREQUENCY SYNTH ENCODER
22pF
Title
C174 4.7pF
33pF
C171
L7
390nH
C173 5.6pF
C170
L6
390nH
C175
22pF
1
Sheet
1
10
of
R99
200
19
Rev
D
ENC_PAYLOAD_CLK
CLK_SYNC
A
B
C
D
comtech aha corporation
PS4540evb_0802
A
B
DCLK
DERR
DEND
DSTART
5
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
2
USER_DACPT
6
12
9
3
USER_DCLK
U19D
SN74LVT125
Package = SMD
11
U19C
SN74LVT125
Package = SMD
8
USER_DEND
ECLK
USER_ERDY
USER_ESTART
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
TEST0
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
TEST7
TEST10
USER_UCLK
4
TDO
3
USER_ERDY
USER_ESTART
5
U18A
SN74LVT125
USER_EEND
Package = SMD
2
HEADER_25X2
Package = TH_WLD_HDR_25X2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
JP3
USER_UDATA0
USER_UDATA1
USER_UDATA2
USER_UDATA3
USER_UDATA4
USER_UDATA5
USER_UDATA6
USER_UDATA7
USER_URDY
USER_UACPT
4
Unencoded Data In
USER_EEND
USER_DACPT
USER_DDATA0
USER_DDATA1
USER_DDATA2
USER_DDATA3
USER_DDATA4
USER_DDATA5
USER_DDATA6
USER_DDATA7
U19A
SN74LVT125
Package = SMD
U19B
SN74LVT125
Package = SMD
5
USER_DRDY
USER_DDATA[7:0]
HEADER_25X2
Package = TH_WLD_HDR_25X2
4
C
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
JP2
Decoded Data Out
1
D
10
USER_DSTART
USER_DRDY
I/O CONN
USER_DERR
USER_DDATA[7:0]
13
1
TEST10
2
4
6
8
10
JTAG PORT
In System
Programming
of CPLDs
HEADER_5X2
1
3
5
7
9
JP6
Package = SMD
9
U18B
SN74LVT125
Package = SMD
6
TEST[7:0]
USER_UCLK
3
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
8
3
VDD_3_3
U18C SN74LVT125
R62
1K
R64
1K
R63
1K
USER_EACPT
USER_EDATA0
USER_EDATA1
USER_EDATA2
USER_EDATA3
USER_EDATA4
USER_EDATA5
USER_EDATA6
USER_EDATA7
Package = TH_WLD_HDR_25X2
USER_ECLK
HEADER_25X2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
JP4
USER_UDATA[7:0]
USER_EDATA[7:0]
Encoded Data Out
USER_UDATA[7:0]
USER_EDATA[7:0]
USER_URDY
USER_UACPT
4
PS4540evb_0802
10
5
TDI
TMS
TCK
USER_CACPT
USER_ROTATE
USER_CDATA0
USER_CDATA1
USER_CDATA2
USER_CDATA3
USER_CDATA4
USER_CDATA5
USER_CDATA6
USER_CDATA7
USER_CDATA8
USER_CDATA9
USER_CDATA10
USER_CDATA11
USER_CDATA12
USER_CDATA13
USER_CDATA14
USER_CDATA15
USER_ROTATE
USER_CACPT
2
USER_DACPT
USER_DCLK
USER_CRDY
USER_CLSB
USER_CSTART
USER_CPCLK
A subsidiary of Comtech Telecommunications Corporation
Date:
Size
B
Friday, March 29, 2002
Document Number
<Doc>
CSCLK
USER_CPCLK
USER_CRDY
USER_CLSB
USER_CSTART
1
Sheet
I/O_CONN, USER Interface Connectors
RES_TERM
USER_DACPT
USER_DCLK
USER_CRDY
USER_CLSB
USER_CSTART
USER_CPCLK
USER_CDATA[15:0]
USER_ECLK
USER_EACPT
USER_UCLK
USER_UDATA[7:0]
USER_URDY
RES_TERM
SMA
USER_CPCLK
1
11
CLK_SYNC_OUT
BUFOEN1
S_UDATA
S_DDATA
S_UCLK
S_DCLK
BUFOEN2 S_CDATA
S_DCLK_IN S_CCLK
S_EDATA
S_ECLK
BUFOEN3
SMA
USER_CRDY
USER_CLSB
USER_CSTART
S_DDATA
S_DCLK
BUFOEN2
S_DCLK_IN
CLK_SYNC_OUT
BUFOEN1
S_EDATA
S_ECLK
BUFOEN3
USER_CDATA[15:0]
Title
USER_CDATA[15:0]
USER_ECLK
USER_EACPT
USER_UCLK
USER_UDATA[7:0]
USER_URDY
Package = TH_WLD_HDR_25X2
HEADER_25X2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
Channel Data In
JP5
2
USER_CDATA[15:0]
of
19
Rev
A
S_CDATA
S_CCLK
S_UDATA
S_UCLK
CSCLK
A
B
C
D
comtech aha corporation
Page 29 of 37
A subsidiary of Comtech Telecommunications Corporation
A
B
C
1
5
2
4
6
HEADER 3X2
1
3
5
JP9
IN
1
3
IN
3
4
4
3
VDD_2_5
PCB Footprint = D
C179
C180
22uF
22uF
TANTALUM
VDD_1_8
3
Note:
1. PCB board should have large
pad for TAB
GND_SIGNAL
VDD_5_0
9
8
7
6
5
4
3
2
AGND
Package = TO_263_3
3
2
Friday, March 29, 2002
Document Number
AHA4540_EVB
PC I/O, Power
Package = TO_263_3
OUT
MIC29300-3.3BU
Date:
Size
A
5
4
3
2
1
VDD_3_3
PCB Footprint = D
Sheet
1
13
1
of
19
Rev
A
RIN
Put on bottom side
if top side too full
C177
C178
22uF
22uF
TANTALUM
C114
10uF
TANTALUM
ANALOG_12
RS232
Package = RtAn_9Pin_DSUB
9
8
7
6
1
JDR1
TAB AREA = TAB AREA
REG4
IN
Title
1
TXOUT
2
TAB AREA = TAB AREA
REG2
MIC29150-12BU
1 IN
OUT 3
C131
10uF
TANTALUM
ANALOG_16
PC I/O, Power
C113
C132
22uF
22uF
TANTALUM
AGND
Package = TO_263_3
OUT
MIC39300-1.8BU
TAB AREA = TAB AREA
REG3
Package = TO_263_3
OUT
REG1
MIC39300-2.5BU
TAB AREA = 1000mm^2
C181
10uF
TANTALUM
VDD_5_0
PCB Footprint = X
VDD_5_0
ANALOG_16
VDD_5_0
GND
2
D
GND
2
GND
2
GND
Page 30 of 37
2
5
A
B
C
D
comtech aha corporation
PS4540evb_0802
PS4540evb_0802
A
B
C
D
USER_DACPT
USER_DCLK
USER_ECLK
USER_EACPT
USER_CRDY
USER_CLSB
USER_CSTART
USER_CPCLK
USER_CDATA[15:0]
USER_UCLK
5
USER_DCLK
USER_ECLK
USER_EACPT
USER_CRDY
USER_CLSB
USER_CSTART
USER_CPCLK
USER_CDATA[15:0]
USER_UCLK
USER_UDATA[7:0]
USER_URDY
51
51
4
R161
R160
51
51
R138
51
R118
51
51
USER_UDATA7
R135
R117
51
51
51
R116
R107
R105
USER_UDATA6
51
R108
USER_UDATA5
51
R109
51
R121
51
R122
51
51
51
USER_UDATA2
R112
R111
R110
USER_UDATA4
USER_CDATA14
USER_UDATA3
USER_CDATA13
USER_CDATA15
51
R123
51
R124
51
R114
R113
51
USER_UDATA1
USER_CDATA12
USER_UDATA0
USER_CDATA11
3
51
R125
51
R115
3
USER_CDATA9
51
R126
USER_CDATA8
51
R127
USER_CDATA7
51
R128
USER_CDATA6
51
R129
USER_CDATA5
51
R46
USER_CDATA4
51
R130
R45
51
2
2
USER_CDATA3
4
USER_CDATA10
USER_UDATA[7:0]
USER_URDY
5
USER_CDATA2
51
R131
USER_CDATA1
51
R132
USER_CDATA0
A subsidiary of Comtech Telecommunications Corporation
Date:
Size
B
Title
51
R133
Friday, March 29, 2002
Document Number
<Doc>
Resistor Terminations, LVPECL
51
R134
1
Sheet
1
14
of
19
Rev
A
A
B
C
D
comtech aha corporation
Page 31 of 37
5
4
C122
0.1uF
3
7
15
1
12
16
5
6
3
MAX3221
V+
V-
VCC
EN
FORCEON
FORCEOFF
C2+
C2-
C1+
C1-
10
9
13
A subsidiary of Comtech Telecommunications Corporation
Date:
Size
A
Title
Package = SSOP16
INVALID
ROUT
TOUT
RS232 interface
INVALIDN
ROUT
TXOUT
Sheet
15
1
of
19
Rev
A
C
D
2
Friday, March 29, 2002
Document Number
<Doc>
A
C121
0.1uF
0.1uF
0.1uF
RIN
TIN
1
A
RS232EN
C120
C119
2
4
8
U16
2
B
VDD_3_3
RIN
11
RS232 interface
3
B
C
R69
1K
VDD_3_3
TXIN
4
GND
Page 32 of 37
14
D
5
comtech aha corporation
PS4540evb_0802
A
B
C
D
SMA
J1
SMA
J3
2
SMA
J5
2
SMA
J7
2
SMA
J9
SMA
J13
5
1
1
1
1
1
1
R104
51
R15
51
R14
51
R13
51
R12
51
R11
51
S_DCLK_IN
CSCLK
S_CCLK
S_CDATA
S_UCLK
S_UDATA
4
3
Route Data and Clock for each
interface together. (Same
Length Traces)
Place 51 ohm resistors near
components at the receiving
end of the trace, not near
SMA connector.
SMA
3
S_ECLK
S_EDATA
BUFOEN3
S_DCLK
S_DDATA
BUFOEN2
CLK_SYNC_OUT
BUFOEN1
5
2
2
5
2
U12B
SN74LVT125
Package = SMD
6
U12A
SN74LVT125
Package = SMD
3
U6B
SN74LVT125
Package = SMD
6
U6A
SN74LVT125
Package = SMD
3
U5A
SN74LVT125
Package = SMD
3
A subsidiary of Comtech Telecommunications Corporation
2
Date:
Size
B
Title
1
1
1
SMA
J2
SMA
J4
SMA
J6
1
1
SMA
J8
SMA
J10
Friday, March 29, 2002
Document Number
<Doc>
SMA
Place all SN74LVT125
buffers inline with the
SMA connector and the IC
they go to. Including
buffers on IO_CONN page.
2
1
1
4
2
2
2
4
1
4
2
2
2
2
PS4540evb_0802
2
5
1
Sheet
S_ECLK
S_EDATA
S_DCLK
S_DDATA
USER_CLK_SYNC
1
16
of
19
Rev
A
A
B
C
D
comtech aha corporation
Page 33 of 37
Page 34 of 37
5
4
3
C116
0.1uF
A subsidiary of Comtech Telecommunications Corporation
Date:
Size
A
Title
C117
0.1uF
10K
R67
2
Friday, March 29, 2002
Document Number
<Doc>
SWITCHES
C118
0.1uF
10K
R68
SW3
SW2
SW1
SW0
Sheet
17
1
1
of
19
Rev
A
C
D
A
C115
0.1uF
10K
R66
2
A
SW_PB
Package = EVQPPD
SW_PB
Package = EVQPPD
SW3
SW_PB
Package = EVQPPD
SW2
SW1
SW_PB
Package = EVQPPD
SW0
10K
R65
VDD_3_3
3
B
USR FUNCTION
USR FUNCTION
USR FUNCTION
FPGA LOAD
PROGRAM
SWITCHES
4
B
C
D
5
comtech aha corporation
PS4540evb_0802
C2
0.033uF
AGND
R6 390
4
R8
1K
R10 3.9K
VCO1
ENCODER
0.033uF
C3
2
3
-
+
OP283
Package = SO_8
1
U3A
3
5
JTOS_200
Package = BK377
V_TUNE
U2
VCO
RF_OUT
AGND
13
2
51
R80
Title
C4
0.033uF
2
3
-
+
70
R56
GND_SIGNAL
VCO_OUT
GND_SIGNAL
51
R82
18
of
19
Rev
A
Put R82 near last component in
chain. Near U11
Package = uMAX
MAX997
6
Put R56 near
U4.6
U4
VCO1, Voltage Controlled Oscillator Circuit 1
1K
R9
3.3K
R3
C
A subsidiary of Comtech Telecommunications Corporation
Date:
Size
B
Friday, March 29, 2002
Document Number
VC01
1
Sheet
A
C1
0.33uF
R4
180
ANALOG_16
D
A
10K
24.9K
VDD_3_3
1
B
5
R7
1M
R5
R2
ANALOG_12
2
7
B
C
CLKADJ[1]
CLKADJ[0]
3
2
VCC_12V
D
8
4
4
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
1
3
4
6
7
8
9
10
11
12
14
PS4540evb_0802
8
4
5
comtech aha corporation
Page 35 of 37
Page 36 of 37
A subsidiary of Comtech Telecommunications Corporation
A
B
C
D
5
5
LEDN[7:0]
4
LEDN[7:0]
4
LEDN7
LEDN6
LEDN5
LEDN4
LEDN3
LEDN2
LEDN1
LEDN0
R35
R33
R31
R29
180
180
180
180
R34
R32
R30
R28
3
180
180
180
180
3
LED
D8
LED
D7
LED
D6
LED
D5
LED
D4
LED
D3
LED
D2
LED
D1
Date:
Size
A
Title
2
Friday, March 29, 2002
Document Number
AHA4540_EVB
LEDs
Package = SS
Package = SS
Package = SS
Package = SS
Package = SS
Package = SS
Package = SS
Package = SS
VDD_3_3
2
Sheet
LEDS
19
1
1
of
19
Rev
A
A
B
C
D
comtech aha corporation
PS4540evb_0802
A
B
C
CLKADJ[1]
CLKADJ[0]
5
R21
1M
R19
10K
C5
0.33uF
R16 24.9K
R18
180
C6
0.033uF
AGND
R20 390
4
0.033uF
C7
R22
1K
-
+
OP283
Package = SO_8
1
VCO2
DECODER
R24 3.9K
2
3
U17A
ANALOG_16
8
4
5
3
3
JTOS_200
Package = BK377
V_TUNE
U7
ANALOG_12
2
VCC_12V
D
4
RF_OUT
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
AGND
1
3
4
6
7
8
9
10
11
12
14
PS4540evb_0802
13
2
2
51
R81
A subsidiary of Comtech Telecommunications Corporation
Date:
Size
B
Title
C8
0.033uF
+
-
3
2
U8
MAX997
Package = uMAX
6
GND_SIGNAL
Friday, March 29, 2002
Document Number
<Doc>
Sheet
1
51
R83
VCO_OUT
19
of
19
Rev
A
GND_SIGNAL
Put near receiver. (U13)
70
R57
1
VC02, Voltage Controlled Oscillator Ckt 2
1K
R23
3.3K
R17
VDD_3_3
7
8
4
5
A
B
C
D
comtech aha corporation
Page 37 of 37