ETC GMM7324110CNS-6

GMM7324110CNS/SG-6/7/8
4,194,304 WORDS x 32 BIT
CMOS DYNAMIC RAM MODULE
Description
The GMM7324110CNS/SG is a 4M x 32
bits Dynamic RAM MODULE which is
assembled 8 pieces of 4M x 4bit EDO
DRAMs in 24(26) pin SOJ package on single
sides the printed circuit board with decoupling
capacitors. The GMM7324110CNS/SG is
optimized for application to the systems
which are required high density and large
capacity such as main memory of the
computers and an image memory systems,
and to the others which are requested compact
size. The GMM7324110CNS/SG provides
common data inputs and Extended Data
Outputs.
GMM7324110CNS/SG (Single Side)
Features
* 72 pins Single In-Line Package
- GMM7324110CNS : Solder plating
- GMM7324110CNSG : Gold plating
* Extended Data Out (EDO) Mode Capability
* Single Power Supply
* Fast Access Time & Cycle Time
(Unit: ns)
tRAC tCAC tRC
tHPC
GMM7324110CNS/SG-6
60
15
104
25
GMM7324110CNS/SG-7
70
18
124
30
GMM7324110CNS/SG-8
80
20
144
35
1
* Low Power
Active : 4,840/4,400/3,960 mW (MAX)
Standby : 44mW (CMOS level : MAX)
* RAS Only Refresh, CAS before RAS Refresh,
Hidden Refresh Capability
* All inputs and outputs TTL Compatible
* 2048 Refresh Cycles/32ms
Pin Configuration (Top View)
Pin Symbol Pin Symbol Pin Symbol Pin Symbol
36
37
72
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
VSS
DQ0
DQ16
DQ1
DQ17
DQ2
DQ18
DQ3
DQ19
VCC
NC
A0
A1
A2
A3
A4
A5
A6
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
A10
DQ4
DQ20
DQ5
DQ21
DQ6
DQ22
DQ7
DQ23
A7
NC
VCC
A8
A9
NC
RAS2
NC
NC
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
NC
NC
VSS
CAS0
CAS2
CAS3
CAS1
RAS0
NC
NC
WE
NC
DQ8
DQ24
DQ9
DQ25
DQ10
DQ26
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
DQ11
DQ27
DQ12
DQ28
VCC
DQ29
DQ13
DQ30
DQ14
DQ31
DQ15
NC
PD1
PD2
PD3
PD4
NC
VSS
1
GMM7324110CNS/SG
Block Diagram
CAS0
CAS
RAS0
RAS
OE
M0
WE
A0-A10
CAS
M1
RAS
OE
CAS1
WE
A0-A10
CAS
M2
RAS
OE
WE
A0-A10
CAS
M3
RAS
OE
CAS2
CAS
RAS2
RAS
OE
WE
A0-A10
M4
WE
A0-A10
CAS
M5
RAS
OE
CAS3
WE
A0-A10
CAS
M6
RAS
OE
WE
A0-A10
CAS
M7
RAS
OE
WE
A0-A10
I/O1
I/O2
I/O3
I/O4
DQ 0
DQ 1
DQ 2
DQ 3
I/O1
I/O2
I/O3
I/O4
DQ 4
DQ 5
DQ 6
DQ 7
I/O1
I/O2
I/O3
I/O4
DQ 8
DQ 9
DQ 10
DQ 11
I/O1
I/O2
I/O3
I/O4
DQ 12
DQ 13
DQ 14
DQ 15
I/O1
I/O2
I/O3
I/O4
DQ 16
DQ 17
DQ 18
DQ 19
I/O1
I/O2
I/O3
I/O4
DQ 20
DQ 21
DQ 22
DQ 23
I/O1
I/O2
I/O3
I/O4
DQ 24
DQ 25
DQ 26
DQ 27
I/O1
I/O2
I/O3
I/O4
DQ 28
DQ 29
DQ 30
DQ 31
WE
A0-A10
VCC
M0-M7
*M0-M7 : 4M x 4 EDO DRAM
M0-M7
*C0-C7 : 0.22uF Capacitor
C0-C7
VSS
2
GMM7324110CNS/SG
Pin Description
Pin
A0-A10
Function
Address Inputs
Pin
Function
PD1-PD4
Presence Detect
Data Input/Output
VCC
Power (+5V)
RAS0,RAS2
Row Address Strobe
VSS
Ground
CAS0-CAS3
Column Address Strobe
NC
No Connection
DQ0-DQ34
WE
Read/Write Enable
Presence Detect Pins (Optional)
Pin
60ns
70ns
80ns
PD1
VSS
VSS
VSS
PD2
NC
NC
NC
PD3
NC
VSS
NC
PD4
NC
NC
VSS
Absolute Maximum Ratings*
Symbol
Parameter
Rating
Unit
0 ~ 70
C
TA
Ambient Temperature under Bias
TSTG
Storage Temperature (Plastic)
-55 ~ 125
C
VIN/VOUT
Voltage on any Pin Relative to VSS
-1.0 ~ 7.0
V
VCC
Power Supply Voltage
-1.0 ~ 7.0
V
IOUT
Short Circuit Output Current
50
mA
PD
Power Dissipation
8
W
*Note: 1. Stress greater than above “ A
bsolute Maximum Ratings?may cause permanent damage to the device.
Recommended DC Operating Conditions (TA = 0 ~ 70C)
Symbol
Parameter
Min
Typ
Max
Unit
Note
VCC
Supply Voltage
4.5
5.0
5.5
V
1
VIH
Input High Voltage
2.4
-
6.5
V
1
VIL
Input Low Voltage
-1.0
-
0.8
V
1
*Note: 1. All voltages referenced to VSS.
3
GMM7324110CNS/SG
DC Electrical Characteristics (VCC = 5V+/-10%, TA = 0 ~ 70C)
Symbol
Parameter
Min
Max
Unit
VOH
Output Level
Output “ H
?Level Voltage (IOUT = -5mA)
2.0
VCC
V
VOL
Output Level
Output “ L
?Level Voltage (IOUT = 4.2mA)
0
0.4
V
ICC1
Operating Current
Average Power Supply Operating Current
(RAS, CAS, Address Cycling: tRC = tRC min)
60ns
-
880
70ns
-
800
80ns
-
720
-
16
ICC2
ICC3
ICC4
ICC5
ICC6
ICC7
II(L)
IO(L)
Standby Current (TTL)
Power Supply Standby Current
(RAS, CAS = VIH)
mA
60ns
-
880
70ns
-
800
80ns
-
720
EDO Page Mode Current
Average Power Supply Current
EDO Page Mode
(RAS = VIL , CAS, Address cycling: tHPC = tHPC min)
60ns
-
880
70ns
-
800
80ns
-
720
-
8
60ns
-
880
70ns
-
800
80ns
-
720
-
40
mA
Input Leakage Current
Any Input (0V<=VIN<=7V)
All Other Pins Not Under Test = 0V
-80
80
uA
Output Leakage Current
(DOUT is Disabled, 0V<=VOUT<=7V)
-10
10
uA
CAS before RAS Refresh Current
(tRC = tRC min)
Standby Current RAS = VIH
CAS = VIL
DOUT = Enable
1, 2
mA
RAS Only Refresh Current
Average Power Supply Current
RAS Only Mode
(RAS Cycling, CAS = VIH, tRC = tRC min)
Standby Current (CMOS)
Power Supply Standby Current
(RAS, CAS>=VCC-0.2V)
Note
mA
2
mA
1, 3
mA
mA
1
Note: 1. ICC depends on output load condition when the device is selected. ICC(max) is specified at the output open
condition.
2. Address can be changed once or less while RAS = VIL.
3. Address can be changed once or less while CAS = VIH.
4
GMM7324110CNS/SG
Capacitance (VCC = 5V+/-10%, TA = 25C, f = 1MHz)
Symbol
Parameter
Min
Max
Unit
Note
CI1
Input Capacitance (A0~A10)
-
60
pF
1
CI2
Input Capacitance (WE)
-
70
pF
1, 2
C13
Input Capacitance (RAS0,RAS2)
-
42
pF
1, 2
C14
Input Capacitance (CAS0~CAS3)
-
25
pF
1, 2
CI/O
I/O Capacitance (DQ0~DQ31)
-
22
pF
1, 2
Note: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. CAS = VIH to disable DOUT.
AC Electrical Characteristics (VCC = 5V+/-10%, TA = 0 ~ 70C, Notes 1, 15)
The GMM7324110CNS/SG writes data only in early write cycle (twcs>=twcs(min)).
Delayed write cycle is not available because of I/O common.
Read, Write and Refresh Cycle (Common Parameters)
Symbol
Parameter
GMM7324110
CNS/SG-6
GMM7324110
CNS/SG-7
GMM7324110
CNS/SG-8
Min
Max
Min
Max
Min
Max
104
-
124
-
144
-
ns
50
-
60
-
ns
Unit
Note
tRC
Random Read or Write Cycle Time
tRP
RAS Precharge Time
40
-
tRAS
RAS Pulse Width
60
10,000
70 10,000
80 10,000
ns
tCAS
CAS Pulse Width
10
10,000
13 10,000
15 10,000
ns
tASR
Row Address Setup Time
0
-
0
-
0
-
ns
tRAH
Row Address Hold Time
10
-
10
-
10
-
ns
tASC
Column Address Setup Time
0
-
0
-
0
-
ns
tCAH
Column Address Hold Time
10
-
13
-
15
-
ns
tRCD
RAS to CAS Delay Time
20
45
20
52
20
60
ns
9
tRAD
RAS to Column Address Delay Time
15
30
15
35
15
40
ns
10
tRSH
RAS Hold Time
15
-
18
-
20
-
ns
tCSH
CAS Hold Time
48
-
58
-
68
-
ns
tCRP
CAS to RAS Precharge Time
5
-
5
-
5
-
ns
tT
Transition Time (Rise and Fall)
2
50
2
50
2
50
ns
tREF
Refresh Period ( 2048 Cycles )
-
32
32
-
32
ms
-
8
5
GMM7324110CNS/SG
Read Cycle
Symbol
Parameter
GMM7324110
CNS/SG-6
GMM7324110
CNS/SG-7
GMM7324110
CNS/SG-8
Min
Max
Min
Max
Min
Max
Unit Note
tRAC
Access Time from RAS
-
60
-
70
-
80
ns
2, 3
tCAC
Access Time from CAS
-
15
-
18
-
20
ns
3, 4
tAA
Access Time from Column Address
-
30
-
35
-
40
ns
3, 5, 14
tRCS
Read Command Setup Time
0
-
0
-
0
-
ns
tRCH
Read Command Hold Time to CAS
0
-
0
-
0
-
ns
6
tRRH
Read Command Hold Time to RAS
0
-
0
-
0
-
ns
6
tRAL
Column Address to RAS Lead Time
30
-
35
-
40
-
ns
tCAL
Column Address to CAS Lead Time
18
-
23
-
28
-
ns
tOFF
tOFR
Output Buffer Turn-off Time
-
15
-
15
-
15
ns
7
Output Buffer Turn-off Time to RAS
-
15
-
15
-
15
ns
7,16
tWEZ
Output Buffer Turn-off Time to WE
-
15
-
15
-
15
ns
7
tOH
Output Data Hold Time
3
-
3
-
3
-
ns
tOHR
Output Data Hold Time form RAS
3
-
3
-
3
-
ns
tRCHR
Read Command Hold Time from
60
-
70
-
80
-
ns
0
-
0
-
0
-
ns
RAS
tCLZ
CAS to Output in low-Z
Write Cycle
Symbol
6
Parameter
GMM7324110
CNS/SG-6
GMM7324110
CNS/SG-7
GMM7324110
CNS/SG-8
Min
Max
Min
Max
Min Max
Unit Note
tWCS
Write Command Setup Time
0
-
0
-
0
-
ns
tWCH
Write Command Hold Time
10
-
13
-
15
-
ns
tWP
Write Command Pulse Width
10
-
10
-
10
-
ns
tRWL
Write Command to RAS Lead Time
10
-
13
-
15
-
ns
tCWL
Write Command to CAS Lead Time
10
-
13
-
15
-
ns
tDS
Data-in Setup Time
0
-
0
-
0
-
ns
12
tDH
Data-in Hold Time
10
-
15
-
15
-
ns
12
11
GMM7324110CNS/SG
Refresh Cycle
Symbol
Parameter
GMM7324110
CNS/SG-6
GMM7324110
CNS/SG-7
GMM7324110
CNS/SG-8
Min
Max
Min
Max
Min
Max
Unit
tCSR
CAS Set-up Time
(CAS-before-RAS Refresh Cycle)
5
-
5
-
5
-
ns
tCHR
CAS Hold Time
(CAS-before-RAS Refresh Cycle)
10
-
10
-
10
-
ns
tRPC
RAS Precharge to CAS Hold Time
0
-
0
-
0
-
ns
tWRP
WE Set-up Time
(CAS-before-RAS Refresh Cycle)
0
-
0
-
0
-
ns
tWRH
WE Hold Time
(CAS-before-RAS Refresh Cycle)
10
-
10
-
10
-
ns
Note
Extended Data Out (EDO) Mode Cycle
Symbol
Parameter
GMM7324110
CNS/SG-6
GMM7324110
CNS/SG-7
Min
Max
Min
GMM7324110
CNS/SG-8
Max Min
Unit
Note
Max
tHPC
EDO Mode Cycle Time
25
-
30
-
35
-
ns
tCP
EDO Mode CAS Precharge Time
10
-
13
-
15
-
ns
tRASP
EDO Mode RAS Pulse Width
-
100,000
-
100,000
-
100,000
ns
13
tACP
Access Time from CAS Precharge
-
35
-
40
-
45
ns
3,14
tRHCP
RAS Hold Time from CAS Precharge
35
-
40
-
45
-
ns
tRCHP
Read Command Hold Time from
CAS Precharge
35
-
40
-
45
-
ns
tDOH
Output Data Hold Time from CAS
Low
3
-
3
-
3
-
ns
7
GMM7324110CNS/SG
Notes:
1. AC measurements assume tT = 5ns.
2. Assumes that tRCD<=tRCD(max) and tRAD<=tRAD(max). If tRCD or tRAD is greater than the maximum
recommended value shown in this table, tRAC exceeds the value shown.
3. Measured with a load circuit equivalent to 1TTL loads and 100pF.
4. Assumes that tRCD>=tRCD(max) and tRAD<=tRAD(max).
5. Assumes that tRCD<=tRCD(max) and tRAD>=tRAD(max).
6. Either tRCH or tRRH must be satisfied for a read cycles.
7. tOFF(max) defines the time at which the outputs achieve the open circuit condition and is not
referenced to output voltage levels.
8. VIH (min) and VIL(max) are reference levels for measuring timing of input signals. Also,
transition times are measured between VIH and VIL.
9. Operation with the tRCD(max) limit insures that tRAC(max) can be met, tRCD(max) is specified as a
reference point only, if tRCD is greater than the specified tRCD(max) limit, then access time is
controlled exclusively by tCAC.
10. Operation with the tRAD(max) limit insures that tRAC(max) can be met, tRAD(max) is specified as a
reference point only, if tRAD is greater than the specified tRAD(max) limit, then access time is
controlled exclusively by tAA.
11. tWCS is not restrictive operating parameter. It is included in the data sheet as electrical
characteristics only. If tWCS>=tWCS(min), the cycle is an early write cycle and the data out pin
will remain open circuit (high impedance) throughout the entire cycle.
12. These parameters are referenced to CAS leading edge in early write cycles.
13. tRASP is defines RAS pulse width in EDO Mode cycles.
14. Access time is determined by the longer of tAA or tCAC or tACP.
15. An initial pause of 200us is required after power up followed by a minimum of eight
initialization cycles (any combination of cycles containing RAS clock such as RAS only refresh).
If the internal refresh counter is used, a minimum of eight CAS before RAS refresh cycles are
required.
16. tOFF and tOFR are determined by the later rising edge of RAS or CAS.
Timing Waveforms : Please refer to attached Timing Waveform-7
8
GMM7324110CNS/SG
Package Dimension
Unit: mil (mm)
* (1mil = 1/1000 inches)
4250(107.95)
133(3.38)
3984(101.19)
133(3.38)
1000(25.4)
2- φ 125
+3, -0
(3.175)
R62(1.57)
250
(6.35)
80
(2.032)
1750(44.45)
1750(44.45)
250
(6.35)
250
(6.35)
R62(1.57)
400(10.16)
100(2.54)
DETAIL “ A
200(5.08)
MAX
DETAIL “ A
41+/-3(1.04+/-0.076) : Gold plating
36+/-3(0.914+/-0.076) : Solder plating
MIN 100
(2.540)
MAX 10 (0.254)
125(3.175)
MIN
50 (1.27)
Tolerances : +/-5 (0.127) unless otherwise specified.
16
47(1.19) MIN
54(1.37) MAX