HANBit HMD1M32M2G 4Mbyte(1Mx32) Fast Page Mode, 1K Refresh, 72Pin SIMM, 5V Design Part No. HMD1M32M2G DESCRIPTION The HMD1M32M2G is an 1M x 32 bits Dynamic RAM MODULE which is assembled 2 pieces of 1M x 16bit DRAMs in 42 pin SOJ package on single sides the printed circuit board with decoupling capacitors. The HMD1M32M2G is optimized for application to the systems, which are required high density and large capacity such as main memory of the computers and an image memory systems, and to the others, which are, requested compact size. The HMD1M32M2G provides common data and outputs. PIN ASSIGNMENT Features PIN SYMBOL PIN SYMBOL PIN SYMBOL w 72 pins Single In-Line Package 1 Vss 25 DQ22 49 DQ8 w Fast Page Mode Capability 2 DQ0 26 DQ7 50 DQ24 3 DQ16 27 DQ23 51 DQ9 4 DQ1 28 A7 52 DQ25 5 DQ17 29 NC 53 DQ10 6 DQ2 30 Vcc 54 DQ26 7 DQ18 31 A8 55 DQ11 8 DQ3 32 A9 56 DQ27 9 DQ19 33 NC 57 DQ12 Active: 1,870/1,650/1,430 mW(MAX) 10 Vcc 34 /RAS2 58 DQ28 Standby: 11mW(CMOS level : MAX) 11 NC 35 NC 59 Vcc 12 A0 36 NC 60 DQ29 w Single +5V± 0.5V power supply w Fast Access Time & Cycle Time tRAC tCAC tRC tPC HMD1M32M2G-6 60 15 110 40 HMD1M32M2G-7 70 18 130 45 w Low Power w /RAS Only Refresh, /CAS before /RAS Refresh, Hidden Refresh Capability 13 A1 37 NC 61 DQ13 w All inputs and outputs TTL Compatible 14 A2 38 NC 62 DQ30 w 1,024 Refresh Cycles/16ms 15 A3 39 Vss 63 DQ14 16 A4 40 /CAS0 64 DQ31 17 A5 41 /CAS2 65 DQ15 18 A6 42 /CAS3 66 NC 19 NC 43 /CAS1 67 PD1 20 DQ4 44 /RAS0 68 PD2 21 DQ20 45 NC 69 PD3 PRESENCE DETECT PINS (Optional) PIN 60NS 70NS PD1 Vss Vss PD2 Vss Vss PD3 NC Vss 22 DQ5 46 NC 70 PD4 NC 23 DQ21 47 /WE 71 NC 24 DQ6 48 NC 72 Vss PD4 NC PIN DESCRIPTION PIN A0 – A9 FUNCTION PIN PD1 – PD4 Address Inputs FUNCTION Presence Detect DQ0 – DQ31 Data Input/Output Vcc Power (+5V) /RAS0, /RAS2 Row Address Strobe Vss Ground /CAS0 - /CAS3 Column Address Strobe NC No Connection /WE URL:www.hbe.co.kr REV.1.0 (August.2002) Read/Write Enable - 1 HANBiT Electronics Co., Ltd HANBit HMD1M32M2G FUNCTIONAL BLOCK DIAGRAM U0 /RAS0 /RAS /CAS0 /LCAS /CAS1 /OE /RAS2 /CAS2 /LCAS /CAS3 /UCAS DQ0-DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 /UCAS /RAS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 U1 DQ8-DQ15 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ16-DQ23 DQ8 DQ9D Q10 DQ11 DQ12 DQ13 DQ14 DQ15 /OE DQ24-DQ31 /WE A0-A9 Vcc 0.1uF Capacitor Vss ABSOLUTE MAXIMUM RATINGS* SYMBOL RATING UNIT 0 ~ 70 C Storage Temperature (Plastic) -55 ~ 125 C Voltage on any Pin Relative to Vss -1.0 ~ 7.0 V VCC Power Supply Voltage -1.0 ~ 7.0 V IOUT Short Circuit Output Current 50 mA Power Dissipation 2 W TA TSTG VIN/VOUT PD PARAMETER Ambient Temperature under Bias *NOTE: 1. Stress greater than above absolute Maximum Ratings? URL:www.hbe.co.kr REV.1.0 (August.2002) 2 May cause permanent damage to the device. HANBiT Electronics Co., Ltd HANBit HMD1M32M2G RECOMMENDED DC OPERATING CONDITIONS (TA = 0 ~ 70C) PARAMETER SYMBOL MIN TYP. MAX UNIT Supply Voltage Vcc 4.5 5.0 5.5 V Ground Vss 0 0 0 V Input High Voltage VIH 2.4 - Vcc+1 V Input Low Voltage VIL -1.0 - 0.8 V *NOTE: All voltages referenced to Vcc DC AND OPERATING CHARACTERISTICS SYMBOL PARAMETER MIN MAX UNIT 2.4 Vcc V 0 0.4 V 60ns - 340 70ns - 300 - - - - 4 - 340 NOTE Output Level VOH Output High Level Voltage (IOUT = -5mA) Output Level VOL Output Low Level Voltage (IOUT = 4.2mA) Operating Current ICC1 Average Power Supply Operating Current mA 1,2 (/RAS,/CAS,Address Cycling : tRC = tRC min) Standby Current (TTL) ICC2 Power Supply Standby Current mA (/RAS,/CAS = VIH) /RAS Only Refresh Current 60ns ICC3 Average Power Supply Current mA 2 /RAS Only Mode 70ns (/RAS Cycling, /CAS = VIH,: tRC = tRC min) 300 Fast Page Mode Current ICC Average Power Supply Current 60ns - 340 mA 1,3 70ns - 300 mA 1,3 - 2 mA Fast Page Mode ICC4 (/RAS = VIL, /CAS, Address Cycling : tPC = tPC min) Standby Current (CMOS) ICC5 Power Supply Standby Current (/RAS,/CAS >= Vcc – 0.2V) /CAS before /RAS Refresh Current ICC6 (tRC URL:www.hbe.co.kr REV.1.0 (August.2002) 60ns - 340 70ns - 300 = tRC min) 3 mA HANBiT Electronics Co., Ltd HANBit HMD1M32M2G Standby Current /RAS = VIH ICC7 /CAS = VIL - 10 mA -10 10 uA -10 10 uA 1 DOUT = Enable Input Leakage Current II(L) Any Input (0V<=VIN<=7V) All Other Pins Not Under Test = 0V Output Leakage Current IO(L) (DOUT is Disabled, 0V<=VOUT<=7V) Note: 1.Icc depends on output load condition when the device is selected. Icc (max) is specified at the output open condition. 2. Address can be changed once or less while /RAS = VIL. 3. Address can be changed once or less while /CAS = VIH CAPACITANCE o ( TA=25 C, Vcc = 5V+/- 10%, f = 1Mhz ) DESCRIPTION SYMBOL MIN MAX UNITS Input Capacitance (A0-A9) CI1 - 35 pF 1 Input Capacitance (/WE) C I2 - 34 pF 1,2 Input Capacitance (/RAS0,/RAS2) CI3 - 27 pF 1,2 Input Capacitance (/CAS0-/CAS3) CI4 - 27 pF 1,2 CDQ1 - 20 pF 1,2 Input/Output Capacitance (DQ0-31) NOTE Note: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. /CAS = VIH to disable DOUT. AC CHARACTERISTICS o ( 0 C ≤ TA ≤ 70oC , Vcc = 5V±10%, See notes 1,15.) The GMM731000CNS/SG writes data only in early write cycle (twcs>=twcs(min)) Delayed write cycle is not available because of I/O common. READ, WRITE AND REFRESH CYCLE (Common Parameters) -6 SYMBOL -7 PARAMETER UNIT MIN MAX MIN MAX tRC Random Read or Write Cycle Time 110 - 130 - ns tPR /RAS Precharge Time 40 - 50 - ns tRAS /RAS Pulse Width 60 10K 70 10K ns tCAS /CAS Pulse Width 15 10K 18 10K ns tASR Row Address Setup Time 0 - 0 - ns tRAH Row Address Hold Time 10 - 10 - ns tASC Column Address Setup Time 0 - 0 - ns URL:www.hbe.co.kr REV.1.0 (August.2002) 4 NOTE HANBiT Electronics Co., Ltd HANBit HMD1M32M2G tCAH Column Address Hold Time 10 - 15 - ns 9 tRCD /RAS to /CAS Delay Time 20 45 20 52 ns 10 tRAD /RAS to Column Address Delay Time 15 30 15 35 ns tRSH /RAS Hold Time 15 - 18 - ns tCSH /CAS Hold Time 60 - 70 - ns tCRP /CAS to /RAS Precharge Time 5 - 5 - ns tT Transition Time (Rise and Fall) 3 50 3 50 ns Refresh Period (1024 Cycle) - 16 - 16 ms tREF 8 READ CYCLE -6 SYMBOL -7 PARAMETER MIN MAX MIN MAX UNIT NOTE tRAC Access Time from /RAS - 60 - 70 ns 2,3 tCAC Access Time from /CAS - 15 - 18 ns 3,4 Access Time from Column Address - 30 - 35 ns 3,5,14 tRCS Read Command Setup Time 0 - 0 - ns tRCH Read Command Hold Time to /CAS 0 - 0 - ns 6 tRRH Read Command Hold Time to /RAS 0 - 0 - ns 6 tRAL Column Address to /RAS Lead Time 30 - 35 - ns tOFF Output Buffer Turn-off Time - 15 - 15 ns 7 tAA WRITE CYCLE -6 SYMBOL PARAMETER -7 MIN MAX MIN MAX UNIT NOTE 11 twcs Write Command Setup Time 0 - 0 - ns tWCH Write Command Hold Time 10 - 15 - ns Write Command Pulse Width 10 - 10 - ns tRWL Write Command to /RAS Lead Time 15 - 18 - ns tCWL Write Command to /CAS Lead Time 15 - 18 - ns tDS Data-in Setup Time 0 - 0 - ns 12 tDH Data-in Hold Time 10 - 15 - ns 12 NOTE tWP REFRESH CYCLE -6 SYMBOL tCRS tCHR PARAMETER -7 MIN MAX MIN MAX UNIT /CAS Setup Time (/CAS-before-/RAS Refresh Cycle) 10 - 10 - ns /CAS Hold Time (/CAS-before-/RAS Refresh Cycle) 10 - 10 - ns URL:www.hbe.co.kr REV.1.0 (August.2002) 5 HANBiT Electronics Co., Ltd HANBit tRPC HMD1M32M2G /RAS Precharge to /CAS Hold Time 5 - 5 - ns FAST PAGE MODE CYCLE -6 SYMBOL PARAMETER -7 MIN MAX MIN MAX UNIT NOTE tPC Fast Page Mode Cycle Time 40 - 45 - ns tCP Fast Page Mode /RAS Precharge Time 10 - 10 - ns tRASP Fast Page Mode /CAS Pulse Time 60 100K 70 100K ns 13 Access Time from /CAS Precharge - 35 - 40 ns 14 35 - 40 - ns tACP /RAS Hold Time from /CAS Precharge tRHCP Note: 1. AC measurements assume tT = 5ns. 2. Assumes that tRCD<=tRCD(max) and tRCD<=tRCD(max). If tRCD or tRCD is greater than the maximum recommended value shown in this table, tRCD exceeds the value shown. 3. Measured with a load circuit equivalent to 2TTL loads and 100PpF. 4. Assumes that tRCD >= tRCD (max) and tRCD<= tRCD (max). 5.Assumes that tRCD <= tRCD (max) and tRCD>= tRCD (max). 6.Either tRCH or tRRH must be satisfied for a read cycles. 7. tOFF(max) defines the time at which the outputs achieve the open circuit condition and is not referenced to output voltage levels. 8. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH and VIL. 9. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only, if tRCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC . 10. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only, if tRAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA. 11. TWCS is not restrictive operating parameter. It is included in the data sheet as electrical characteristics only. If twcs >= twcs (min), the cycle is an early write cycle and the data out pin will remain open circuit(high impedance) throughout the entire cycle. 12. These parameters are referenced to /CAS leading edge in early write cycles. 13. tRASP is defines /RAS pulse width in Fast Page Mode cycles. 14. Access time is determined by the longer of tAA or tCAC or tACP . 15. An initial pause of 200us is required after power up followed by a minimum of eight initialization cycle (eny combination of cycles containing /RAS clock such as /RAS only refresh). If the internal refresh count is used, a mnimum of eight /CAS before /RAS refresh cycle are required. URL:www.hbe.co.kr REV.1.0 (August.2002) 6 HANBiT Electronics Co., Ltd HANBit HMD1M32M2G PACKAGING INFORMATION 107.95 101.19 3.18 R1.57 mm 3.38 mm 19.05 10.16 6.35 6.35 mm 2.03 mm R1.57±1.0 6.35 95.25 mm 5.08 MAX 2.54 mm 0.25 mm MAX MIN 1.27 mm 1.27±0.08 mm ORDERING INFORMATION Part Number Density Org. Package HMD1M32M2G-6 4MByte X32 72 Pin-SIMM URL:www.hbe.co.kr REV.1.0 (August.2002) 7 Component Number 2EA Vcc MODE SPEED 5V FP 60ns HANBiT Electronics Co., Ltd HANBit HMD1M32M2G-7 URL:www.hbe.co.kr REV.1.0 (August.2002) HMD1M32M2G 4MByte x 32 72 Pin-SIMM 8 2EA 5V FP 70ns HANBiT Electronics Co., Ltd