HM62W256 Series 256 k SRAM (32-kword × 8-bit) ADE-203-084H (Z) Rev. 8.0 Nov. 1997 Features • Low voltage operation SRAM Operating Supply Voltage: 3.0 V to 3.6 V • 0.8 µm Hi-CMOS process • High speed Access time: 55/70/85 ns (max) • Low power Standby: 0.33 µW (typ) • Completely static memory No clock or timing strobe required • Directly LVTTL compatible: All inputs and outputs Ordering Information Type No. Access Time Package HM62W256LFP-7T 70 ns 450 mil 28-pin plastic SOP (FP-28DA) HM62W256LFP-5SLT HM62W256LFP-7SLT HM62W256LFP-8SLT 55 ns 70 ns 85 ns HM62W256LFP-7ULT 70 ns HM62W256LT-7 70 ns HM62W256LT-7SL HM62W256LT-8SL 70 ns 85 ns HM62W256LTM-7 70 ns HM62W256LTM-5SL HM62W256LTM-7SL HM62W256LTM-8SL 55 ns 70 ns 85 ns HM62W256LTM-7UL 70 ns 8 mm × 14 mm 32-pin TSOP (normal type) (TFP-32DA) 8 mm × 13.4 mm 28-pin TSOP (normal type) (TFP-28DA) HM62W256 Series Pin Arrangement HM62W256LFPSeries HM62W256LT Series OE A11 NC A9 A8 A13 WE VCC A14 A12 A7 A6 A5 NC A4 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A14 1 28 VCC A12 2 27 WE A7 3 26 A13 A6 4 25 A8 A5 5 24 A9 A4 6 23 A11 A3 7 22 OE A2 8 21 A10 A1 9 20 CS A0 10 19 I/O7 I/O0 11 18 I/O6 I/O1 12 17 I/O5 (Top view) I/O2 13 16 I/O4 HM62W256LTM Series VSS 14 15 I/O3 (Top view) OE A11 A9 A8 A13 WE VCC A14 A12 A7 A6 A5 A4 A3 22 23 24 25 26 27 28 1 2 3 4 5 6 7 (Top view) Pin Description Pin name Function A0 – A14 Address inputs I/O0 – I/O7 Input/output CS Chip select WE Write enable OE Output enable NC No connection VCC Power supply VSS Ground 2 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A10 CS NC I/O7 I/O6 I/O5 I/O4 I/O3 VSS I/O2 I/O1 I/O0 A0 NC A1 A2 21 20 19 18 17 16 15 14 13 12 11 10 9 8 A10 CS I/O7 I/O6 I/O5 I/O4 I/O3 V SS I/O2 I/O1 I/O0 A0 A1 A2 HM62W256 Series Block Diagram V CC (MSB) A12 V SS A5 A7 A6 A8 • • • • A13 A14 • • Row Decoder Memory Matrix 512 × 512 • • • • A4 (LSB) A3 I/O0 • • • • • • • Column I/O • • • • • • Input Data Control Column Decoder • • I/O7 • • A2 A1 A0 A10 A9 A11 (LSB) (MSB) • • • • CS WE Timing Pulse Generator Read/Write Control OE 3 HM62W256 Series Function Table WE CS OE Mode VCC Current I/O Pin Ref. Cycle X H X Not selected I SB , I SB1 High-Z — H L H Output disable I CC High-Z — H L L Read I CC Dout Read cycle (1)–(3) L L H Write I CC Din Write cycle (1) L L L Write I CC Din Write cycle (2) Note: X: H or L Absolute Maximum Ratings Parameter Power supply voltage *1 Symbol Value VCC –0.5 to 4.6 V *1 VT –0.5 Power dissipation PT 1.0 W Operating temperature Topr 0 to + 70 °C Storage temperature Tstg –55 to +125 °C Storage temperature under bias Tbias –10 to +85 °C Terminal voltage *2 Unit *3 to VCC + 0.5 V Notes: 1. Relative to VSS 2. VT min: –3.0 V for pulse half-width ≤ 50 ns 3. Maximum voltage is 4.6 V Recommended DC Operating Conditions (Ta = 0 to +70°C) Parameter Symbol Min Typ Max Unit Supply voltage VCC 3.0 3.3 3.6 V VSS 0 0 0 V VIH 2.0 — VCC+0.3 V — 0.8 V Input high(logic 1) voltage Input low(logic 0) voltage Note: 4 VIL 1. VIL min: –3.0 V for pulse half-width ≤ 50 ns –0.3 *1 HM62W256 Series DC Characteristics (Ta = 0 to +70°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V) Parameter Symbol Min Typ*1 Max Unit Test conditions Input leakage current |ILI| — — 1 µA VSS ≤ Vin ≤ VCC Output leakage current |ILO | — — 1 µA CS = VIH or OE = VIH or WE = VIL, VSS ≤ VI/O ≤ VCC Operating power supply current (DC) I CCDC1 — — 15 mA CS = VIL, others = VIH/VIL I I/O = 0 mA I CCDC2 — — 10 mA CS ≤ 0.2 V, V IH ≥ V CC – 0.2 V, VIL ≤ 0.2 V, II/O = 0 mA HM62W256-5 I CCAC1 — — 30 mA min cycle, duty = 100 %, CS = VIL, others = VIH/VIL I I/O = 0 mA HM62W256-7 I CCAC1 — — 30 HM62W256-8 I CCAC1 — — 27 I CCAC2 — — 15 mA Cycle time ≥ 1 µs, duty = 100% I I/O = 0 mA, CS ≤ 0.2 V, VIH ≥ V CC – 0.2 V, VIL ≤ 0.2 V I SB — 0.1 1 mA CS = VIH I SB1 — 0.1 50 µA Vin ≥ 0 V, CS ≥ V CC – 0.2 V, Average operating power supply current Standby power supply current Output low voltage VOL Output high voltage VOH *2 — 0.1 10 — 0.1 5*3 — — 0.4 V I OL = 2.0 mA — — 0.2 V I OL = 100 µA VCC – 0.2 — — V I OH = –100 µA 2.4 — V I OH = –2.0 mA — Notes: 1. Typical values are at VCC = 3.3 V, Ta = +25°C and not guaranteed. 2. This characteristic is guaranteed only for L-SL version. 3. This characteristic is guaranteed only for L-UL version. Capacitance (Ta = 25°C, f = 1.0 MHz) Parameter Input capacitance *1 Input/output capacitance Note: *1 Symbol Min Typ Max Unit Test Conditions Cin — — 5 pF Vin = 0 V CI/O — — 8 pF VI/O = 0 V 1. This parameter is sampled and not 100% tested. 5 HM62W256 Series AC Characteristics (Ta = 0 to +70°C, VCC = 3.3 V ± 0.3 V, unless otherwise noted.) Test Conditions • • • • Input pulse levels: 0.4 V to 2.4 V Input rise and fall time: 5 ns Input reference level: 1.4 V Output timing reference level: HM62W256-5: 1.4 V HM62W256-7/8: 0.8 V/2.0 V Output Load 500Ω Dout 50 pF* 1.4 V (Including scope & jig) Read Cycle HM62W256 -5 -7 -8 Parameter Symbol Min Max Min Max Min Max Unit Notes Read cycle time t RC 55 — 70 — 85 — ns Address access time t AA — 55 — 70 — 85 ns Chip select access time t ACS — 55 — 70 — 85 ns Output enable to output valid t OE — 30 — 35 — 45 ns Chip selection to output in low-Z t CLZ 5 — 10 — 10 — ns 2 Output enable to output in low-Z t OLZ 5 — 5 — 5 — ns 2 Chip deselection to output in high-Z t CHZ 0 20 0 25 0 30 ns 1, 2 Output disable to output in high-Z t OHZ 0 20 0 25 0 30 ns 1, 2 Output hold from address change t OH 10 — 10 — 10 — ns Notes: 1. t CHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. This parameter is sampled and not 100% tested. 6 HM62W256 Series Read Timing Waveform (1) (WE = VIH) t RC Address Valid address t AA t ACS CS t OH t OE t OLZ OE t OHZ t CHZ High impedance Dout Valid data Read Timing Waveform (2) (WE = VIH, CS = VIL , OE = VIL ) t RC Valid address Address tAA t OH t OH Dout Valid data Read Timing Waveform (3) (WE = VIH, OE = VIL )*1 t ACS CS t CLZ Dout Note: 1. High impedance t CHZ Valid data Address must be valid prior to or simultaneously with CS going low. 7 HM62W256 Series Write Cycle HM62W256 -5 -7 -8 Parameter Symbol Min Max Min Max Min Max Unit Notes Write cycle time t WC 55 — 70 — 85 — ns Chip selection to end of write t CW 45 — 60 — 75 — ns 4 Address setup time t AS 0 — 0 — 0 — ns 5 Address valid to end of write t AW 45 — 60 — 75 — ns Write pulse width t WP 40 — 50 — 55 — ns 3, 8 Write recovery time t WR 0 — 0 — 0 — ns 6 Write to output in high-Z t WHZ 0 25 0 25 0 30 ns 1, 2, 7 Data to write time overlap t DW 30 — 30 — 35 — ns Data hold from write time t DH 0 — 0 — 0 — ns Output active from end of write t OW 10 — 10 — 10 — ns 2 Output disable to output in high-Z t OHZ 0 20 0 25 0 30 ns 1, 2, 7 Notes: 1. t OHZ and t WHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. This parameter is samples and not 100% tested. 3. A write occurs during the overlap (tWP) of a low CS and a low WE. A write begins at the later transition of CS going low or WE going low. A write ends at the earlier transition of CS going high or WE going high. tWP is measured from the beginning of write to the end of write. 4. t CW is measured from CS going low to the end of write. 5. t AS is measured from the address valid to the beginning of write. 6. t WR is measured from the earlier of WE or CS going high to the end of write cycle. 7. During this period, I/O pins are in the output state so that the input signals of the opposite phase to the outputs must not be applied. 8. In the write cycle with OE low fixed, tWP must satisfy the following equation to avoid a problem of data bus contention, tWP ≥ tWHZ max + tDW min. 8 HM62W256 Series Write Timing Waveform (1) (OE Clock) t WC Address Valid address t AW t WR OE t CW CS *1 t WP t AS WE t OHZ High impedance Dout t DW High impedance Din Notes: 1. t DH Valid data If CS goes low simultaneously with WE going low or after WE going low, the outputs remain in the high impedance state. 9 HM62W256 Series Write Timing Waveform (2) (OE Low Fixed) t WC Address Valid address t WR t CW CS *1 t AW t OH tWP WE tAS t WHZ t OW *2 *3 Dout t DW t DH *4 High impedance Din Notes: 1. 2. 3. 4. 10 Valid data If CS goes low simultaneously with WE going low or after WE going low, the outputs remain in the high impedance state. Dout is the same phase of the write data of this write cycle. Dout is the read data of next address. If CS is low during this period, I/O pins are in the output state. Therefore, the input signals of the opposite phase to the output must not be applied to them. HM62W256 Series Low VCC Data Retention Characteristics (Ta = 0 to +70°C) Parameter Symbol Min Typ* 1 Max Unit Test conditions*6 VCC for data retention VDR 2.0 — V CS ≥ V CC – 0.2 V, Vin ≥ 0 V µA VCC = 3.0 V, Vin ≥ 0 V CS ≥ V CC – 0.2 V, See retention waveform Data retention current Chip deselect to data retention time Operation recovery time Notes: 1. 2. 3. 4. 5. 6. I CCDR t CDR tR 3.6 *2 — 0.05 30 — 0.05 8*3 — 0.05 3*4 — — ns — — ns 0 *5 t RC Typical values are at VCC = 3.0 V, Ta = 25°C and not guaranteed. 10 µA max. at Ta = 0 to +40°C. This characteristics guaranteed for only L-SL version. 2.5 µA max. at Ta = 0 to +40°C. This characteristics guaranteed for only L-UL version. 0.6 µA max. at Ta = 0 to +40°C. t RC = read cycle time. CS controls address buffer, WE buffer, OE buffer, and Din buffer. If CS controls data retention mode, other input levels (address, WE, OE, I/O) can be in the high impedance state. Low V CC Data Retention Timing Waveform Data retention mode V CC 3.0 V tR t CDR 2.0 V V DR CS 0V CS > VCC – 0.2 V 11 HM62W256 Series Package Dimensions HM62W256LFP Series (FP-28DA) Unit: mm 18.00 18.75 Max 15 14 1.27 0.15 0.40 ± 0.08 0.38 ± 0.06 11.80 ± 0.30 1.70 0° – 8° 1.00 ± 0.20 0.20 M Dimension including the plating thickness Base material dimension 12 0.15 0.20 +– 0.10 1.12 Max 0.17 ± 0.05 0.15 ± 0.04 1 3.00 Max 8.40 28 Hitachi Code JEDEC EIAJ Weight (reference value) FP-28DA Conforms Conforms 0.82 g HM62W256 Series Package Dimensions HM62W256LT Series (TFP-32DA) Unit: mm 8.00 8.20 Max 17 1 16 12.40 32 0.50 0.08 M Dimension including the plating thickness Base material dimension 0.17 ± 0.05 0.125 ± 0.04 1.20 Max 0.10 0.80 14.00 ± 0.20 0.45 Max 0.13 ± 0.05 0.22 ± 0.08 0.20 ± 0.06 0° – 5° Hitachi Code JEDEC EIAJ Weight (reference value) 0.50 ± 0.10 TFP-32DA Conforms Conforms 0.26 g 13 HM62W256 Series Package Dimensions HM62W256LTM Series (TFP-28DA) Unit: mm 8.00 8.20 Max 8 11.80 21 22 7 28 1 0.22 ± 0.05 0.20 ± 0.04 0.55 0.10 M 0.80 13.40 ± 0.30 0.63 Max Dimension including the plating thickness Base material dimension 14 0.50 ± 0.10 +0.10 0.05 –0.05 0.10 0.145 ± 0.05 0.125 ± 0.04 1.20 Max 0° – 5° Hitachi Code JEDEC EIAJ Weight (reference value) TFP-28DA — — 0.22 g HM62W256 Series When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi’s permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user’s unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS. Hitachi, Ltd. Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi Semiconductor (America) Inc. 2000 Sierra Point Parkway Brisbane, CA. 94005-1897 USA Tel: 800-285-1601 Fax:303-297-0447 Hitachi Europe GmbH Continental Europe Dornacher Straße 3 D-85622 Feldkirchen München Tel: 089-9 91 80-0 Fax: 089-9 29 30-00 Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 01628-585000 Fax: 01628-585160 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 049318 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071 Copyright © Hitachi, Ltd., 1997. All rights reserved. Printed in Japan. 15 HM62W256 Series Revision Record Rev. Date Contents of Modification Drawn by Approved by 0.0 Mar. 27, 1992 Initial issue Y. Saito Y. Kawashima 1.0 Dec. 20, 1992 Full specification Y. Saito Y. Kawashima 2.0 Feb. 25, 1993 Addition of HM62W256LT Series Y. Saito Y. Kawashima 3.0 Apr. 1, 1993 Operation Supply Voltage: 3.0V – 3.6 V to Single 3.3 V Supply f = 2 MHz to f = 1 MHz Function Table Not selected to Standby Absolute Maximum Rating Relative to VCC to Relative to VSS DC Characteristics I CCAC2 Cycle time: 500 ns to 1 µs Low VCC Data Retention Timing Waveforms Change of Notes K. Imato T. Matumoto 4.0 Sep. 10, 1993 Absolute Maximum Rating VT = –0.5 to VCC + 0.5 V to –0.5 to VCC + 0.3 V DC Characteristics I CCDC1 (max): 5.0 mA to 15 mA I CCDC2 (max): 2.5 mA to 10 mA AC Characteristics tDW (min): 30/40 ns to 30/35 ns Addition of notes for Low V CC Data retention Timing Waveform Y. Saito K. Yoshizaki 5.0 Mar. 18, 1994 DC Characteristics I CCAC2 (max): 10 mA to 15 mA Y. Saito K. Yashizaki 6.0 Oct. 31, 1994 Y. Saito Addition of HM62W256LTM Series (TFP-28DA) Addition of Block Diagram AC Characteristics Addition of note 12 Low VCC data retention characteristics I CCDR (typ): —/— µA to 0.2/0.2 µA Note 2: 20 µA max at Ta = 0 to 40°C to 10 µA max at Ta = 0 to 40°C K. Yoshizaki 7.0 Jun. 19, 1995 Feature Low power (standby): 0.66 µW to 0.33 µW Deletion of HM62W256LFP-8T Deletion of HM62W256LT-8 Deletion of HM62W256LTM-8 Addition of HM62W256LFP-5SLT/7ULT Addition of HM62W256LTM-5SLT/7ULT Change of Block Diagram Absolute maximum Ratings Terminal voltage VT: –0.5 to V CC + 0.3 V to –0.5 to VCC + 0.5 V K. Yoshizaki 16 M. Higuchi HM62W256 Series Revision Record (cont) Rev. Date Contents of Modification Drawn by Approved by M. Higuchi K. Yoshizaki 7.0 Jun. 19, 1995 DC Characteristics Addition of note 3. I CCAC1 (max): 30/27 mA to 30/30/27 mA I SB1 (typ): 0.2/0.2/ µA to 0.1/0.1/0.1 µA I SB1 (max): 50/10 µA to 50/10/5 µA Capacitance Cin (max): 8 pF to 5 pF CI/O (max): 10 pF to 8 pF AC Characteristics Addition of Output timing reference level: HM62W256-5: 1.4 V Change order of notes t RC (min): 70/85 ns to 55/70/85 ns t AA (max): 70/85 ns to 55/70/85 ns t ACS (max): 70/85 ns to 55/70/85 ns t OE (max): 35/45 ns to 30/35/45 ns t CLZ (min): 10/10 ns to 5/10/10 ns t OLZ (min): 5/5 ns to 5/5/5 ns t CHZ (max): 25/30 ns to 20/25/30 ns t OHZ (max): 25/30 ns to 20/25/30 ns t OH (min): 10/10 ns to 10/10/10 ns t WC (min): 70/85 ns to 55/70/85 ns t CW (min): 60/75 ns to 45/60/75 ns t AW (min): 60/75 ns to 45/60/75 ns t WP (min): 50/55 ns to 40/50/55 ns t WHZ (max): 25/30 ns to 25/25/30 ns t DW (min): 30/35 ns to 30/30/35 ns t OW (min): 10/10 ns to 10/10/10 ns Low VCC Data Retantion Characteristics I CCDR (typ): 0.2/0.2 µA to 0.05/0.05/0.05 µA I CCDR (max): 30/8 µA to 30/8/3 µA 8.0 Nov. 1997 Change of Format Change of Subtitle 17