Direct Rambus RIMM™ with 128/144Mbit RDRAMs Preliminary Overview Key Timing Parameters/Part Numbers The Rambus® RIMMTM module is a general purpose highperformance memory subsystem suitable for use in a broad range of applications including computer memory, personal computers, workstations, and other applications where high bandwidth and low latency are required. The following table lists the frequency and latency bins available from RIMM modules. An optional -LP designator is used to indicate low power modules. The Rambus RIMM module consist of 128Mb/144Mb Direct Rambus DRAM devices. These are extremely highspeed CMOS DRAMs organized as 8M words by 16 or 18 bits. The use of Rambus Signaling Level (RSL) technology permits 600MHz ,711MHz or 800MHz transfer rates while using conventional system and board design technologies. Direct RDRAM devices are capable of sustained data transfers at 1.25 ns per two bytes (10ns per 16 bytes). The RDRAM architecture enables the highest sustained bandwidth for multiple, simultaneous randomly addressed memory transactions. The separate control and data buses with independent row and column control yield over 95% bus efficiency. The Direct RDRAM's 16-banks architecture supports up to four simultaneous transactions per device. Table 1: RIMM Module Frequency and Latency Organization I/O Freq. MHz t rac (Row Access Time) ns x16 600 53 x16 711 45 x16 800 45 x16 800 40 x18 600 53 x18 711 45 x18 800 45 x18 800 40 Features w High speed 800,711 and 600 MHz RDRAM storage w 184 edge connector pads with 1 mm pad spacing w Maximum module PCB size: 133.5mm x 31.75mm x 1.37mm(5.21” x 1.25” x 0.05”) w Each RDRAM has 32 banks, for a total of 512, 384, 256, 192 or 128 banks on each 256MB, 192MB, 128MB, 96MB, or 64MB module respectively w Gold plated edge connector pad contacts wSerial Presence Detect(SPD) support w Operates from a 2.5 volt supply (¡¾ 5%) w Low power and powerdown self refresh modes w Separate Row and Column buses for higher efficiency Form Factor The Rambus RIMM modules are offered in a 184-pad 1mm edge connector pad pitch from factor suitable for either 184 or 168 contact RIMM connectors. The RIMM module is suitable for desktop and other system applications. Figure 1 shows an eight device Rambus RIMM module without heat spreader. This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.0/Dec.99 1 RIMM with 128/144Mb RDRAM Table 2: Module Pad Number and Signal Names Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 2 Pin Name Gnd LDQA8 Gnd LDQA6 Gnd LDQA4 Gnd LDQA2 Gnd LDQA0 Gnd LCTMN Gnd LCTM Gnd NC Gnd LROW1 Gnd LCOL4 Gnd LCOL2 Gnd LCOL0 Gnd LDQB1 Gnd LDQB3 Gnd LDQB5 Gnd LDQB7 Gnd LSCK Vcmos SOUT Vcmos NC Gnd NC Vdd Vdd NC NC NC NC Pin B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 Pin Name Gnd LDQA7 Gnd LDQA5 Gnd LDQA3 Gnd LDQA1 Gnd LCFM Gnd LCFMN Gnd NC Gnd LROW2 Gnd LROW0 Gnd LCOL3 Gnd LCOL1 Gnd LDQB0 Gnd LDQB2 Gnd LDQB4 Gnd LDQB6 Gnd LDQB8 Gnd LCMD Vcmos SIN Vcmos NC Gnd NC Vdd Vdd NC NC NC NC Pin A47 A48 A49 A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 A63 A64 A65 A66 A67 A68 A69 A70 A71 A72 A73 A74 A75 A76 A77 A78 A79 A80 A81 A82 A83 A84 A85 A86 A87 A88 A89 A90 A91 A92 Pin Name NC NC NC NC Vref Gnd SCL Vdd SDA SVdd SWP Vdd RSCK Gnd RDQB7 Gnd RDQB5 Gnd RDQB3 Gnd RDQB1 Gnd RCOL0 Gnd RCOL2 Gnd RCOL4 Gnd RROW1 Gnd NC Gnd RCTM Gnd RCTMN Gnd RDQA0 Gnd RDQA2 Gnd RDQA4 Gnd RDQA6 Gnd RDQA8 Gnd Pin B47 B48 B49 B50 B51 B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62 B63 B64 B65 B66 B67 B68 B69 B70 B71 B72 B73 B74 B75 B76 B77 B78 B79 B80 B81 B82 B83 B84 B85 B86 B87 B88 B89 B90 B91 B92 Pin Name NC NC NC NC Vref Gnd SA0 Vdd SA1 SVdd SA2 Vdd RCMD Gnd RDQB8 Gnd RDQB6 Gnd RDQB4 Gnd RDQB2 Gnd RDQB0 Gnd RCOL1 Gnd RCOL3 Gnd RROW0 Gnd RROW2 Gnd NC Gnd RCFMN Gnd RCFM Gnd RDQA1 Gnd RDQA3 Gnd RDQA5 Gnd RDQA7 Gnd Rev.1.0 Dec.99 RIMM with 128/144Mb RDRAM Table 3: Module Connector Pad Description Signal Module Connector Pads Gnd A1, A3, A5, A7, A9, A11, A13, A15, A17, A19, A21, A23, A25, A27, A29, A31, A33, A39, A52, A60, A62, A64, A66, A68, A70, A72, A74, A76, A78, A80, A82, A84, A86, A88, A90, A92, B1, B3, B5, B7, B9, B11, B13, B15, B17, B19, B21, B23, B25, B27, B29, B31, B33, B39, B52, B60, B62, B64, B66, B68, B70, B72, B74, B76, B78, B80, B82, B84, B86, B88, B90, B92 LCFM B10 LCFMN B12 LCMD B34 LCOL4.. LCOL0 A20, B20, A22, B22, A24 LCTM A14 LCTMN A12 I/O Type Description Ground reference for RDRAM core and interface. 72 PCB connector pads. I RSL Clock from master. Interface clock used for receiving RSL signals from the Channel. Positive polarity. I RSL Clock from master. Interface clock used for receiving RSL signals from the Channel. Negative polarity. I VCMOS Serial Command used to read from and write to the control registers. Also used for power management. I RSL Column bus. 5-bit bus containing control and address information for column accesses. I RSL Clock to master. Interface clock used for transmitting RSL signals to the Channel. Positive polarity. I RSL Clock to master. Interface clock used for transmitting RSL signals to the Channel. Negative polarity. LDQA8.. A2, B2, A4, B4, A6, B6, A8, B8, A10 I/O LDQA0 RSL Data bus A. A 9-bit bus carrying a byte of read or write data between the Channel and the RDRAM. LDQA8 is non-functional on x16 RDRAM devices. LDQB8.. LDQB0 I/O RSL Data bus B. A 9-bit bus carrying a byte of read or write data between the Channel and the RDRAM. LDQB8 is non-functional on x16 RDRAM devices. I RSL Row bus. 3-bit bus containing control and address information for row accesses. I VCMOS Serial Clock input. Clock source used to read from and write to the RDRAM control registers. B32, A32, B30, A30, B28, A28, B26, A26, B24 LROW2.. B16, A18, B18 LROW0 LSCK A34 NC A16, B14, A38, B38, A40, B40, A77, B79 These pads are not connected. These 8 connector pads are reserved for future use. NC A43, B43, A44, B44, A45, B45, A46, B46, A47, B47, A48, B48, A49, B49, A50, B50 These pads are not connected. These 16connector pads art reserved for future use. The 168 contact RIMM connector does not connect to these PCB pads. RCFM B83 RCFMN B81 Rev.1.0 Dec.99 I RSL Clock from master. Interface clock used for receiving RSL signals from the Channel. Positive polarity. I RSL Clock from master. Interface clock used for receiving RSL signals from the Channel. Negative polarity. 3 RIMM with 128/144Mb RDRAM Signal Module Connector Pads RCMD B59 Description Serial Command Input used to read from and write to the control registers. Also used for power management. I VCMOS I RSL Column bus. 5-bit bus containing control and address information for column accesses. I RSL Clock to master. Interface clock used for transmitting RSL signals to the Channel. Positive polarity. I RSL Clock to master. Interface clock used for transmitting RSL signals to the Channel. Negative polarity. RDQA8.. A91, B91, A89, B89, A87, B87, A85, I/O RDQA0 B85, A83 RSL Data bus A. A 9-bit bus carrying a byte of read or write data between the Channel and the RDRAM. RDQA8 is non-functional on x16 RDRAM devices. RDQB8.. RDQB0 RSL Data bus B. A 9-bit bus carrying a byte of read or write data between the Channel and the RDRAM. RDQB8 is non-functional on x16 RDRAM devices. I RSL Row bus. 3-bit bus containing control and address information for row accesses. I VCMOS Serial Clock input. Clock source used to read from and write to the RDRAM control registers. RCOL4.. RCOL0 A73, B73, A71, B71, A69 RCTM A79 RCTMN A81 B61, A61, B63, A63, B65, A65, B67, I/O A67, B69 RROW2.. B77, A75, B75 RROW0 RSCK A59 SA0 B53 I SVDD Serial Presence Detect Address 0. SA1 B55 I SVDD Serial Presence Detect Address 1. SA2 B57 I SVDD Serial Presence Detect Address 2. SCL A53 I SVDD Serial Presence Detect Clock. SDA A55 I/O SVDD Serial Presence Detect Data (Open Collector I/O) SIN B36 SOUT 4 I/O Type I/O VCMOS Serial I/O for reading from and writing to the control registers. Attaches to SIO0 of the first RDRAM on the module. I/O VCMOS Serial I/O for reading from and writing to the control registers. Attaches to SIO1 of the last RDRAM on the module. A36 SVDD A56, B56 SWP A57 VCMOS A35, B35, A37, B37 Vdd A41, A42, A54, A58, B41, B42, B54, B58 Vref A51, B51 SPD Voltage. Used for signals SCL, SDA, SWE, SA0, SA1 and SA2. I SVDD Serial Presence Detect Write Protect (active high). When low, the SPD can be written as well as read. CMOS I/O Voltage. Used for signals CMD, SCK, SIN, SOUT. I Supply voltage for the RDRAM core and interface logic. Logic threshold reference voltage for RSL signals. Rev.1.0 Dec.99 RIMM with 128/144Mb RDRAM 4 RDQA8 RDQA7 RDQA6 RDQA5 RDQA4 RDQA3 RDQA2 RDQA1 RDQA0 RCFM RCFMN RCTM RCTMN RROW2 RROW1 RROW0 RCOL4 RCOL3 RCOL2 RCOL1 RCOL0 RDQB0 RDQB1 RDQB2 RDQB3 RDQB4 RDQB5 RDQB6 RDQB7 RDQB8 64MB DQA8 DQA7 DQA6 DQA5 DQA4 DQA3 DQA2 DQA1 DQA0 CFM CFMN CTM CTMN ROW2 ROW1 ROW0 COL4 COL3 COL2 COL1 COL0 DQB0 DQB1 DQB2 DQB3 DQB4 DQB5 DQB6 DQB7 DQB8 6 DQA8 DQA7 DQA6 DQA5 DQA4 DQA3 DQA2 DQA1 DQA0 CFM CFMN CTM CTMN ROW2 ROW1 ROW0 COL4 COL3 COL2 COL1 COL0 DQB0 DQB1 DQB2 DQB3 DQB4 DQB5 DQB6 DQB7 DQB8 96MB Gnd 8 DQA8 DQA7 DQA6 DQA5 DQA4 DQA3 DQA2 DQA1 DQA0 CFM CFMN CTM CTMN ROW2 ROW1 ROW0 COL4 COL3 COL2 COL1 COL0 DQB0 DQB1 DQB2 DQB3 DQB4 DQB5 DQB6 DQB7 DQB8 SA0 SA1 SA2 1 per 2 RDRAMs Plus one Near Connector 0.1§Þ Gnd 128MB DQA8 DQA7 DQA6 DQA5 DQA4 DQA3 DQA2 DQA1 DQA0 CFM CFMN CTM CTMN ROW2 ROW1 ROW0 COL4 COL3 COL2 COL1 COL0 DQB0 DQB1 DQB2 DQB3 DQB4 DQB5 DQB6 DQB7 DQB8 SOUT 12 LDQA8 LDQA7 LDQA6 LDQA5 LDQA4 LDQA3 LDQA2 LDQA1 LDQA0 LCFM LCFMN LCTM LCTMN LROW2 LROW1 LROW0 LCOL4 LCOL3 LCOL2 LCOL1 LCOL0 LDQB0 LDQB1 LDQB2 LDQB3 LDQB4 LDQB5 LDQB6 LDQB7 LDQB8 SIN RLSCK RCMD 192MB 5 Rev.1.0 Dec.99 LSCK LCMD VREF 16 0.1§Þ SDA Vcc SCL SDA WP A0A1A2 SCL SWP Gnd SVDD 256MB Gnd VREF Serial Presence Detect 1 per 2 RDRAMs SVDD 0.1§Þ VCMOS 2 per RDRAM 0.1§Þ N Vdd Module Capacity Direct RDRAM (128/144Mb) UN SIO0 SIO1 SCK CMD Vref Direct RDRAM (128/144Mb) U3 SIO0 SIO1 SCK CMD Vref Direct RDRAM (128/144Mb) U2 SIO0 SIO1 SCK CMD Vref Direct RDRAM (128/144Mb) U1 SIO0 SIO1 SCK CMD Vref Note 1: Rambus Channel signals form a loop through the RIMM module, with the exception of the SIO chain. Note 2: See Serial Presence Detection Specification for information on the SPD device and its contents Figure 2: RIMM Module Functional Diagram RIMM with 128/144Mb RDRAM Absolute Maximum Ratings Signal Parameter Min Max Unit VI,ABS Voltage applied to any RSL or CMOS pin with respect to Gnd - 0.3 V DD + 0.3 V VDD,ABS Voltage on VDD with respect to Gnd - 0.5 V DD + 1.0 V TSTORE Storage temperature - 50 100 ºC DC Recommended Electrical Conditions Signal Parameter and Conditions Min Max Unit VDD Supply voltage 2.50 - 0.13 2.50 + 0.13 V VCMOS CMOS I/O power supply at pad for 2.5V controllers: CMOS I/O power supply at pad for 1.8V controllers: 2.5 - 0.13 1.8 - 0.1 2.5 + 0.25 1.8 + 0.2 V V VREF Reference voltage 1.4 - 0.2 1.4 + 0.2 V VIL RSL input low voltage VREF - 0.5 VREF - 0.2 V VIH RSL input high voltage VREF + 0.2 VREF + 0.5 V VIL,CMOS CMOS input low voltage - 0.3 0.5VCMOS - 0.25 V VIH,CMOS CMOS input high voltage 0.5VCMOS + 0.25 VCMOS + 0.3 V 0.3 V VOL,CMOS CMOS output low voltage @ IOL,CMOS = 1mA VOH,CMOS CMOS output high voltage @ IOH,CMOS = -0.25mA V VCMOS - 0.3 IREF VREF current @ VREF,MAX -10 x no. RDRAMsa 10 x no. RDRAMsa §Ë ISCK,CMD CMOS input leakage current @ (0 ≤ VCMOS ≤ VDD ) -10 x no. RDRAMsa 10 x no. RDRAMsa §Ë ISIN,SOUT CMOS input leakage current @ (0 ≤ VCMOS ≤ VDD ) -10.0 §Ë 10.0 a. The tale below shows the number of 128Mb or 144Mb RDRAM devices contained in a RIMM module of listed memory storage capacity RIMM Module Capacity: Number of 128Mb or 144Mb RDRAM devices: 6 256MB 192MB 128MB 96MB 64MB 16 12 8 6 4 Rev.1.0 Dec.99 RIMM with 128/144Mb RDRAM RIMM Module Current Profile RIMM Module Capacity: No. of 128/144Mb RDRAMs: IDD RIMM module power conditionsa IDD1 IDD2 IDD3 IDD4 IDD5 IDD6 One RDRAM in Readb, balance in NAP mode One RDRAM in Readb, balance in Standby mode One RDRAM in Readb, balance in Active mode One RDRAM in Write, balance in NAP mode One RDRAM in Read, balance in Standby mode One RDRAM in Read, balance in Active mode 256/288MB 192/216MB 128/144MB 96/108MB 16 12 8 6 64/72MB 4 Freq. Max Max Max Max Max 800 690/658 675/641 660/625 652/616 645/608 711 633/605 618/589 603/572 596/564 589/556 600 556/532 541/516 527/500 520/492 512/484 800 2302/2354 1857/1885 1412/1416 1189/1181 967/947 711 2142/2199 1725/1757 1307/1316 1099/1095 890/874 600 1928/2005 1547/1596 1167/1188 787/779 800 3506/3560 2740/2769 1974/1979 1591/1583 1208/1188 711 3222/3318 2517/2578 1811/1838 1459/1468 1106/1098 600 2889/3006 2253/2331 1616/1655 1297/1317 977/983 Unit mA mA mA 979/979 800 794/766 778/750 763/733 756/724 748/716 711 765/705 750/688 735/672 728/663 720/655 600 668/625 654/609 639/594 632/586 625/578 800 2405/2462 1960/1993 1515/1524 1293/1290 1070/1055 711 2273/2298 1856/1857 1439/1415 1230/1195 1022/974 600 2040/2098 1660/1690 1280/1281 1090/1077 900/872 800 3609/3668 2843/2878 2077/2087 1694/1692 1311/1296 711 3353/3418 2648/2678 1943/1938 1590/1568 1238/1198 600 3002/3100 2365/2424 1729/1748 1410/1410 1092/1073 mA mA mA a. Specifications in this table are maximum guidelines. Actual power will depend on individual RDRAM component specifications, memory controller and usage patterns. Please refer to specific RIMM module vendor data sheets for additional information. Max current computed for x18 144Mb RDRAMs. X16 128Mb RDRAMs use 8mA less current per RDRAM in Read. b. I/O current is a function of the % of 1’s, to add I/O power for 50% 1’s for a X16 need to add 257mA or 290mA for X18ECC module for the following : VDD = 2.5V, VTERM = 1.8V, V REF = 1.4V and VDIL = VREF - 0.5V. Rev.1.0 Dec.99 7 RIMM with 128/144Mb RDRAM AC Electrical Specifications Symbol Parameter and Condition Min Typ Max Unit Z Module Impedance 25.2 28 30.8 §Ù TPD Average clock delay form finger to finger of all RSL clock nets (CTMN, CFM, and CFMN) - See Tablea ns Ä TPD ¥ Propagation delay variation of RSL signals with respect to TPDb,c for 4, 6, 8, and 12 device modules -21 21 ps Propagation delay variation of RSL signals with respect to TPDb,c for 16 device modules -24 24 ps Ä TPD-CMOS ¥ Propagation delay variation of SCK and CMD signals with respect to an average clock delayb -100 100 ps V¥á /VIN Attenuation Limit See Tablea % VXF /VIN Forward crosstalk coefficient (300ps input rise time 20%-80%) See Tablea % VXB /VIN Backward crosstalk coefficient (300ps input rise time 20%-80%) See Tablea % a. Table below lists parameters and specifications for different storage capacity RIMM Modules that use 128Mb or 144Mb RDRAM devices. b. TPD or Average clock delay is defined as the average delay from finger to finger of all RSL clock nets (CTM, CTMN, CFM, and CFMN) c. If the RIMM module meets the following specification , then it is compliant to the specification. If the RIMM module does not meet these specification. Then the specification can be adjusted by the “ Adjusted ¥Ä TPD Specification ” table Adjusted ¥Ä TPD Specification Adjusted Min/Max Asolute Min/Max Symbol Parameter and Conditions Unit Ä TPD ¥ Propagation delay variation of RSL signals with respect to TPD for 4,6 and 8 device modules +/-[17+(18*N*¥ Ä Z0)]a -30 30 ns Propagation delay variation of RSL signals with respect to TPD for 12 device modules +/-[20+(18*N*¥ Ä Z0)]a -40 40 ps Propagation delay variation of RSL signals with respect to TPD for 16 device modules +/-[24+(18*N*¥ Ä Z0)]a -50 50 ps a. Where : N =Number of RDRAM devices installed on the RIMM module ¥Ä Z0 = delta Z0% = (max Z0 - min Z0)/(min Z0) (max Z0 and min Z0 are obtained from the loaded (high impedance) impedance coupons of all RSL layers on the modules) 8 Rev.1.0 Dec.99 Direct Rambus RIMM™ with 128/144Mbit RDRAMs Preliminary AC Electrical Specifications for RIMM Modules RIMM Module Capacity: No. of 128/144Mb RDRAMs: 256/288MB 192/216MB 128/144MB 96/108MB 16 12 8 6 64/72MB 4 Symbol TPD V¥á /VIN VXF /VIN VXB /VIN RDC Rev. 1.0/Dec.99 Unit Parameter and Condition for -800 & -600 RIMM Module Max Max Max Max Max Propagation Delay, all RSL signals -800,-711 2.06 1.76 1.50 1.4 1.25 ns Propagation Delay, all RSL signals -600 2.10 1.76 1.60 1.40 1.25 ns Attenuation Limit -800,-711 25 20 16 14 12 % Attenuation Limit -600 21 18 10 9 8 % Forward crosstalk coefficient (300ps input rise time @ 20%-80%) -800,-711 8 6 4 3 2 % Forward crosstalk coefficient (300ps input rise time @ 20%-80%) -600 8 6 4 3 2 % Backward crosstalk coefficient (300ps input rise time @ 20%-80%) -800,-711 2.5 2.3 2.0 1.8 1.5 % Backward crosstalk coefficient (300ps input rise time @ 20%-80%) -600 2.5 2.3 2.0 1.8 1.5 % DC Resistance Limit -800,-711 1.2 1.1 0.8 0.7 0.6 §Ù DC Resistance Limit -600 1.2 1.1 0.8 0.7 0.6 §Ù 9 RIMM with 128/144Mb RDRAM Physical Dimensions The following defines the RIMM module dimensions. All units are in millimeters. The height of the module is 31.75mm. 133.35 ¾ ¡ 0.15 1.27 ¡¾ 0.1 3.0 ¾ ¡ 4.0 0.15 Top Area - N Components 31.75 R 2.0 17.78 Detail A A1 5.675 45.0 4.5 Detail B A92 11.5 27.5 55.175 ¡¾ Max. 7.37 Including Heat spreader 0.08 B92 B1 1.0 0.8 ¡¾ 0.1 2.99 ¡¾ 0.05 R 1.0 3.0 ¡¾ 0.1 2.0 Detail A ¡¾ 0.1 0.15 ¡¾ 0.1 Detail B Note 1.Tolerances on all dimensions ¡¾ 0.127mm unless otherwise specified. 2.Thickness(* Mark) includes plating and/or metallization. Figure 3: RIMM Module PCB Physical Description Module Weight The maximum RIMM Module weight is 75gm(2.625oz) with a center of mass 35mm (1.378 in.) upwards from bottom edge. 10 Rev.1.0 Dec.99 RIMM with 128/144Mb RDRAM Standard RIMM Module Marking The RIMM modules available from RIMM module manufacturers will be marked per Figure 4 below. This industry standard marking will help OEMs and users identify the Rambus RIMM modules for use in specific system application. This marking also assists OEMs or users to specify and verify if the correct RIMM I modules are installed in their system. In the diagram, a label is shown attached to the RIMM module’s heat spreader. This label contains suggested vendor specific information. Information contained on the label is specific to the RIMM module and provides RDRAM information without requiring removal of the RIMM module’s heat spreader. F HYMR16416H-745 G100 KOREA YWWDVXX S100 H J Label Field K A B C 128MB/ 8 R A M B U S 711-45 G D Description Marked Text E Unit A Module Memory capacity Number of 8-bit or 9-bit Mbytes of RDRAM storage in RIMM module 256MB, 192MB, 128MB, 96MB, 64MB MBytes B Number of DRDRAMs Number of RDRAM devices contained in the RIMM module /16, /12, /8, /6, /4 RDRAM devices C ECC support Indicates whether the RIMM module supports 8-bit (no ECC) or 9-bit (ECC) Bytes Blank = 8-bit Byte ECC = 9-bit Byte D Memory Speed Data transfer speed for RDRAM RIMM module 800, 711, 600 E tRAC Row Access Time (Optional field) -40, -45, -50, -53 F Gerber Version PCB Gerber file revision used on RIMM Module (Optional field) Rev 1.00 = G100 G SPD Version SPD Code Version (Optional field) Rev 1.00 = S100 H Country Country Area Korea I Vendor HME specific RIMM module Information Product Part No J Vendor HME specific Date code, Ass’y Vender YWWDV K Device Version Device Mask Revision(XX) E5,E6,E7 … … . MHz ns Figure 4: Standard RIMM Module Marking Rev.1.0 Dec.99 11 Serial Presence Detect Serial Presence Detect Contents The following table lists the contents of the serial presence detect device. Byte (Dec) Description 0 SPD revision level 1 Total number of bytes in the SPD 2 Option Entry Symbol Value (HEX) 2 02 256 08 Device type DRDRAM 01 3 Module type RIMM 01 4 Row address bits, Column address bits 9,6 96 72M 16d (4 bank bits) 84 128/144M 32d (5 bank bits) C5 9,6 04 5 05 Bank address bits and byte 5 6 Refresh Bank Bits 72M 128/144M 7 tREF - Refresh interval 32 8 Protocol version 2 9 Miscellaneous device configuration field -LP 1 tSCK tREF 20 02 - tDQS,Min no -LP 10 11 12 13 tRP-R,Min tRAS-R,Min tRCD-R,Min tRR-R,Min 01 -LP S28IECO - no -LP S28IECO 05 -40-800 8cycles tRP-R,Min 08 -45-800 8cycles tRP-R,Min 08 -45-711 8cycles tRP-R,Min 08 -53-600 8cycles tRP-R,Min 08 -40-800 20cycles tRAS-R,Min 14 -45-800 20cycles tRAS-R,Min 14 -45-711 20cycles tRAS-R,Min 14 -53-600 20cycles tRAS-R,Min 14 -40-800 8cycles tRCD-R,Min 08 -45-800 10cycles tRCD-R,Min 0A -45-711 8cycles tRCD-R,Min 08 -53-600 8cycles tRCD-R,Min 08 -40-800 8cycles tRR-R,Min 08 -45-800 8cycles tRR-R,Min 08 -45-711 8cycles tRR-R,Min 08 -53-600 8cycles tRR-R,Min 08 This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.0/Dec.99 1 Serial Presence Detect Byte (Dec) 14 15 16 17 Description tPP-R,Min Min tCYCLE for range A Max tCYCLE for range A tCDLY range for range A Entry Symbol Value (HEX) -40-800 8cycles tPP-R,Min 08 -45-800 8cycles tPP-R,Min 08 -45-711 8cycles tPP-R,Min 08 -53-600 8cycles tPP-R,Min 08 -40-800 2.50 ns tCYCLE 13 -45-800 2.50 ns tCYCLE 13 -45-711 2.80 ns tCYCLE 15 -53-600 3.33 ns tCYCLE 1A -40-800 3.83 ns tCYCLE 1E -45-800 3.83 ns tCYCLE 1E -45-711 3.83 ns tCYCLE 1E -53-600 3.83 ns tCYCLE 1E -40-800 5-9 tCYCLE 59 -45-800 5-9 tCYCLE 59 -45-711 5-9 tCYCLE 59 Option -53-600 18 tCYCLE 59 tCYCLE AA 0 Reserved 00 19 tCLS and tCAS range for range A Min tCYCLE for range B 20 Max tCYCLE for range B 0 Reserved 00 21 tCDLY range for range B 0 Reserved 00 22 tCLS and tCAS range for range B 0 Reserved 00 23 Min tCYCLE for range C 0 Reserved 00 24 Max tCYCLE for range C 0 Reserved 00 25 tCDLY range for range C 0 Reserved 00 26 tCLS and tCAS range for range C 0 Reserved 00 27 Min tCYCLE for range D 0 Reserved 00 28 Max tCYCLE for range D 0 Reserved 00 29 tCDLY range for range D 0 Reserved 00 30 tCLS and tCAS range for range D 0 Reserved 00 31 tPDNXA,Max 4§ Á tPDNXA,Max 04 32 tPDNXB,Max 9000 cylces tPDNXB,Max 8D 33 tNAPXA,Max 50 ns tNAPXA,Max 32 34 tNAPXB,Max 40 ns tNAPXB,Max 28 fIMIN fIMAX 11 35 fIMIN[11:8], fIMAX[11:8] -800 -711 -600 2 5-9 2tCYCLE for tCYCLE & t CYCLE 261MHz, 400MHz 261MHz, 357MHz 261MHz, 300MHz 11 11 Rev.1.0 Dec.99 Serial Presence Detect Byte (Dec) 36 37 Description fIMIN [7:0] fIMAX [7:0] Entry Symbol Value (HEX) -800 261MHz fIMIN 05 -711 261MHz 05 -600 261MHz 05 -800 400MHz -711 357MHz 65 -600 300MHz 2C Option fIMAX 90 38 Reserved 39 Max. time between Current Control 100 ms tCCTRL,MAX 64 40 Max. time between Temp. Calibration 100 ms tTEMP,MAX 64 41 Max. time between Temp. Calibration Enable and Command 150 tCYCLE tTCEN,MIN 96 42 Maximum RAS to Precharge time 64§ Á 40 43 Maximum time that a Device can stay in Nap Mode 10§ Á tRAS-R, MAX tNLIMIT, MAX 0A 44 ACTREFPT, PCHREFPT 6, 6 tCYCLE tCYCLE 66 45 CPCHREFPT_DC, RDREFPT_DC 5, 5 tCYCLE tCYCLE 55 46 RETREFPT_DC, WRREFPT_DC 5, 13 tCYCLE tCYCLE 5D 47~49 50 51 52 53 00 Reserved fRAS[11:8] fRAS[7:0] PMAX, HI, PMAX, LO, Tj (assumes active-write current is max, Tj = 100) Heat Spreader, Tplate (assumes heat spreader present, Tplate = 100) 00 -800 01 -711 01 01 -600 01 01 -800 90 -711 65 65 -600 2C 2C -800 0,0,(100-64) -711 0,0,(100-64) 24 -600 0,0,(100-64) 24 -800 1,(100-64) -711 1,(100-64) A4 -600 1,(100-64) A4 fRAS fRAS É ¡ É ¡ 01 90 24 A4 54 PSTBY,HI TBD mA - 55 PACTI,HI TBD mA - 56 PACTRW,HI TBD mA - 57 PSTBY,LO TBD mA - 58 PACTI,LO TBD mA - 59 PACTRW,LO TBD mA - 60 PNAP PRESA TBD mA - Reserved - - 61 Rev.1.0 Dec.99 3 Serial Presence Detect Byte (Dec) Option Entry Symbol Value (HEX) Reserved - - 62 PRESB 63 Checksum for locations 0 - 62 TBD Manufacturer ID code TBD - Module manufacturing location TBD - - 73 - 90 Module part number TBD - 91 - 92 Module revision code TBD - - 93 Module Manufacturing Year TBD - - 94 Module manufacturing week TBD - - 95 - 98 Module serial number Number of devices on module TBD - - 4D 4 Ea 04 6D 6 06 8D 8 08 12D 12 0C 16D 16 10 x16 16 x18 18 4D All 4 6D All 6 3F 8D All 8 FF 12D All 16 FF 16D All 16 FF 4D - 6D - 00 8D Bit 00 00 0F VDD, VTERM 10 FF 64 - 71 72 99 100 101 102 Number of devices on module Device enables Device enables Device Enables 12D All12 105 Module Vdd, Module Voltage Interface Level 16D 2.5V, All 1.8V 16 106 Module VDD tolerance 103~104 107-113 4 Description Bit - 10 12 Bit Bit 5% DC, 2% AC 0F 00 52 Reserved 114 CDLY0/1 for tCDLY = 3 - tCYCLE 00 115 CDLY0/1 for tCDLY = 4 2/0 tCYCLE 20 116 CDLY0/1 for tCDLY = 5 3/0 tCYCLE 30 117 CDLY0/1 for tCDLY = 6 3/1 tCYCLE 31 118 CDLY0/1 for tCDLY = 7 3/2 tCYCLE 32 119 CDLY0/1 for tCDLY = 8 4/2 tCYCLE 42 120 CDLY0/1 for tCDLY = 9 5/2 tCYCLE 52 Rev.1.0 Dec.99 Serial Presence Detect Byte (Dec) Description Option Entry Symbol Value (HEX) 121 CDLY0/1 for tCDLY = 10 - tCYCLE 00 122 CDLY0/1 for tCDLY = 11 - tCYCLE 00 123 CDLY0/1 for tCDLY = 12 - tCYCLE 00 124 CDLY0/1 for tCDLY = 13 - tCYCLE 00 125 CDLY0/1 for tCDLY = 14 - tCYCLE 00 126 CDLY0/1 for tCDLY = 15 - tCYCLE 00 127 Checksum for bytes 99 - 126 TBD TBD Undefined 128+ Open for Customer Use - - Undefined Min Max Unit 2.2 3.6 V fSCL = 100 KHz 5.0 mA EEPROM Component AC and DC Characteristics Symbol Parameter Test Condition SVDD power supply ISVdd Active power supply current ISVdd1 standby current VIN = GND or SVDD 100 §Ë ISLI Input leakage current VIN = GND or SVDD 10 §Ë ISLO Output leakage current VOUT = GND or SVDD 10 §Ë VSIL Input Low Voltage -0.3 SVDD x 0.3 V VSIH Input High Voltage SVDD x 0.7 SVDD + 0.3 V VSOL Output Low Voltage 0.4 V Rev.1.0 Dec.99 ISOL = 3.0 mA 5 Serial Presence Detect EEPROM Component AC Timing Parameters Symbol fSCL T1 Parameter and Conditions Min Max Unit SCL frequency 100 KHz Noise suppression time constant for SCL, SDA 100 ns 0.7 §Á tSAA SCL Low to SDA Data Out Valid 0.3 tSBUF Time bus must be free before a new transmission can start 6.7 §Á Start Condition Hold Time 4.5 §Á tSLOW Clock Low Time 6.7 §Á tSHIGH Clock High Time 4.5 §Á tSSU:STA Start Condition Setup Time 6.7 §Á tSHD:DAT Data In Hold Time 0 §Á tSSU:DAT Data In Setup Time 500 ns tSHD:STA tSR SDA and SCL Rise Time 1 §Á tSF SDA and SCL Fall Time 300 ns Stop Condition Setup Time 6.7 §Á tSDH Data Out Hold Time 300 ns tSWR EEPROM Write Cycle Time tSSU:STO 15 ms SPD Timing Diagram 6 Rev.1.0 Dec.99