HYS64D128020GBDL-[6/7]-A DDR-SDRAM SO-DIMM Modules 2.5V 200Pin DDR-I SDRAM Small Outline Modules 1GB Module PC1600, PC2100 & PC2700 Preliminary Data Sheet V0.6, 2003-01-07 • 200-pin Unbuffered 8-Byte Dual-In-Line DDR-I SDRAM non-parity Small Outline Modules • Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave) • 128M x 64 organization with two memory banks • Auto Refresh (CBR) and Self Refresh • JEDEC standard Double Data Rate Synchronous DRAMs (DDR-I SDRAM) • Serial Presence Detect with E2PROM • Single +2.5V (± 0.2V) power supply • Jedec standard form factor: 67.60mm ´ 31.75mm ´ 3.80mm • All inputs and outputs SSTL_2 compatible • Uses eight 1Gbit DDR-I SDRAM components (2x 64Mb x8) made of stacked 512Mb dies in P-TFBGA package. • Gold plated contacts Performance -6 -7 Unit Component Speed Grade DDR333 DDR266A Module Speed Grade PC2700 PC2100 fCK Clock Frequency (max.) @ CL = 2.5 166 143 MHz fCK Clock Frequency (max.) @ CL = 2 133 133 MHz The HYS64D128020GBDL are industry standard 200-pin 8-byte Small Outline Dual in-line Memory Modules (DIMMs) organized as 128M x 64 in two memory banks. The memory array is designed with Double Data Rate Synchronous DRAMs. A variety of decoupling capacitors are mounted on the PC board. The DIMMs feature serial presence detect based on a serial E2PROM device using the 2-pin I2C protocol. The first 128 bytes are programmed with configuration data and the second 128 bytes are available to the customer. INFINEON Technologies AG 1 V0.6, 2003-01-07 HYS64D128020GBDL-[6/7]-A DDR-SDRAM SO-DIMM Modules Ordering Information Type Compliance Code HYS64D128020GBDL-6-A PC2700S-2533-0-Z HYS64D128020GBDL-7-A PC2100S-2033-0-Z Note: Description SDRAM Technology 1GB SO-DIMM w/ 2 banks 512Mbit Stacked Die in a FBGA All part numbers end with a place code, designating the silicon die revision. Reference information available on request. Example: HYS 64D128020GBDL-8-A, indicating Rev.A die is used for DDR-SDRAM components. The Compliance Code which is printed on the module labels describes the speed sort class (“e.g. PC2100”), the module type (“S”), the latencies (e.g. 2033 means CAS latency = 2.0, RCD latency = 3 and row precharge latency = 3), the JEDEC SPD Revision (“0”) and the Raw Card used on this DIMM (“Z”). Pin Definitions and Functions Pin Name Pin Function Pin Name Pin Function A0 - A12 Address Inputs CS0, CS1 Chip Selects BA0, BA1 Bank Selects VDD Power (+ 2.5 V) DQ0 - DQ63 Data Input/Output VSS Ground RAS Row Address Strobe VDDQ I/O Driver power supply CAS Column Address Strobe VDDID VDD Indentification flag WE Read/Write Input VREF I/O reference supply CKE0 - CKE1 Clock Enable VDDSPD Serial EEPROM power supply DQS0 - DQS8 SDRAM low data strobes SCL Serial bus clock CLK0 - CLK1, SDRAM clock (positive lines) SDA Serial bus data line CLK0 - CLK1 SDRAM clock (negative lines) SA0 - SA2 slave address select DM0 - DM8 data masks NC no connect DQS0 - DQS8 data strobes DU Dont use, reserved Address Format Density Organization Memory Banks SDRAMs # of SDRAMs SDRAM density 1024 MB 128M ´ 64 2 64M x 8 16 512 Mbit INFINEON Technologies AG 2 # of row/ Refresh bank/ column bits 13/2/11 8k Period Interval 64 ms 7.8 ms V0.6, 2003-01-07 HYS64D128020GBDL-[6/7]-A DDR-SDRAM SO-DIMM Modules Pin Configuration Pin # Front Side Pin # Back Side 1 3 VREF 2 VREF 51 VSS VSS 4 VSS 53 DQ19 5 DQ0 6 DQ4 55 DQ24 56 DQ28 105 A7 106 A6 155 VDD 156 VDD 7 DQ1 8 DQ5 57 VDD 58 VDD 107 A5 108 A4 157 VDD 158 CK1 9 VDD 10 VDD 59 DQ25 60 DQ29 109 A3 110 A2 159 VSS 160 CK1 11 DQS0 12 DM0 61 DQS3 62 DM3 111 A1 112 A0 161 VSS 162 VSS 13 DQ2 14 DQ6 63 VSS 64 VSS 113 VDD 114 VDD 15 VSS 16 VSS 65 DQ26 66 DQ30 115 A10/AP 116 BA1 165 DQ49 166 DQ53 17 DQ3 18 DQ7 67 DQ27 68 DQ31 117 BA0 118 RAS 167 168 VDD 19 DQ8 20 DQ12 69 VDD 70 VDD 119 WE 120 CAS 169 DQS6 170 DM6 21 VDD 22 VDD 71 (CB0) 72 (CB4) 121 CS0 122 CS1 171 DQ50 172 DQ54 23 DQ9 24 DQ13 73 (CB1) 74 (CB5) 123 DU 124 DU 173 75 VSS 76 VSS 125 VSS 126 VSS 175 DQ51 176 DQ55 25 DQS1 26 DM1 27 VSS 28 Front Side Back Side Pin # 52 VSS 101 A9 102 A8 151 DQ42 152 DQ46 54 DQ23 103 VSS 104 VSS 153 DQ43 154 DQ47 Pin # Front Side Pin # Back Side Pin # Front Side Pin # Back Side 163 DQ48 164 DQ52 VDD VSS 174 VSS 77 (DQS8) 78 (DM8) 127 DQ32 128 DQ36 177 DQ56 178 DQ60 29 DQ10 30 DQ14 79 (CB2) 80 (CB6) 129 DQ33 130 DQ37 179 31 DQ11 32 DQ15 81 VDD 82 VDD 131 132 VDD 181 DQ57 182 DQ61 33 VDD 34 VDD 83 (CB3) 84 (CB7) 133 DQS4 134 DM4 183 DQS7 184 DM7 35 CK0 36 VDD 85 DU 86 DU 135 DQ34 136 DQ38 185 VSS 37 CK0 38 VSS 87 VSS 88 VSS 137 187 DQ58 188 DQ62 VSS 40 VSS 39 VSS Pin # VDD VSS 138 VSS VDD VSS 180 186 VDD 89 (CK2) 90 VSS 139 DQ35 130 DQ39 189 DQ59 190 DQ63 41 DQ16 42 DQ20 91 (CK2) 92 VDD 141 DQ40 142 DQ44 191 VDD 192 VDD 43 DQ17 44 DQ21 93 VDD 94 VDD 143 VDD 193 SDA 194 SA0 45 VDD 145 DQ41 146 DQ45 195 SCL 196 SA1 VDD 144 46 VDD 95 CKE1 96 CKE0 47 DQS2 48 DM2 97 DU 98 DU 147 DQS5 148 DM5 197 Vddspd 198 SA2 DQ18 50 DQ22 99 A12 100 A11 149 VSS 199 Vddid 200 DU 49 VSS 150 back side INFINEON Technologies 3 pin 199 pin 39 pin 41 pin 40 pin 42 front side pin 200 pin 1 pin 2 Note: Pins 71, 72, 73, 74, 77, 78, 79, 80, 83, 84, 89 and 91 are reserved for x72 variants of this module and are not used on the x64 versions. Pin 86 is reserved for a registered variant of this module and is not used on the unbuffered version V0.6, 2003-01-07 HYS64D128020GBDL-[6/7]-A DDR-SDRAM SO-DIMM Modules CS0 CS1 CS0 DQS0 DM0 DQ[7:0] DM2 DQ[47:40] A0-A12, BA0, BA1 RAS, CAS, WE CKE0 CKE1 DM7 D3 DM DQ[63:56] 8x D7 DQ[7:0] Serial SPD (256wordx8bit) D0 - D7 D0 - D7 D0 - D7 D0 - D7 SA0 SA1 SA2 VDD D0 - D7 D0 - D7 VSS VDDID D0 - D7, SPD D0 - D7, SPD open CS1 DQS A0 A1 A2 SPD VDDSPD VREF D6 DQ[7:0] CS0 DQS7 DQ[7:0] 8x 8x CS1 DM DM3 DM DQ[55:48] DQS CS1 DQS DM6 D2 CS0 D5 DQ[7:0] CS0 DQS6 DQ[7:0] DQS3 8x CS1 DM 8x CS1 DM DM5 D1 CS0 DQ[31:24] CS0 DQS DQS2 D4 DQ[7:0] DQS DQS5 DQ[7:0] 8x 8x CS1 DM DM1 DM DQ[39:32] DQS CS1 DQS DM4 D0 DQ[7:0] CS0 DQ[23:16] CS0 DQS4 DM 8x DQS1 DQ[15:8] CS1 DQS SCL SDA WP CLK0 / CLK0 CLK1 / CLK1 SCL SDA 8 Loads 8 Loads Note 1. DQ wiring may differ than describes in this drawing, however DQ/DM/DQS relationship must be maintained as shown. 2. All resistors are 22 Ohm. Block Diagram: Two Banks 128M x 64 DDR-SDRAM SO-DIMM Modules using x8 Organized SDRAMs INFINEON Technologies AG 4 V0.6, 2003-01-07 HYS64D128020GBDL-[6/7]-A DDR-SDRAM SO-DIMM Modules Absolute Maximum Ratings Parameter Symbol Limit Values Unit min. max. Input / Output voltage relative to VSS VIN, VOUT -0.5 3.6 Power supply voltage on VDD/VDDQ to VSS VDD, VDDQ -0.5 3.6 V V Storage temperature range TSTG -55 +150 o Power dissipation (per SDRAM component) PD – 1 W Data out current (short circuit) IOS – 50 mA C Permanent device damage may occur if “Absolute Maximum Ratings” are exceeded. Functional operation should be restricted to recommended operation conditions. Exposure to higher than recommended voltage for extended periods of time affect device reliability Supply Voltage Levels Parameter Symbol Limit Values Unit min. nom. max. Notes Device Supply Voltage VDD 2.3 2.5 2.7 V Output Supply Voltage VDDQ 2.3 2.5 2.7 V Input Reference Voltage VREF 0.49 x VDDQ 0.5 x VDDQ 0.51 x VDDQ V 2 Termination Voltage VTT VREF - 0.04 VREF VREF + 0.04 V 3 EEPROM supply voltage VDDSPD 2.3 2.5 3.6 V 1 1 Under all conditions, VDDQ must be less than or equal to VDD 2 Peak to peak AC noise on VREF may not exceed ± 2% VREF (DC). VREF is also expected to track noise variations in VDDQ. 3 VTT of the transmitting device must track VREF of the receiving device. DC Operating Conditions (SSTL_2 Inputs) (VDDQ = 2.5 V, TA = 70 °C, Voltage Referenced to VSS) Parameter Symbol Limit Values min. Unit Notes max. DC Input Logic High VIH (DC) VREF + 0.15 VDDQ + 0.3 V DC Input Logic Low VIL (DC) -0.30 VREF - 0.15 V Input Leakage Current IIL -5 5 Output Leakage Current IOL -5 5 mA mA 1 1 2 1) The relationship between the VDDQ of the driving device and the VREF of the receiving device is what determines noise margins. However, in the case of VIH (max) (input overdrive), it is the VDDQ of the receiving device that is referenced. In the case where a device is implemented such that it supports SSTL_2 inputs but has no SSTL_2 outputs (such as a translator), and therefore no VDDQ supply voltage connection, inputs must tolerate input overdrive to 3.0 V (High corner VDDQ + 300 mV). 2) For any pin under test input of 0 V £ VIN £ VDDQ + 0.3 V. Values are shown per DDR-SDRAM component. INFINEON Technologies 5 V0.6, 2003-01-07 HYS64D128020GBDL-[6/7]-A DDR-SDRAM SO-DIMM Modules Operating, Standby and Refresh Currents 1GB, 2 banks -6 PC2700S-2533 Symbol Parameter/Condition 1GB, 2 banks -7 PC2100S-2033 Unit Notes TYP MAX TYP MAX IDD0 Operating Current: one bank; active / precharge; tRC = tRC MIN; DQ, DM, and DQS inputs changing once per clock cycle; address and control inputs changing once every two clock cycles 1360 1560 1208 1400 mA 1 IDD1 Operating Current: one bank; active/read/precharge; burst length 4; Refer to the following page for detailed test conditions. 1552 1760 1416 1600 mA 1, 3 IDD2P Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE <= VIL MAX 120 176 112 160 mA 2 IDD2F Precharge Floating Standby Current: /CS >= VIH MIN, all banks idle; CKE >= VIH MIN; address and other control inputs changing once per clock cycle, VIN = VREF for DQ, DQS and DM. 576 656 496 560 mA 2 440 528 384 448 mA 2 256 320 224 288 mA 2 Active Standby Current: one bank active; CS >= VIH MIN; CKE >= VIH MIN; IDD3N tRC = tRAS MAX; DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 688 800 608 720 mA 2 Operating Current: one bank active; burst length 2; reads; continuous burst; address and IDD4R control inputs changing once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR200 and DDR266(A), CL=3 for DDR333 and DDR400; IOUT = 0mA 1680 1960 1424 1680 mA 1, 3 Operating Current: one bank active; Burst = 2; writes; continuous burst; address and IDD4W control inputs changing once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR200 and DDR266(A), CL=3 for DDR333 and DDR400 1600 1880 1368 1600 mA 1 2328 2600 2200 2480 mA 1 40 56 40 56 mA 3056 3440 2536 3000 mA Precharge Quiet Standby Current: /CS >= VIH MIN, all banks idle; IDD2Q CKE >= VIH MIN; address and other control inputs stable at >= VIH MIN or <= VIL MAX; VIN = VREF for DQ, DQS and DM. IDD3P Active Power-Down Standby Current: one bank active; power-down mode; CKE <= VIL MAX; VIN = VREF for DQ, DQS and DM. IDD5 Auto-Refresh Current: tRC = tRFC MIN, distributed refresh IDD6 Self-Refresh Current: CKE <= 0.2V; external clock on IDD7 Operating Current: four bank; four bank interleaving with burst length 4; Refer to the following page for detailed test conditions. 4 1, 3 1. The module IDD values are calculated from the component IDD datasheet values as: IDDx[component] * m + IDD3N[component] * n with m, n number of components of bank 1 and 2; n=0 for 1 bank modules 2. The module IDD values are calculated from the component IDD datasheet values as: IDDx[component] * (m + n) 3. DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load conditions 4. Test condition for typical values : VDD = 2.5V ,Ta = 25°C, test condition for maximum values: test limit at VDD = 2.7V ,Ta = 10°C INFINEON Technologies AG 6 V0.6, 2003-01-07 HYS64D128020GBDL-[6/7]-A DDR-SDRAM SO-DIMM Modules Electrical Characteristics & AC Timing for DDR-I components (for reference only) (0 °C £ TA £ 70 °C; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V) Symbol DDR333 -6 Parameter DDR266A -7 Unit Notes + 0.75 ns 1-4 + 0.75 ns 1-4 0.45 0.55 tCK 1-4 0.45 0.55 min. max. min. max. DQ output access time from CK/CK - 0.7 + 0.7 - 0.75 DQS output access time from CK/CK - 0.6 + 0.6 - 0.75 tCH CK high-level width 0.45 0.55 tCL CK low-level width 0.45 0.55 tHP Clock Half Period tAC tDQSCK tCK tCK Clock cycle time tCK 1-4 min (tCL, tCH) min (tCL, tCH) ns 1-4 CL = 2.5 6 12 7 12 ns 1-4 CL = 2.0 7.5 12 7.5 12 ns 1-4 1-4 tDH DQ and DM input hold time 0.45 0.5 ns tDS DQ and DM input setup time 0.45 0.5 ns 1-4 tIPW Control and Addr. input pulse width (each input) 2.2 2.2 ns 1, 10 tDIPW DQ and DM input pulse width (each input) 1.75 1.75 ns 1-4, 11 tHZ Data-out high-impedence time from CK/CK - 0.7 + 0.7 - 0.75 + 0.75 ns 1-4, 5 tLZ 1-4, 5 Data-out low-impedence time from CK/CK - 0.7 + 0.7 - 0.75 + 0.75 ns tDQSS Write command to 1st DQS latching transition 0.75 1.25 0.75 1.25 tCK 1-4 tDQSQ DQS-DQ skew (for DQS & associated DQ signals) + 0.5 ns 1-4 tQHS Data hold skew factor tQH Data Output hold time from DQS tDQSL,H + 0.40 + 0.50 + 0.75 tHP-tQHS tHP-tQHS ns 1-4 ns 1-4 DQS input low (high) pulse width (write cycle) 0.35 0.35 tCK 1-4 tDSS DQS falling edge to CK setup time (write cycle) 0.2 0.2 tCK 1-4 tDSH DQS falling edge hold time from CK (write cycle) 0.2 0.2 tCK 1-4 tMRD Mode register set command cycle time 2 2 tCK 1-4 tWPRES Write preamble setup time 0 0 ns 1-4, 7 tWPST Write postamble 0.40 tCK 1-4, 6 tWPRE Write preamble 0.25 0.25 tCK 1-4 0.75 0.9 ns tIS tIH Address and control input setup time Address and control input hold time fast slew rate 0.60 0.40 0.60 slow slew rate 0.8 1.0 ns fast slew rate 0.75 0.9 ns slow slew rate 0.8 1.0 2-4, 10,11 ns tRPRE Read preamble 0.9 1.1 0.9 1.1 tCK 1-4 tRPST Read postamble 0.40 0.60 0.40 0.60 tCK 1-4 tRAS Active to Precharge command 42 70,000 45 120,000 ns 1-4 tRC Active to Active/Auto-refresh command period 60 65 ns 1-4 tRFC Auto-refresh to Active/Auto-refresh command period 72 75 ns 1-4 tRCD Active to Read or Write delay 18 20 ns 1-4 tRP Precharge command period 18 20 ns 1-4 tRRD Active bank A to Active bank B command 12 15 ns 1-4 tWR Write recovery time 15 15 ns 1-4 tDAL Auto precharge write recovery + precharge time tCK 1-4,9 INFINEON Technologies (twr/tck) + (trp/tck) 7 V0.6, 2003-01-07 HYS64D128020GBDL-[6/7]-A DDR-SDRAM SO-DIMM Modules Symbol DDR333 -6 Parameter max. DDR266A -7 Notes tCK 1-4 tWTR Internal write to read command delay tXSNR Exit self-refresh to non-read command 75 75 ns 1-4 tXSRD Exit self-refresh to read command 200 200 tCK 1-4 tREFI Average Periodic Refresh Interval ms 1-4, 8 7.8 min. 1 Unit min. 1 max. 7.8 1. Input slew rate >=1V/ns for DDR266 & DDR333 and = 1V/ns for DDR200. 2. The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals other than CK/CK, is VREF. CK/CK slew rate are >= 1.0 V/ns. 3. Inputs are not recognized as valid until VREF stabilizes. 4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (Note 3) is VTT. 5. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ). 6. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 7. The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS. 8. A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device. 9. For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time. 10. These parameters guarantee device timing, but they are not necessarily tested on each device 11. Fast slew rate >= 1.0 V/ns , slow slew rate >= 0.5 V/ns and < 1V/ns for command/address and CK & CK slew rate >1.0 V/ ns, measured between VOH(ac) and VOL(ac) INFINEON Technologies AG 8 V0.6, 2003-01-07 HYS64D128020GBDL-[6/7]-A DDR-SDRAM SO-DIMM Modules SPD Codes Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Description SPD Entry Value Number of SPD Bytes 128 Total Bytes in Serial PD 256 Memory Type DDR-SDRAM Number of Row Addresses 13 Number of Column Addresses 11 Number of DIMM Banks 2 Module Data Width x64 Module Data Width (cont’d) 0 Module Interface Levels SSTL_2.5 SDRAM Cycle Time at CL = 2.5 7ns, 6ns SDRAM Access Time from Clock at CL = 2.5 0.75ns, 0.6ns DIMM Config non-ECC Refresh Rate/Type Self-Refresh 7.8ms SDRAM Width, Primary x8 Error Checking SDRAM Data Width na Minimum Clock Delay for Back-to-Back Random Column Address tCCD = 1 CLK 16 17 18 19 20 21 22 Burst Length Supported 2, 4 & 8 Number of SDRAM Banks 4 Supported CAS Latencies CAS latency = 2 & 2.5 CS Latencies CS latency = 0 WE Latencies Write latency = 1 SDRAM DIMM Module Attributes unbuffered SDRAM Device Attributes: General 23 24 25 26 27 28 29 30 31 32 33 34 35 36-40 41 42 43 44 45 46-61 62 Min. Clock Cycle Time at CAS Latency = 2 Conc. AP weak driver 7.5ns Max. Data Access Time from Clock for CL = 2 0.75ns, 0.7ns Minimum Clock Cycle Time at CL = 1.5 not supported PC2100 70 75 20ns, 18ns Minimum Row Active to Row Active Delay tRRD 15ns, 12ns Minimum RAS to CAS Delay tRCD 20ns, 18ns Minimum RAS Pulse Width tRAS 45ns, 42ns Module Bank Density (per bank) 512 MByte Addr. and Command Setup Time 0.9 ns, 0.75ns Addr. and Command Hold Time 0.9 ns, 0.75ns Data Input Setup Time 0.5ns, 0.45 ns Data Input Hold Time 0.5ns, 0.45 ns Superset Information – Minimum Core Cycle Time tRC 65 ns, 60 ns Min. Auto Refresh Cmd Cycle Time tRFC 75ns, 72 ns Maximum Clock Cycle Time tck 12 ns Max. DQS-DQ Skew tDQSQ 0.5 ns, 0.4 ns X-Factor tQHS 0.75ns, 0.5 ns Superset Information (may be used in future) SPD Revision INFINEON Technologies Revision 0.0 9 60 70 00 82 08 00 01 0E 04 0C 01 02 20 C1 75 75 75 70 00 00 Maximum Data Access Time from Clock at CL = 1.5 not supported Minimum Row Precharge Time PC2700 80 08 07 0D 0B 02 40 00 04 50 3C 50 2D 48 30 48 2A 80 90 90 50 50 75 75 45 45 00 41 4B 3C 48 30 32 75 28 50 00 00 V0.6, 2003-01-07 HYS64D128020GBDL-[6/7]-A DDR-SDRAM SO-DIMM Modules Byte# 63 64 65-71 72 73-90 91-92 93-94 95-98 99-127 128-255 Description SPD Entry Value Checksum for Bytes 0 - 62 – Manufacturers JEDEC ID – Manufacturer PC2100 F5 PC2700 39 C1 INFINEO(N) Assembly Manufacturing Location Module Part Number Module Revision Code Module Manufacturing Date Module Serial Number Superset Information Open for Customer Use INFINEON Technologies AG 10 V0.6, 2003-01-07 HYS64D128020GBDL-[6/7]-A DDR-SDRAM SO-DIMM Modules Package Outlines DDR-SDRAM SO-DIMM Modules 67.6 ± 0.15 3.8 max. 31.75 ± 0.13 63.6 1 2.15 39 11.4 11.55 2.45 1± 1 2.45 47.4 4.2 1.0 40 0. 199 2.15 42 200 6 4 2 41 20 1.8 4 0.2 - 0.25 0.15 Detail of Chamfer 2.55 Detail of Contacts 0.2 - 0.45 0.15 0.6 L-DIM-200-20 INFINEON Technologies AG 11 V0.6, 2003-01-07