INFINEON HYS64D16020GDL-7-A

D a t a S h e e t , R e v . 1 . 0 2 , J a n . 2 00 4
H Y S 6 4 D 1 6 0 2 0 G D ( L ) - [ 7 / 8 ] -A
U n b u f f e r e d D D R S D R AM S O M o d u l e s
DDR SDRAM SO
M e m or y P r o du c t s
N e v e r
s t o p
t h i n k i n g .
Edition 2004-01
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
Edition
2004-01 Germany
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Published
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D a t a S h e e t , R e v . 1 . 0 2 , J a n . 2 00 4
D ata
Sh ee t, Re v . 1 .0 2, J an . 2 00 4
H Y S 6 4 D 1 6 0 2 0 G D ( L ) - [ 7 / 8 ] -A
U n b u f f e r e d D D R S D R AM S O M o d u l e s
DDR SDRAM SO
M
Pdu
r ocdt su c t s
M eemm
oroyr y
Pro
N e v e r
s t o p
t h i n k i n g .
HYS64D16020GD(L)-[7/8]-A
Unbuffered DDR SDRAM SO Modules
HYS64D16020GD(L)-[7/8]-A
Revision History:
Rev. 1.02
Previous Version:
Rev. 1.01
2004-01
Page
Subjects (major changes since last revision)
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Data Sheet
4
Rev. 1.02, 2004-01
HYS64D16020GD(L)-[7/8]-A
Unbuffered DDR SDRAM SO Modules
Table of Contents
1
1.1
1.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3
3.1
3.2
3.3
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current Specification and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
SPD Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Data Sheet
5
12
12
14
16
Rev. 1.02, 2004-01
11042003-YIV7-VK6M
HYS64D16020GD(L)-[7/8]-A
Unbuffered DDR SDRAM SO Modules
Overview
1
Overview
1.1
Features
•
•
•
•
•
•
•
•
•
•
•
•
200-pin Unbuffered 8-Byte Dual-In-Line DDR SDRAM non-parity Small Outline Modules
One rank 16M x 64 organization
JEDEC standard Double Data Rate Synchronous DRAMs (DDR SDRAM)
Single + 2.5 V (± 0.2 V) power supply
Built with 128 Mbit DDR SDRAMs organised as x 16 in 66-Lead TSOPII packages
Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave)
Auto Refresh (CBR) and Self Refresh
All inputs and outputs SSTL_2 compatible
Serial Presence Detect with E2PROM
JEDEC standard form factor: 67.60 mm × 31.75 mm × 3.00 / 3.80 mm
JEDEC standard reference layout Raw Card A
Gold plated contacts
Table 1
Performance -8/-7
Part Number Speed Code
Speed Grade
max. Clock Frequency
–7
Unit
Component
DDR266A
DDR200
—
Module
PC2100-2033
PC1600-2022
—
143
125
MHz
133
100
MHz
@CL2.5
@CL2
1.2
–8
fCK2.5
fCK2
Description
The HYS64/72D16000GU and HYS64/72D32020GU are industry standard 184-pin 8-byte Dual in-line Memory
Modules (DIMMs) organized as 16M x 64 and 32M × 64 for non-parity and 16M x 72 and 32M x 72 for ECC main
memory applications. The memory array is designed with 128Mbit Double Data Rate Synchronous DRAMs. A
variety of decoupling capacitors are mounted on the PC board. The DIMMs feature serial presence detect based
on a serial E2PROM device using the 2-pin I2C protocol. The first 128 bytes are programmed with configuration
data and the second 128 bytes are available to the customer.
Data Sheet
6
Rev. 1.02, 2004-01
11042003-YIV7-VK6M
HYS64D16020GD(L)-[7/8]-A
Unbuffered DDR SDRAM SO Modules
Overview
Table 2
Ordering Information
Type
Compliance Code
Description
SDRAM Technology
PC2100-20330-A
two ranks 128 MB SO-DIMM
128 Mbit (x16)
PC1600-20220-A
two ranks 128 MB SO-DIMM
128 Mbit (x16)
PC2100 (CL=2):
HYS64D16020GDL-7-A
PC1600 (CL=2):
HYS64D16020GDL-8-A
Note: All part numbers end with a place code, designating the silicon-die revision. Reference information available
on request. Example: HYS 64D32020GDL-8-B, indicating Rev.B die are used for DDR-SDRAM
components. The Compliance Code which is printed on the module labels describes the speed sort class
(“for example PC2100”), the latencies (for example 20330 means CAS latency = 2, trcd latency = 3 and trp
latency = 3) and the Raw Card used for this module
Data Sheet
7
Rev. 1.02, 2004-01
11042003-YIV7-VK6M
HYS64D16020GD(L)-[7/8]-A
Unbuffered DDR SDRAM SO Modules
Pin Configuration
2
Pin Configuration
Table 3
Pin Definitions and Functions
Symbol
Type1)
Function
A0 - A11
I
Address Inputs
BA0, BA1
I
Bank Selects
DQ0 - DQ63
I/O
Data Input/Output
CB0 - CB7
I/O
Check Bits (×72 organization only)
RAS, CAS, WE
I
Command Inputs
CKE0 - CKE1
I
Clock Enable
DQS0 - DQS8
I/O
SDRAM low data strobes
CK0 - CK2,
I
SDRAM clock (positive lines)
CK0 - CK2
I
SDRAM clock (negative lines)
DM0 - DM8
DQS9 - DQS17
I
I/O
SDRAM low data mask/
high data strobes
S0, S1
I
Chip Selects for Rank0 and Rank1
VDD
PWR
Power (+2.5 V)
VSS
GND
Ground
VDDQ
PWR
I/O Driver power supply
VDDID
PWR
VDD Indentification flag
VREF
AI
I/O reference supply
VDDSPD
PWR
Serial EEPROM power supply
SCL
I
Serial bus clock
SDA
I/O
Serial bus data line
SA0 - SA2
I
slave address select
NC
NC
Not Connected
1) I: Input; O: Output; I/O: bidirectional In-/Output; AI: Analog Input; PWR: Power Supply; GND: Signal Ground; NC: Not
Connected
Note: S1 and CKE1 are used on two rank modules only
Data Sheet
8
Rev. 1.02, 2004-01
11042003-YIV7-VK6M
HYS64D16020GD(L)-[7/8]-A
Unbuffered DDR SDRAM SO Modules
Pin Configuration
Table 4
Pin Configuration
Frontside
Backside
PIN#
Symbol
PIN#
Symbol
PIN#
Symbol
PIN#
Symbol
1
VREF
48
A0
93
VSS
140
NC /
DM8/DQS17
2
DQ0
49
NC / CB2
94
DQ4
141
A10
3
VSS
50
VSS
95
DQ5
142
NC / CB6
4
DQ1
51
NC / CB3
96
VDDQD
143
VDDQD
5
DQS0
52
BA1
97
DM0/DQS9
144
NC / CB7
6
DQ2
98
DQ6
7
VDD
99
DQ7
8
DQ3
53
DQ32
100
VSS
145
VSS
9
NC
54
VDDQ
101
NC
146
DQ36
10
NC
55
DQ33
102
NC
147
DQ37
11
VSS
56
DQS4
103
NC
148
VDD
12
DQ8
57
DQ34
104
VDDQ
149
DM4/DQS13
Key
Key
13
DQ9
58
VSS
105
DQ12
150
DQ38
14
DQS1
59
BA0
106
DQ13
151
DQ39
15
VDDQ
60
DQ35
107
DM1/DQS10
152
VSS
16
CK1
61
DQ40
108
VDD
153
DQ44
17
CK1
62
VDDQ
109
DQ14
154
RAS
18
VSS
63
WE
110
DQ15
155
DQ45
19
DQ10
64
DQ41
111
CKE1
156
VDDQ
20
DQ11
65
CAS
112
VDDQ
157
S0
21
CKE0
66
VSS
113
NC (BA2)
158
S1
22
VDDQ
67
DQS5
114
DQ20
159
DM5/DQS14
23
DQ16
68
DQ42
115
NC / A12
160
VSS
24
DQ17
69
DQ43
116
VSS
161
DQ46
25
DQS2
70
VDD
117
DQ21
162
DQ47
26
VSS
71
NC
118
A11
163
NC
27
A9
72
DQ48
119
DM2/DQS11
164
VDDQ
28
DQ18
73
DQ49
120
VDD
165
DQ52
29
A7
74
VSS
121
DQ22
166
DQ53
30
VDDQ
75
CK2
122
A8
167
NC (A13)
31
DQ19
76
CK2
123
DQ23
168
VDD
32
A5
77
VDDQ
124
VSS
169
DM6/DQS15
33
DQ24
78
DQS6
125
A6
170
DQ54
34
VSS
79
DQ50
126
DQ28
171
DQ55
35
DQ25
80
DQ51
127
DQ29
172
VDDQ
36
DQS3
81
128
VDDQ
173
NC
37
A4
82
VSS
VDDID
129
DM3/DQS12
174
DQ60
38
VDD
83
DQ56
130
A3
175
DQ61
39
DQ26
84
DQ57
131
DQ30
176
VSS
Data Sheet
9
Rev. 1.02, 2004-01
11042003-YIV7-VK6M
HYS64D16020GD(L)-[7/8]-A
Unbuffered DDR SDRAM SO Modules
Pin Configuration
Table 4
Pin Configuration (cont’d)
Frontside
Backside
PIN#
Symbol
PIN#
Symbol
PIN#
Symbol
PIN#
Symbol
40
DQ27
85
VDD
132
VSS
177
DM7/DQS16
41
A2
86
DQS7
133
DQ31
178
DQ62
42
VSS
87
DQ58
134
NC / CB4
179
DQ63
43
A1
88
DQ59
135
NC / CB5
180
VDDQ
44
NC / CB0
89
VSS
136
VDDQ
181
SA0
45
NC / CB1
90
NC
137
CK0
182
SA1
46
VDD
91
SDA
138
CK0
183
SA2
47
NC / DQS8
92
SCL
139
VSS
184
VDDSPD
Note: Pins 44, 45, 47, 49, 51, 134, 135, 140 and 144 are NC (“not connected”) on ×64 organised non-ECC
modules.
Table 5
Address Format
Refresh
Density Organization Memory SDRAMs # of
SDRAM # of
Ranks
SDRAMs density row/rank/
columns
bits
128 MB
16M × 64
2
8M × 16
8
128Mbit 12/2/9
4K
Period Interval
64 ms
15.6 µs
back side
Figure 1
Data Sheet
pin 199
pin 39
pin 41
pin 40
pin 42
front side
pin 200
pin 1
pin 2
Note: Pins 71, 72, 73, 74, 77, 78, 79, 80, 83, 84, 89 and 91 are reserved for x72 variants of this module and are
not used on the x64 versions. Pin 86 is reserved for a registered variant of this module and is not used on
the unbuffered version
Pin Configuration
10
Rev. 1.02, 2004-01
11042003-YIV7-VK6M
HYS64D16020GD(L)-[7/8]-A
Unbuffered DDR SDRAM SO Modules
Pin Configuration
S1
S0
DQS0
DM0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS1
DM1
S
LDQ S
LDM
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5 D0
6
7
UDQS
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
S
LDQ S
LD M
S
LDQS
LD M
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
UDQS
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
DQS3
DM3
0
1
2
3
4
5
6
7
D1
DQS4
DM4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
0
1
2
3
4
D4
5
6
7
UDQ S
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS2
DM2
S
LDQS
LDM
DQS5
DM5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
UDQ S
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
S
LDQ S
LDM
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5 D2
6
7
UDQS
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
0
1
2
3
4
5 D6
6
7
UDQ S
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
S
S
LDQS
LD M
LDQS
LD M
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
U DQS
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
DQS6
DM6
0
1
2
3
4
D5
5
6
7
S
LDQS
LDM
DQS7
DM7
0
1
2
3
4
5 D3
6
7
0
1
2
3
4
5
6
7
D7
UDQS
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
#Unless otherwise noted, resistor values are 22 Ω ± 5%
BA0-BA1
SDRAMS D0-D7
A0-An
SDRAMS D0-D7
RAS
SDRAMS D0-D7
CAS
WE
SDRAMS D0-D7
SDRAMS D0-D7
CKE0
SDRAMS D0-D3
CKE1
SDRAMS D4-D7
VDDSPD
VREF
SPD
SDRAMS D0-D7
VDD
SDRAMS D0-D7 VDD and VDDQ
VSS
SDRAMS D0-D7, SPD
Data Sheet
SCL
SA0
A0
SA1
A1
SA2
A2
SDA
WP
CK0
CK0
4 loads
CK1
4 loads
CK1
CK2
0 loads
CK2
Note: DQ wiring may differ from that described
in this drawing; however DQ/DM/DQS
relationships are maintained as shown.
VDDID strap connections:
(for memory device VDD, VDDQ)
Strap out (open): VDD = VDDQ
Strap in (closed): VDD VDDQ
≠
VDDID
Figure 2
Serial Presence Detect (SPD)
Block Diagram: Two Rank 16M x 64 DDR-SDRAM SO-DIMM Modules using x16 Organized
128Mbit SDRAMs on Raw Card Version A
11
Rev. 1.02, 2004-01
11042003-YIV7-VK6M
HYS64D16020GD(L)-[7/8]-A
Unbuffered DDR SDRAM SO Modules
Electrical Characteristics
3
Electrical Characteristics
3.1
Operating Conditions
Table 6
Absolute Maximum Ratings
Parameter
Symbol
Voltage on I/O pins relative to VSS
VIN, VOUT
Values
min.
typ.
max.
Unit Note/ Test
Condition
–0.5
–
VDDQ +
V
–
0.5
Voltage on inputs relative to VSS
Voltage on VDD supply relative to VSS
Voltage on VDDQ supply relative to VSS
Operating temperature (ambient)
Storage temperature (plastic)
Power dissipation (per SDRAM component)
Short circuit output current
VIN
VDD
VDDQ
TA
TSTG
PD
IOUT
–0.5
–
+3.6
V
–
–0.5
–
+3.6
V
–
–0.5
–
+3.6
V
–
0
–
+70
°C
–
-55
–
+150
°C
–
–
2.0
–
W
–
–
50
–
mA
–
Attention: Permanent damage to the device may occur if “Absolute Maximum Ratings” are exceeded. This
is a stress rating only, and functional operation should be restricted to recommended operation
conditions. Exposure to absolute maximum rating conditions for extended periods of time may
affect device reliability and exceeding only one of the values may cause irreversible damage to
the integrated circuit.
Data Sheet
12
Rev. 1.02, 2004-01
11042003-YIV7-VK6M
HYS64D16020GD(L)-[7/8]-A
Unbuffered DDR SDRAM SO Modules
Electrical Characteristics
Table 7
Electrical Characteristics and DC Operating Conditions
Parameter
Symbol
VDD
Output Supply Voltage
VDDQ
EEPROM supply voltage
VDDSPD
Supply Voltage, I/O Supply VSS,
Voltage
VSSQ
Input Reference Voltage
VREF
I/O Termination Voltage
VTT
Device Supply Voltage
Unit Note/Test Condition 1)
Values
Min.
Typ.
Max.
2.3
2.5
2.7
V
2.3
2.5
2.7
V
2)
2.3
2.5
3.6
V
—
0
V
—
0
0.49 × VDDQ 0.5 × VDDQ 0.51 × VDDQ V
3)
VREF – 0.04
VREF + 0.04 V
4)
Input High (Logic1) Voltage VIH(DC)
VREF + 0.15
7)
Input Low (Logic0) Voltage VIL(DC)
–0.3
Input Voltage Level,
CK and CK Inputs
VIN(DC)
–0.3
VDDQ + 0.3 V
VREF – 0.15 V
VDDQ + 0.3 V
Input Differential Voltage,
CK and CK Inputs
VID(DC)
0.36
VDDQ + 0.6
V
7)5)
VI-Matching Pull-up
Current to Pull-down
Current
VIRatio
0.71
1.4
—
6)
Input Leakage Current
II
–2
2
µA
Any input 0 V ≤ VIN ≤ VDD;
All other pins not under test
= 0 V 7)8)
Output Leakage Current
IOZ
–5
5
µA
DQs are disabled;
0 V ≤ VOUT ≤ VDDQ 7)
Output High Current,
Normal Strength Driver
IOH
—
–16.2
mA
VOUT = 1.95 V 7)
Output Low
Current, Normal Strength
Driver
IOL
16.2
—
mA
VOUT = 0.35 V 7)
(System)
7)
7)
1) 0 °C ≤ TA ≤ 70 °C
2) Under all conditions, VDDQ must be less than or equal to VDD.
3) Peak to peak AC noise on VREF may not exceed ± 2% VREF (DC). VREF is also expected to track noise variations in VDDQ.
4) VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal
to VREF, and must track variations in the DC level of VREF.
5) VID is the magnitude of the difference between the input level on CK and the input level on CK.
6) The ratio of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire
temperature and voltage range, for device drain to source voltage from 0.25 to 1.0 V. For a given output, it represents the
maximum difference between pull-up and pull-down drivers due to process variation.
7) Inputs are not recognized as valid until VREF stabilizes.
8) Values are shown per component
Data Sheet
13
Rev. 1.02, 2004-01
11042003-YIV7-VK6M
HYS64D16020GD(L)-[7/8]-A
Unbuffered DDR SDRAM SO Modules
Electrical Characteristics
3.2
Current Specification and Conditions
Table 8
IDD Conditions
Parameter
Symbol
Operating Current 0
one bank; active/ precharge; DQ, DM, and DQS inputs changing once per clock cycle;
address and control inputs changing once every two clock cycles.
IDD0
Operating Current 1
one bank; active/read/precharge; Burst Length = 4; see component data sheet.
IDD1
Precharge Power-Down Standby Current
all banks idle; power-down mode; CKE ≤ VIL,MAX
IDD2P
Precharge Floating Standby Current
CS ≥ VIH,,MIN, all banks idle; CKE ≥ VIH,MIN;
address and other control inputs changing once per clock cycle; VIN = VREF for DQ, DQS and DM.
IDD2F
Precharge Quiet Standby Current
CS ≥ VIHMIN, all banks idle; CKE ≥ VIH,MIN; VIN = VREF for DQ, DQS and DM;
address and other control inputs stable at ≥ VIH,MIN or ≤ VIL,MAX.
IDD2Q
Active Power-Down Standby Current
one bank active; power-down mode; CKE ≤ VILMAX; VIN = VREF for DQ, DQS and DM.
IDD3P
Active Standby Current
one bank active; CS ≥ VIH,MIN; CKE ≥ VIH,MIN; tRC = tRAS,MAX;
DQ, DM and DQS inputs changing twice per clock cycle;
address and control inputs changing once per clock cycle.
IDD3N
Operating Current Read
one bank active; Burst Length = 2; reads; continuous burst;
address and control inputs changing once per clock cycle;
50% of data outputs changing on every clock edge;
CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B; IOUT = 0 mA
IDD4R
Operating Current Write
one bank active; Burst Length = 2; writes; continuous burst;
address and control inputs changing once per clock cycle;
50% of data outputs changing on every clock edge;
CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B
IDD4W
Auto-Refresh Current
tRC = tRFCMIN, burst refresh
IDD5
Self-Refresh Current
CKE ≤ 0.2 V; external clock on
IDD6
Operating Current 7
four bank interleaving with Burst Length = 4; see component data sheet.
IDD7
Data Sheet
14
Rev. 1.02, 2004-01
11042003-YIV7-VK6M
HYS64D16020GD(L)-[7/8]-A
Unbuffered DDR SDRAM SO Modules
Electrical Characteristics
HYS64D16020GD(L)-8-A
IDD Specification and Conditions -8/-7
HYS64D16020GD(L)-8-A
Part Number & Organization
Table 9
Unit
Note 1)2)
128MB
×64
–8
–7
Symbol
max.
max.
IDD0
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
IDD6
IDD7
480
540
mA
3)
540
620
mA
3)4)
36
40
mA
5)
280
360
mA
5)
280
360
mA
5)
120
120
mA
5)
280
360
mA
5)
500
620
mA
3)4)
520
620
mA
3)
860
940
mA
3)
12
12
mA
5)
1220
1300
mA
3)4)
1) Module IDD values are calculated on the basis of component IDD and can be measured differently according to DQ loading
capacity.
2) Test condition for maximum values: VDD = 2.7 V, TA = 10 °C
3) The module IDDx values are calculated from the IDDx values of the component data sheet as follows:
m × IDDx[component] + n × IDD3N[component] with m and n number of components of rank 1 and 2; n=0 for 1 rank modules
4) DQ I/O (IDDQ) currents are not included in the calculations (see note 1)
5) The module IDDx values are calculated from the corrponent IDDx data sheet values as: (m + n) × IDDx[component]
Data Sheet
15
Rev. 1.02, 2004-01
11042003-YIV7-VK6M
HYS64D16020GD(L)-[7/8]-A
Unbuffered DDR SDRAM SO Modules
Electrical Characteristics
3.3
AC Characteristics
Table 10
AC Timing - Absolute Specifications –8/–7
Parameter
Symbol
–8
–7
DDR200
DDR266A
Min Max.
.
Min.
Max.
Unit
Note/
Test Condition 1)
DQ output access time from CK/CK
tAC
–
0.8
+0.8
–0.75
+0.75
ns
2)3)4)5)
DQS output access time from CK/CK
tDQSCK
–
0.8
+0.8
–0.75
+0.75
ns
2)3)4)5)
CK high-level width
tCH
0.4
5
0.55
0.45
0.55
tCK
2)3)4)5)
CK low-level width
tCL
0.4
5
0.55
0.45
0.55
tCK
2)3)4)5)
Clock Half Period
tHP
tCK2.5
tCK2
tCK1.5
tDH
tDS
tIPW
min. (tCL, tCH)
ns
2)3)4)5)
Clock cycle time
DQ and DM input hold time
DQ and DM input setup time
Control and Addr. input pulse width
(each input)
min. (tCL, tCH)
8
12
7
12
ns
CL = 2.5 2)3)4)5)
10
12
7.5
12
ns
CL = 2.0 2)3)4)5)
10
12
—
—
ns
CL = 1.5 2)3)4)5)
0.6
—
0.5
—
ns
2)3)4)5)
0.6
—
0.5
—
ns
2)3)4)5)
2.5
—
2.2
—
ns
2)3)4)5)6)
DQ and DM input pulse width (each
input)
tDIPW
2.0
—
1.75
—
ns
2)3)4)5)6)
Data-out high-impedance time from
CK/CK
tHZ
–
0.8
+0.8
–0.75
+0.75
ns
2)3)4)5)7)
Data-out low-impedance time from
CK/CK
tLZ
–
0.8
+0.8
–0.75
+0.75
ns
2)3)4)5)7)
Write command to 1st DQS latching
transition
tDQSS
0.7
5
1.25
0.75
1.25
tCK
2)3)4)5)
DQS-DQ skew (DQS and associated
DQ signals)
tDQSQ
—
+0.6
—
+0.5
ns
2)3)4)5)
Data hold skew factor
tQHS
tQH
—
1.0
—
0.75
ns
2)3)4)5)
tHP
—
tHP –
tQHS
—
ns
2)3)4)5)
0.3
5
—
0.35
—
tCK
2)3)4)5)
DQS falling edge to CK setup time (write tDSS
cycle)
0.2
—
0.2
—
tCK
2)3)4)5)
DQS falling edge hold time from CK
(write cycle)
tDSH
0.2
—
0.2
—
tCK
2)3)4)5)
Mode register set command cycle time
tMRD
tWPRES
tWPST
2
—
2
—
tCK
2)3)4)5)
DQ/DQS output hold time
–
tQHS
DQS input low (high) pulse width (write
cycle)
Write preamble setup time
Write postamble
Data Sheet
tDQSL,H
0
—
0
—
ns
2)3)4)5)8)
0.4
0
0.60
0.40
0.60
tCK
2)3)4)5)9)
16
Rev. 1.02, 2004-01
11042003-YIV7-VK6M
HYS64D16020GD(L)-[7/8]-A
Unbuffered DDR SDRAM SO Modules
Electrical Characteristics
Table 10
AC Timing - Absolute Specifications –8/–7
Parameter
Symbol
–8
–7
DDR200
DDR266A
Min Max.
.
Min.
Max.
Unit
Note/
Test Condition 1)
2)3)4)5)
Write preamble
tWPRE
0.2
5
—
0.25
—
tCK
Address and control input setup time
tIS
1.1
—
0.9
—
ns
fast slew rate
3)4)5)6)10)
1.1
—
1.0
—
ns
slow slew rate
3)4)5)6)10)
Address and control input hold time
tIH
1.1
—
0.9
—
ns
fast slew rate
3)4)5)6)10)
1.1
—
1.0
—
ns
slow slew rate
3)4)5)6)10)
Read preamble
Read preamble setup time
Read postamble
tRPRE
tRPRE1.5
tRPRES
tRPST
tRAS
Active to Active/Auto-refresh command tRC
Active to Precharge command
CL > 1.5 2)3)4)5)
NA
tCK
tCK
—
NA
ns
2)3)4)5)12)
0.4
0
0.60
0.40
0.60
tCK
2)3)4)5)
50
120E+3
45
120E+3 ns
2)3)4)5)
70
—
65
—
ns
2)3)4)5)
0.9
1.1
0.9
0.9
1.1
1.5
1.1
CL = 1.5 2)3)4)5)11)
period
Auto-refresh to Active/Auto-refresh
command period
tRFC
80
—
75
—
ns
2)3)4)5)
Active to Read or Write delay
tRCD
tRP
tRAP
tRRD
20
—
20
—
ns
2)3)4)5)
20
—
20
—
ns
2)3)4)5)
20
—
20
—
ns
2)3)4)5)
15
—
15
—
ns
2)3)4)5)
tWR
tDAL
15
—
15
—
ns
2)3)4)5)
tCK
2)3)4)5)13)
tWTR
tWTR1.5
tXSNR
tXSRD
tREFI
1
—
1
—
CL > 1.5 2)3)4)5)
2
—
—
—
tCK
tCK
80
—
75
—
ns
2)3)4)5)
200 —
200
—
tCK
2)3)4)5)
—
—
7.8
µs
2)3)4)5)14)
Precharge command period
Active to Autoprecharge delay
Active bank A to Active bank B
command
Write recovery time
Auto precharge write recovery +
precharge time
Internal write to read command delay
Exit self-refresh to non-read command
Exit self-refresh to read command
Average Periodic Refresh Interval
(twr/tCK) + (trp/tCK)
7.8
CL = 1.5 2)3)4)5)
1) 0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5 V ± 0.2 V, VDD = +2.5 V ± 0.2 V
2) Input slew rate ≥ 1 V/ns for DDR266, and = 1 V/ns for DDR200
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference
level for signals other than CK/CK, is VREF. CK/CK slew rate are ≥ 1.0 V/ns.
4) Inputs are not recognized as valid until VREF stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT.
6) These parameters guarantee device timing, but they are not necessarily tested on each device.
Data Sheet
17
Rev. 1.02, 2004-01
11042003-YIV7-VK6M
HYS64D16020GD(L)-[7/8]-A
Unbuffered DDR SDRAM SO Modules
Electrical Characteristics
7) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred
to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
8) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge.
A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were
previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress,
DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS.
9) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but
system performance (bus turnaround) degrades accordingly.
10) Fast slew rate ≥ 1.0 V/ns , slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns,
measured between VOH(ac) and VOL(ac).
11) CAS Latency 1.5 operation is supported on DDR200 devices only
12) tRPRES is defined for CL = 1.5 operation only
13) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock
cycle time.
14) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
Data Sheet
18
Rev. 1.02, 2004-01
11042003-YIV7-VK6M
HYS64D16020GD(L)-[7/8]-A
Unbuffered DDR SDRAM SO Modules
SPD Contents
4
SPD Contents
Table 11
SPD Codes for PC2100 & PC1600
Description
HEX.
HEX.
0
Number of SPD Bytes
128
80
80
1
Total Bytes in Serial PD
256
08
08
2
Memory Type
DDR-SDRAM
07
07
3
Number of Row Addresses
12
0C
0C
4
Number of Column Addresses
9
09
09
5
Number of DIMM Ranks
2
02
02
6
Module Data Width
×64
40
40
7
Module Data Width (cont’d)
0
00
00
8
Module Interface Levels
SSTL_2.5
04
04
9
SDRAM Cycle Time at CL = 2.5
7 ns/8 ns
70
80
10
Access Time from Clock at
CL = 2.5
0.75 ns/0.8 ns
75
80
11
DIMM config
non-ECC/ECC
00
02
12
Refresh Rate/Type
Self-Refresh 15.6 ms
80
80
13
SDRAM Width, Primary
×16
10
10
14
Error Checking SDRAM Data
Witdh
na
00
00
15
Minimum Clock Delay for Backto-Back Random Column
Address
tCCD = 1 CLK
01
01
16
Burst Length Supported
2, 4 & 8
0E
0E
17
Number of SDRAM Ranks
4
04
04
18
Supported CAS Latencies
CAS latency = 2 & 2.5
0C
0C
19
CS Latencies
CS latency = 0
01
01
20
WE Latencies
Write latency = 1
02
02
21
SDRAM DIMM Module Attributes unbuffered
20
20
22
SDRAM Device Attributes:
General
Concurrent Auto Precharge,
weak driver
C1
C1
23
Min. Clock Cycle Time at CAS
Latency = 2
7.5 ns/10 ns
75
A0
24
Access Time from Clock for
CL = 2
0.75 ns/0.8 ns
75
80
25
Minimum Clock Cycle Time for
CL = 1.5
not supported
00
00
26
Access Time from Clock at
CL = 1.5
not supported
00
00
27
Minimum Row Precharge Time
20 ns
50
50
Data Sheet
128MB
x64
2ranks
–7
128MB
x64
2ranks
–8
Byte#
19
Rev. 1.02, 2004-01
11042003-YIV7-VK6M
HYS64D16020GD(L)-[7/8]-A
Unbuffered DDR SDRAM SO Modules
SPD Contents
Table 11
Byte#
SPD Codes for PC2100 & PC1600 (cont’d)
Description
128MB
x64
2ranks
–7
128MB
x64
2ranks
–8
HEX.
HEX.
28
Minimum Row Act. to Row Act.
Delay tRRD
15 ns
3C
3C
29
Minimum RAS to CAS Delay tRCD 20 ns
50
50
30
Minimum RAS Pulse Width tRAS
2D
32
31
Module Rank Density (per Rank) 64 MByte
10
10
32
Addr. and Command Setup Time 0.9 ns/1.1 ns
90
B0
33
Addr. and Command Hold Time
0.9 ns/1.1 ns
90
B0
34
Data Input Setup Time
0.5 ns/0.6 ns
50
60
35
Data Input Hold Time
0.5 ns/0.6 ns
50
60
36 to 40
Superset Information
–
41
Minimum Core Cycle Time tRC
65 ns/70 ns
41
46
42
Min. Auto Refresh Cmd Cycle 75 ns/80 ns
Time tFRC
4B
50
43
Maximum Clock Cycle Time tCK
12 ns
30
30
44
Max. DQS-DQ Skew tDQSQ
0.5 ns/0.6 ns
32
3C
45
X-Factor tQHS
0.75 ns/1.0 ns
75
A0
46 to 61
Superset Information
–
00
00
62
SPD Revision
Revision 0.0
00
00
63
Checksum for Bytes 0 - 62
–
88
7D
64
Manufactures JEDEC ID Codes
–
C1
C1
65 to 71
Manufactures
–
Infineon
Infineon
45 ns/50 ns
72
Module Assembly Location
–
–
–
73 to 90
Module Part Number
–
–
–
91 to 92
Module Revision Code
–
–
–
93 to 94
Module Manufacturing Date
–
–
–
95 to 98
Module Serial Number
–
–
–
99 to 127
–
–
–
–
128 to 255
open for Customer use
–
–
–
Data Sheet
20
Rev. 1.02, 2004-01
11042003-YIV7-VK6M
HYS64D16020GD(L)-[7/8]-A
Unbuffered DDR SDRAM SO Modules
PRELIMINARY
5
Package Outlines
Package Outlines
67.6
3.8 MAX.
31.75
4 ±0.1
1.8 ±0.05
63.6 ±0.1
(2.15)
1
(2.45)
18.45 ±0.1
100
1±0.1
1.8 ±0.1
0.15
(2.4)
11.4 ±0.1
47.4 ±0.1
(2.7)
(2.15)
1.5 ±0.1
4 ±0.1
1±0.1
200
20 ±0.1
101
6 ±0.1
(2.45)
2 MIN.
2.55
0.25 -0.18
Detail of contacts
0.45 ±0.03
0.6 ±0.1
Burnished, no burr allowed
Figure 3
Data Sheet
Package Outlines Raw Card A : DDR-SDRAM SO-DIMM Modules Raw Card A
21
Rev. 1.01, 2003-11
11042003-YIV7-VK6M
www.infineon.com
Published by Infineon Technologies AG