5 D 4 3 2 1 D IT8711F Application Circuit V0.2 Page1 : Revision History Page2 : IT8711F Page3 : Serial & Parallel Ports Page4 : VID,IR,CIR,FDC & Smart Card Reader Connector Page5 : Layout & Routing Guideline C C REVISION HISTORY SCHEMATIC REVISION PCB REVISION MODIFICATION ITEMS DRAWING AND MODIFICATION DESCRITION DATE For INTEL Chipset April 17,2001 IT-8711-CG-S01 First Draft N/A VER 0.1 B B 1. Modify U1 Pin27 Connect to 3VSB 2. Adding VID Circuit 3. Modify R11 & R12 from 22 ohm to 4.7K ohm 4. Modify R33 & RN8 from 1k ohm to 150 ohm 5. Add JP8 for Keyboard/Mouse Power supplied by VCC/VCCH 6. Add Layout/Routing Guidelines for 3VSB circuit 7. Swap IT8711 Pin67 and Pin68 off-page connector label IT-8711-CG-S01 N/A VER 0.2 June 21,2001 A A Preliminary For Reference Only ITE, Inc. Title IT8711F Revision History ** Subject to Change Without Notice 5 4 3 2 Size Document Number IT-8711-CG-S01 V0.2 Date: Monday, January 07, 2002 Rev 0.2 Sheet 1 1 of 5 3 2 JP1 1 2 3 Power On Strapping JP1 : This power-on straping pin is reserved for ITE test. During LRESET#, a pill-up on this pin is needed. JP2 : 1-2 : Enable KBC 2-3 : Disable KBC JP3 : 1-2 : Base Address = 2Eh/2Fh 2-3 : Base Address = 4Eh/4Fh 1 JP2 JP3 1 2 3 4 1 2 3 5 GND R1 R2 R3 1K 1K 1K VCC3 VCC5 D BC1 0.1uF JP5 Keyboard Lock Jumper 4 4 4 4 4 4 4 4 VCC5 VCC3 JBB2 JBB1 JAB2 JAB1 JBCY JBCX JACY JACX JBB2 JBB1 JAB2 JAB1 JBCY JBCX JACY JACX R5 1K VREF 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 JP4 1 2 3 KBLK# KBLK#/CIRTX CIRTX 4 CIRTX Note : VREF Pull-up to +5V for Game Port Reference U1 VCC3 DCD2# SIN2 GND RI2# CTS2# DTR2# RTS2# DSR2# SOUT2 GA20 KBRST# KCLK KDAT MCLK MDAT PWBTIN# PWBOUT# SLPSX# PWRCTL# VID0 VID1 VID2 VID3 VID4 MIDI_OUT MIDI_IN 3VSB GND VBAT KBLK#/CIRTX 3 DCD2# 3 RXD2 C R6 4.7K Pin GA20 & KBRST# connect to South Bridge VCCH R7 4.7K 3 3 3 3 3 3 RI2# CTS2# DTR2# RTS2# DSR2# TXD2 4 4 4 4 KCLK KDAT MCLK MDAT 4 4 4 4 4 4 4 PWBOUT# SLPSX# PWRCTL# VID0 VID1 VID2 VID3 VID4 MIDI_OUT MIDI_IN GA20 KBRST# R8 4.7K R9 SW1 33 C4 1uF Power Control Signals. Please reference Power Control Suggestion Applications Circuitry of page 5. 3VSB B BC3 0.1uF PC Board Layout Checklist .Place BC3 close to IT8711F .Recommended net "3VSB" minimum trace width 12mils 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 DCD2#/GP62 SIN2/GP63 GND RI2#/GP10 CTS2#/GP11 DTR2#/GP12 RTS2#/GP13 DSR2#/GP14 SOUT2/GP15 GA20/GP16 KRST#/GP17 KCLK/GP20 KDAT/GP21 MCLK/GP22 MDAT/GP23 PWBTIN#/GP24 PWBTOUT#/GP25 SLPSX#/GP26 PWRCTL#GP27 VID0/GP30 VID1/GP31 VID2/GP32 VID3/GP33 VID4/GP34 GP35 GP36 VCCH GND VBAT KBLK#/CIRTX/GP40 + 2 D1 1N4148 1 JP6 C5 4.7UF/10V LI-BAT 1 2 3 Tantalum cap. (Spare for battery installation glitch) PC Board Layout Checklist .Place C3 close to IT8711F .Recommended net "VBAT" minimum trace width 12mils .Isolated the VBAT pin29 and Chipset A 4 4 4 4 4 4 4 4 CIRRX IRTX IRRX SCPSNT# SCRST SCPWR SCCLK SCIO IT8711F 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 BAT1 JVR/GP61 JACX/GP50 JACY/GP51 JBCX/GP52 JBCY/GP53 JAB1/GP54 JAB2/GP55 JBB1/GP56 JBB2/GP57 VCC DSR1# SOUT1/JP3 SIN1 RTS1#/JP2 DTRI1#/JP1 DCD1# RI1# CTS1# PD7 PD6 R4 10K VCC3 Keyboard CIRTX Only one function ( Keyboard lock or could be select at the same time CIRRX/GP41 IRTX/GP42 IRRX/GP43 PME# SCPSNT#/GP44 SCRST/GP45 SCPWR/GP46 SCCLK/GP47 SCIO/GP60 LDRQ# LFRAME# LRESET# SERIRQ LAD0 LAD1 LAD2 LAD3 PCICLK DENSEL# MTRA# JP4 : 1-2 for 2-3 for NOTE : CIRTX ) D CIRRX IRTX IRRX SCPSNT# SCRST SCPWR SCCLK SCIO DSR1# SOUT1/JP3 SIN1 RTS1#/JP2 DTR1#/JP1 DCD1# RI1# CTS1# PD7 PD6 PD5 PD4 GND PD3 PD2 PD1 PD0 STB# AFD# ERR# INIT# SLIN# BUSY ACK# SLCT PE WPT# INDEX# TRK0# DSKCHG# RDATA# DIR# WGATE# HDSEL# STEP# WDATA# VCC GND CKLIN DRVA# 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PD5 PD4 GND PD3 PD2 PD1 PD0 STB# AFD# ERR# INIT# SLIN# BUSY ACK# SLCT PE WPT# INDEX# TRK0# DSKCHG# RDATA# DIR# WGATE# HDSEL# STEP# WDATA# VCC3 GND CLKIN DRVA# DSR1# TXD1 RXD1 RTS1# DTR1# DCD1# RI1# CTS1# PD7 PD6 3 3 3 3 3 3 3 3 3 3 PD5 PD4 3 3 PD3 PD2 PD1 PD0 STB# AFD# ERR# INIT# SLIN# BUSY ACK# SLCT PE WPT# INDEX# TRK0# DSKCHG# RDATA# DIR# WGATE# HDSEL# STEP# WDATA# 3 3 3 3 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 DRVA# C BC2 0.1uF U2 VCC5 4 MTRA# DENSEL# PCICLK LAD3 LAD2 LAD1 LAD0 SERIRQ LRESET# LFRAME# LDRQ# PME# C3 0.1UF 4 4 VCC NC 1 8 OUT GND 7 R10 22 VCC3 MTRA# DENSEL# PCICLK LAD3 LAD2 LAD1 LAD0 SERIRQ LRESET# LFRAME# LDRQ# PME# 14 LDRQ# R11 4.7K PME# R12 4.7K B 24MHz\OSC 3VSB Low Pin Count (LPC) Interface Signals A Preliminary For Reference Only ITE, Inc. Title IT8711F ** Subject to Change Without Notice 5 4 3 2 Size Document Number IT-8711-CG-S01 V0.2 Date: Monday, January 07, 2002 Rev 0.2 Sheet 1 2 of 5 5 4 3 2 1 Serial Ports +12V +12V VCCH D2 1N4001 -12V -12V U3 100pF NDCD1# NDSR1# NRXD1 NRTS1# NTXD1 NCTS1# NDTR1# NRI1# GD75232 R13 4.7K COM1 D3 1N4001 NDCD1# NRXD1 NDSR1# NDTR1# NTXD1 NCTS1# NRTS1# NRI1# 100pF 1 2 3 4 5 6 7 8 9 10 100pF +12V RA0 RA1 RA2 DY0 DY1 RA3 DY2 RA4 -12V 100pF VCC RY0 RY1 RY2 DA0 DA1 RY3 DA2 RY4 GND 100pF 20 19 18 17 16 15 14 13 12 11 100pF VCC5 DCD1# RXD1 DSR1# DTR1# TXD1 CTS1# RTS1# RI1# DCD1# RXD1 DSR1# DTR1# TXD1 CTS1# RTS1# RI1# 100pF 2 2 2 2 2 2 2 2 100pF VCC5 D 1 6 2 7 3 8 4 9 5 Optional D R14 10K D4 1N4148 R17 10K D5 1N4148 RING# C6 C7 C8 C9 C10 C11 C12 C13 NDCD2# NRXD2 NDSR2# NDTR2# NTXD2 NCTS2# NRTS2# NRI2# COM2 NDCD2# NTXD2 1 3 5 7 9 100pF 100pF 100pF GD75232 C 100pF NRTS2# NRI2# 100pF +12V RA0 RA1 RA2 DY0 DY1 RA3 DY2 RA4 -12V 100pF VCC RY0 RY1 RY2 DA0 DA1 RY3 DA2 RY4 GND 1 2 3 4 5 6 7 8 9 10 100pF DCD2# RXD2 DSR2# DTR2# TXD2 CTS2# RTS2# RI2# 20 19 18 17 16 15 14 13 12 11 100pF 2 2 2 2 2 2 2 2 U4 VCC5 DCD2# RXD2 DSR2# DTR2# TXD2 CTS2# RTS2# RI2# R15 10K DB9 TO CHIPSET VCC5 Q1 2N7002 NRI1# NRXD2 NDTR2# NDSR2# NCTS2# 2 4 6 8 10 Q2 2N7002 R16 NRI2# 10K Head10 Optional C C14 C15 C16 C17 C18 C19 C20 C21 Parallel Port VCC5 D6 VCC5 1 3 5 7 2 2 2 2 ACK# BUSY PE SLCT ACK# BUSY PE SLCT 8P4R-2.2K 7 5 3 1 RN7 8P4R-22 2 4 6 8 R18 2.2K B 1 14 2 15 3 16 4 17 5 18 6 19 7 20 8 21 9 22 10 23 11 24 12 25 13 180pF PD4 PD5 PD6 PD7 180pF PD4 PD5 PD6 PD7 8P4R-22 2 4 6 8 180pF 2 2 2 2 RN6 180pF 1 3 5 7 180pF PD0 PD1 PD2 PD3 RN4 LPT1 180pF PD0 PD1 PD2 PD3 8P4R-2.2K 7 5 3 1 8P4R-22 2 4 6 8 180pF 2 2 2 2 RN5 180pF 1 3 5 7 180pF STB# AFD# INIT# SLIN# 180pF ERR# STB# AFD# INIT# SLIN# 180pF ERR# 2 2 2 2 180pF A 2 8 6 4 2 180pF 1 3 5 7 8P4R-2.2K 2 4 6 8 180pF RN3 RN2 8 6 4 2 180pF B 8P4R-2.2K 2 4 6 8 180pF 1 3 5 7 180pF RN1 1N4148 A Preliminary For Reference Only ITE, Inc. C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 Print-Fem Title Serial & Parallel Ports ** Subject to Change Without Notice 5 4 3 2 Size Document Number IT-8711-CG-S01 V0.2 Date: Monday, January 07, 2002 Rev 0.2 Sheet 1 3 of 5 5 4 3 VCC5 Game & MIDI Port 2 1 IR & CIR Connector VCC5 VCC5 2 2 2 2 JAB1 JBB1 JACX JBCX 2 MIDI_OUT 2 2 2 2 2 JBCY JACY JBB2 JAB2 MIDI_IN JAB1 JBB1 JACX JBCX MIDI_OUT R27 JBCY JACY JBB2 JAB2 MIDI_IN R30 1 2 3 4 5 CN3 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K D R25 R26 2.2K 2.2K R28 R29 2.2K 2.2K 470 470 1 9 2 10 3 11 4 12 5 13 6 14 7 15 8 2 IRRX 2 IRTX IRRX IRTX VCCH JP7 1 2 3 VCC5 R19 R20 R21 R22 R23 R24 1 2 3 4 5 CN1 CIRRX 2 CIRRX CIRTX 2 CIRTX CN2 D PS/2 Mouse Port VCC5 VCCH JP8 1 2 3 C39 C40 C41 C42 C43 C44 C45 C46 C47 C48 DB15 L1 PVCC PS/2 MOUSE CN4 FB 1 1 0.01uF 0.01uF 0.001uF 0.001uF 0.001uF 0.01uF 0.01uF 0.001uF 0.001uF 0.001uF GND R31 2.2K R32 2.2K VCC5 8P4R-150 B 2 2 2 2 2 CN7 LED NC SCRREST RFU SCRIO SCRPRES# NC 8 9 10 11 12 13 14 2 2 1 GND VID Control VCC5 VCC NC SCRFET# SCRCLK RFU GND NC FB AT KEYBOARD CN5 7 3 5 2 4 1 6 C52 220PF AT-KB C53 .1UF B Smart Card Reader Connector 2 SCPWR 2 SCCLK FB L6 C51 220PF FDC_CON 1 2 3 4 5 6 7 L5 GND KCLK 1 DIR# STEP# WDATA# WGATE# TRK0# WPT# RDATA# HDSEL# DSKCHG# KDAT GND 2 DIR# STEP# WDATA# WGATE# TRK0# WPT# RDATA# HDSEL# DSKCHG# 2 KDAT 2 KCLK R35 2.2K 2 2 2 2 2 2 2 2 2 2 DRVA# R34 2.2K 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 1 2 DRVA# INDEX# MTRA# GND GND GND GND GND GND GND GND GND GND GND GND GND GND NC GND NC 2 2 INDEX# 2 MTRA# DENSEL# NC NC INDEX# MTRA# NC DRVA# NC DIR# STEP# WDATA# WGATE# TRK0# WPT# RDATA# HDSEL# DSKCHG# FB 1 L4 1 2 4 6 8 PVCC 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 C PS2-MS Keyboard Port CN6 DENSEL# C50 220PF 2 2 RN8 FB FB GND GND C49 220PF R33 150 2 DENSEL# L2 L3 1 2 1 VCC5 FDC Connector 1 3 5 7 C MDAT MCLK 2 GND 2 MDAT 2 MCLK 9 4 6 2 8 1 5 3 7 SCRST 2 SCIO SCPSNT# 2 2 VID0 VID1 VID2 VID3 VID4 VCC3 47K 47K 47K 47K 47K R40 R41 R42 R43 R44 820 820 820 820 820 R45 R46 R47 R48 R49 To PWM DC-DC Converter VID0 VID1 VID2 VID3 VID4 From CPU SMCARDCN A A R36 4.7K Preliminary For Reference Only ITE, Inc. VCCH Title Flash ROM ** Subject to Change Without Notice 5 4 3 2 Size Document Number IT-8711-CG-S01 V0.2 Date: Monday, January 07, 2002 Rev 0.2 Sheet 1 4 of 5 5 4 3 2 1 LAYOUT/ROUTING GUIDELINES 1.For clock Lines : 1)If possible, please avoid using any through-hole. D D 2)Please make the trace length short, and the trace width wide enough. 3)The spacing to the closest neighbor should be wide enough. 4)The discrete damping resistors and capacitors are recommended. 5)Please don't share the I/O clock, 24/48MHz, with other device. 2.For the VBAT circuits : 1)Place the 1uF capacitor of VBAT pin close to ITE I/O chip. 2)VBAT should be routed with a minimum trace width of 12 mils. 3)Isolate the VBAT pin of ITE I/O chip from the pin G1/VCCRTC of INTEL's ICH with diode. 4)The 4.7uF/10V tantalum capacitor connected to the diode of battery is spare for battery installation glitches. 3.For the 3VSB circuits : 1)Place the 0.1uF capacitor of pin27 close to ITE I/O chip. C C 2)3VSB should be routed with a minimum trace width of 12 mils. 4.Please don't remove the pull-up resistor of LDRQ#. 5.Please don't change the resistors and capacitors values in the Game and MIDI circuits. 6. The physical pin layout of Smart Card Reader connector MUST match with the pin arrangement of the 2x7 connector in ITE schematics. 7.IT8711F Power Control Suggestion Applications Circuitry. South Bridge SIO_WAKEUP 3VSB SLP_S5# (or SLP_S3#) 3VSB 8.2K B 8.2K VCCH B VCCH PWBTOUT# SLPSX# (Pin 17) (Pin 18) IT8711F PWBTIN# (Pin 16) 20K PWRCTL# (Pin 19) ATX Power Supply PSON# System On/Off Button A A Preliminary For Reference Only ITE, Inc. Title Layout & Routing Guideline ** Subject to Change Without Notice 5 4 3 2 Size Document Number IT-8711-CG-S01 V0.2 Date: Monday, January 07, 2002 Rev 0.2 Sheet 1 5 of 5