NSC LM4931

LM4931
Audio Subsystem with Mono High Efficiency
Loudspeaker and Stereo Headphone Amplifiers
General Description
Key Specifications
The LM4931 is an integrated audio subsystem that supports
voice and digital audio functions. The LM4931 includes a
high quality stereo DAC, voice band codec, a stereo headphone amplifier and a high-power high efficiency mono
speaker amplifier. It is primarily designed for demanding
applications in mobile phones and other portable devices.
The LM4931 features an I2S serial interface for full range
audio, a 16-bit PCM bi-directional serial interface for the
voice band codec and an I2C/SPI compatible interface for
control. The full range music path features an SNR of 86dB
with an 18-bit 48kHz input. The headphone amplifier delivers
at least 26mWRMS to a 32Ω single-ended stereo load with
less than 1% distortion (THD+N) when AVDD = 3.3VDC. The
mono speaker amplifier delivers up to 570mWRMS into an 8Ω
load with less than 1% distortion when AVDD = 3.3VDC.
The LM4931 employs advanced techniques to reduce power
consumption, to reduce controller overhead, and to eliminate
click and pop. Boomer audio power amplifiers were designed specifically to provide high quality output power with
a minimal amount of external components. It is therefore
ideally suited for mobile phone and other low voltage applications where minimal power consumption, PCB area, and
cost are primary requirements.
j PLS
OUT
at AVDD = 5V, 8Ω
1% THD+N
j PLS
OUT
1% THD+N
j PH/P
1.1W (typ)
at AVDD = 3.3V, 8Ω
OUT
570mW (typ)
at AVDD = 5V & AVDD = 3.3V, 32Ω
1% THD+N
26mW (typ)
j Supply voltage range
DVDD
2.7V to 4.0V
AVDD (Note 8)
2.7V to 5.0V
j Shutdown current
1.1µA (typ)
j PSRR at 217Hz, AVDD = 3V
62dB (typ)
j SNR (Voice Codec)
75dB (typ)
j SNR (Audio DAC)
86dB (typ)
Features
n 18-bit 44.1kHz or 48kHz stereo DAC
n 16-bit 8kHz , 12kHz , 16kHz, or 24kHz voice-band
codec
n PLL for operation from common system clocks
n Either I2C or SPI compatible serial interface
n I2S digital audio data serial interface
n PCM voice audio data serial interface
n Differential analog microphone input
n 26mW/channel stereo headphone amplifier
n 570mW mono high efficiency BTL 8Ω amplifier
n 32-step volume control for audio output amplifiers with
1.5dB step size.
n Unity-gain stable headphone amplifiers
n No snubber networks or bootstrap capacitors are
required by the headphone or hands-free amplifiers
n Adjustable digital side-tone attenuation
n 16-step volume control for microphone preamp with 2dB
step size
n Configurable GPIO/Status Port
n Available in the 42 bump micro-SMD package
Applications
n
n
n
n
2.5 and 3G Mobile Phones and Multimedia Terminals
PDAs, Internet Appliances and Portable Gaming
Portable DVD/CD/AAC/MP3 Players
Digital Cameras and Toys
Boomer ® is a registered trademark of National Semiconductor Corporation.
© 2006 National Semiconductor Corporation
DS201009
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LM4931 Audio Subsystem with Mono High Efficiency Loudspeaker and Stereo Headphone
Amplifiers
July 2006
LM4931
Typical Application
20100957
FIGURE 1. Typical I2S + Voice codec application circuit for mobile phones
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2
LM4931
Connection Diagrams
42-Bump micro SMD
42-Bump micro SMD Marking
201009I7
Top View
XY - Date Code
TT - Die Tracebility
G - Boomer Family
C9 - LM4931ITL
20100958
Top View (Bump Side Down)
Order Number LM4931ITL
See NS Package Number TLA42YVA
Pin Descriptions
PIN
PIN NAME
D/A
I/O
DESCRIPTION
A1
MIC_P
A
I
Microphone positive differential input
A2
MIC_N
A
I
Microphone negative differential input
A3
VDD(MIC)
A
I
Analog Vdd for microphone section
A4
MODE
D
I
Selects between SPI and I2C control interfaces (I2C = 0, SPI = 1)
A5
SDA/SDI
D
I/O
I2C_SDA or SPI_SDI depending on the MODE control
A6
NC
N/A
N/A
No Connect
B1
MIC_P
A
I
Microphone positive differential input
B2
MIC_BIAS
A
O
2V ultra clean power supply for microphones
B3
BYPASS
A
I
Click and Pop / VDD/2 reference filter
B4
ADDR/ENB
D
I
I2C_ADDR or SPI_ENB depending on the MODE control
B5
SCL/SCK
D
I
I2C_SCL or SPI_SCK depending on the MODE control
B6
PCM_SDI
D
I
PCM_SDI voice data input
C1
VSS(MIC)
A
I
Analog Vss for microphone section
C2
MIC_REF
A
I
Filter for microphone power supply
C3
NC
N/A
N/A
No Connect
C4
PCM_SDO
D
O
PCM_SDO serial data output
C5
PCM_SYNC
D
I/O
PCM_SYNC pulse for the PCM bus
C6
PCM-CLK
D
I/O
PCM_SYNC pulse for the PCM bus
D1
HPL
A
O
Left Headphone output
D2
VSS(HP)
A
I
Analog Vss for Headphone and Mixer sections
D3
VSS(HP)
A
I
Analog Vss for Headphone and Mixer sections
D4
I2S_SDI
D
I
I2S serial data input
2
D5
I S_CLK
D
I/O
I2S clock signal
D6
VSSD
D
I
Digital Vss
E1
VDD(HP)
A
I
Analog Vdd for Headphone and Mixer sections
E2
HPR
A
O
Right Headphone output
E3
GPIO
D
O
Configurable multi purpose output
E4
I2S_WS
D
I/O
I2S word select signal
E5
MCLK
D
I
Input clock from 10MHz - 24.576MHz
E6
VDDD
D
I
Digital Vdd
F1
LS+
A
O
Loudspeaker positive output
F2
VDD(LS)
A
I
Analog Vdd for Loudspeaker section
F3
HP_SENSE
A
I
Input for headphone connection sense circuit
3
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LM4931
Pin Descriptions
(Continued)
F4
NC
N/A
N/A
No Connect
F5
PLL_OUT
D
O
PLL filter output
F6
VDD(PLL)
D
I
Digital Vdd for PLL section
G1
LS+
A
O
Loudspeaker positive output
G2
VSS(LS)
A
I
Analog Vss for Loudspeaker section
G3
LS-
A
O
Loudspeaker negative output
G4
VSS(PLL)
D
I
Digital Vss for PLL section
G5
PLL_IN
D
I
PLL filter input
G6
VDD(PLL)
D
I
Digital Vdd for PLL section
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4
Junction Temperature
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Thermal Resistance
Analog Supply Voltage
6.0V
Digital Supply Voltage
6.0V
Storage Temperature
θJA - TLA42YVA
105˚C/W
Operating Ratings
Temperature Range
-65˚C to +150˚C
Power Dissipation (Note 3)
150˚C
TMIN ≤ TA ≤ TMAX
Internally Limited
−40˚C ≤ TA ≤ +85˚C
Supply Voltage
ESD Susceptibility
Human Body Model (Note 4)
Machine Model (Note 5)
2500V
DVDD (Note 8)
2.7V - 4.0V
200V
AVDD (Note 8)
2.7V - 5.0V
Electrical Characteristics DVDD = 3V, AVDD = 3V, RLHP = 32Ω, RLHF = 8Ω
(Notes 1, 2)
The following specifications apply for the circuit shown in Figure 1, unless otherwise specified. Limits apply for TA = 25˚C.
Symbol
Parameter
Conditions
LM4931
Units
(Limits)
Typical
(Note 6)
Limits
(Note 7)
400
500
1
2
µA (max)
400
1200
µA (max)
Power
Mode 0
DISD
Digital Shutdown Current
fMLCK = 12MHz (Note 9)
No MCLK
µA (max)
DIST
Digital Standby Current
Mode 1, fMCLK = 12MHz
DIDD
Digital Power Supply Current
Mode 2, 3, 4
1.3
3.2
mA (max)
Mode 5, 6, 7
2.8
7
mA (max)
fMLCK = 12MHz
Mode 8, 9, 10
3.2
7.5
mA (max)
PLLIDD
PLL Quiescent Current
fMCLK = 12MHz
2.8
3.5
mA (max)
AISD
Analog Shutdown Current
Mode 0, No load
0.1
2.5
µA (max)
AIST
Analog Standby Current
Mode 1, No load
100
200
µA (max)
Mode 2
7.8
19
mA (max)
Mode 3
5.3
10
mA (max)
Mode 4
8.6
15
mA (max)
Mode 5
8.4
15
mA (max)
Mode 6
6.0
15
mA (max)
Mode 7
9.2
15
mA (max)
Mode 8, 9, 10
10.1
16
mA (max)
No Load
AIDD
Analog Power Supply Quiescent
Current
Loudspeaker Amplifier
VFS
Full-Scale Output Voltage
Loudspeaker Amplifier)
8Ω load, 0dB gain setting
THD+N
Total Harmonic Distortion + Noise
fOUT = 1kHz, POUT = 200mW
POLS
Loudspeaker Amplifier Output
Power
THD = 1% (max), fOUT = 1kHz
PSRR
Power Supply Rejection Ratio
(Loudspeaker Amplifier)
CB = 1.0µF
VRIPPLE = 200mVP-P
fRIPPLE = 217Hz
2.6
VP-P
0.4
%
470
350
mW (min)
54
dB
71
dB
Signal = VO at 0dBFS, f = 1kHz,
Noise = digital zero, A-weighted,
0dB gain setting (Note 10)
SNR (Voice)
Signal-to-Noise Ratio of Voice
Channel (Loudspeaker Amplifier)
fMCLK = 12.288MHz, PLL disabled
5
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LM4931
Absolute Maximum Ratings (Notes 1, 2)
LM4931
Electrical Characteristics DVDD = 3V, AVDD = 3V, RLHP = 32Ω, RLHF = 8Ω
(Notes 1, 2) (Continued)
The following specifications apply for the circuit shown in Figure 1, unless otherwise specified. Limits apply for TA = 25˚C.
Symbol
Parameter
Conditions
LM4931
Typical
(Note 6)
fMCLK = 12MHz, PLL active
Signal-to-Noise Ratio of Music
SNR (Music) Channel (Loudspeaker Amplifier)
Output Noise
eN (Music)
Output Noise
VOS
Offset Voltage
VCR
Volume Control Range
(Loudspeaker Amplifier)
70
dB
fMCLK = 12.288MHz, PLL disabled
78
dB
fMCLK = 12MHz, PLL active
76
dB
fMCLK = 12.288MHz, PLL disabled
120
µV
fMCLK = 12MHz, PLL active
140
µV
10
mV
–34.5
dB
Signal = VO at 0dBFS, f = 1kHz,
Noise = digital zero, A-weighted,
0dB gain setting (Note 10)
A-weighted filter, Vin = digital zero (Note
10)
Minimum Gain
Maximum Gain
SS
Limits
(Note 7)
Units
(Limits)
Volume Control Step Size
(Loudspeaker Amplifier)
12
dB
1.5
dB
Headphone Amplifier
VFS
Full Scale Ouput Voltage
(Headphone Amplifier)
32Ω load, 0dB gain setting
2.6
VP-P
THD+N
Total Harmonic Distortion + Noise
(Headphone Amplifier)
fIN = 1kHz, POUT = 7.5mW,
32Ω stereo load
0.04
%
POHP
Output Power (Headphone
Amplifier)
THD = 0.5%, fOUT = 1KHz
26
PSRR
Power Supply Rejection Ratio
(Headphone Amplifier)
CB = 1.0µF
VRIPPLE = 200mVPP
fRIPPLE = 217Hz
62
dB
fMCLK = 12.288MHz, PLL disabled
75
dB
fMCLK = 12MHz, PLL active
73
dB
SNR (Voice)
SNR (Music)
Signal-to-Noise Ratio of Voice
Channel (Headphone Amplifier)
Signal-to-Noise Ratio of Music
Channel (Headphone Amplifier)
XTALK
Stereo Channel-to-Channel
Crosstalk
∆ACH-CH
Stereo Channel-to-Channel Gain
Mismatch
eN (Music)
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Output Noise
19
mW (min)
Signal = VO at 0dBFS, f = 1kHz and 1%
THD+N,
Noise = digital zero, A-weighted,
0dB gain setting (Note 10)
Signal = VO at 0dBFS, f = 1kHz and 1%
THD+N,
Noise = digital zero, A-weighted,
0dB gain setting (Note 10)
fMCLK = 12.288MHz, PLL disabled
86
dB
fMCLK = 12MHz, PLL active
82
dB
fS = 48kHz,
fIN = 1kHz sinewave at –3dBFS
62
dB
0.3
dB
fMCLK = 12.288MHz, PLL disabled
45
µV
fMCLK = 12MHz, PLL active
65
µV
A-weighted filter,
Vin = digital zero (Note 10)
6
(Notes 1, 2) (Continued)
The following specifications apply for the circuit shown in Figure 1, unless otherwise specified. Limits apply for TA = 25˚C.
Symbol
Parameter
Conditions
LM4931
Typical
(Note 6)
VCR
SS
Volume Control Range
(Headphone Amplifier)
Limits
(Note 7)
Units
(Limits)
Minimum Gain
–46.5
dB
Maximum Gain
0
dB
1.5
dB
2
V
Minimum Gain
6
dB
Maximum Gain
36
dB
2
dB
dB
Volume Control Stepsize
(Headphone Amplifier)
Microphone Amplifier
VBIAS
Mic Bias Voltage
GCR
Gain Control Range (Microphone
Amplifier)
SS
Gain Control Stepsize
(Microphone Amplifier)
Voice Codec (Typical numbers are with 1.024MHz voice clock and 8kHz sampling frequency)
RVDAC
Voice DAC Ripple
300Hz-3.3kHz through headphone output.
+/- 0.15
RVADC
Voice ADC Ripple
300Hz-3.3kHz through headphone output.
+/- 0.25
dB
PBVDAC
Voice DAC Passband
–3dB Point
3.46
kHz
SBAVDAC
Voice DAC Stopband Attenuation
Above 4kHz
72
dB
UPBVDAC
Upper Passband Cutoff Frequency Upper – 3dB Point
3.47
kHz
LPBVDAC
Lower Passband Cutoff Frequency Lower – 3dB Point
0.230
kHz
SBAVADC
Voice ADC Stopband Attenuation
Above 4kHz
65
dB
SBANOTCH
Voice ADC Notch Attenuation
Centered on 55Hz, figure gives worst
case attenuation for 50Hz & 60Hz
58
dB
81
dB
SNR (Voice)
Signal-to-Noice Ratio of Voice
Channel (Voice ADC path)
Signal = VO at 0dBFS, f = 1kHz and 1%
THD+N,
MIC_P, MIC_N Terminated to ground,
A-weighted, 36dB MIC Preamp gain
setting (Note 10)
fMCLK = 12.288MHz, PLL disabled
STR
SS
Side Tone Range
fMCLK = 12MHz, PLL active
80
dB
Minimum Gain
–30
dB
Maximum Gain
0
dB
3
dB
Side Tone Step Size
Audio DAC (Typical numbers are with 6.144MHz audio clock and 48kHz sampling frequency)
RDAC
Audio DAC Ripple
20Hz–20kHz through headphone output
PBDAC
Audio DAC Passband width
–3dB point
SBADAC
Audio DAC Stop band Attenuation
DRDAC
Audio DAC Dynamic Range
SNRDAC
Audio DAC SNR Digital Filter
Section
+/-0.1
dB
22.7
kHz
Above 24kHz
76
dB
DC – 20kHz
97
dB
DC – 20kHz
97
dB
PLL
fIN
Input Frequency on MCLK pin
12
10
25
MHz (min)
MHz (max)
fSPI
Maximum SPI Frequency
400
4000
kHz (max)
SPI/I2C
tSPISETD
SPI Data Setup Time
100
ns (min)
tSPISETENB
SPI ENB Setup Time
100
ns (min)
tSPIHOLDD
SPI Data Hold Time
100
ns (min)
7
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LM4931
Electrical Characteristics DVDD = 3V, AVDD = 3V, RLHP = 32Ω, RLHF = 8Ω
LM4931
Electrical Characteristics DVDD = 3V, AVDD = 3V, RLHP = 32Ω, RLHF = 8Ω
(Notes 1, 2) (Continued)
The following specifications apply for the circuit shown in Figure 1, unless otherwise specified. Limits apply for TA = 25˚C.
Symbol
Parameter
Conditions
LM4931
Typical
(Note 6)
Limits
(Note 7)
Units
(Limits)
tSPIHOLDENB
SPI ENB Hold Time
100
ns (min)
tSPICL
SPI Clock Low Time
500
ns (min)
tSPICH
SPI Clock HighTime
500
ns (min)
tSPIT
SPI Clock Transition Time
5
ns (min)
fCLKI2C
I2C_CLK Frequency
3400
kHz (max)
400
2
tI2CHOLD
I C_DATA Hold Time
100
ns (min)
tI2CSET
I2C_DATA Setup Time
100
ns (min)
40
60
% (min)
% (max)
PCM/I2S
fCLKPCM
PCM_CLK Frequency
128
PCM_CLK Duty Cycle
50
I2S_CLK Frequency
fCLKI2S
I2S_RES = 0
I2S_RES = 1
kHz
1536
3072
I2S_WS Duty Cycle
50
kHz
kHz
40
60
% (min)
% (max)
Electrical Characteristics DVDD = 3.3V, AVDD = 5V, RLHP = 32Ω, RLHF = 8Ω
(Notes 1, 2)
The following specifications apply for the circuit shown in Figure 1, unless otherwise specified. Limits apply for TA= 25˚C.
Symbol
Parameter
Conditions
LM4931
Units
(Limits)
Typical
(Note 6)
Limits
(Note 7)
500
600
µA (max)
500
1600
µA (max)
Mode 2, 3, 4
1.6
3.5
mA (max)
Mode 5, 6, 7
3.5
8
mA (max)
Mode 8, 9, 10
4.0
8
mA (max)
3.3
4
mA (max)
Power
Mode 0
DISD
Digital Shutdown Current
fMCLK = 12MHz (Note 9)
DIST
Digital Standby Current
Mode 1, fMCLK = 12MHz
No MCLK
1
µA (max)
fMCLK = 12MHz
DIDD
Digital Power Supply Current
PLLIDD
PLL Quiescent Current
fMCLK = 12MHz
AIDD
Analog Shutdown Current
Mode 0, No Load
0.6
3
µA (max)
AIST
Analog Standby Current
Mode 1, No Load
220
450
µA (max)
No Load
AIDD
Analog Power Supply Quiescent
Current
Mode 2
18.5
32
mA (max)
Mode 3
7.3
12
mA (max)
Mode 4
19.6
29
mA (max)
Mode 5
19.4
30
mA (max)
Mode 6
8.4
26
mA (max)
Mode 7
20.5
30
mA (max)
22
32
mA (max)
Mode 8, 9, 10
Loudspeaker Amplifier
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8
(Notes 1, 2) (Continued)
The following specifications apply for the circuit shown in Figure 1, unless otherwise specified. Limits apply for TA= 25˚C.
Symbol
Parameter
Conditions
LM4931
Typical
(Note 6)
VFS
Full-Scale Output Voltage (Mono
speaker amplifie)r
8Ω load, 0dB gain setting
THD+N
Total Harmonic Distortion + Noise
POLS
PSRR
SNR (Voice)
SNR (Music)
Limits
(Note 7)
Units
(Limits)
2.6
VP-P
fOUT = 1kHz, POUT = 400mW
0.16
%
Loudspeaker Amplifier Output
Power
THD = 1%, fOUT = 1kHz
1.1
W
Power Supply Rejection Ratio
(Loudspeaker Amplifier)
CB = 1.0µF
VRIPPLE = 200mVPP
fRIPPLE = 217Hz
56
dB
fMCLK = 12.288MHz, PLL disabled
70
dB
fMCLK = 12MHz, PLL active
69
dB
fMCLK = 12.288MHz, PLL disabled
74
dB
fMCLK = 12MHz, PLL active
73
dB
fMCLK = 12.288MHz, PLL disabled
250
µV
fMCLK = 12MHz, PLL active
320
µV
10
mV
–34.5
dB
Signal-to-Noise Ratio of Voice
Channel (Loudspeaker Amplifier)
Signal-to-Noise Ratio of Music
Channel (Loudspeaker Amplifier)
Signal = VO at 0dBFS, f = 1kHz
Noise = digital zero, A-weighted
0dB gain setting (Note 10)
Signal = VO at 0dBFS, f = 1kHz
Noise = digital zero, A-weighted
0dB gain setting (Note 10)
A-Weighted filter, VIN= digital zero (Note
10)
eN (Music)
Output Noise
VOS
Offset Voltage
VCR
Volume Control Range
(Loudspeaker Amplifier)
SS
Volume Control Step Size
Minimum Gain
Maximum Gain
12
dB
1.5
dB
Headphone Amplifier
VFS
Full-Scale Output Voltage
(Headphone Amplifier)
32Ω stereo load, 0dB gain setting
2.6
VP-P
THD+N
Total Harmonic Distortion + Noise
(Headphone Amplifier)
fIN = 1kHz, POUT = 7.5mW
32Ω stereo load
0.05
%
POHP
Output Power (Headphone
Amplifier)
THD = 0.5%, fOUT = 1kHz
26
PSRR
Power Supply Rejection Ratio
(Headphone Amplifier)
CB = 1.0µF
VRIPPLE = 200mVPP
fRIPPLE = 217Hz
70
dB
fMCLK = 12.288MHz, PLL disabled
75
dB
fMCLK = 12MHz, PLL active
73
dB
fMCLK = 12.288MHz, PLL disabled
86
dB
fMCLK = 12MHz, PLL active
82
dB
SNR (Voice)
SNR (Music)
Signal-to-Noise Ratio of Voice
Channel (Headphone Amplifier)
Signal-to-Noise Ratio of Music
Channel (Headphone Amplifier)
20
mW (min)
Signal = VO at f = 1kHz and 1% THD+N,
Noise = digital zero, A-weighted
0dB gain setting (Note 10)
Signal = VO at f = 1kHz and 1% THD+N,
Noise = digital zero, A-weighted
0dB gain setting (Note 10)
9
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LM4931
Electrical Characteristics DVDD = 3.3V, AVDD = 5V, RLHP = 32Ω, RLHF = 8Ω
LM4931
Electrical Characteristics DVDD = 3.3V, AVDD = 5V, RLHP = 32Ω, RLHF = 8Ω
(Notes 1, 2) (Continued)
The following specifications apply for the circuit shown in Figure 1, unless otherwise specified. Limits apply for TA= 25˚C.
Symbol
Parameter
Conditions
LM4931
Typical
(Note 6)
XTALK
Stereo Channel-to-Channel
Crosstalk
∆ACH-CH
Stereo Channel-to-Channel Gain
Mismatch
eN (Music)
VCR
SS
Output Noise
Volume Control Range
(Headphone Amplifier)
Limits
(Note 7)
Units
(Limits)
62
dB
0.3
dB
fMCLK = 12.288MHz, PLL disabled
45
µV
fMCLK = 12MHz, PLL active
70
µV
fS = 48kHz
fIN = 1kHz sinewave at –3dBFS
A-Weighted filter
VIN = digital zero (Note 10)
Minimum Gain
-46.5
dB
Maximum Gain
0
dB
1.5
dB
Volume Control Step Size
(Headphone Amplifier)
Microphone Amplifier
VBIAS
Mic Bias Voltage
GCR
Gain Control Range (Microphone
Amplifier)
SS
Gain Control Step Size
2
V
Minimum Gain
6
dB
Maximum Gain
36
dB
2
dB
Voice Codec (Typical numbers arew ith 1.024MHz voice clock and 8kHz sampling frequency
RVDAC
Voice DAC Ripple
300Hz - 3.3kHz through headphone
output
+/-0.15
dB
RVADC
Voice ADC Ripple
300Hz - 3.3kHz through headphone
output
+/-0.25
dB
PBVDAC
Voice DAC Passband
–3dB Point
3.46
kHz
SBAVDAC
Voice DAC Stopband Attenuation
Above 4kHz
72
dB
UPBVADC
Upper Passband Cutoff Frequency Upper – 3dB Point
3.47
kHz
LPBVADC
Lower Passband Cutoff Frequency Lower – 3dB Point
0.230
kHz
SBAVADC
Voice ADC Stopband Attenuation
Above 4kHz
65
dB
SBANOTCH
Voice ADC Notch Attenuation
Centered on 55Hz, figure gives worst
case attenuation for 50Hz & 60Hz
58
dB
dB
SNR (Voice)
Signal-to-Noise Ratio of Voice
Channel (Voice ADC path)
STR
Side Tone Range
SS
Side Tone Step Size
Signal = VO at f = 1kHz and 1% THD+N,
MIC_P, MIC_N terminated to ground,
A-weighted, 36dB MIC Preamp gain
setting (Note 10)
fMCLK = 12.288MHz, PLL disabled
83
fMCLK = 12MHz, PLL active
81
dB
Minimum
–30
dB
Maximum
0
dB
3
dB
Audio DAC (Typical numbers are with 6.144MHz audio clock and 48kHz sampling frequency)
RDAC
Audio DAC Ripple
20Hz – 20kHz through headphone output
PBDAC
Audio DAC Passband width
–3dB point
SBADAC
Audio DAC Stop band Attenuation
Above 24kHz
76
dB
DRDAC
Audio DAC Dynamic Range
DC – 20kHz
97
dB
SNRDAC
Audio DAC SNR Digital Filter
Section
DC – 20kHz
97
dB
PLL
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10
+/- 0.1
dB
22.7
kHz
(Notes 1, 2) (Continued)
The following specifications apply for the circuit shown in Figure 1, unless otherwise specified. Limits apply for TA= 25˚C.
Symbol
Parameter
Conditions
LM4931
Units
(Limits)
Typical
(Note 6)
Limits
(Note 7)
Input Frequency on MCLK pin
12
10
20
MHz (min)
MHz (max)
fSPI
Maximum SPI Frequency
400
4000
kHz (max)
tSPISETD
SPI Data Setup Time
100
ns (min)
tSPISETENB
SPI ENB Setup Time
100
ns (min)
tSPISETHOLDD
SPI Data Hold Time
100
ns (min)
tSPIHOLDENB
SPI ENB Hold Time
100
ns (min)
tSPICL
SPI Clock Low Time
500
ns (min)
tSPICH
SPI Clock High Time
500
ns (min)
tSPIT
SPI Clock TransitionTime
5
ns (min)
tCLKI2C
I2C_CLK Frequency
3400
kHz (max)
tI2CHOLD
I2C_DATA Hold Time
100
ns (min)
100
ns (min)
fIN
SPI/I2C
tI2CSET
400
2
I C_DATA Setup Time
PCM/I2S
fCLKPCM
fCLKI2S
PCM_CLK Frequency
128
PCM_CLK Duty Cycle
50
I2S_CLK Frequency
I2S_RES = 0
I2S_RES = 1
I2S_WS Duty Cycle
kHz
40
60
1536
3072
50
% (min)
% (max)
kHz
40
60
% (min)
% (max)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional but do not guarantee specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which
guarantee specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not guaranteed for parameters where no limit
is given, however, the typical value is a good indication of device performance.
Note 2: All voltages are measured with respect to the relevant GND pin unless otherwise specified. All grounds should be coupled as close as possible to the
device.
Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX ,θJA, and the ambient temperature, TA. The maximum
allowable power dissipation is PDMAX = (TJMAX – TA) / θJA or the number given in Absolute Maximum Ratings, whichever is lower. For the LM4931, see power
derating currents for more information.
Note 4: Human body model: 100pF discharged through a 1.5kΩ resistor.
Note 5: Machine model: 220pF - 240pF discharged through all pins.
Note 6: Typicals are measured at 25˚C and represent the parametric norm.
Note 7: Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 8: Best operation is achieved by maintaining 3.0V ≤ AVDD ≤ 5.0 and 3.0V ≤ DVDD ≤ 3.6V and AVDD ≥ DVDD.
Note 9: Digital shutdown current is measured with system clock set for PLL output while the PLL is disabled.
Note 10: Disabling or bypassing the PLL will result in an improvement in noise measurements.
Note 11: Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis.
11
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LM4931
Electrical Characteristics DVDD = 3.3V, AVDD = 5V, RLHP = 32Ω, RLHF = 8Ω
LM4931
System Control
The LM4931 is controlled via either a three wire SPI or a two wire I2C compatible interface, selectable with the MODE pin When
MODE is cleared the device is in I2C mode, when MODE is set the device is in SPI mode. This interface is used to configure the
operating mode, interfaces, data converters, mixers and amplifiers. The LM4931 is controlled by writing 8 bit data into a series
of write-only registers, the device is always a slave for both type of interfaces.
THREE WIRE, SPI INTERFACE (MODE = 1)
20100959
20100960
FIGURE 2.
When the part is configured as an SPI device and the enable (ENB) line is lowered the serial data on SDI is clocked in on the
rising edge of the SCK line. The protocol used is 16bit, MSB first. The upper 8 bits (15:8) are used to select an address within
the device, the lower 8 bits (7:0) contain the updated data for this register.
TWO WIRE I2C COMPATIBLE INTERFACE (MODE = 0)
20100961
20100962
FIGURE 3.
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12
(Continued)
When the part is configured as an I2C device then the LM4931 will respond to one of two addresses, according to the ADDR input.
If ADDR is low then the address portion of the I2C transaction should be set to write to 0010000. When ADDR is high then the
address input should be set to write to 1110000. The LM4931 uses the following 11 registers to store configuration information:
SYSTEM CONTROL TABLE
Address
Register Name
00000000
BASIC_CONFIG
Controls the output mode configuration
Description
00000001
VOICE_CONFIG
Controls the settings for the voice codec
00000010
MIC_GAIN
Controls the gain and muting of the microphone pre-amplifier
00000011
HP_GAIN
Controls the gain and muting of the headphone amplifier
00000100
LS_GAIN
Controls the gain and muting of the loudspeaker amplifier
00000101
PLL_M
Sets the PLL input divider
00000110
PLL_N
Sets the PLL feedback divider
00000111
PLL_P
Sets the PLL output divider
00001000
CLK_MUX
Configures the clock divider
00001001
INTERFACES
Controls the format of the PCM, I2S and GPIO interfaces
00001010
PMC_CONFIG
Controls the power management functions
13
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LM4931
System Control
LM4931
Basic Configuration Register
This register used to configure the basic function of the chip.
DEFAULT CHART FOR BASIC_CONFIG (00h)
DATA BIT
7
6
5
4
3
2
1
0
DEFAULT
0
0
0
0
0
0
0
0
BASIC_CONFIG (00h) (SET = LOGIC 1, CLEAR = LOGIC 0)
Address
Register
Description
3:0
MODE
The LM4931 can be placed in one of several modes that dictate the basic operation.
When a new mode is selected the LM4931 will change operation silently and will
reconfigure the power management profile automatically. The modes are described as
follows: (Note 13)
3:0
Mono Speaker
Amplifier
Source
Headphone
Left Source
Headphone
Right Source
Comment
0000
None
None
None
Powerdown
mode
0001
None
None
None
Standby mode
0010
Voice
None
None
Mono speaker
mode
0011
None
Voice
Voice
Headphone call
mode
0100
Voice
Voice
Voice
Conference call
mode
0101
Audio (L+R)
None
None
L+R mixed to
mono speaker
0110
None
Audio (Left)
Audio (Right)
Headphone
stereo audio
0111
Audio (L+R)
Audio (Left)
Audio (Right)
L+R mixed to
mono speaker +
stereo
headphone
audio
1000
Audio (Left)
Voice
Voice
Mixed mode
1001
Voice + Audio
(Left)
Voice
Voice
Mixed mode
1010
Voice
Audio (Left)
Audio (Left)
Mixed mode
2
4
SOFTRESET
If set, resets the LM4931, excluding the I C/SPI registers and PLL. SOFTRESET should
be cleared to resume normal operation.
5
DAC_
DITHER_OFF
Disables the audio DAC dither.
6
BYPASS_BYPASS If set the power management and control circuit will assume that bypass is at VDD/2
even when such condition is false. (Note 12)
7
RSVD
RESERVED (Note 14)
Note 12: It is recommended to alter this bit only while the part is in Powerdown mode.
Note 13: Modes 8, 9, and 10 are only available if the sample rate of the I2S is an integer multiple of the sample rate of the PCM. For example, 48kHz (I2S) and 8kHz
(PCM) would be acceptable.
Note 14: Reserved bits should be set to zero when programming the associated register.
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14
LM4931
Voice Codec Configuration Register
This register configures the voiceband codec, sidetone attenuation, and selected control functions.
DEFAULT CHART FOR VOICE_CONFIG (01h)
DATA BIT
7
6
5
4
3
2
1
0
DEFAULT
0
0
0
0
0
0
0
0
VOICE_CONFIG (01h) (SET = LOGIC 1, CLEAR = LOGIC 0)
Address Register
Description
3:0
Programs the attenuation of the digital sidetone. Attenuation is set as follows:
SIDETONE_ATTEN
3:0
Sidetone
Attenuation
3:0
Sidetone
Attenuation
0000
Mute
1000
–9dB
0001
–30dB
1001
–6dB
0010
–27dB
1010
–3dB
0011
–24dB
1011
0dB
0100
–21dB
1100
0dB
0101
–18dB
1101
0dB
0110
–15dB
1110
0dB
0111
–12dB
1111
0dB
4
AUTO_SIDE
This will automatically disable the sidetone when in a VOICE over loudspeaker mode
except when the headphone is connected and the loudspeaker is muted by the
HP_SENSE control.
5
RSVD
RESERVED (Note 14)
6
VADC_DITHER_OFF
Disables the Voice ADC dither.
7
VDAC_DITHER_OFF
Disables the Voice DAC dither.
15
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LM4931
Microphone Gain Registers
This register is used to control the gain of the microphone preamplifier.
DEFAULT CHART FOR MIC_GAIN (02h)
DATA BIT
7
6
5
4
3
2
1
0
DEFAULT
0
0
0
0
0
0
0
0
MIC_GAIN (02h) (SET = LOGIC 1, CLEAR = LOGIC 0)
Address
Register
Description
3:0
MIC_GAIN
Programs the gain of the microphone pre-amplifier. Gain is
set as follows:
3:0
Mic Gain
0000
6dB
0001
8dB
0010
10dB
0011
12dB
0100
14dB
0101
16dB
0110
18dB
0111
20dB
1000
22dB
1001
24dB
1010
26dB
1011
28dB
1100
30dB
1101
32dB
1110
34dB
1111
36dB
4
MIC_MUTE
If set the microphone pre-amplifier and the ADC output are
muted.
5
RSVD
RESERVED (Note 14)
6
RSVD
RESERVED (Note 14)
7
HPF_DISABLE
If set the HPF is disabled, this is useful for wider bandwidth
use of the ADC.
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16
LM4931
Headphone Gain Registers
This register is used to control the gain of the headphone amplifier.
DEFAULT CHART FOR HP_GAIN (03h)
DATA BIT
7
6
5
4
3
2
1
0
DEFAULT
0
0
0
0
0
0
0
0
HP_GAIN (03h) (SET = LOGIC 1, CLEAR = LOGIC 0)
Address
Register
4:0
HP_GAIN
5
HP_MUTE
Description
Programs the gain of the headphone amplifier. Gain is set as follows:
4:0
Headphone Gain
4:0
Headphone Gain
00000
–46.5dB
10000
–22.5dB
00001
–45dB
10001
–21dB
00010
–43.5dB
10010
–19.5dB
00011
–42dB
10011
–18dB
00100
–40.5dB
10100
–16.5dB
00101
–39dB
10101
–15dB
00110
–37.5dB
10110
–13.5dB
00111
–36dB
10111
–12dB
01000
–34.5dB
11000
–10.5dB
01001
–33dB
11001
–9dB
01010
–31.5dB
11010
–7.5dB
01011
–30dB
11011
–6dB
01100
–28.5dB
11100
–4.5dB
01101
–27dB
11101
–3dB
01110
–25.5dB
11110
–1.5dB
01111
–23dB
11111
0dB
If set the headphone amplifier is muted.
Defines if a high or low voltage at the HP_SENSE pin should indicate that a
headphone is plugged in.
6
HP_SENSE_TYPE
HP_SENSE_TYPE
HP_SENSE_IN
0
High = HP Plugged In
1
Low = HP Plugged In
The HP_SENSE_OUTPUT signal can be configured to appear on the GPIO pin.
7
HP_SENSE_OUTPUT If set, the polarity of the HP_CONNECTED output from the GPIO pin is reversed, so if
the headphone is connected a 0 is reported on the GPIO rather than a 1. This does not
alter the operation of the loudspeaker auto-muting function (as defined in Loudspeaker
Gain Register)
17
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LM4931
Loudspeaker Gain Register
This register configures the loudspeaker amplifier gain and muting conditions.
DEFAULT CHART FOR LS_GAIN (04h)
DATA BIT
7
6
5
4
3
2
1
0
DEFAULT
0
0
0
0
0
0
0
0
LS_GAIN (04h) (SET = LOGIC 1, CLEAR = LOGIC 0)
Address
Register
4:0
LS_GAIN
Description
Programs the gain of the loudspeaker amplifier. Gain is set as follows:
4:0
Loudspeaker Gain
4:0
Loudspeaker Gain
00000
–34.5dB
10000
–10.5dB
00001
–33dB
10001
–9dB
00010
–31.5dB
10010
–7.5dB
00011
–30dB
10011
–6dB
00100
–28.5dB
10100
–4.5dB
00101
–27dB
10101
–3dB
00110
–25.5dB
10110
–1.5dB
00111
–24dB
10111
0dB
01000
–22.5dB
11000
1.5dB
01001
–21dB
11001
3dB
01010
–19.5dB
11010
4.5dB
01011
–18dB
11011
6dB
01100
–16.5dB
11100
7.5dB
01101
–15dB
11101
9dB
01110
–13.5dB
11110
10.5dB
01111
–12dB
11111
12dB
5
LS_MUTE
If set the loudspeaker amplifier is muted.
6
LS_AUTO_MUTE
If set the loudspeaker amplifier is automatically muted when the headphone sense
detects that the headphones have been connected. This uses the conditions set by
HP_SENSE_TYPE to determine if the headphones are connected.
7
LS_PWDN
If set the Class D amplifier is disabled. If an external amplifier is being used, an enable
signal can be accessed on the GPIO.
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18
This register is used to control the frequency divider (M divider) which sits before the PLL phase comparator, it also allows the
3 MSBs of the N_divider’s modulus input to be programmed. See Figure 4 for further explanation.
DEFAULT CHART FOR PLL_M (05h)
DATA BIT
7
6
5
4
3
2
1
0
DEFAULT
0
0
0
0
0
0
0
0
PLL_M (05h) (SET = LOGIC 1, CLEAR = LOGIC 0)
Address
Register
Description
4:0
PLL_M
Programs the PLL input divider from divide by 4 to divide by 31. It is also
possible to bypass the divider if PLL_M = 1 or divide by 2 if PLL_M = 2. Setting
PLL_M = 3 will default to divide by 4.
7:5
PLL_N_MOD1
Programs the modulus bits [4:2] of the PLL feedback divider .
This register is used to control the integer of the PLL feedback divider (fractional N divider).
DEFAULT CHART FOR PLL_N (06h)
DATA BIT
7
6
5
4
3
2
1
0
DEFAULT
0
0
0
0
0
0
0
0
PLL_N (06n) (SET = LOGIC 1, CLEAR = LOGIC 0)
Address
Register
Description
6:0
PLL_N
Programs the PLL feedback divider from divide by 4 to divide by 127, PLL_N
inputs from 0 to 3 are rounded to 4.
7
FAST_VCO
If set the VCO operates best at frequencies up to 100MHz, normally the VCO is
tuned for outputs around 50MHz.
This register is used to control the PLL output divider (P divider), it also allows the 2 LSBs of the N divider’s modulus input to be
programmed.
DEFAULT CHART FOR PLL_P (07h)
DATA BIT
7
6
5
4
3
2
1
0
DEFAULT
0
0
0
0
0
0
0
0
PLL_P (07h) (SET = LOGIC 1, CLEAR = LOGIC 0)
Address
Register
Description
3:0
PLL_P
Programs the PLL output divider from divide by 4 to divide by 15, PLL_P inputs
from 0 to 3 are rounded to 4. It is recommended that P = 4 to keep the VCO
around its nominal frequency of 50MHz.
5:4
PLL_N_MOD2
Programs the PLL feedback divider modulus bits [1:0].
7:6
DITHER_LEVEL
Programs the magnitude of the PLL dither level.
7:6
PLL Dither Level
00
32
01
16
10
48
11
0
The N divider is a fractional divider as such:
N = PLL_N + (PLL _NMOD/32)
If the Modulus input is zero then the N divider is simpler an integer N divider. The output from the PLL is determined by the
following formula:
Fout = (Fin*N)/(PLL_M*PLL_P)
19
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LM4931
PLL Configuration Registers
LM4931
PLL Configuration Registers
(Continued)
20100963
FIGURE 4.
AUDIO CLOCK REQUIREMENTS
Input Clock
Sample Rate
Required Clock
M
N
N_MOD
P
Output Clock
Error (Hz)
12.000MHz
48kHz
12.288MHz
14
57
11
4
12.288MHz
0.2Hz
13.000MHz
48kHz
12.288MHz
4
15
4
4
12.288MHz
4.1Hz
14.400MHz
48kHz
12.288MHz
9
30
23
4
12.288MHz
1.9Hz
16.200MHz
48kHz
12.288MHz
11
33
12
4
12.288MHz
0.3Hz
16.800MHz
48kHz
12.288MHz
8
23
13
4
12.288MHz
1.1Hz
19.200MHz
48kHz
12.288MHz
13
33
9
4
12.288MHz
1.8Hz
19.440MHz
48kHz
12.288MHz
11
27
26
4
12.288MHz
0.3Hz
19.680MHz
48kHz
12.288MHz
13
32
15
4
12.288MHz
0.7Hz
19.800MHz
48kHz
12.288MHz
16
39
23
4
12.287MHz
0.1Hz
12.000MHz
44.1kHz
11.2896MHz
8
32
27
4
11.290MHz
1.7Hz
13.000MHz
44.1kHz
11.2896MHz
6
20
27
4
11.290MHz
2.9Hz
14.400MHz
44.1kHz
11.2896MHz
14
43
29
4
11.290MHz
2.3Hz
16.200MHz
44.1kHz
11.2896MHz
15
41
26
4
11.289MHz
0.9Hz
16.800MHz
44.1kHz
11.2896MHz
17
57
4
5
11.290MHz
1.6Hz
19.200MHz
44.1kHz
11.2896MHz
15
35
9
4
11.290MHz
0.8Hz
19.440MHz
44.1kHz
11.2896MHz
15
34
27
4
11.289MHz
1.6Hz
19.680MHz
44.1kHz
11.2896MHz
7
16
2
4
11.290MHz
0.2Hz
19.800MHz
44.1kHz
11.2896MHz
17
48
15
5
11.289MHz
3.0Hz
1.536MHz
48kHz
12.288MHz
1
32
0
4
12.288MHz
0Hz
1.4112MHz
44.1kHz
11.2896MHz
1
32
0
4
11.2896MHz
0Hz
I2S Inputs:
Other examples:
19.44MHz
32kHz
8.192MHz
17
50
5
4
8.193MHz
6Hz
24.576MHz
44.1kHz
11.2896MHz
14
26
11
4
11.2868MHz
2.3Hz
66MHz
48kHz
12.288MHz
12
17
28
4
12.288MHz
4.1Hz
100MHz
48kHz
12.288MHz
24
23
19
4
12.288MHz
1.6Hz
100MHz
44.1kHz
11.2896MHz
31
28
0
4
11.2899MHz
2.8Hz
Please note that the Error (Hz) column is relative to sample rate. For instance:
If the Sample Rate is 48kHz and the input clock is 12.000MHz, then the solution shown in the table is:
Output Clock = 12.000MHz * (57 + 11/32) / (14 * 4) = 12.287946MHz. = 47.99979kHz * 256
Error = 48kHz – 47.99979kHz = 0.2Hz
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20
LM4931
Clock Divider Configuration Registers
This register is used to control the multiplexers in the clock module.
DEFAULT CHART FOR CLK_MUX (08h)
DATA BIT
7
6
5
4
3
2
1
0
DEFAULT
0
0
0
0
0
0
0
0
CLK_MUX (08h) (SET = LOGIC 1, CLEAR = LOGIC 0)
Address
Register
Description
Programs the PLL input multiplexer to select. (Note 12)
0
PLL_INPUT
PLL_INPUT
PLL Input Source
0
MCLK
1
I2S Input Clock
If set the master clock is divided by two, for example allowing for a
24.576MHz or PCI clock to be used. (Note 12, 15)
1
FAST_CLOCK
FAST_CLOCK
MCLK Frequency
0
Normal
1
Divided by 2
Selects which clock is passed to the audio sub-system: (Note 12)
AUDIO_CLK_SEL
2
AUDIO_CLK_SEL
Audio Sub-system
Input Source
0
PLL Output
1
MCLK / MCLK/2
Selects which clock is passed to the voice sub-system: (Note 12)
VOICE_CLK_SEL
3
4
VOICE_CLK_SEL
PLL_DISABLE
Audio Sub-system
Input Source
0
PLL Output
1
MCLK / MCLK/2
Powers down the PLL if it is not required.
Programs the Q divider (divides from the PLL output frequency of
12.288MHz).
6:5
7
Q_DIV
RSVD
6:5
Divide Value
00
12 (1.024MHz/8kHz)
01
8 (1.536MHz/12kHz)
10
6 (2.048MHz/16kHz)
11
4 (3.072MHz/24kHz)
RESERVED (Note 14)
Note 15: For inputs greater than 50Mhz, the input clock divider FAST_CLOCK should be set.
21
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LM4931
Clock Divider Configuration Registers
(Continued)
20100964
FIGURE 5.
The voice codec operates at 128*fs, so it requires a 1.024MHz clock to operate on 8kHz data. The Audio DAC also operates at
128*fs, i.e. 6.144MHz for 48kHz data, 5.6448MHz for 44.1kHz data etc. It is expected that the PLL is used to drive the audio
system unless a 12.288MHz or 24.576MHz (AC’97) master clock is supplied and the sample rate is always 48kHz, in which case
the PLL can be bypassed to reduce power.
The voice codec is always driven from the divided down clock from the PLL output or a divided down version of the master clock.
When using the voice codec for 8kHz operation, program the PLL as you would for 48kHz operation and use Q to divide by
(2*FSaudio/FSvoice).
The PLL can also use the I2S clock input as a source. In this case, the audio DAC uses the clock from the output of the PLL and
the voice codec either uses a divided by 6 clock or a divided version of the MCLK pin.
MCLK must be less than or equal to 50MHz if the input divider is to be used, otherwise MCLK can be any frequency up to 25MHz.
The comparison frequency after the M divider should be less than 5MHz
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22
LM4931
Digital Interface Configuration Registers
This register is used to control the format of the PCM, I2S, and GPIO interfaces.
DEFAULT CHART FOR INTERFACES (09h)
DATA BIT
7
6
5
4
3
2
1
0
DEFAULT
0
0
0
0
0
0
0
0
INTERFACES (09h) (SET = LOGIC 1, CLEAR = LOGIC 0)
Address
Register
Description
If set the data is assumed to be in either A-law or
u-law 8-bit companded form, otherwise it is assumed
to be up to 16 bits of MSB first linear 2’s
complement PCM format. (Note 12)
0
PCM_COMPANDED
1
PCM_ALAW_ULAW
If set the data is assumed to be A-law, otherwise it is
u-law companded. (Note 12)
2
PCM_MS
When set the PCM operates in a master mode.
3
PCM_LONG
When set the PCM operates in long mode. (Note 12)
4
I2S_MS
When set the I2S operates in a master mode.
This selects if each word is 16 or 32 bits long: (Note
16)
5
2
I S_RES
I2S_RES
Word Length
0
16
1
32
In 32 bit mode the 18 MSBs are passed to the DAC.
In 16 bit mode all 16 bits are passed to the DAC.
6
RSVD
RESERVED (Note 14)
7
RSVD
RESERVED (Note 14)
Note 16: Always operate the digital IO at the lowest frequency possible to save power and reduce noise. Obviously this can limit the resolution of the I2S interface
from 18 bits to 16 bits, but if only 16 bit data is available use the 16 bit mode to reduce I/O power.
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LM4931
Power Management Configuration Registers
This register is used to control the power management settings.
DEFAULT CHART FOR PMC_CONFIG (0Ah)
DATA BIT
7
6
5
4
3
2
1
0
DEFAULT
0
0
0
0
0
0
0
0
PMC_CONFIG (0Ah) (SET = LOGIC 1, CLEAR = LOGIC 0)
Address
0
Register
ZXD_DISABLE
Description
If set then zero cross detection is ignored when changing modes or
gains. (Note 19)
Set to accommodate a selected bypass capacitor value to give correct
turn-on delay and click/pop performance. Value is set as follows: (Note
17)
2:1
CAP_SIZE
2:1
Delay
00
short
0.1µF/25ms
Capacitor Size/Time
01
medium
1µF/100ms
10
long
2.2µF/200ms
11
test
Test Mode/1ms
Set the GPIO port function: (Note 18)
5:3
GPIO_SETUP
5:3
GPIO
000
HP_CONNECTED
001
VC_CLOCK
010
GPIO_DATA
011
EXT_LS_ENABLE
100
VOICE_ADC_SD
101
VOICE_DAC_SD
110
DAC_LEFT_SD
111
DAC_RIGHT_SD
6
RSVD
RESERVED (Note 14)
7
CLASS_D_DITHER
When set enables dither in the class D amplifier
Note 17: The effect of CAP_SIZE will vary with the audio clock frequency. The delays quoted are for a 12.288MHz MCLK. These will scale inversely to the MCLK
frequency. For example if used in a 44.1kHz application where the PLL output is 11.2896MHz, “01” or 100ms will be 100ms*11.2896/12.288 = 108.8ms. It is
suggested that to save power earlier during the shutdown cycle, the PLL can be disabled and the MCLK or MCLK/2 can be used to bypass the PLL and also provide
longer shutdown times for further reduced click and pop.
Note 18: VC_CLOCK is only supplied over the GPIO port if the voice codec is enabled.
Note 19: To ensure a successful transition into Powerdown Mode, ZXD_DISABLE must be set whenever there is no audio input signal present.
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LM4931
Audio Interfaces
I2S
The LM4931 supports both master and slave I2S transmission at either 16 or 32 bits per word at clock rates up to 3.072MHz
(48kHz stereo, 32bit). The basic format is shown below:
20100907
FIGURE 6.
PCM
The PCM interface is both master and slave and is compatible with National Semiconductor’s AAI, Motorola’s SSI, and Texas
Instrument’s McBSP audio codec interfaces. The protocol is short frame sync MSB first 2’s complement 16 bit linear. The MSB
always follows the sync pulse. In the case of companded data the first 8 bits are used and the interface can be slowed to 8 clock
cycles per sync. In PCM_LONG mode the PCM_SYNC signal is inverted relative to that shown below.
20100965
FIGURE 7.
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LM4931
Typical Performance Characteristics
MIC PreAmp + ADC Frequency Response
(MIC Gain = 6dB)
MIC PreAmp + ADC Frequency Response Zoom
(MIC Gain = 6dB)
20100901
20100925
MIC PreAmp + ADC Frequency Response
(MIC Gain = 36dB)
MIC PreAmp + ADC Frequency Response Zoom
(MIC Gain = 36dB)
20100933
20100934
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26
(Continued)
MIC PreAmp + ADC Frequency Response High Cutoff
(MIC Gain = 6dB)
MIC PreAmp + ADC Frequency Response High Cutoff
(MIC Gain = 36dB)
20100935
20100936
MIC PreAmp + ADC Frequency Response Low Cutoff
(MIC Gain = 6dB)
MIC PreAmp + ADC Frequency Response Low Cutoff
(MIC Gain = 36dB)
20100937
20100942
ADC THD+N vs MIC Input Voltage
(MIC Gain = 6dB), AVDD = 3V
ADC THD+N vs MIC Input Voltage
(MIC Gain = 6dB), AVDD = 5V
20100943
20100944
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LM4931
Typical Performance Characteristics
LM4931
Typical Performance Characteristics
(Continued)
ADC THD+N vs MIC Input Voltage
(MIC Gain = 36dB, AVDD = 5V)
ADC THD+N vs MIC Input Voltage
(MIC Gain = 36dB, AVDD = 3V)
20100945
20100946
MIC PreAmp + ADC PSRR vs Frequency
Top Trace = 36dB MIC Gain, Bottom Trace = 6dB MIC
Gain, AVDD = 3V
MIC PreAmp + ADC PSRR vs Frequency
Top Trace = 36dB MIC Gain, Bottom Trace = 6dB MIC
Gain, AVDD = 5V
20100947
20100948
Headphone Sense In Hysteresis Loop
(AVDD = 5V)
Headphone Sense In Hysteresis Loop
(AVDD = 3V)
20100927
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20100928
28
(Continued)
I2S DAC Frequency Response
( Handsfree Output)
I2S DAC Frequency Response Zoom
(Handsfree Output)
20100974
20100973
I2S DAC Frequency Response Zoom
(Headphone Output)
I2S DAC Frequency Response Zoom
(Headphone Output)
20100932
20100931
THD+N vs I2S Input Voltage
(Handsfree Output, 0dB Handsfree Gain, AVDD = 5V)
THD+N vs I2S Input Voltage
(Handsfree Output, 0dB Handsfree Gain, AVDD = 3V)
20100978
20100977
29
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LM4931
Typical Performance Characteristics
LM4931
Typical Performance Characteristics
(Continued)
THD+N vs I2S Input Voltage
(Headphone Output, 0dB Headphone Gain, AVDD = 5V)
THD+N vs I2S Input Voltage
(Headphone Output, 0dB Headphone Gain, AVDD = 3V)
20100979
20100980
I2S DAC Crosstalk
(Top Trace = Left to Right, Bottom Trace = Right to Left)
MIC Bias Dropout Voltage vs
MIC Bias Current
20100981
20100941
PCM DAC Frequency Response
(Handsfree Output)
PCM DAC Frequency Response Zoom
(Handsfree Output)
20100984
20100983
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30
(Continued)
PCM DAC Frequency Response
(Headphone Output)
PCM DAC Frequency Response Zoom
(Headphone Output)
20100950
20100951
THD+N vs PCM Input Voltage
(Handsfree Output, 0dB Handsfree Gain, AVDD = 3V)
THD+N vs PCM Input Voltage
(Handsfree Output, 0dB Handsfree Gain, AVDD = 5V)
20100987
20100988
THD+N vs PCM Input Voltage
(Headphone Output, 0dB Headphone Gain, AVDD = 3V)
THD+N vs PCM Input Voltage
(Headphone Output, 0dB Headphone Gain, AVDD = 5V)
20100989
20100990
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LM4931
Typical Performance Characteristics
LM4931
Typical Performance Characteristics
(Continued)
PSRR vs Frequency
(AVDD = 5V, RL = 32Ω, Headphone Output, Mode 6)
PSRR vs Frequency
(AVDD = 3V, RL = 32Ω, Headphone Output, Mode 6)
20100991
20100992
PSRR vs Frequency
(AVDD = 3V, RL = 32Ω, Headphone Output, Mode 7)
PSRR vs Frequency
(AVDD = 5V, RL = 32Ω, Headphone Output, Mode 7)
20100993
20100994
PSRR vs Frequency
(AVDD = 3V, RL = 8Ω, Handsfree Output)
PSRR vs Frequency
(AVDD = 5V, RL = 8Ω, Handsfree Output)
20100995
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20100996
32
(Continued)
THD+N vs Frequency
(AVDD = 5V, RL = 8Ω, PO = 400mW, Handsfree Output)
THD+N vs Frequency
(AVDD = 3V, RL = 32Ω, PO = 200mW, Handsfree Output)
20100998
20100997
THD+N vs Frequency
(AVDD = 3V, RL = 8Ω, PO = 7.5mW, Headphone Output)
THD+N vs Frequency
(AVDD = 5V, RL = 32Ω, PO = 7.5mW, Headphone Output)
20100999
201009A0
THD+N vs Output Power
(AVDD = 3V, RL = 8Ω, f = 1kHz, Handsfree Output)
THD+N vs Output Power
(AVDD = 5V, RL = 8Ω, f = 1kHz, Handsfree Output)
201009A2
201009A1
33
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LM4931
Typical Performance Characteristics
LM4931
Typical Performance Characteristics
(Continued)
THD+N vs Output Power
(AVDD = 5V, RL = 32Ω, f = 1kHz, Headphone Output)
THD+N vs Output Power
(AVDD = 3V, RL = 32Ω, f = 1kHz, Headphone Output)
201009A3
(AVDD
201009A4
THD+N vs Frequency
(AVDD = 3.3V, RL = 32Ω, PO = 7.5mW, Headphone
Output)
THD+N vs Frequency
= 3.3V, RL = 8Ω, PO = 200mW, Handsfree Output)
201009A5
201009A8
THD+N vs Output Power
(AVDD = 3.3V, RL = 32Ω, f = 1kHz, Headphone Output)
THD+N vs Output Power
(AVDD = 3.3V, RL = 8Ω, f = 1kHz, Handsfree Output)
201009A6
201009A7
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34
LM4931
Application Information
REFERENCE DESIGN BOARD AND LAYOUT
LM4931ITL Board Layout
201009I8
FIGURE 8. LM4931ITL Demo Board Schematic
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LM4931
Application Information
(Continued)
20100967
FIGURE 9. LM4931ITL Demo Board Composite View
20100970
FIGURE 10. LM4931ITL Demo Board Silkscreen
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36
LM4931
Application Information
(Continued)
20100971
FIGURE 11. LM4931ITL Demo Board Top Layer
20100966
FIGURE 12. LM4931ITL Demo Board Bottom Layer
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LM4931
Application Information
(Continued)
20100968
FIGURE 13. LM4931ITL Demo Board Inner Layer 1
20100969
FIGURE 14. LM4931ITL Demo Board Inner Layer 2
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38
LM4931
Application Information
(Continued)
LM4931 DEMO BOARD BILL OF MATERIALS
Part Description
QTY
Reference Designator
Cer Cap 10nF 50V 10% 0805
1
C15
Cer Cap 150nF 50V 10% 0805
1
C12
Cer Cap 68pF 50V 10% 0805
1
C16
Cer Cap 0.022uF 50V 10% 0805
2
C13, C14
Cer Cap 0.1uF 50V 10% 0805
4
C4, C6, C17, C19
Tant Cap 1uF 16V 10% Case=A 3216
9
C1–C3, C5, C7–C9, C18, C20
Tant Cap 47uF 16V 10% Case=C 6032
2
C10–C11
Res 22.6 ohm 1/10W 1% 0805
1
R12
Res 300 ohm 1/10W 1% 0805
1
R11
Res 422 ohm 1/10W 1% 0805
1
R13
Res 1K Ohm 1/10W 1% 0805
2
R9, R10
Res 2K Ohm 1/10W 1% 0805
2
R1, R4
Res 5K Ohm 1/10W 1% 0805
4
R2, R6, R8, R99
L1, L2
Inductor 1mH
2
Stereo Headphone Jack
1
P1
Header 1 X 2
22
JP3, JP5–JP10, Jp14, S1, S3–S15
Header 1 X 3
4
Header 1 X 5
4
I2C/SPI CONTROL INTERFACE (JP11)
Pin
Function
1
VDD_D
2
SCL/SCK
3
VSS_D
4
ADDR/ENB
5
VSS_D
6
SDA/SDI
PCM INTERFACE (JP12)
Pin
Function
1
MCLK
2
PCM_CLK
3
PCM_SDI
4
PCM_SYNC
5
PCM_SDO
6
VSS_D
7
VSS_D
8
VSS_D
9
VSS_D
10
VSS_D
I2S INTERFACE (JP13)
Pin
Function
1
MCLK
2
I2S_CLK
3
I2S_SDI
4
I2S_WS
39
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LM4931
Application Information
(Continued)
I2S INTERFACE (JP13) (Continued)
5
VSS_D
6
VSS_D
7
VSS_D
8
VSS_D
9
VSS_D
10
VSS_D
MIC JACK (JP1)
Pin
Function
1
VSS_HP
2
MIC_N
3
MIC_P
EXTERNAL MASTER CLOCK INPUT MCLK/XTAL (JP3)
Pin
Function
1
VSS_D
2
MCLK
DIGITAL SUPPLY VOLTAGE AND (JP7)
Pin
Function
1
VDD_D
2
VSS_D
PLL SUPPLY VOLTAGE AND GND (JP9)
Pin
Function
1
VDD_PLL
2
VSS_PLL
ANALOG SUPPLY VOLTAGE AND GND MIC AND HEADPHONE (JP8)
Pin
Function
1
VDD_A
2
VSS_A
ANALOG SUPPLY VOLTAGE AND GND FOR LOUDSPEAKER (JP10)
Pin
Function
1
VDD_LS
2
VSS_LS
ALTERNATE STEREO HEADPHONE OUTPUT (JP15)
Pin
Function
1
HPR
2
VSS_HP
3
HPL
LOUDSPEAKER DIRECT OUTPUT (JP5)
www.national.com
Pin
Function
1
LS+
2
LS-
40
LM4931
Application Information
(Continued)
LOUDSPEAKER FILTERED OUTPUT — FOR MEASUREMENT PURPOSES (JP6)
Pin
Function
1
Filtered LS+
2
Filtered LSMULTI-USE PORT GPIO (JP14)
Pin
Function
1
VSS_D
2
GPIO
PCM LOOPBACK JUMPER
Pin
Function
1
PCM_SDI
2
PCM_SDO
MODE Select Jumper (S1)
Jumper IN = LOW
Jumper OUT = HIGH
Crystal MCLK Jumper (S13)
Jumper IN = MCLK Supplied by on-board crystal oscillator
Jumper OUT = MCLK supplied by other source, crystal oscillator isolated
MCLK to PCM Bus and I2S Bus Jumper (S14)
Jumper IN = MCLK connected to PCM bus and I2S bus
Jumper OUT = MCLK isolated from PCM bus and I2S bus
PLL FILTER SELECT JUMPERS (S6–S9)
Jumper
IN/OUT
Function
S6 + S7
IN
2nd Order Filter Select
S8 + S9
OUT
S6 + S7
OUT
S8 + S9
IN
3rd Order Filter Select
POWER SUPPLY JUMPERS (S3–S5, S10–S12)
Jumper
Function
S3
connects VDD_D and VDD_PLL
S4
connects VDD_PLL and VDD_LS
S5
connects VDD_A and VDD_LS
S10
connects VSS_D and VSS_PLL
S11
connects VSS_PLL and LSGND
S12
connects VSS_A and LSGND
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LM4931
Application Information
bit data as shown on Figure 2 in the Three Wire, SPI
Interface timing diagram. The first 8 bits corresponds to the
register address given on the System Control Table on
page 13. The second 8 bits contains the data to write to the
desired control register. These fields are transmitted subsequently to form a 16 bit word. For each SPI transfer, ENB is
lowered and the data bits are written to the SDI pin with the
most significant bit (MSB) first. All serial data are sampled at
the rising edge of the SCK signal. Once all the data bits have
been sampled, ENB transitions from logic-high to logic-low
to complete the SPI sequence. All 16 bits must be received
before any data latch can occur. Any excess CLK and DATA
transitions will be ignored after the sixteenth rising clock
edge has occurred. For any data sequence longer than 16
bits, only the first 16 bits will get loaded into the shift register
and the rest of the bits will be disregarded.
(Continued)
LM4931ITL DEMO BOARD OPERATION
The LM4931ITL demo board is a complete evaluation platform, designed to give easy access to the control pins of the
part and comprises all the necessary external passive components. Besides the separate analog (JP8), digital (JP7),
PLL (JP9) and Loudspeaker (JP10) supply connectors, the
board features seven other major input and control blocks:
an SPI/I2C compatible selectable interface bus (JP11) for the
control lines, a PCM interface bus (JP12) for voiceband
digital audio, an I2S interface bus (JP13) for full-range digital
audio, an analog mic jack input (JP1) for connection to an
external microphone, a high efficiency class D BTL mono
output (JP5) for connection to an external speaker, a stereo
headphone output (JP15 or P1), and an external MCLK input
(JP3) for use in place of the crystal on the demoboard.
SPI Operational Requirements
SPI/I2C Interface Bus (JP11)
This is the main control bus for the LM4931. This interface
may either be configured as a two-wire, I2C compatible
interface by setting MODE = 0 (S1 = IN) or a three-wire SPI
interface by setting MODE = 1 (S1 = OUT).
1. The data bits are transmitted with the MSB first.
2. The maximum clock rate is 4MHz for the SCK pin.
3. SCK must remain logic-high for at least 500ns (tSPICH )
after the rising edge of SCK, and SCK must remain logic-low
for at least 500ns (tSPICL) after the falling edge of SCK.
4. The serial data bits are sampled at the rising edge of SCK.
Any transition on SDI must occur at least 100ns
(tSPISETHOLDD) before the rising edge of SCK. Also, any
transition on SDI must occur at least 100ns (tSPISETD) after
the rising edge of SCK and stabilize before the next rising
edge of SCK.
5. ENB should be logic-low only during serial data transmission.
6. ENB must be logic-low at least 100ns (tSPISETENB ) before
the first rising edge of SCK, and ENB has to remain logic-low
at least 100ns (tSPIHOLDENB) after the sixteenth rising edge
of SCK.
7. If ENB remains logic-high for mtore than 10ns before all
16 bits are transmitted then the data latch will be aborted.
8. If ENB is logic-low for more than 16 SCK pulses then only
the first 16 data bits will be latched and activated when ENB
transitions to logic-high.
9. ENB must remain logic-low for at least 100ns (tSPIHOLDENB ) to latch in the data.
10. Coincidental rising or falling edges of SCK and ENB are
not allowed. If SCK is to be held logic-high after the data
transmission, the falling edge of SCK must occur at least
100ns before ENB transitions to logic-low for the next set of
data.
I2C Compatible Mode (MODE = 0)
The two-wire I2C compatible interface consists of an SDA
line (data) and SCL line (clock). Each transmission from the
baseband controller to the LM4931 is given MSB first and
must follow the timing intervals given in the Electrical Characteristics section of the datasheet to create the start and
stop conditions for a proper transmission. The start condition
is detected if SCL is high on the falling edge of SDA. The
stop condition is detected if SCL is high on the rising edge of
SDA. Repeated start signals are handled correctly. Data is
then transmitted as shown in Figure 3 for the Two Wire I2C
Compatible Interface. After the start condition has been
achieved the chip address is sent, followed by a set write bit,
wait for ack (SDA will be pulled low by LM4931), data bits
15-8, wait for ACK (SDA will be pulled low by LM4931), data
bits 7-0, wait for ACK (SDA will be pulled low by LM4931)
and finally the stop condition is given.
This same sequence follows for any I2C control bus transmission to the LM4931. The chip address is hardwire selected by the ADDR Select pin (JP11, pin 4) which may be
software enabled high or low with the LM4931 demonstration control software. If ADDR is low, then the chip address is
set to 0010000b. If ADDR is high, the address is set to
1110000b. The 11 control registers are shown on page 13 in
the System Control Table. Data is sampled only if the
address is in range and the R/W bit is clear. Data for each
register is given in the System Control section of the
datasheet.
Pull-up resistors are required to achieve reliable operation.
10kΩ pull-up resistors on the SDA and SCL lines achieves
best results when used with National’s parallel-to-serial interface board. Lower value pull-up resistors will decrease the
rise and fall times on the bus which will in turn decrease
susceptibility to bus noise that may cause a false trigger. The
cost comes at extra current use. Control bus reliability will
thus depend largely on bus noise and may vary from design
to design. Low noise is critical for reliable operation.
LM4931 Evaluation Software
The LM4931 demoboard can be easily evaluated with the
accompanying LM4931 Evaluation Software. The Windows 95/98/2000/NT/XP compatible software is a GUI that
allows easy access to all the I2C/SPI internal registers of the
device. The GUI controls the PC parallel port to deliver the
appropriate I2C/SPI commands via the National Semiconductor I2C/SPI Interface Card, in order to properly program
the LM4931.
PCM Bus Interface (JP12)
PCM_SDO, PCM_SYNC, PCM_SDI, and PCM_CLK form
the PCM interface bus for simple communication with most
baseband ICs with voiceband communications and follow
the PCM-1900 communications standard. The PCM interface features a frame length of 16 bits, A-law and u-law
companded, linear mode, short or long frame sync, an
SPI Mode (MODE = 1)
The SPI interface consists of three lines: the serial data input
pin (SDI), the clock input pin (SCK), and the SPI enable pin
(ENB).The serial data bits are organized into two fields of 8
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42
often render conventional audio measurement techniques
useless. This output band-limits the output to 20kHz, filtering
out the switching noise for measurement purposes. This
measurement output is not intended to provide power to a
load.
(Continued)
energy-saving power down mode, and master or slave operation. PCM_SYNC is the word sync line for the bus. It may
be set in the INTERFACES (09h) register (bit 3 PCM_LONG) for short or long frame sync. A short frame sync is 1
PCM_CLK cycle (PCM_LONG=0), a long frame sync is an
inverted version of short sync (PCM_LONG=1). This is illustrated by Figure 7 in the PCM timing diagram under the
Audio Interfaces section. PCM_CLK is the bit clock for the
bus. Its frequency is fixed at 128kHz and may be generated
by the LM4931 when the PCM section is set to operate in
master mode by setting bit 2 of the INTERFACES (09h)
register. Clearing this same bit (bit 2) places the PCM section into slave mode where an external clock must be provided.
The other two lines, PCM_SDO and PCM_SDI, are for serial
data out and serial data in, respectively. The type of data
may also be set in the INTERFACES (09h) register by bits 0
and 1. Bit 0 controls whether the data is linear or companded. If set to 1, the 8 MSBs are presumed to be companded data and the 8 LSBs are ignored. If cleared to 0, the
data is treated as 2’s complement PCM data. Bit 1 controls
which PCM law is used if Bit 0 is set for companded (G711)
data. If set to 1, the companded data is assumed to be A-law.
If cleared to 0, the companded data is treated as µ-law.
Stereo Headphone Out (JP15 or P1)
This is the stereo headphone output. Each channel is singleended, with 47uF DC blocking capacitors mounted on the
demo board. The jack (P1) features a typical stereo headphone pinout. An alternate, pinned connection is also provided (JP15).
Headphone sense is incorporated into the jack on the demo
board. In this application HP_SENSE is pulled low by the
1kΩ resistor when no headphone is present. This gives a
corresponding logic low output on the HP_SENSE pin.
When a headphone is placed in the jack the 1kΩ pull-down
is disconnected and a 100kΩ pull-up resistor creates a high
voltage condition on HP_SENSE. This information may be
placed on the GPIO pin to reliably drive an external microcontroller with headphone status.
It is important to note that if using the alternate connection
(JP15) for stereo headphone operation, HP sense is still tied
to the mini-jack, requiring a physical plug to break the connection. HP sensing will then require a plug be placed in the
jack (dummy plug).
I2S Interface Bus (JP13)
The I2S standard provides a uni-directional serial interface
designed specifically for digital audio. For the LM4931, the
interface provides access to a 48kHz, 18 bit full-range stereo
audio DAC. This interface uses a three port system of clock
(I2S_CLK), data (I2S_SDI), and word (I2S_WS). The clock
and word lines can be either master or slave as set by bit 4
in the INTERFACES (09h) register.
A bit clock (I2S_CLK) at 32 or 64 times the sample frequency
is generated by the I2S system master (unless set as a
slave) and a word select (I2S_WS) line is driven at a frequency equal to the sampling rate of the audio data, up to
48kHz. The word length is set by bit 5 of the INTERFACES
(09h) register. When bit 5 is cleared, a word length of 16 bits
is selected. When set, the word length is set to 32 bits. All
18MSBs are passed to the DAC when the I2S interface is set
to 32 bit word mode. In 16 bit mode, all 16 bits are sent to the
DAC. The word line is registered to change on the negative
edge of the bit clock. The serial data (I2S_SDI) is sent MSB
first, again registered on the negative edge of the bit clock,
delayed by 1 bit clock cycle relative to the changing of the
word line (see Figure 6).
MIC Jack (JP1)
This jack is for connection to an external microphone like the
kind typically found in mobile phones. Pin 1 is GND, pin 2 is
the negative input pin, and pin 3 is the positive pin, with
phantom voltage supplied by MIC_BIAS on the LM4931.
GPIO (JP14)
This pin provides simple status updates from the LM4931 to
an external microcontroller if desired. The GPIO output may
be configured in the PMC_CONFIG (0Ah) register. Bits of
the PMC_CONFIG (0Ah) register may be used to set the
GPIO to output information regarding whether the headphone is connected, the voice-codec clock, an external LS
enable signal, and shutdown status for the voiceband ADC,
voiceband DAC, and the Left and Right channels of the full
range-audio DAC. The voice-codec clock is only provided
over the GPIO port if the voice codec is enabled. These
outputs can be useful for simple software/driver development to monitor mode changes, or as a simple debugging
tool.
BASIC OPERATION
The LM4931 is a highly integrated audio subsystem with
many different operating modes available. These modes
may be controlled in the BASIC_CONFIG (00h) register by
bits 3:0. These mode settings are shown in the BASIC_CONFIG (00h) register table and are described here below:
MCLK/XTAL_IN (JP3)
This is the input for an external Master Clock. The jumper at
S13 must be removed (disconnecting the onboard crystal
from the circuit) when using an external Master Clock. Additionally, the jumper S14 may be used to connect the MCLK
with the PCM and I2S interface buses.
Powerdown Mode (0000b)
Part is powered down, analog outputs are not biased. This is
a minimum current mode. All part features are shut down.
High-Efficiency Class D BTL Mono Out (JP5)
This is the high-efficiency mono speaker output, designed for
use with an 8Ω speaker. The outputs are driven in bridgetied-load (BTL) mode, so both sides have signal. Outputs are
normally biased at one half AVDD when the LM4931 is in
active mode. The class D amplifier provides exceptional
power use savings versus standard class AB amplifiers. A
measurement output (JP6) is also provided, since the
switching characteristics of an unfiltered Class D output
Standby Mode (0001b)
The LM4931 is powered down, but outputs are still biased at
one half AVDD. This comes at some current cost, but provides a much faster turn-on time with zero "click and pop"
transients on the headphone out. Standby mode can be
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LM4931
Application Information
LM4931
Application Information
Powerdown prevent unwanted audio artifacts that may occur
during rapid mode changes with the outputs active. The
LM4931 also features a soft reset. This reset is enabled by
setting bit 4 of the BASIC_CONFIG (00h) register. DAC
dither may also be controlled in this register (bit 5).
(Continued)
toggled into and out of rapidly and is ideal for saving power
whenever continuous audio is not a requirement. All other
part functions are suspended.
The VOICE_CONFIG (01h) register is used to set various
configuration parameters on the voiceband and full-range
audio codecs. SIDETONE_ATTEN (bits 3:0) refers to the
level of signal from the MIC input that is fed back into the
analog audio output path (commonly used in headphone
applications and killed in hands-free applications). Setting
the AUTOSIDE bit (bit 4) automatically mutes the sidetone in
voice over mono speaker modes so feedback isn’t an issue.
Dither for the voice ADC and DAC may be disabled by
setting bits 6 or 7, respectively. Bit 5 is reserved.
Mono Speaker Mode (0010b)
Part is active. All analog outputs are biased. Audio from the
voiceband codec is routed to the mono speaker out. Stereo
headphone out is muted.
Headphone Call Mode (0011b)
Part is active. All analog outputs are biased. Audio from
voiceband codec is routed to the stereo headphones. Both
left and right channels are the same. Mono speaker out is
muted.
The MIC_GAIN (02h) register provides for microphone
preamplifier gains of 6dB to 36dB in 2dB steps (bits 3:0). A
quick mute bit is provided for the mic (bit 4) as well as a bit
to disable the high-pass filter on the voice ADC, allowing
wider bandwidth usage through the microphone input.
Conference Call Mode (0100b)
Part is active. All analog outputs are biased. Audio from the
voiceband codec is routed to the mono speaker out and to
the stereo headphones.
The HP_GAIN (03h) register provides settings for headphone control. Bits 4:0 set the gain of the headphone output
from –46.5dB to 0dB in 1.5dB steps. A quick mute bit is also
provided (bit 5). Additionally, the LM4931 may be configured
to react to a high or low HP_SENSE voltage (bit 6) and may
also provide this output on the GPIO pin in either positive or
negative form (bit 7). This will only be seen on the GPIO
output if it is configured to show HP_CONNECTED as described in the GPIO section.
The LS_GAIN (04h) register is used to set the mono class D
loudspeaker gain. Bits 4:0 set this from –34.5dB to +12dB in
1.5dB steps. A quick mute (bit 5) is provided as well as an
auto-mute bit (bit 6) that, if set, automatically mutes the
loudspeaker when headphone sense detects that headphones have been connected. A powerdown bit (bit 7) is also
provided to independently shutdown just the class D amplifier.
CLK_MUX (08h) is the clock divider register. Bit 0 sets the
PLL input source. When clear, MCLK is used, when set, the
I2S input clock is used. Bit 1 gives a divide by 2 for usage
with a faster MCLK (like 24.576MHz). Bit 2 selects which
clock is passed to the full range audio subsystem. If clear,
the PLL output is used. If set, MCLK (or MCLK/2 if set) is
used directly. Bit 3 does the same for the voice codec
subsystem. If clear, the PLL output is used. If set, MCLK or
MCLK/2 is used. Bit 4 powers down the PLL (if not needed).
Bits 6:5 program the Q divider, that can be further used to
divide down the PLL output frequency. Bit 7 is reserved.
The INTERFACES (09h) register controls all the digital interface configurations. This may be used to set the PCM
configuration and I2S configuration as stated above in the
PCM Bus Interface and I2S Bus Interface sections. Bits 6 is
reserved for test modes.
The PMC_CONFIG (0Ah) register controls various power
management responsibilities including bypass capacitor size
(bits 2:1). Zero crossing disable (bit 0) is also provided to
allow the LM4931 to change modes regardless of zero
crossing detect status. If set, the LM4931 will change modes
immediately without waiting for the outputs to cross zero.
Bits 6 is reserved.
L+R Mixed to Mono Speaker (0101b)
Part is active. All analog outputs are biased. Full-range audio
from the 18bit/48kHz audio DAC is mixed together and
routed to the mono speaker out. Stereo headphones are
muted.
Headphone Stereo Audio (0110b)
Part is active. All analog outputs are biased. Full-range audio
from the 18bit/48kHz audio DAC is sent to the stereo headphone jack. Each channel is heard discretely. The mono
speaker is muted.
L+R Mixed to Mono Speaker + Stereo Headphone
Audio (0111b)
Part is active. All analog outputs are biased. Full-range audio
from the 18bit/48kHz audio DAC is sent discretely to the
stereo headphone jack and also mixed together and sent to
the mono speaker out.
Mixed Mode (1000b)
Part is active. All analog outputs are biased. This provides
one channel (the left channel) of full range audio to the mono
speaker out. Audio from the voiceband codec is then sent to
the stereo headphones, the same on each channel.
Mixed Mode (1001b)
Part is active. All analog outputs are biased. Mixed voiceband and full-range audio (left channel only) is sent to the
mono speaker out. Audio from the voiceband codec only is
sent to the stereo headphones, the same on each channel.
Mixed Mode (1010b)
Part is active. All analog outputs are biased. Audio from the
voiceband codec is sent to the mono speaker out. The left
channel only of the full range audio is then sent to both the
left and right channels of the stereo headphone out.
REGISTERS
The LM4931 starts on power-up with all registers cleared in
Powerdown mode. Powerdown mode is the recommended
time to make setup changes to the digital interfaces (PCM
bus, I2S bus). Although the configuration registers can be
changed in any mode, changes made during Standby or
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PLL Registers
The PLL will accept incoming clock frequencies from 10MHz
to 25MHz. However, since the control clocks, PCM clocks,
and I2S clocks all operate at fixed, defined frequencies the
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momentarily from near ground potential to VDD. The two
outputs can pulse independently with the exception that they
both may never pulse simultaneously as this would result in
zero volts across the BTL load. The minimum width of each
pulse is approximately 160ns. However, pulses on the same
output can occur sequentially, in which case they are concatenated and appear as a single wider pulse to achieve an
effective 100% duty cycle. This results in maximum audio
output power for a given supply voltage and load impedance.
The LM4931 can achieve much higher efficiencies than
class AB amplifiers while maintaining acceptable THD performance. The short (160ns) drive pulses emitted at the
LM4931 outputs means that good efficiency can be obtained
with minimal load inductance. The typical transducer load on
an audio amplifier is quite reactive (inductive). For this reason, the load can act as it’s own filter, so to speak. This
"filter-less" switching amplifier/transducer load combination
is much more attractive economically due to savings in
board space and external component cost by eliminating the
need for a filter.
(Continued)
PLL must also be configured to match the incoming frequency and provide the correct output for all the parts of the
subsystem.
The first register, PLL_M (05h), sets the PLL input divider.
Bits 4:0 of this register are used to set the divider from 4 to
31. It is also possible to bypass the divider (M =1) by setting
PLL_M to 0001b. Setting PLL_M to 0010b gives a divide by
2. Setting PLL_M to 0011b gives a default divider of 4 (as
does setting to 0100b). Values above that are identical to
their base 10 integer values. Bits 7:5 programs the modulus
bits of the PLL feedback divider.
The second PLL register, PLL_N (06h), sets the PLL feedback divider. Bits 6:0 are used to set the PLL feedback
divider from divide by 4 to divide by 127. Values set from 0 to
3 are rounded to 4. This register also may be used to alter
the speed of the VCO. Setting bit 7 (FAST_VCO) tunes the
VCO operation for frequencies up to 100MHz. Normally it is
tuned for outputs around 50MHz.
The final PLL register, PLL_P (07h), sets the PLL output
divider. Bits 3:0 set this from divide by 4 to divide by 15.
Inputs of 0 to 3 are rounded to 4. It is also recommended that
P = 4 to keep the VCO around its nominal operating frequency (50MHz if PLL_N bit 7 is clear). The divider modulus
may be set by bits 5:4. Additionally, the dither level for the
PLL is controlled in this register in bits 7:6.
The Audio Clock Requirements table details how different
clock values may be generated for a given input clock.
CLASS D POWER DISSIPATION AND EFFICIENCY
In general terms, efficiency is considered to be the ratio of
useful work output divided by the total energy required to
produce it with the difference being the power dissipated,
typically, in the IC. The key here is “useful” work. For audio
systems, the energy delivered in the audible bands is considered useful including the distortion products of the input
signal. Sub-sonic (DC) and super-sonic components
( > 22kHz) are not useful. The difference between the power
flowing from the power supply and the audio band power
being transduced is dissipated in the LM4931 and in the
transducer load. The amount of power dissipation in the
LM4931 is very low. This is because the ON resistance of the
switches used to form the output waveforms is typically less
than 0.25Ω. This leaves only the transducer load as a potential "sink" for the small excess of input power over audio
band output power. The LM4931 dissipates only a fraction of
the excess power requiring no additional PCB area or copper plane to act as a heat sink.
PLL Loop Filter
The LM4931 demoboard features an onboard second and
third order PLL loop filter. Jumpers (S6-S9) configure the
demoboard to select between the second and third order
PLL loop filters. Reference values for the loop filters are
given in the LM4931 Demo Board Bill of Materials section.
For a more detailed discussion on how to optimize a second
and third order PLL loop filter, please refer to Note 20.
Note 20: http://www.national.com/appinfo/wireless/files/
DeansBook_4_01.pdf.
DUAL MICROPHONE SUPPORT
ANALOG INPUTS AND OUTPUTS
The LM4931 features a high-efficiency class D mono BTL
output for connection to an 8Ω external speaker. This output
can provide up to 1.1W of power into an 8 ohms load with a
5V analog supply. A single-ended stereo headphone output
is also featured, providing up to 26mW of power per channel
into 32Ω with a 5V analog supply. The MIC Jack input (JP1)
provides for a low level analog input. Pin 3 provides the
power to the MIC and the positive input of the LM4931. Gain
for the MIC preamp is set in the MIC_GAIN (02h) register.
The LM4931 can be configured to accept two separate
microphone inputs when used in conjunction with the
LMS4684. The LMS4684 is a dual SPDT analog switch that
will allow the MIC_P and MIC_N inputs of the LM4931 to
switch between a differential handset microphone and a
single-ended handsfree microphone. The MIC DETECT
block shown in Figure 16 can be implemented with a microphone jack’s mechanical control pin to set the voltage at the
IN1 and IN2 pins of the LMS4684. The voltage applied at the
IN1 and IN2 pins sets the position of the switch. For a more
detailed discussion on the operation of the analog switch,
please refer to the LMS4684 datasheet.
HIGH EFFICIENCY CLASS D AMPLIFIER FUNCTION
The class D mono output signals generated by the LM4931
consist of two, BTL connected, output signals that pulse
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LM4931
Application Information
LM4931
Application Information
(Continued)
20100902
FIGURE 15. Dual Mirophone Setup
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46
LM4931
Revision History
Rev
Date
1.0
6/30/04
Description
Re-webd.
1.1
7/24/06
Input a couple of text edits on table (LS-GAIN 04h).... per Alvin Fok, then re-released D/S to the WEB.
47
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LM4931 Audio Subsystem with Mono High Efficiency Loudspeaker and Stereo Headphone
Amplifiers
Physical Dimensions
inches (millimeters) unless otherwise noted
42-Bump micro SMD
Order Number LM4931ITL
NS Package Number TLA42YVA
X1 = 3.507 ± 0.03mm X2 = 3.931 ± 0.03 X3 = 0.600 ± 0.075
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.
For the most current product information visit us at www.national.com.
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(b) support or sustain life, and whose failure to perform when
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device or system whose failure to perform can be reasonably
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