MAS MAS9560

DA9560.001
20 January, 2005
MAS9560
Stereo Audio Driver DAC
This is preliminary information on a new
product under development. Micro Analog
Systems Oy reserves the right to make any
changes without notice.
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16-Bit Stereo Audio DAC
Stereo Headphone Drivers
Mono Earpiece Driver
Mono Loudspeaker Driver
Mixing of Analog and Digital
Audio Signals
Integrated LDO
Flexible Power Down Control
DESCRIPTION
The MAS9560 Stereo Audio DAC chip is specially
intended to audio applications in portable devices. It
has both analog and digital inputs for audio data thus
enabling the mixing of signals. MAS9560 is equipped
with integrated high performance LDO, which
ensures high quality of output signal even in noisy
power supply environment. MAS9560 has three
audio outputs (for headphone, earpiece and
loudspeaker) making it an ideal choice for space
critical applications. Since current consumption is a
critical factor in portable devices, MAS9560 has
flexible power down control enabling the shutting
down of the parts of the circuit that are not in use.
FEATURES
APPLICATIONS
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16-Bit Stereo Audio DAC
Stereo Headphone Drivers (25 mW)
Mono Earpiece Driver (100 mW)
Mono Loudspeaker Driver (410 mW)
-50 dB to 32 dB Analog Volume Control
Mute for All Volume Controls
Analog and Digital Signal Mixing
Integrated LDO
Flexible Power Down Control
Audio Sample Rates from 8 kHz to 48 kHz
I2C/SPI Compatible Serial Control Port
I2S Digital Audio Interface
Supply Voltage Range 2.7 V to 5.5 V
Digital I/O Voltage Range 1.8 V to 5.5 V
Package QFN 6x6 40ld
Compatible with DAC3560C
•
Portable devices with sophisticated audio
functions:
• Cell Phones
• PDAs
• MP3 players with integrated AM/FM radio
1 (25)
DA9560.001
20 January, 2005
CBP
Reference
Generator
SREF
VLDO
VBAT
BLOCK DIAGRAM
LDO
LSVDD
LSP
LSN
AUXL
LSVSS1
LSVSS2
AUXR
EPVDD
EPP
AIN
EPN
stereo/
mono
EPVSS1
EPVSS2
Σ
Σ
IOVDD
stereo/
mono
XRES
DAI
WSI
CLI
I2S
Digital
Audio
Interface
HPVDD
Σ
DAC
HPL
Σ
DAC
HPR
stereo/
mono
SDO
SDI
XCS
1
I C/SPI
Control
Interface
2
HPCM
HPVSS
Temperature
Protection
AVSS
DVSS
MODE
SCLK
Figure 1. Block diagram of MAS9560
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DA9560.001
20 January, 2005
DETAILED BLOCK DESCRIPTION
◆ DAC
MAS9560 contains two digital-to-analog converters
(DACs), which values are set through I2S bus (see
I2S section for further description). The sampling
rate of DACs is defined by WSI or CLI. In over
sampling mode the sampling frequency is the
frequency of CLI pin divided by four (fCLI/4). WSI is
used as a sampling clock in default mode.
The reference block, which provides reference level
for analog audio signals, has two modes:
ƒ
ƒ
LDO mode: Audio reference level = VLDO/2.
(SREF pin). This is half of integrated voltage
regulator's output voltage.
Non-LDO mode: Audio reference level =
VLDO/2. VLDO should be connected to VBAT
in Non-LDO mode.
◆ Audio Drivers
◆ I2C/SPI Control Interface
MAS9560 contains three audio drivers, all of which
can be used simultaneously or separately. One
driver is for loudspeaker, one for earpiece and one
for headphone. The two latter ones have analog
volume control from –30 dB gain to +6 dB gain in
1.5 dB steps, whereas the control range for
loudspeaker driver is from –30 dB to +12 dB in 1.5
dB steps (see Control Register section p.18) The
main features of each driver is as follows:
MAS9560 has many user selectable options. These
selections are mainly made by using registers,
which are programmed via one of the two standard
control interface protocols: I2C or SPI. The used
control interface type is selected with MODE pin.
ƒ
ƒ
ƒ
Loudspeaker Driver: mono, differential output,
output power: 410 mW @ VDD = 2.7 V, 1100
mW @ VDD = 5.0 V
Earpiece Driver: mono, differential output,
output power: 100 mW @ VDD = 2.7 V, 300 mW
@ VDD = 5.0 V
Headphone Driver: stereo, single-ended output,
output power: 25 mW @ VDD = 2.7 V, 80 mW
@ VDD = 5.0 V
All the drivers are short-circuit protected.
◆ Digital Audio Interface
Inter-IC Sound (I2S) bus is a 3-wire serial interface
for transmission of 2-channel (stereo) Pulse Code
Modulation digital data between MAS9560 and
external digital audio source, for example MP3
player.
◆ Registers
MAS9560 has 11 on-chip registers, which byte
length is 8 bits. Reset register is write-only, all other
registers permit read and write access.
◆ Power Management
MAS9560 has Block Control Register, which allows
separate blocks to be turned on and off
independently. This can be used to reduce power
consumption, since typically all the blocks are not
needed at the same time. If, for example, only
loudspeaker is used as an output, the drivers for
earpiece and headphone can be disabled.
Additionally MAS9560 has Mode Control Register,
which can be used to select operating mode for
MAS9560. These four modes are as follows:
ƒ
Zero Power, where all digital and analog blocks
are in power down mode. This is a default
mode after startup.
ƒ
Analog stand-by, which is intended to be used
as a wait state when starting the device. The
purpose of this operating mode is to suppress
audible plops caused by abrupt amplification
changes when blocks in audio chain are waking
up.
ƒ
Aux to Line, where DACs are disabled and only
analog signaling is used.
ƒ
Full Power, where all blocks are active.
◆ LDO Voltage Regulator
MAS9560 has integrated low dropout voltage
regulator, which output voltage is fixed 2.86 V. In
power supply noisy environments the usage of this
LDO in powering headphone and earpiece drivers
improves the PSRR of these drivers to 100 dB and
over. 10 nF bypass capacitor can be connected to
CBP pin further improving the performance. In case
LDO is not used (non-LDO mode) its output pin
(VLDO) must be connected to external voltage
source since it is supplying power for analog frontend.
◆ Temperature Protection
MAS9560 is equipped with over temperature
protection.
The integrated LDO can also be disabled by using
Mode-Control-Register.
◆ Reference Block
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20 January, 2005
PIN CONFIGURATION
MAS
9560A1
YYWW
XXXXX.X
QFN 6x6 40ld
39
40
2
1
EXPOSED PAD
1 2
40 39
TOP VIEW
BOTTOM VIEW
Top Marking Information:
YYWW = Year, Week
XXXXX.X = Lot Number
PIN DESCRIPTION
G = Ground, I = Input, O = Output, P = Power
Pin Name
Pin
Number
Type
VBAT
LSVSS1
LSP
LSVDD
LSN
LSVSS2
N/C
DVSS
MODE
IOVDD
SDI
SCLK
SDO
XCS
DAI
WSI
CLI
XRES
N/C
N/C
AIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
P
G
O
P
O
G
G
I
P
I/O
I
O
I
I
I
I
I
I
Function
Power Supply Voltage
GND for Loudspeaker Driver
Loudspeaker Differential Output (Positive)
Power Supply Voltage for Loudspeaker Driver
Loudspeaker Differential Output (Negative)
GND for Loudspeaker Driver
Not Connected
Digital GND
Control Interface (I2C / SPI) Selection
Digital I/O Power Supply Voltage
SPI Data In or I2C Data In/Out
SPI or I2C Clock Signal
SPI Data Out
SPI Chip Select
I2S Data In
I2S Word Strobe Input
I2S Clock Signal
Reset Input
Not Connected
Not Connected
Analog Input (Mono)
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DA9560.001
20 January, 2005
Pin Name
Pin
Number
AUXL
22
AUXR
23
HPCM
24
HPVSS
25
HPL
26
HPR
27
HPVDD
28
N/C
29
SREF
30
CBP
31
EPVSS2
32
EPN
33
EPVDD
34
EPP
35
EPVSS1
36
AVSS
37
N/C
38
N/C
39
VLDO (AVDD)
40
Exposed Pad
Type
I
I
O
G
O
O
P
O
I
G
O
P
O
G
G
P
Function
Analog Auxiliary (AUX) Input Left Channel (Stereo)
Analog Auxiliary (AUX) Input Right Channel (Stereo)
Headphone Common Output
GND for Headphone Driver
Headphone Output (Left Channel)
Headphone Output (Right Channel)
Power Supply Voltage for Headphone Driver
Not Connected
Audio Signal Reference Level
Pin for LDO Bypass Capacitor
Earpiece Ground
Earpiece Differential Output (Negative)
Power Supply for Earpiece Driver
Earpiece Differential Output (Positive)
GND for Earpiece Driver
Analog Ground
Not Connected
Not Connected
LDO Output (Analog Power Supply)
Exposed pad should be soldered to GND layer to improve heat
dissipation
Note: Pins EPVDD and HPVDD have to be connected to VLDO pin.
DETAILED PIN DESCRIPTIONS
◆ Power supply pins
The power supply of MAS9560 is divided into
functional sections so that:
ƒ DVSS is connected internally with all digital
parts
ƒ IOVDD and DVSS are connected internally with
all digital inputs and outputs
ƒ DVSS is ground connection for all digital parts
ƒ All GND pins are internally connected together
ƒ LSVDD and VBAT are internally connected
together
Other power supply pins should be connected as
follows:
ƒ VLDO should be connected to VBAT in nonLDO mode. If LDO mode is selected, VLDO is
the output of LDO.
ƒ HPVDD and EPVDD can be driven by VLDO in
LDO mode to reduce power supply noise
ƒ HPVSS, EPVSS, LSVSS must be connected to
analog ground (AVSS). The pins are internally
connected together.
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20 January, 2005
ABSOLUTE MAXIMUM RATINGS
All voltages with respect to ground.
Parameter
Supply Voltage
(VBAT and LSVDD are internally
connected together)
Voltage Range for Other Pins
Symbol
Pin Name
Min
Max
Unit
VBAT
VBAT, LSVDD
-0.3
6
V
-0.3
VBAT + 0.3
V
2
+175
(limited)
+150
1.2
kV
°C
ESD Rating (HBM)
Junction Temperature
TJmax
Storage Temperature
TS
-55
°C
W
Power Dissipation (TA = +85°C)
(Exposed pad soldered to PCB)
Stresses beyond those listed may cause permanent damage to the device. The device may not operate under
these conditions, but it will not be destroyed.
RECOMMENDED OPERATING CONDITIONS
All voltages with respect to ground.
Parameter
Operating Junction
Temperature
Operating Ambient
Temperature
Master Supply Voltage
Symbol
Digital Interface
Voltage
Earpiece Supply
Voltage
Headphone Supply
Voltage
Conditions
Min
Nom
Max
Unit
TJ
-40
+125
°C
TA
-40
+85
°C
VBAT,
LSVDD
Master Supply Voltage
Analog Operating
Supply Voltage
Pin
Name
VBAT
IO_VDD
LDO mode,
VBAT and LSVDD
internally connected
Non-LDO mode,
VBAT and LSVDD
internally connected
3.0
3.6
5.5
V
2.7
3.6
5.5
V
Internally connected
together
2.7
5.5
VLDO,
HPVDD,
EPVDD
IOVDD
2.7
VBAT
V
1.5
VBAT
V
EPVDD
2.7
VBAT
V
HPVDD
2.7
VBAT
V
VBAT,
LSVDD,
VLDO,
EPVDD,
HPVDD
VBAT,
LSVDD
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20 January, 2005
RECOMMENDED EXTERNAL COMPONENTS
Parameter
LDO Output
Capacitance
Effective Series
Resistance
LDO Bypass
Capacitance
(Optional: if
CBYPASS is not
used, noise
performance and
PSRR decline,
but rise time is
improved.)
LDO Input
Capacitance
Symbol
Pin
Name
Min
CL_LDO
VLDO
ESR
CBP_LDO
CBP
CIN_LDO
VBAT
Typ
Max
Unit
Note
0.23
CIN_LDO
µF
0.01
3
Ohm
1. Ceramic and film capacitors
can be used.
2. The value of CL LDO should be
smaller than or equal to the
value of CIN LDO.
1. When within this range, stable
with all IOUT = 0 mA…150 mA
values.
1. Ceramic and film capacitors are
best suited. For maximum
output voltage accuracy DC
leakage
current
through
capacitor should be kept as low
as possible. In any case DC
leakage current must be below
100 nA.
0.01
µF
0.5
µF
1. A big enough input capacitance
is needed to prevent possible
impedance
interactions
between the supply and LDO.
2. Ceramic, tantalum, and film
capacitors can be used. If a
tantalum capacitor is used, it
should be checked that the
surge current rating is sufficient
for the application.
3. In the case that the inductance
between a battery and LDO is
very small (< 0.1 µH), a 0.47 µF
input capacitor is sufficient.
4. The value of CIN_LDO should not
be smaller than the value of
CL_LDO.
When selecting capacitors, tolerance and temperature coefficient must be considered to make sure that the capacitance and resistance
are between the above specified limits in all potential operating conditions.
Analog Input
Coupling
Capacitor
SREF Bypass
Capacitor
CAIN,
CAUXL,
CAUXR
CSREF
AUXL,
AUXR,
AIN
SREF
Load Resistance:
Headphone
RL_HP
Load Resistance:
Earpiece
Load Resistance:
Loudspeaker
RL_EP
HPR,
HPL,
HPCM
EPP,
EPN
LSP,
LSN
RL_S
470
nF
1. Affects on input signal's pass band
frequence.
3.3
µF
1. A too small value capacitor cannot
effectively prevent disturbance
from getting to signal ground.
16
32
ohm
16
32
ohm
4
8
ohm
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20 January, 2005
ELECTRICAL CHARACTERISTICS IN LDO MODE
◆ Integrated LDO Characteristics
LSVDD = VBAT = 3.6V, EPVDD = HPVDD = VLDO = 2.86V (LDO-mode), -40°C ≤ TA ≤ +85°C, , typical values at TA = +27°C,
IOUT = 1.0 mA, CIN_LDO = 1.0 µF, CL_LDO = 1.0 µF, CBP_LDO = 10 nF, unless otherwise noted
Parameter
Pin
Name
Conditions
Min
Nom
Max
Unit
Output Voltage
VLDO
Operational Mode
2.75
2.86
2.95
V
Standby Mode, LDO not
bypassed
2.86
Standby Mode, LDO bypassed
VBAT
Zero Power Mode, LDO not
bypassed
Dropout Voltage
0
Zero Power Mode, LDO bypassed
VBAT
IOUT = 1 mA
IOUT = 50 mA
IOUT = 150 mA
1.7
70
200
VLDO
mV
Continuous Output
Current
VLDO
0
Short Circuit Current
VLDO
RL = 0 Ω
Peak Output Current
VLDO
VOUT > 95%* VOUT(NOM)
410
mA
Line Regulation
VLDO
3.6 V < VBAT < 5.3 V,
IOUT = 60 mA
0.7
mV
Load Regulation
VLDO
5
10
Overshoot
VLDO
Start-up Delay
(From the time LDO is
enabled via register until
VLDO is 90% of the
nominal VOUT)
Thermal Protection/
Threshold High
Thermal Protection/
Threshold Low
VLDO
w/o CBP_LDO
VLDO
Noise Density
VLDO
PSRR
VLDO
Rise Time (10%… 90%)
VLDO
450
mA
675
mA
mV
IOUT = 1 mA to 50 mA
IOUT = 1 mA to 150 mA
300 Hz < f < 50 kHz
CBP_LDO = 10 nF
w/o CBP_LDO
IOUT = 50 mA,
f = 1 kHz
f = 1 kHz
f = 10 kHz
f = 100 kHz
IOUT = 30mA
CBP_LDO = 10 nF
w/o CBP_LDO
w/o CBP_LDO
Output Noise Voltage
200
150
µVrms
20
110
100
nV
Hz
67
65
48
dB
4
16
3
ms
µs
%
10
17
µs
145
160
175
°C
135
150
165
°C
The hysteresis of 10°C prevents the device from turning on too soon after thermal shut-down.
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20 January, 2005
◆ Analog Audio Inputs (AIN, AUXL, AUXR) in LDO mode
LSVDD = VBAT = 3.6V, EPVDD = HPVDD = VLDO = 2.86 V (LDO-mode), -40°C ≤ TA ≤ +85°C, typical
values at TA = +27°C, unless otherwise noted
Parameter
Pin Name
Min
Input Range
AIN, AUXL, AUXR
Input Clipping Level
AIN, AUXL, AUXR
Input Resistance
AIN, AUXL,
AUXR
Nom
Max
2.05
VPP
VLDO
Gain = -20 dB
23
Gain = 0 dB
14
Gain = +20 dB
3
Gain Setting Range
AIN, AUXL, AUXR
-20
Gain Step Size
AIN, AUXL, AUXR
1.5
Absolute Gain Error
AIN, AUXL, AUXR
-1.2
Unit
V
kΩ
20
dB
2
2.5
dB
0
1.2
dB
◆ Analog Audio Outputs (Headphone, Earpiece, Loudspeaker) in LDO mode
LSVDD = VBAT = 3.6V, EPVDD = HPVDD = VLDO = 2.86 V (LDO-mode), -40°C ≤ TA ≤ +85°C, typical
values at TA = +27°C, unless otherwise noted
Parameter
Pin Name
Volume Range
(Headphone and
Earpiece)
HPL,HPR
,EPP,EP
N
Volume Range
(Loudspeaker)
Volume Control Step
Size
Headphone Output
Power
Earpiece Output Power
Loudspeaker Output
Power
Conditions
Min
Nom
Max
Unit
-30
6
dB
LSP,LSN
-30
12
dB
HPL,HPR
,EPP,EP
N,LSP,LS
N
1.0
2.0
dB
1.5
HPL,
HPR,
(HPCM)
THD < 0.1%, f = 1 kHz, RL = 32 Ω
EPP,
EPN
THD < 0.2%, f = 1 kHz, RL = 32 Ω
100
mW
THD < 1%, f = 1 kHz, RL = 8 Ω
410
mW
LSP, LSN
25
mW
(25)
Headphone Short
Circuit Current
HPL,
HPR,
HPCM,
VLDO,
AVSS
250
350
450
mA
Earpiece Short Circuit
Current
EPP,
EPN,
VLDO,
AVSS
250
350
450
mA
LSP, LSN
800
1000
mA
Loudspeaker Short
Circuit Current
Headphone and
Earpiece Output Signal
Reference Level
HPL,
HPR,
HPCM,
EPP,
EPN
SREF settled
VLDO/2
V
Loudspeaker Output
Signal Reference Level
LSP, LSN
SREF settled
LSVDD/
2
V
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20 January, 2005
◆ Dynamic Performance in LDO mode
LSVDD = VBAT = 3.6 V, EPVDD = HPVDD = VLDO = 2.86 V (LDO-mode), -40°C ≤ TA ≤ +85°C, typical values
at TA = +27°C, unless otherwise noted
Parameter
Pin Name
Conditions
Headphone Full Scale
Output Level
HPL,HPR
, HPCM
No load, Volumes = 0 dB
2.04
Vpp
EPP,
EPN
No load, Volumes = 0 dB
4.08
Vpp
Loudspeaker Full Scale
Output Level
LSP,LSN
No load, Volumes = 0 dB
4.08
Vpp
Absolute 0 dB Gain,
Analog In to Analog Out
(unweighted), DAC off
AIN,
AUXL,
AUXR,
HPL,
HPR,
HPCM,
EPP,
EPN,
LSP, LSN
Earpiece Full Scale
Output Level
Mute Level
Dynamic Range, Digital
In to Analog Out
(unweighted)
AIN,
AUXL,
AUXR,
HPL,
HPR,
HPCM,
EPP,
EPN,
LSP, LSN
HPL,
HPR,
(HPCM)
Min
Analog to Headphone
-1.2
0
+1.2
Analog to Earpiece
-1.2
0
+1.2
Analog to Loudspeaker
-1.2
0
+1.2
Headphone
-40
-75
Earpiece
-40
-75
Loudspeaker
-40
-75
Analog Input (AIN)
-40
-60
Auxiliary Input (AUXL, AUXR)
-40
-65
fSAMPLE =
48 kHz with 16bit data,
Bandwidth =
20 Hz… 20 kHz
Unit
dB
dB
81
dB
DAC to
Earpiece
76
dB
DAC to
Loudspeaker
76
dB
DAC to
Headphone
86
dB
DAC to
Earpiece
82
dB
DAC to
Loudspeaker
82
dB
DAC off, Analog to Headphone
92
dB
AIN,
AUXL,
AUXR,
EPP,EPN
DAC off, Analog to Earpiece
89
dB
AIN,
AUXL,
AUXR,
LSP, LSN
DAC off, Analog to Loudspeaker
82
dB
LSP, LSN
HPL,
HPR,
(HPCM)
EPP,
EPN
LSP, LSN
Dynamic Range, Analog
In to Analog Out
(unweighted)
Max
DAC to
Headphone
EPP,
EPN
Dynamic Range, Digital
In to Analog Out
(A-weighted)
Nom
AIN,
AUXL,
AUXR,
HPL,
HPR,
HPCM,
fSAMPLE =
48 kHz with 16bit data,
Bandwidth =
20 Hz… 20 kHz
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20 January, 2005
Dynamic Range, Analog
In to Analog Out
(A-weighted)
AIN,
AUXL,
AUXR,
HPL,
HPR,
HPCM,
DAC off, Analog to Headphone
95
dB
AIN,
AUXL,
AUXR,
EPP,
EPN
DAC off, Analog to Earpiece
86
dB
DAC off, Analog to Loudspeaker
85
dB
HPL,
HPR,
(HPCM)
f = 50 Hz... 20 kHz, RL = 32 Ω,
Pout = 15 mW
-65
dB
f = 150 Hz... 20 kHz, RL = 32 Ω,
Pout = 50 mW
-55
dB
THD + Noise
EPP,
EPN
Loudspeaker
LSP, LSN
f = 150 Hz... 20 kHz, RL = 8 Ω,
Pout = 200 mW
-58
dB
-73
dB
120
dB
120
dB
63
dB
AIN,
AUXL,
AUXR,
LSP, LSN
Headphone
THD + Noise
Earpiece
THD + Noise
Mute Level
Headphone PSRR
Earpiece PSRR
Loudspeaker PSRR
(-63)
HPL,
HPR,
(HPCM),
EPP,
EPN,
LSP, LSN
HPL,
HPR,
HPCM,
VBAT
f = 1.0 kHz, VBAT ≥ 3.1 V,
EPP,
EPN,
VBAT
f = 1.0 kHz, VBAT ≥ 3.1 V,
LSVDD,
LSP, LSN
RL = 32 Ω, Vripple = 0.5 Vpp, Zero
audio signal
RL = 32 Ω, Vripple = 0.5 Vpp, Zero
audio signal
f = 1.0 kHz, LSVDD ≥ 3.1 V,
40
RL = 8 Ω, Vripple = 0.5 Vpp, Zero
audio signal
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20 January, 2005
◆ Current Consumption
LSVDD = VBAT = 3.6V, EPVDD = HPVDD = VLDO = 2.86V (LDO-mode), -40°C ≤ TA ≤ +85°C, , typical values at TA = +27°C, IOUT = 1.0 mA,
CIN_LDO = 1.0 µF, CL_LDO = 1.0 µF, CBP_LDO = 10 nF, unless otherwise noted
Control Bits
VBAT
Mono
DAC
AIN
AUX
LS
EP
HPR
HPL
HPC
Typical Current
[mA]
Maximum Current
[mA]
Current measurement test setup
x
x
x
x
x
x
x
x
x
x
x
3.00 V
3.60 V
5.50 V
3.00 V
3.60 V
5.50 V
x
x
x
3.1
3.1
3.1
7.5
7.5
7.5
5.4
5.5
5.3
10
10
10
8.4
12
37
20
25
70
x
x
x
x
x
x
5.8
5.8
5.8
10
10
10
7.1
7.1
7.1
12
12
12
19
22
47
40
40
80
x
x
x
x
x
x
x
x
x
x
x
x
x
4.6
4.6
4.6
7
7
7
x
9.0
13
37
20
25
70
4.9
4.9
4.9
8
8
8
Note: Above values measured with following loads: loudspeaker LSP-LSN 22 ohm (nominal load 8 ohm cannot
be used in testing due to tester limitations), earphone EPP-EPN 32 ohm, HPR-HPCM 32 ohm, HPL-HPCM 32
ohm.
12 (25)
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20 January, 2005
ELECTRICAL CHARACTERISTICS IN NON-LDO MODE
◆ Analog Audio Inputs (AIN, AUXL, AUXR) in non-LDO mode
LSVDD = VBAT = EPVDD = HPVDD = VLDO = 2.7 V...5.5 V (non-LDO-mode), -40°C ≤ TA ≤ +85°C,
typical values at TA = +27°C, unless otherwise noted
Parameter
Pin Name
Conditions
Full Scale Input Level
AIN, AUXL, AUXR
Volumes = 0 dB
Input Clipping Level
AIN, AUXL, AUXR
Input Resistance
AIN, AUXL, AUXR
Min
Nom
Max
Unit
0.715 x
VLDO
VLDO
Vpp
VLDO
V
Gain = -20 dB
23
Gain = 0 dB
14
Gain = +20 dB
3
Gain Setting Range
AIN, AUXL, AUXR
-20
Gain Step Size
AIN, AUXL, AUXR
1.5
Absolute Gain Error
AIN, AUXL, AUXR
-1.2
kΩ
20
dB
2
2.5
dB
0
1.2
dB
◆ Analog Audio Outputs (Headphone, Earpiece, Loudspeaker) in non-LDO mode
LSVDD = VBAT = EPVDD = HPVDD = VLDO = 2.7 V...5.5 V (non-LDO-mode), -40°C ≤ TA ≤ +85°C,
typical values at TA = +27°C, unless otherwise noted
Parameter
Pin
Name
Conditions
Min
Nom
Max
Unit
Headphone Output
Power
HPL,
HPR,
HPCM
HPVDD = 5.5 V, THD < 0.1%,
Earpiece Output
Power
EPP,
EPN
EPVDD = 5.5 V, THD < 0.2%,
Loudspeaker Output
Power
LSP,
LSN
LSVDD = 5.5 V, THD < 1%,
Headphone and
Earpiece Output
Signal Reference
Level
EPP,
EPN,
HPL,
HPR,
HPCM
SREF settled
VLDO/2
V
Loudspeaker Output
Signal Reference
Level
LSP,
LSN
SREF settled
VBAT/2
V
80
mW
300
mW
1100
mW
f = 1 kHz, RL = 32 Ω
f = 1 kHz, RL = 32 Ω
f = 1 kHz, RL = 8 Ω
◆ Dynamic Performance in non-LDO mode
LSVDD = VBAT = EPVDD = HPVDD = VLDO = 3.6 V (non-LDO-mode), -40°C ≤ TA ≤ +85°C, typical values at TA = +27°C, unless otherwise
noted
Parameter
Pin
Name
Conditions
Headphone
HPL,
Max
Unit
No load, Volumes = 0 dB
HPV
DD
Vpp
EPP,
Full Scale Output Level EPN
No load, Volumes = 0 dB
EPV
DD
Vpp
Loudspeaker
No load, Volumes = 0 dB
LSV
DD
Vpp
Full Scale Output Level HPR
Earpiece
LSP,
Full Scale Output Level LSN
Min
Nom
13 (25)
DA9560.001
20 January, 2005
Dynamic Range,
Digital In to Analog
Out (unweighted)
HPL,
HPR,
(HPCM)
EPP,
EPN
fSAMPLE =
48 kHz with 16-bit
data,
Bandwidth =
20 Hz… 20 kHz
LSP,
LSN
Dynamic Range,
Digital In to Analog
Out (A-weighted)
HPL,
HPR,
(HPCM)
EPP,
EPN
fSAMPLE =
48 kHz with 16-bit
data,
Bandwidth =
20 Hz… 20 kHz
LSP,
LSN
Dynamic Range,
Analog In to Analog
Out
(unweighted)
Dynamic Range,
Analog In to Analog
Out
(A-weighted)
Headphone
THD + Noise
DAC to
Headphone
82
dB
DAC to
Earpiece
76
dB
DAC to
Loudspeaker
76
dB
DAC to
Headphone
86
dB
DAC to
Earpiece
82
dB
DAC to
Loudspeaker
82
dB
AIN,
AUXL,
AUXR,
HPL,
HPR,
HPCM
DAC off , Analog to HP
84
dB
AIN,
AUXL,
AUXR,
EPP,
EPN
DAC off, Analog to EP
92
dB
AIN,
AUXL,
AUXR,
LSP,
LSN
DAC off, Analog to LS
92
dB
AIN,
AUXL,
AUXR,
HPL,
HPR,
HPCM
DAC off, Analog to HP
86
dB
AIN,
AUXL,
AUXR,
EPP,
EPN
DAC off, Analog to EP
96
dB
AIN,
AUXL,
AUXR,
LSP,
LSN
DAC off, Analog to LS
96
dB
HPL,
HPR,
(HPCM)
f = 50 Hz... 20 kHz,
RL = 32 Ω,
VBAT = 2.7 V
-62
dB
Pout = 15 mW
VBAT = 3.6 V
(-61)
-66
(-66)
VBAT = 5.0 V
-68
(-68)
Earpiece
EPP,
f = 150 Hz... 20 kHz,
VBAT = 2.7 V
-54
dB
14 (25)
DA9560.001
20 January, 2005
THD + Noise
Loudspeaker
THD + Noise
EPN
LSP,
LSN
Mute Level
HPL,
HPR,
(HPCM)
, EPP,
EPN,
LSP,
LSN
Headphone PSRR
HPL,
HPR,
HPCM,
VBAT
Earpiece PSRR
Loudspeaker PSRR
RL = 32 Ω,
VBAT = 3.6 V
-62
Pout = 50 mW
VBAT = 5.0 V
-68
f = 150 Hz... 20 kHz,
RL = 8 Ω,
VBAT = 2.7 V
-56
VBAT = 3.6 V
-58
Pout = 200 mW
VBAT = 5.0 V
-62
mW
-75
dB
f = 1.0 kHz, VBAT ≥ 3.1 V, RL = 32 Ω,
Vripple = 0.5 Vpp, Zero audio signal
54
dB
EPP,
EPN,
VBAT
f = 1.0 kHz, VBAT ≥ 3.1 V, RL = 32 Ω,
Vripple = 0.5 Vpp, Zero audio signal
69
dB
LSVDD,
LSP,
LSN
f = 1.0 kHz, LSVDD ≥ 3.1 V, RL = 8 Ω,
Vripple = 0.5 Vpp, Zero audio signal
63
dB
◆ Definitions
Dynamic Range: Dynamic range means the
difference between the highest and lowest levels of
the signal. Due to the fact that the dynamic range of
a loudspeaker (or similar) would significantly affect
the dynamic range measurement of MAS9560, the
following has been made: THD+N has been
40
measured at –60 dB, and dynamic range has been
derived of that by adding 60 dB to that value. For
example THD+N = -30 dB Æ Dynamic range = 90
dB.
THD+N: Total Harmonic Distortion + Noise
15 (25)
DA9560.001
20 January, 2005
CONTROL INTERFACES
MAS9560 registers (detailed description below) are controlled either via I2C- or SPI bus. On-chip DAC data is
written using I2S-bus.
Pin
Bus
Function
MODE
I2C/SPI
Select I2C (MODE=1) or SPI (MODE=0)
SCLK
I2C /SPI
Serial Data Clock for I2C and SPI
SDI
I2C /SPI
Serial Data I/O for I2C and input for SPI
SDO
SPI
Serial Data Output for SPI
XCS
SPI
Chip Select for SPI (active low)
2
DAI
IS
Serial Data input for I2S
WSI
I2S
Frame Identification for I2S
CLI
I2S
Serial Data Clock for I2S
◆ I2C Description
I2C – bus is selected by setting pin MODE = 1. I2C bus is a 2-wire serial interface, so two lines, a serial
data line (SDI) and serial clock line (SCLK), are
required. MAS9560 data line is bi-directional for
data acknowledge and transmit, but clock line is
just a receiver, i.e., the clock is gotten from the
master. Default state for both lines is high, since all
devices connected on the bus form together an
AND-function because of pull-up resistors.
A master is controlling the bus, enabling clock and
giving start and stop requests, so data transfer for
MAS9560 is started with start-pulse given by a
master device. As the master is changing SDI level
from high to low while SCLK is high, this action is
recognized as the start pulse. Stop pulse is similarly
created: when SCLK is high SDI level is changed
from low to high. During the data transition data line
(SDI) level may not change when clock (SCLK) is
high, because this is interpreted either as start or
stop pulse.
Data is transmitted in bytes, one byte is 8-bit long.
Several bytes can be sent one by one until the
master gives stop signal.
I2C data format is shown in table 1 below. The first
byte in I2C data after start pulse specifies unique
device code and transfer mode. Device code is
specified by 7 bits and is 1001 101 for MAS9560,
last (8th) bit selects read/write-mode (r/w): high for
read and low for write. After first byte is read,
MAS9560 acknowledges it by pulling data line (SDI)
down, keeping data line down and releasing the
line only after the master driven clock line (SCLK) is
again pulled down.
After the device specific code MAS9560 is set as
receiver for data as described above, sub-address
is given as a second byte. This addresses the initial
register number, and the following byte is the data
which is written to the register. In case the fourth
byte is written (and no stop bit is given), MAS9560
changes to increment mode and this fourth byte is
written to a following register. All registers can be
written by one start-stop sequence. On-chip
incremental counter is just 4-bits long. Incrementing
stops at address 0x0F to prevent overflow. In write
mode MAS9560 gives acknowledge pulse after
every byte.
I2C bus can also be used to read register values. In
this case a sequence is as follows: First byte 1001
1010 is written after start pulse (MAS9560
acknowledges) after which register address is
given, which is acknowledged by device. Next a
new start pulse is given by the master and byte
1001 1011 is acknowledged by MAS9560, after
which register (specified in initial sequence) data is
written to data bus (MSB first). After that MAS9560
gives NAK (no acknowledge) signal which
continues until ACK (acknowledge) or STOP signal
is given by the master. In case ACK signal is given,
the incremental mode of MAS9560 is enabled and
next register data is written to SDI bus by
MAS9560. The data is again followed by NAK
signal, and the reading sequence can be repeated
or stopped.
Values of unspecified bits in registers with less than
8-bits are not set to any initial value, and their value
can vary from time to time.
16 (25)
DA9560.001
20 January, 2005
1st byte
2nd byte
3rd byte
4th byte
device id
r/w
Register address
code
code
1001 101
1/0
0000 a3 a2 a1 a0
xxxx xxxx
xxxx xxxx
Called as DW when Write
Called as DR when Read
Table 1. I2C Data Format
◆ SPI Description
mode stops at address 0x0F to prevent address
overflow and device reset.
Serial Peripheral Interface (SPI) bus is a 4-wire
serial communication interface between a master
and a slave device. SPI bus is selected by setting
MODE pin to low. SCLK pin is clock, XCS pin chip
select, SDI data pin and SDO data out pin. Data
writing is started with pulling device specific XCS
pin low, and first bit (MSB) is written at next SCLK
rising edge.
The following byte written to SDI is either register
input data (write mode) or it is ignored (read mode).
In the read mode the selected register’s data can
be read from SDO pin at SCLK falling edge. Data
transfer stops with rising XCS pin.
In case XCS pin is held low after two first bytes, the
increment mode is enabled and the following
written/read bytes can be transferred to/from the
next registers. SDO output is at the high impedance
state when MAS9560 is not in read mode.
The first byte defines register address and whether
data will be read or write, see table 2 below. Bit 5:
Read = 1 and Write = 0. Note that incremental
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Function
x
x
R/W
x
A3
A2
A1
A0
Table 2. SPI first byte
◆ I2S Description
Inter-IC Sound (I2S) bus is a 3-wire serial interface
for transmission of 2-channel (stereo) Pulse Code
Modulation digital data for DACs. Data is sent in 2’s
complement format MSB first. The receiver ignores
extra bits from the transmitter, if more than 16 bits
are transmitted. In case byte length is less than 16
bits, data is still 2’s complement and unspecified
bits are set to zero.
Word Select pin (WSI-pin) can be configured in
MAS9560. The default setting is: WSI = ‘0’ when
data for Channel 1 (left channel) is read, and WSI =
‘1’ when Channel 2 (right channel) is read. This can
be changed with POL byte (see register description
for I2S Interface Control Register – p. 17).
Left justified format varies also depending on the
delay before the first data byte. Default delay is one
clock pulse, but this delay can be configured with
DEL bit.
MAS9560 supports only Left-Justified Format.
17 (25)
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20 January, 2005
Vh -
CLI
Vl Vh -
DAI
Vl programmable delay bit
Vh -
WSI
Vl -
left 16-bit audio sample
right 16-bit audio sample
Figure 1. I2S Bus
◆ Resetting Registers
When I2C is used:
First register 0x00 is the reset register, writing to
which will set all registers to default values. Writing
to register 0x00 sets default values to all registers,
after which following data will be written to registers
as incrementing starts. However, note that when
starting data write with the reset sequence, the byte
following the reset address is unused and the byte
after that is written to register 0x01 (DW-byte,
Reset-address-byte, unused data byte, data byte
for register 0x01). On-chip incremental counter is 4bits long: at address 0x0F incrementing stops.
When SPI is used:
Writing to the first register (0x00) resets all
registers. In case writing sequence is started with
reset, the byte following the reset address is
unused, similarly to I2C-mode.
Register reset can be performed externally by
setting XRESET pin low.
CONTROL REGISTERS
MAS9560 has 11 on-chip registers, which are
controlled through I2C- or SPI-bus (see section
Control Interfaces above). Register byte length is 8
bits for all registers, however, some bits are unused
and their value is not set and can vary (they are
non-repeatable). Reset register is write-only, all
other registers permit read and write access.
◆ Register Map
Sub-Address
Register
0x00
Reset Register
0x01
Block Control Register
0x02
Mode Control Register
0x03
I2S-Interface Control Register
0x04
Left Headphone Volume Control
0x05
Right Headphone Volume Control
0x06
Earpiece Volume Control
0x07
Loudspeaker Volume Control
0x08
Left Input Aux Gain Control
0x09
Right Input Aux Gain Control
0x0A
Ain Input Gain Control
0x0B… 0x0F
Unused
18 (25)
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20 January, 2005
◆ Register Description
Name
SubAddress
Direction
Default
after
Reset
Reset Register
0x00
Write
0x00
Reset
0xXX
Write
X
Function
Writing to the register clears all internal
registers to their default reset values.
Register value cannot be read.
Block Control Register
0x01
R/W
0x00
Ignored, if Standby or Zero Power Mode
PDAC
0x01[7]
R/W
0
DAC power: 1 = on, 0 = off
PAIN
0x01[6]
R/W
0
AIN power: 1 = on, 0 = off
PAUX
0x01[5]
R/W
0
AUX power: 1 = on, 0 = off
PL
0x01[4]
R/W
0
Loudspeaker driver power: 1 = on, 0 = off
PE
0x01[3]
R/W
0
Earpiece driver power: 1 = on, 0 = off
PRH
0x01[2]
R/W
0
Right Headphone driver power:
1 = on, 0 = off
PLH
0x01[1]
R/W
0
Left Headphone driver power:
1 = on, 0 = off
PCH
0x01[0]
R/W
0
Common Headphone driver power:
1 = on, 0 = off
Mode Control Register
0x02
R/W
0x00
-
0x02[7:5]
-
-
Unused
BYPLDO
0x02[4]
R/W
0
Bypass LDO (in non-LDO mode only):
1 = on (bypass LDO with 100 ohm on-chip
resistor connected between VLDO and
VBAT)
0 = off (LDO not bypassed, so on-chip
resistor not connected between VLDO and
VBAT)
SNLDOM
0x02[3]
R/W
0
Select Non-LDO mode: 1 = on, 0 = off
LDO is always disabled at Zero Power
Mode
SMM
0x02[2]
R/W
0
Select Stereo/Mono mode:
1 = Mono, 0 = Stereo
In Mono Mode AUXL and AUXR are
combined together and only left channel
DAC signal is used.
19 (25)
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PM
0x02[1:0]
R/W
00
Power Mode [1:0]
00 Zero Power Mode
01 Standby Mode
11 Operating Mode
10 Undefined (do not use)
I2S Control Register
0x03
R/W
0x00
-
0x03[7:5]
-
-
Unused
POL
0x03[4]
R/W
0
Invert Word Strobe Input (WSI) polarity:
POL = 0 -> Left Channel @ WSI = 0
POL = 1 -> Right Channel @ WSI = 0
DEL
0x03[3]
R/W
0
Delayed Bit: 1 = Delay, 0 = no Delay
SR
0x03[2:0]
R/W
000
Sample Rate [2:0]
000, 110 or 111: sample rate defined by
WSI, DAC data not filtered.
SR[2:0] LP Filter –3dB frequency:
001
fCLI/128 * 0.65
010
fCLI/64 * 0.65
011
fCLI/32 * 0.65
100
fCLI/16 * 0.65
101 fCLI/8 * 0.65
fCLI refers to I2S clock (CLI pin) frequency.
The above mentioned SR[2:0] register bits
allow filtering the DAC output by setting the
filter frequency.
An example: DAC data is given in stereo
mode as 16 bit data. Sampling frequency
WSI = 8 kHz, and CLI frequency is 2*16*8
kHz (2 channels, 16 bit each, 8 kHz
sampling freq). Highest signal frequency is
4 kHz (according to Nyqvist theorem), and
thus low pass filtering can be set to 4 kHz.
Now SR[2:0] = 011, which sets –3 dB
frequency to 5.2 kHz (= 2*16*8 kHz /
32*0.65).
0x04
R/W
0
-
0x04[7:5]
-
-
Unused
LHV
0x04[4:0]
R/W
00000
LHV[4:0] Left Headphone volume gain
Left Headphone
Volume Register
00000
Mute
00001
-30 dB
...
in steps of 1.5 dB
11001...11111
6 dB
20 (25)
DA9560.001
20 January, 2005
0x05
R/W
0
-
0x05[7:5]
-
-
Unused
RHV
0x05[4:0]
R/W
00000
RHV[4:0] Right Headphone volume gain
Right Headphone
Volume Register
00000
Mute
00001
-30 dB
...
in steps of 1.5 dB
11001...11111
6 dB
0x06
R/W
0
-
0x06[7:5]
-
-
Unused
EV
0x06[4:0]
R/W
00000
EV[4:0] Earpiece volume gain
Earpiece
Volume Register
00000
Mute
00001
-30 dB
...
in steps of 1.5 dB
11001...11111
6 dB
0x07
R/W
0
-
0x07[7:5]
-
-
Unused
LV
0x07[4:0]
R/W
00000
LV[4:0] Loudspeaker volume gain
Loudspeaker
Volume Register
00000
Mute
00001
-30 dB
...
in steps of 1.5 dB
11101...11111
12 dB
Left AUX Gain Register
0x08
R/W
0
-
0x08[7:5]
-
-
Unused
ALV
0x08[4:0]
R/W
00000
ALV[4:0] Left AUX pre-amplifier gain
00000
Mute
00001
-20 dB
...
in steps of 2 dB
10101...11111
20 dB
21 (25)
DA9560.001
20 January, 2005
Right AUX Gain Register
0x09
R/W
0
-
0x09[7:5]
-
-
Unused
ARV
0x09[4:0]
R/W
00000
ARV[4:0] Right AUX pre-amplifier gain
00000
Mute
00001
-20 dB
...
in steps of 2 dB
10101...11111
20 dB
AIN Gain Register
0x0A
R/W
0
-
0x0A[7:5]
-
-
Unused
AIV
0x0A[4:0]
R/W
00000
AIV[4:0] AIN pre-amplifier gain
00000
Mute
00001
-20 dB
...
in steps of 2 dB
10101...11111
20 dB
Note: Unused register bit values are undefined.
I2C BUS TIMING
LSVDD = VBAT = 3.6V, EPVDD = HPVDD = VLDO = 2.86V (LDO-mode), -40°C ≤ TA ≤ +85°C, typical
values at TA = +27°C, unless otherwise noted
Parameter
Pin Name
Conditions
Min
Nom
Max
Unit
Input Low Voltage
SCLK,
SDI
tbd
IOVDD
Input High Voltage
SCLK,
SDI
tbd
IOVDD
Start Condition Setup
Time
SCLK,
SDI
tbd
ns
Stop Condition Setup
Time
SCLK,
SDI
tbd
ns
Data Setup Time before
clock rising edge
SCLK,
SDI
tbd
ns
Data Hold Time after
clock falling edge
SCLK,
SDI
tbd
ns
Clock Low Pulse Time
SCLK
tbd
ns
Clock High Pulse Time
SCLK
tbd
ns
Bus Frequency
SCLK
Data Output Low Voltage
SCLK,
SDI
Data Output High
Leakage Current
SCLK,
SDI
Data Output Hold Time
after clock falling edge
SCLK,
SDI
Data Output Setup Time
before clock rising edge
SCLK,
SDI
tbd
MHz
ILOAD = 3
mA
tbd
V
VSDI = 5 V
tbd
µA
fI2C = 1MHz
tbd
ns
tbd
ns
22 (25)
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20 January, 2005
SPI BUS TIMING
LSVDD = VBAT = 3.6V, EPVDD = HPVDD = VLDO = 2.86V (LDO-mode), -40°C ≤ TA ≤ +85°C, typical values at TA = +27°C,
unless otherwise noted
Parameter
Pin
Name
Input Low voltage
SDI,
Input High voltage
SCLK
Conditions
Min
Nom
Unit
tbd
IOVDD
tbd
IOVDD
Input Impedance
Input Leakage Current
Max
0V
< Input < IOVDD
tbd
tbd
pF
tbd
µA
Input Setup Time before
clock rising edge
SDI,
XCS
Tbd
ns
Input Hold Time after clock
falling edge
SDI,
XCS
Tbd
ns
Output Low Voltage
SDO
ILOAD = 0.5 mA,
IOVDD = 1.8 V
Output High Voltage
SDO
ILOAD = -0.5 mA,
IOVDD = 1.8 V
Clock Frequency, read
access
SCLK,
SDI,
SDO
CLOAD = 20 pF,
IOVDD = 3.3 V
tbd
tbd
MHz
Clock Frequency, read
access
SCLK,
SDI,
SDO
CLOAD = 20 pF,
IOVDD = 1.8 V
tbd
tbd
MHz
Clock Frequency, write
access
SCLK,
SDI
CLOAD = 20 pF,
IOVDD = 3.3 V
tbd
tbd
MHz
Clock Frequency, write
access
SCLK,
SDI
CLOAD = 20 pF,
IOVDD = 1.8 V
tbd
tbd
MHz
tbd
V
tbd
V
I2S BUS TIMING
LSVDD = VBAT = 3.6V, EPVDD = HPVDD = VLDO = 2.86V (LDO-mode), -40°C ≤ TA ≤ +85°C, typical values at TA = +27°C,
unless otherwise noted
Parameter
Pin
Name
Input Low Voltage
DAI,
Input High voltage
CLI,
Input Impedance
WSI
Input Leakage Current
Conditions
Min
Nom
Max
Unit
tbd
IOVDD
tbd
0 V < Input < IOVDD
tbd
IOVDD
tbd
pF
tbd
µA
Input Setup Time before
clock rising edge
DAI,
WSI
tbd
ns
Input Hold Time after clock
falling edge
DAI,
WSI
tbd
ns
Clock Frequency (Note 1)
CLI,
DAI
tbd
MHz
Note 1: I2S clock (CLI) frequency ratio will affect to DAC sampling in oversampling mode. See Control Register
description (p. 18)
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DA9560.001
20 January, 2005
PACKAGE (QFN 6x6 40ld) OUTLINE
D
D/2
E
E/2
INDEX AREA
(D/2 x E/2)
A
TOP VIEW
SIDE VIEW
A3
A1
SEATING
PLANE
D2
e
E2
E2/2
NXL
D2/2
2
1
EXPOSED PAD
NXb
BOTTOM VIEW
Parameter
Typ
Unit
D
E
A
A1
D2
E2
e
NXb
6
6
0.9
0.02
4.15
4.15
0.5
0.23
mm
mm
mm
mm
mm
mm
mm
mm
24 (25)
DA9560.001
20 January, 2005
SOLDERING INFORMATION
TBD
EMBOSSED TAPE SPECIFICATIONS
TBD
REEL SPECIFICATIONS
TBD
ORDERING INFORMATION
Product Code
Product
MAS9560A1
Stereo Audio Driver DAC
Package
Comments
QFN 6x6 40ld
LOCAL DISTRIBUTOR
MICRO ANALOG SYSTEMS OY CONTACTS
Micro Analog Systems Oy
Kamreerintie 2, P.O. Box 51
FIN-02771 Espoo, FINLAND
Tel. +358 9 80 521
Fax +358 9 805 3213
http://www.mas-oy.com
NOTICE
Micro Analog Systems Oy reserves the right to make changes to the products contained in this data sheet in order to improve the design or
performance and to supply the best possible products. Micro Analog Systems Oy assumes no responsibility for the use of any circuits shown
in this data sheet, conveys no license under any patent or other rights unless otherwise specified in this data sheet, and makes no claim that
the circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Micro Analog
Systems Oy makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification.
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