ETC LSI53C1000

TECHNICAL
MANUAL
LSI53C1000
PCI to Ultra160
SCSI Controller
Version 2.1
February 2001
®
S14050.A
This document contains proprietary information of LSI Logic Corporation. The
information contained herein is not to be used by or disclosed to third parties
without the express written permission of an officer of LSI Logic Corporation.
LSI Logic products are not intended for use in life-support appliances, devices,
or systems. Use of any LSI Logic product in such applications without written
consent of the appropriate LSI Logic officer is prohibited.
Document DB14-000128-03, Third Edition (February 2001). This document
describes the LSI Logic LSI53C1000 PCI to Ultra160 SCSI Controller and will
remain the official reference source for all revisions/releases of this product until
rescinded by an update.
To receive product literature, visit us at http://www.lsilogic.com.
LSI Logic Corporation reserves the right to make changes to any products herein
at any time without notice. LSI Logic does not assume any responsibility or
liability arising out of the application or use of any product described herein,
except as expressly agreed to in writing by LSI Logic; nor does the purchase or
use of a product from LSI Logic convey a license under any patent rights,
copyrights, trademark rights, or any other of the intellectual property rights of
LSI Logic or third parties.
Ultra SCSI is the term used by the SCSI Trade Association (STA) to describe
Fast-20 SCSI, as documented in the SCSI-3 Fast-20 Parallel Interface standard,
X3.277-199X.
Ultra2 SCSI is the term used by the SCSI Trade Association (STA) to describe
Fast-40 SCSI, as documented in the SCSI Parallel Interface–2 standard, (SPI–2)
X3T10/1142D.
Copyright © 2000–2001 by LSI Logic Corporation. All rights reserved.
TRADEMARK ACKNOWLEDGMENT
The LSI Logic logo design, TolerANT, SCRIPTS, SDMS, SureLINK, and LVDlink
are registered trademarks or trademarks of LSI Logic Corporation. All other brand
and product names may be trademarks of their respective companies.
AP
ii
Preface
This book is the primary reference and technical manual for the LSI Logic
LSI53C1000 PCI to Ultra160 SCSI Controller. This manual contains a
complete functional description for the product and includes physical and
electrical specifications.
Audience
This document was prepared for system designers and programmers
who are using this device to design an Ultra160 SCSI port for PCI-based
personal computers, workstations, servers or embedded applications.
Organization
This document has the following chapters and appendixes:
•
Chapter 1, Introduction, describes the general information about the
LSI53C1000.
•
Chapter 2, Functional Description, describes the main functional
areas of the chip in greater detail, including the interfaces to the
SCSI bus and external memory.
•
Chapter 3, Signal Descriptions, contains the pin diagram and signal
descriptions.
•
Chapter 4, Registers, describes each bit in the operating registers,
and is organized by register address.
•
Chapter 5, SCSI SCRIPTS Instruction Set, defines all of the SCSI
SCRIPTS instructions that are supported by the LSI53C1000.
•
Chapter 6, Specifications, contains the electrical characteristics and
AC timing diagrams.
•
Appendix A, Register Summary, is a register summary.
Preface
iii
•
Appendix B, External Memory Interface Diagram Examples,
contains several example interface drawings for connecting the
LSI53C1000 to external ROMs.
Related Publications
For background please contact:
ANSI
11 West 42nd Street
New York, NY 10036
(212) 642-4900
Ask for document number X3.131-199X (SCSI-2)
Global Engineering Documents
15 Inverness Way East
Englewood, CO 80112
(800) 854-7179 or (303) 397-7956 (outside U.S.) FAX (303) 397-2740
Ask for document number X3.131-1994 (SCSI-2) or X3.253
(SCSI-3 Parallel Interface)
ENDL Publications
14426 Black Walnut Court
Saratoga, CA 95070
(408) 867-6642
Document names: SCSI Bench Reference, SCSI Encyclopedia, SCSI
Tutor
Prentice Hall
113 Sylvan Avenue
Englewood Cliffs, NJ 07632
(800) 947-7700
Ask for document number ISBN 0-13-796855-8, SCSI: Understanding
the Small Computer System Interface
LSI Logic World Wide Web Home Page
www.lsil.com
SCSI SCRIPTS™ Processors Programming Guide, Order Number
S14044.A
iv
Preface
PCI Special Interest Group
2575 N. E. Katherine
Hillsboro, OR 97214
(800) 433-5177; (503) 693-6232 (International); FAX (503) 693-8344
Conventions Used in This Manual
The word assert means to drive a signal true or active. The word
deassert means to drive a signal false or inactive.
Hexadecimal numbers are indicated by the prefix “0x” —for example,
0x32CF. Binary numbers are indicated by the prefix “0b” —for example,
0b0011.0010.1100.1111.
Revision Record
Revision
Date
Remarks
0.1
1/00
Advanced Version
1.0
5/00
Preliminary Version
2.0
11/00
Final Version.
Changed branding from SYM53C1000 to LSI53C1000.
2.1
2/01
Changed Ultra3 references to Ultra160.
Preface
v
vi
Preface
Contents
Chapter 1
Chapter 2
Introduction
1.1
General Description
1.1.1
New Features in the LSI53C1000
1.2
Benefits of Ultra160 SCSI
1.3
Benefits of SureLINK (Ultra160 SCSI Domain Validation)
1.4
Benefits of LVDlink
1.5
Benefits of TolerANT® Technology
1.6
Summary of LSI53C1000 Benefits
1.6.1
SCSI Performance
1.6.2
PCI Performance
1.6.3
Integration
1.6.4
Ease of Use
1.6.5
Flexibility
1.6.6
Reliability
1.6.7
Testability
1-1
1-3
1-4
1-5
1-6
1-6
1-7
1-7
1-9
1-9
1-10
1-10
1-11
1-11
Functional Description
2.1
PCI Functional Description
2.1.1
PCI Addressing
2.1.2
PCI Bus Commands and Functions Supported
2.1.3
PCI Cache Mode
2.2
SCSI Functional Description
2.2.1
SCRIPTS Processor
2.2.2
Internal SCRIPTS RAM
2.2.3
64-Bit Addressing in SCRIPTS
2.2.4
Hardware Control of SCSI Activity LED
2.2.5
Designing an Ultra160 SCSI System
2.2.6
Prefetching SCRIPTS Instructions
2.2.7
Opcode Fetch Burst Capability
2-3
2-3
2-4
2-10
2-18
2-19
2-19
2-20
2-21
2-22
2-31
2-32
Contents
vii
2.3
2.4
2.5
Chapter 3
viii
2.2.8
Load and Store Instructions
2.2.9
JTAG Boundary Scan Testing
2.2.10 Parity/CRC/AIP Options
2.2.11 DMA FIFO
2.2.12 SCSI Data Paths
2.2.13 SCSI Bus Interface
2.2.14 Select/Reselect During Selection/Reselection
2.2.15 Synchronous Operation
2.2.16 Interrupt Handling
2.2.17 Interrupt Routing
2.2.18 Chained Block Moves
Parallel ROM Interface
Serial EEPROM Interface
2.4.1
Default Download Mode
2.4.2
No Download Mode
Power Management
2.5.1
Power State D0
2.5.2
Power State D1
2.5.3
Power State D2
2.5.4
Power State D3
Signal Descriptions
3.1
Signal Organization
3.2
Internal Pull-ups and Pull-downs on LSI53C1000 Signals
3.3
PCI Bus Interface Signals
3.3.1
System Signals
3.3.2
Address and Data Signals
3.3.3
Interface Control Signals
3.3.4
Arbitration Signals
3.3.5
Error Reporting Signals
3.3.6
Interrupt Signals
3.4
SCSI Bus Interface Signals
3.5
General Purpose I/O (GPIO) Signals
3.6
Flash ROM and Memory Interface Signals
3.7
Test Interface Signals
3.8
Power and Ground Signals
3.9
MAD Bus Programming
Contents
2-32
2-33
2-33
2-36
2-37
2-39
2-40
2-41
2-45
2-53
2-55
2-59
2-61
2-61
2-62
2-62
2-63
2-63
2-64
2-64
3-1
3-4
3-4
3-5
3-6
3-7
3-8
3-8
3-9
3-9
3-13
3-14
3-15
3-16
3-17
Chapter 4
Chapter 5
Chapter 6
Registers
4.1
PCI Configuration Registers
4.2
SCSI Registers
4.3
SCSI Shadow Registers
4-1
4-21
4-119
SCSI SCRIPTS Instruction Set
5.1
SCSI SCRIPTS
5.1.1
Sample Operation
5.2
Block Move Instructions
5.2.1
First Dword
5.2.2
Second Dword
5.2.3
Third Dword
5.3
I/O Instructions
5.3.1
First Dword
5.3.2
Second Dword
5.4
Read/Write Instructions
5.4.1
First Dword
5.4.2
Second Dword
5.4.3
Read-Modify-Write Cycles
5.4.4
Move To/From SFBR Cycles
5.5
Transfer Control Instructions
5.5.1
First Dword
5.5.2
Second Dword
5.5.3
Third Dword
5.6
Memory Move Instructions
5.6.1
Read/Write System Memory from a SCRIPT
5.6.2
Second Dword
5.6.3
Third Dword
5.7
Load and Store Instructions
5.7.1
First Dword
5.7.2
Second Dword
5-1
5-3
5-4
5-5
5-13
5-14
5-14
5-14
5-22
5-23
5-23
5-24
5-24
5-25
5-27
5-27
5-33
5-33
5-34
5-35
5-36
5-36
5-37
5-38
5-39
Specifications
6.1
DC Characteristics
6.2
TolerANT Technology Electrical Characteristics
6.3
AC Characteristics
6-1
6-7
6-11
Contents
ix
6.4
6.5
6.6
PCI and External Memory Interface Timing Diagrams
6.4.1
Target Timing
6.4.2
Initiator Timing
6.4.3
External Memory Timing
SCSI Timing Diagrams
Package Drawings
Appendix A
Register Summary
Appendix B
External Memory Interface Diagram Examples
6-13
6-14
6-24
6-41
6-62
6-71
Index
Customer Feedback
Figures
1.1
1.2
2.1
2.2
2.3
2.4
2.5
2.6
2.7
3.1
4.1
4.2
4.3
5.1
5.2
5.3
5.4
5.5
5.6
5.7
x
Typical LSI53C1000 Board Application
Typical LSI53C1000 System Application
LSI53C1000 Block Diagram
DMA FIFO Sections
LSI53C1000 Host Interface SCSI Data Paths
Regulated Termination for Ultra160 SCSI
Determining the Synchronous Transfer Rate
Interrupt Routing Hardware Using the LSI53C1000
Chained Block Move Instruction
LSI53C1000 Signal Grouping
Single Transition Transfer Waveforms
DT Transfer Waveforms (XCLKS Examples)
DT Transfer Waveforms (XCLKH Examples)
SCRIPTS Overview
Block Move Instruction - First Dword
Block Move Instruction - Second Dword
Block Move Instruction - Third Dword
First 32-bit Word of the I/O Instruction
Second 32-Bit Word of the I/O Instruction
Read/Write Instruction - First Dword
Contents
1-2
1-3
2-2
2-36
2-37
2-40
2-45
2-54
2-55
3-3
4-102
4-103
4-104
5-4
5-5
5-13
5-14
5-14
5-22
5-23
5.8
5.9
5.10
5.11
5.12
5.13
5.14
5.15
5.16
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.13
6.14
6.15
6.16
6.17
6.18
6.19
6.20
6.21
6.22
6.23
6.24
6.25
6.26
6.27
Read/Write Instruction - Second Dword
Transfer Control Instructions - First Dword
Transfer Control Instructions - Second Dword
Transfer Control Instructions - Third Dword
Memory Move Instructions - First Dword
Memory Move Instructions - Second Dword
Memory Move Instructions - Third Dword
Load and Store Instruction - First Dword
Load and Store Instructions - Second Dword
LVD Driver
LVD Receiver
Rise and Fall Time Test Condition
SCSI Input Filtering
Hysteresis of SCSI Receivers
Input Current as a Function of Input Voltage
Output Current as a Function of Output Voltage
External Clock
Reset Input
Interrupt Output
PCI Configuration Register Read
PCI Configuration Register Write
Operating Registers/SCRIPTS RAM Read, 32 Bits
Operating Register/SCRIPTS RAM Read, 64 Bits
Operating Register/SCRIPTS RAM Write, 32 Bits
Operating Register/SCRIPTS RAM Write, 64 Bits
Nonburst Opcode Fetch, 32-Bit Address and Data
Burst Opcode Fetch, 32-Bit Address and Data
Back to Back Read, 32-Bit Address and Data
Back to Back Write, 32-Bit Address and Data
Burst Read, 32-Bit Address and Data
Burst Read, 64-Bit Address and Data
Burst Write, 32-Bit Address and Data
Burst Write, 64-Bit Address and Data
External Memory Read
External Memory Write
Normal/Fast Memory (≥ 128 Kbytes) Single Byte
Access Read Cycle
Contents
5-24
5-27
5-33
5-33
5-35
5-36
5-37
5-38
5-40
6-3
6-4
6-8
6-8
6-9
6-9
6-10
6-11
6-12
6-13
6-15
6-16
6-17
6-19
6-21
6-23
6-25
6-27
6-29
6-31
6-33
6-35
6-37
6-39
6-42
6-46
6-48
xi
6.28
B.4
Normal/Fast Memory (≥ 128 Kbytes) Single Byte
Access Write Cycle
Normal/Fast Memory (≥ 128 Kbytes) Multiple Byte
Access Read Cycle
Normal/Fast Memory (≥ 128 Kbytes) Multiple Byte
Access Write Cycle
Slow Memory (≥ 128 Kbytes) Read Cycle
Slow Memory (≥ 128 Kbytes) Write Cycle
≤ 64 Kbytes ROM Read Cycle
≤ 64 Kbytes ROM Write Cycle
Initiator Asynchronous Send
Initiator Asynchronous Receive
Target Asynchronous Send
Target Asynchronous Receive
Initiator and Target ST Synchronous Transfer
Initiator and Target DT Synchronous Transfer
LSI53C1000 329 BGA Chip - Top View
LSI53C1000 329 Ball Grid Array (Bottom view)
LSI53C1000 329 BGA Mechanical Drawing
16 Kbyte Interface with 200 ns Memory
64 Kbyte Interface with 150 ns Memory
128, 256, 512 Kbyte or 1 Mbyte Interface with 150 ns
Memory
512 Kbyte Interface with 150 ns Memory
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.1
3.2
3.3
PCI Bus Commands and Encoding Types
PCI Cache Mode Alignment
New Phases on SCSI Bus
Bits Used for Parity/CRC/AIP Control and Generation
SCSI Parity Errors and Interrupts
SCF Divisor Values
Parallel ROM Support
Default Download Mode Serial EEPROM Data Format
Power States
LSI53C1000 Internal Pull-ups and Pull-downs
System Signals
Address and Data Signals
6.29
6.30
6.31
6.32
6.33
6.34
6.35
6.36
6.37
6.38
6.39
6.40
6.41
6.42
6.43
B.1
B.2
B.3
6-50
6-52
6-54
6-56
6-58
6-60
6-61
6-62
6-63
6-63
6-64
6-66
6-69
6-72
6-76
6-77
B-1
B-2
B-3
B-4
Tables
xii
Contents
2-4
2-11
2-23
2-34
2-35
2-42
2-60
2-61
2-63
3-4
3-5
3-6
3.4
3.5
3.6
3.7
3.8
3.9
3.10
3.11
3.12
3.13
3.14
3.15
4.1
4.2
4.3
4.4
4.5
5.1
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
Interface Control Signals
Arbitration Signals
Error Reporting Signals
Interrupt Signals
SCSI Bus Interface Signals
SCSI Signals
SCSI Control Signals
GPIO Signals
Flash ROM and Memory Interface Signals
Test Interface Signals
Power and Ground Signals
MAD[3:1] Pin Decoding
PCI Configuration Register Map
SCSI Register Map
Maximum Synchronous Offset
DT Transfer Rates
Single Transition Transfer Rates
Read/Write Instructions
Absolute Maximum Stress Ratings
Operating Conditions
LVD Driver SCSI Signals—SD[15:0], SDP[1:0], SREQ/,
SACK/, SMSG/, SIO/, SCD/, SATN/, SBSY/, SSEL/,
SRST/
LVD Receiver SCSI Signals—SD[15:0], SDP[1:0],
SREQ/, SACK/, SMSG/, SIO/, SCD/, SATN/, SBSY/,
SSEL/, SRST/
DIFFSENS SCSI Signals
Input Capacitance
8 mA Bidirectional Signals—GPIO0_FETCH/,
GPIO1_MASTER/, GPIO2, GPIO3, GPIO4
4 mA Bidirectional Signals—MAD[7:0]
4 mA Output Signals—MAS[1:0]/, MCE/,
MOE/_TESTOUT, MWE/, TDO
8 mA PCI Bidirectional Signals—AD[63:0], C_BE[7:0]/,
FRAME/, IRDY/, TRDY/, DEVSEL/, STOP/, PERR/,
PAR, PAR64, REQ64/, ACK64/
Contents
3-7
3-8
3-8
3-9
3-9
3-10
3-12
3-13
3-14
3-15
3-16
3-18
4-2
4-22
4-34
4-105
4-106
5-25
6-2
6-2
6-3
6-3
6-4
6-4
6-5
6-5
6-5
6-6
xiii
6.11
6.12
6.13
6.14
6.15
6.16
6.17
6.18
6.19
6.20
6.21
6.22
6.23
6.24
6.25
6.26
6.27
6.28
6.29
6.30
6.31
6.32
6.33
6.34
6.35
6.36
6.37
6.38
6.39
6.40
6.41
6.42
xiv
Input Signals—CLK, GNT/, IDSEL, INT_DIR, RST/,
SCLK, TCK, TDI, TEST_HSC, TEST_RST/,
TEST_PD, TMS
8 mA Output Signals—INTA/, INTB/, ALT_INTA/,
ALT_INTB/, REQ/, SERR/
TolerANT Technology Electrical Characteristics for
SE SCSI Signals
External Clock
Reset Input
Interrupt Output
PCI Configuration Register Read
PCI Configuration Register Write
Operating Register/SCRIPTS RAM Read, 32 Bits
Operating Register/SCRIPTS RAM Read, 64 Bits
Operating Register/SCRIPTS RAM Read, 32 Bits
Operating Register/SCRIPTS RAM Write, 64 Bits
Nonburst Opcode Fetch, 32-Bit Address and Data
Burst Opcode Fetch, 32-Bit Address and Data
Back to Back Read, 32-Bit Address and Data
Back to Back Write, 32-Bit Address and Data
Burst Read, 32-Bit Address and Data
Burst Read, 64-Bit Address and Data
Burst Write, 32-Bit Address and Data
Burst Write, 64-Bit Address and Data
External Memory Read
External Memory Write
Normal/Fast Memory (≥ 128 Kbytes) Single Byte
Access Read Cycle
Normal/Fast Memory (≥ 128 Kbytes) Single Byte
Access Write Cycle
Slow Memory (≥ 128 Kbytes) Read Cycle
Slow Memory (≥ 128 Kbytes) Write Cycle
≤ 64 Kbytes ROM Read Cycle
≤ 64 Kbytes ROM Write Cycle
Initiator Asynchronous Send
Initiator Asynchronous Receive
Target Asynchronous Send
Target Asynchronous Receive
Contents
6-6
6-6
6-7
6-11
6-12
6-13
6-15
6-16
6-17
6-18
6-20
6-22
6-24
6-26
6-28
6-30
6-32
6-34
6-36
6-38
6-41
6-45
6-48
6-50
6-56
6-58
6-60
6-61
6-62
6-63
6-63
6-64
6.43
6.44
6.45
6.46
6.47
6.48
6.49
6.50
6.51
6.52
A.1
A.2
SCSI-1 Transfers (SE 5.0 Mbytes)
SCSI-2 Fast Transfers 10.0 Mbytes (8-Bit Transfers) or
20.0 Mbytes (16-Bit Transfers) 40 MHz Clock
Ultra SCSI SE Transfers 20.0 Mbytes (8-Bit Transfers)
or 40.0 Mbytes (16-Bit Transfers) Quadrupled 40 MHz
Clock
Ultra2 SCSI Transfers 40.0 Mbyte (8-Bit Transfers) or
80.0 Mbyte (16-Bit Transfers) Quadrupled 40 MHz
Clock
SCSI-2 Fast Transfers 10.0 Mbytes (8-Bit Transfers)
or 20.0 Mbytes (16-Bit Transfers) 40 MHz Clock
Ultra SCSI SE Transfers 20.0 Mbytes (8-Bit Transfers)
or 40.0 Mbytes (16-Bit Transfers) Quadrupled 40 MHz
Clock
Ultra2 SCSI Transfers 40.0 Mbyte (8-Bit Transfers) or
80.0 Mbyte (16-Bit Transfers) Quadrupled 40 MHz
Clock
Ultra160 SCSI Transfers 160.0 Mbyte
(16-Bit Transfers) Quadrupled 40 MHz Clock
Alphanumeric list by Signal Names
Alphanumeric List by BGA Positions
LSI53C1000 PCI Register Map
LSI53C1000 SCSI Register Map
Contents
6-64
6-65
6-65
6-66
6-67
6-67
6-68
6-69
6-74
6-75
A-1
A-3
xv
xvi
Contents
Chapter 1
Introduction
This chapter provides a general overview on the LSI53C1000 PCI to
Ultra160 SCSI Controller. This chapter contains the following sections:
•
Section 1.1, “General Description”
•
Section 1.2, “Benefits of Ultra160 SCSI”
•
Section 1.3, “Benefits of SureLINK (Ultra160 SCSI Domain
Validation)”
•
Section 1.4, “Benefits of LVDlink”
•
Section 1.5, “Benefits of TolerANT® Technology”
•
Section 1.6, “Summary of LSI53C1000 Benefits”
1.1 General Description
The LSI53C1000 brings Ultra160 SCSI performance to host adapter,
workstation, and server designs, making it easy to add a
high-performance SCSI bus to any PCI system.
The LSI53C1000 supports a 64-bit or 32-bit, 66 or 33 MHz PCI bus. The
Ultra160 SCSI features implemented in the LSI53C1000 are: Double
Transition (DT) clocking, Cyclic Redundancy Check (CRC), and Domain
Validation. These features comply with the Ultra160 SCSI industry
initiative.
DT clocking permits the LSI53C1000 to transfer data up to
160 megabytes per second (Mbytes/s). CRC improves the integrity of the
SCSI data transmission through enhanced detection of communication
errors. Asynchronous Information Protection (AIP) augments CRC to
protect all nondata phases, providing complete end-to-end protection of
the SCSI I/O. SureLINK™ Domain Validation detects the SCSI bus
LSI53C1000 PCI to Ultra160 SCSI Controller
1-1
configuration and automatically tests and adjusts the SCSI transfer rate
to optimize interoperability. Three levels of Domain Validation are
provided, assuring robust system operation.
The LSI53C1000 has a local memory bus. This allows local storage of
the device’s BIOS ROM in flash memory or standard EPROMs. The
LSI53C1000 supports programming of local flash memory for BIOS
updates. The chip is packaged in a 329 Ball Grid Array (BGA). Figure 1.1
shows a typical LSI53C1000 board application connected to external
ROM or flash memory.
Figure 1.1
Typical LSI53C1000 Board Application
68-Pin
SCSI
Connector
and
Terminator
SCSI Data,
Parity, and
Control Signals
LSI53C1000
64-Bit / 66MHz
PCI to
Single Channel
Ultra160 SCSI
Controller
Memory
Address/Data
Bus
GPIO/[1:0]
Memory Control
Block
Flash ROM
Serial EEPROM
PCI Interface
PCI Address, Data, Parity and Control Signals
LVDlink™ technology is the LSI Logic implementation of Low Voltage
Differential (LVD). LVDlink transceivers allow the LSI53C1000 to perform
either Single-Ended (SE) or LVD transfers. The LSI53C1000 integrates a
high-performance SCSI core, a 64-bit/66 MHz PCI bus master DMA core,
and the LSI Logic SCSI SCRIPTS™ processor to meet the flexibility
requirements of Ultra160 SCSI standards. It implements multithreaded
I/O algorithms with minimum processor intervention, solving the protocol
overhead problems of previous intelligent and nonintelligent adapter
designs. Figure 1.2 illustrates a typical LSI53C1000 system application.
1-2
Introduction
PCI Bus
Interface
Controller
Typical LSI53C1000 System Application
PCI Bus
One PCI Bus Load
Figure 1.2
LSI53C1000 PCI
to Ultra160 SCSI
Controller
SCSI Bus Fixed Disk, Optical Disk,
Printer, Tape, and Other
SCSI Peripherals
Processor Bus
PCI Graphic Accelerator
PCI Fast Ethernet
Memory
Controller
Central
Processing
Unit
(CPU)
Memory
Typical PCI Computer
System Architecture
1.1.1 New Features in the LSI53C1000
The LSI53C1000 is functionally similar to the LSI53C1010 PCI to Dual
Channel Ultra160 SCSI Multifunction Controller, except that it
implements a single SCSI function. Following is a list of LSI53C1000
features:
•
Supports 66 MHz PCI
•
Complies with PCI 2.2 specification
•
Supports Ultra160 DT clocking for data transfers up to 160 Mbytes/s
General Description
1-3
•
Supports enhanced protection on nondata asynchronous phases
through AIP
•
Supports CRC checking and generation in DT phases
•
Supports Domain Validation
–
Basic (level 1) with Inquiry Command (Inquiry Check)
–
Enhanced (level 2) with Read/Write Buffer
–
Margined (level 3) with margining of LVD drivers and
programmable skew test
•
All cycles to SCRIPTS RAM stay internal to the device, not
generating PCI cycles
•
SCRIPTS engine with improved instruction fetch performance
1.2 Benefits of Ultra160 SCSI
Ultra160 SCSI delivers data up to two times faster than Ultra2 SCSI.
Ultra160 SCSI is an extension of the SPI-3 draft standard that allows
faster synchronous SCSI data transfer rates than Ultra2 SCSI. When
enabled, Ultra160 SCSI performs 80 megatransfers per second
(megatransfers/s) resulting in approximately double the synchronous
data transfer rates of Ultra2 SCSI. The LSI53C1000 performs 16-bit,
Ultra160 SCSI synchronous data transfers as fast as 160 Mbytes/s. This
advantage is most noticeable in heavily loaded systems, or large block
size applications such as video on-demand and image processing.
The Ultra160 data transfer speed is accomplished using DT clocking.
DT clocking refers to transferring data on both polarity edges of the
request or acknowledge signals. Data is clocked on both rising and falling
edges of the request and acknowledge signals. Double-edge clocking
doubles data transfer speeds without increasing the clock rate.
Ultra160 SCSI also includes CRC, which offers higher levels of data
reliability by ensuring complete integrity of transferred data. CRC is a
32-bit scheme, referred to as CRC-32. CRC is guaranteed to detect all
single bit errors, any two bits in error, or any combination of errors within
a single 32-bit range.
1-4
Introduction
AIP is also supported by the LSI53C1000, protecting all nondata phases,
including command, status, and messages. CRC, along with AIP,
provides end-to-end protection of the SCSI I/O.
SureLINK Domain Validation provides 3 levels of integrity checking:
Basic (level 1), Enhanced (level 2), and Margined (level 3). Further
information on SureLINK is available in Section 1.3, “Benefits of
SureLINK (Ultra160 SCSI Domain Validation).”
An advantage of Ultra160 SCSI is that it significantly improves SCSI
bandwidth while preserving existing hardware and software investments.
The primary software changes required are to enable the chip to perform
synchronous negotiations for Ultra160 SCSI rates and to enable the
clock quadrupler. Ultra160 SCSI uses the same connectors as Ultra
SCSI and Ultra2 SCSI. Chapter 2 contains more information on migrating
an Ultra SCSI or Ultra2 SCSI design to an Ultra160 SCSI design.
1.3 Benefits of SureLINK (Ultra160 SCSI Domain Validation)
SureLINK represents the very latest SCSI interconnect management
solution. It ensures robust and low risk Ultra160 SCSI implementations
by extending the Domain Validation guidelines documented in the ANSI
T10 SPI-3 specifications. Domain Validation verifies that the system is
capable of transferring data at Ultra160 speeds, allowing it to renegotiate
to lower speed and bus width if necessary. SureLINK is the software
control for the manageability enhancements in the LSI53C1000. Fully
integrated in the Storage Device Management System (SDMS™)
software solution, SureLINK provides Domain Validation at boot time as
well as throughout system operation. SureLINK extends to the DMI
(Desktop Management Interface) based System Management
components of SDMS, providing the network administrator remote
management capability.
SureLINK Domain Validation provides 3 levels of integrity checking:
Basic (level 1), Enhanced (level 2), and Margined (level 3). The basic
check consists of an inquiry command to detect gross problems. The
enhanced check sends a known data pattern using the Read and Write
Buffer commands to detect additional problems. Margined check verifies
that the physical parameters have some degree of margin. By varying
LVD drive strength and REQ/ACK timing characteristics, level 3 verifies
Benefits of SureLINK (Ultra160 SCSI Domain Validation)
1-5
that no errors occur on the transfers. These altered signals are only used
during the diagnostic check and not during normal system operation. If
errors occur with any of these checks, the system can drop back to a
lower transmission speed, on a per-target basis, to ensure robust system
operation.
1.4 Benefits of LVDlink
The LSI53C1000 supports LVD through LVDlink. This signaling
technology increases the reliability of SCSI data transfers over longer
distances than are supported by SE SCSI. The low current output of LVD
allows the I/O transceivers to be integrated directly onto the chip. LVD
provides the reliability of High Voltage Differential (HVD) SCSI without
the added cost of external differential transceivers. Ultra160 SCSI with
LVD allows a longer SCSI cable and more devices on the bus, with the
same cables defined in the SCSI-3 Parallel Interface standard for Ultra
SCSI. LVD provides a long-term migration path to even faster SCSI
transfer rates without compromising signal integrity, cable length, or
connectivity.
For backward compatibility to existing SE devices, the LSI53C1000
features universal LVDlink transceivers that support LVD SCSI and SE
SCSI. This allows use of the LSI53C1000 in both legacy and Ultra160
SCSI applications.
1.5 Benefits of TolerANT® Technology
The LSI53C1000 features TolerANT technology, which includes active
negation on the SCSI drivers and input signal filtering on the SCSI
receivers. Active negation causes the SCSI Request, Acknowledge,
Data, and Parity signals to be actively driven HIGH rather than passively
pulled up by terminators.
TolerANT receiver technology improves data integrity in unreliable
cabling environments where other devices would be subject to data
corruption. TolerANT receivers filter the SCSI bus signals to eliminate
unwanted transitions, without the long signal delay associated with
RC-type input filters. This improved driver and receiver technology helps
eliminate double clocking of data which is the single biggest reliability
1-6
Introduction
issue with SCSI operations. TolerANT input signal filtering is a built-in
feature of the LSI53C1000 and all LSI Logic Fast SCSI, Ultra SCSI,
Ultra2 SCSI, and Ultra160 SCSI devices.
The benefits of TolerANT technology include increased noise immunity
when the signal transitions to HIGH, better performance due to balanced
duty cycles, and improved fast SCSI transfer rates. In addition, TolerANT
SCSI devices do not cause glitches on the SCSI bus at power-up or
power-down. This protects other devices on the bus from data corruption.
When used with the LVDlink transceivers, TolerANT technology provides
excellent signal quality and data reliability in real world cabling
environments. TolerANT technology is compatible with both the
Alternative One and Alternative Two termination schemes proposed by
the American National Standards Institute.
1.6 Summary of LSI53C1000 Benefits
This section provides a summary of the LSI53C1000 features and
benefits. It contains information on SCSI Performance, PCI Performance,
Integration, Ease of Use, Flexibility, Reliability, and Testability.
1.6.1 SCSI Performance
The LSI53C1000:
•
Performs wide, Ultra160 SCSI synchronous data transfers as fast as
160 Mbytes/s using DT clocking.
•
Supports CRC checking and generation in DT phases.
•
Protects nondata phases with AIP.
•
Supports Domain Validation:
•
–
Basic (Level 1)
–
Enhanced (Level 2)
–
Margined (Level 3)
Includes integrated LVDlink universal transceivers:
–
Supports SE and LVD signals.
–
Allows greater device connectivity and longer cable length.
Summary of LSI53C1000 Benefits
1-7
1-8
–
LVDlink transceivers save the cost of external differential
transceivers.
–
Supports a long-term performance migration path.
•
Bursts of up to 512 bytes across the PCI bus with an independent
896–920 byte FIFO.
•
Handles phase mismatches in SCRIPTS without interrupting the
system processor.
•
Includes an on-chip SCSI clock quadrupler that allows the chip to
achieve Ultra160 SCSI transfer rates with an input frequency of
40 MHz.
•
Includes 8 Kbytes of internal RAM for SCRIPTS instruction storage.
•
Supports 31 levels of SCSI synchronous offset in the Single
Transition (ST) mode and 62 levels in the DT mode.
•
Supports variable block size and scatter/gather data transfers.
•
Performs sustained Memory-to-Memory DMA transfers to
approximately 100 Mbytes/s.
•
Minimizes the SCSI I/O start latency.
•
Performs complex bus sequences without interrupts, including
restoring data pointers.
•
Reduces ISR overhead through a unique interrupt status reporting
method.
•
Includes RAID Ready SCSI on the motherboard with a separate
interrupt for routing to a RAID adapter.
•
Supports Load/Store SCRIPTS instructions to increase the
performance of data transfers to and from the chip registers without
using PCI cycles.
•
Includes SCRIPTS support of 64-bit addressing.
•
Supports target disconnect and later reconnect with no interrupt to
the system processor.
•
Supports multithreaded I/O algorithms in SCSI SCRIPTS with fast
I/O context switching.
•
Supports expanded Register Move instructions to support additional
arithmetic capability.
Introduction
1.6.2 PCI Performance
The LSI53C1000:
•
Complies with PCI 2.2 specification.
•
Supports a 64-bit/66 MHz PCI interface for 528 Mbytes/s bandwidth
that:
–
Can function in a 32-bit or 64-bit PCI slot
–
Operates at 33 or 66 MHz
–
Supports dual address cycle (DAC) generation for all SCRIPTS
•
Bursts 4/8, 8/16, 16/32, 32/64, or 64/128 Qword/Dword transfers
across the PCI bus.
•
Supports 32-bit or 64-bit word data bursts with variable burst lengths.
•
Prefetches up to 8 Dwords of SCRIPTS instructions.
•
Bursts SCRIPTS opcode fetches across the PCI bus.
•
Performs zero wait-state bus master data bursts up to 528 Mbytes/s
(@ 66 MHz).
•
Supports PCI Cache Line Size (CLS) register.
•
Supports PCI Write and Invalidate, Read Line, and Read Multiple
commands.
•
Complies with PCI Bus Power Management Specification,
Revision 1.1.
•
Complies with PC99.
1.6.3 Integration
The following features ease integration of the LSI53C1000 into a system.
•
Ultra160 SCSI PCI Controller.
•
Integrated LVD transceivers.
•
Full 32-bit or 64-bit PCI DMA bus master.
•
Memory-to-Memory Move instructions allow use as a third-party PCI
bus DMA controller.
•
Integrated SCRIPTS processor.
Summary of LSI53C1000 Benefits
1-9
1.6.4 Ease of Use
The following features of the LSI53C1000 make the device user friendly.
•
Up to 1 Mbyte of add-in memory support for BIOS and SCRIPTS
storage.
•
Reduced SCSI development effort.
•
Compiler-compatible with existing LSI53C7XX and LSI53C8XX
family SCRIPTS.
•
Direct connection to PCI and SCSI SE and LVD.
•
Development tools and sample SCSI SCRIPTS available.
•
Maskable and pollable interrupts.
•
Wide SCSI, A or P cable, and up to 15 devices are supported.
•
Three programmable SCSI timers: Select/Reselect,
Handshake-to-Handshake, and General Purpose.
•
Software for PC-based operating system support.
•
Support for relative jumps.
•
SCSI Selected As ID bits for responding with multiple IDs.
1.6.5 Flexibility
The following features increase the flexibility of the LSI53C1000:
1-10
•
Universal LVD transceivers are backward compatible with SE
devices.
•
High level programming interface (SCSI SCRIPTS).
•
Programs local and bus flash memory.
•
Tailored SCSI sequences execute from main system RAM or internal
SCRIPTS RAM.
•
Flexible programming interface to tune I/O performance or to adapt
to unique SCSI devices.
•
Support for changes in the logical I/O interface definition.
•
Low level access to all registers and all SCSI bus signals.
•
Fetch, Master, and Memory Access control pins.
•
Separate SCSI and system clocks.
Introduction
•
SCSI clock quadrupler bits enable Ultra160 SCSI transfer rates with
a 40 MHz SCSI clock input.
•
Selectable INT pin disable bit.
•
Compatible with 3.3 V and 5 V PCI.
1.6.6 Reliability
The following features enhance the reliability of the LSI53C1000:
•
CRC and AIP provide end-to-end SCSI I/O protection.
•
2 kV ESD protection on SCSI signals.
•
Protection against bus reflections due to impedance mismatches.
•
Controlled bus assertion times (reduces RFI, improves reliability, and
eases FCC certification).
•
Latch-up protection greater than 150 mA.
•
Voltage feed-through protection (minimum leakage current through
SCSI pads).
•
A high proportion of pins are power and ground.
•
Power and ground isolation of I/O pads and internal chip logic.
•
TolerANT technology provides:
–
Active negation of SCSI Data, Parity, Request, and Acknowledge
signals for improved fast SCSI transfer rates.
–
Input signal filtering on SCSI receivers improves data integrity,
even in noisy cabling environments.
1.6.7 Testability
The following features enhance the testability of the LSI53C1000:
•
All SCSI signals accessible through programmed I/O.
•
SCSI bus signal continuity checking.
•
Support for single-step mode operation.
•
JTAG boundary scan.
Summary of LSI53C1000 Benefits
1-11
1-12
Introduction
Chapter 2
Functional Description
This chapter provides a functional description of the LSI53C1000. This
chapter is divided into the following sections:
•
Section 2.1, “PCI Functional Description”
•
Section 2.2, “SCSI Functional Description”
•
Section 2.3, “Parallel ROM Interface”
•
Section 2.4, “Serial EEPROM Interface”
•
Section 2.5, “Power Management”
The LSI53C1000 is composed of the following modules:
•
64-bit PCI Interface
•
PCI to Wide Ultra160 SCSI Controller
•
ROM/Flash Memory Controller
•
Serial EEPROM Controller
Figure 2.1 illustrates the relationship between these modules.
LSI53C1000 PCI to Ultra160 SCSI Controller
2-1
Figure 2.1
LSI53C1000 Block Diagram
PCI Bus
64-Bit PCI Interface, PCI Configuration Register
Wide Ultra160 SCSI Channel
SCSI SCRIPTS
Processor
Operating
Registers
Serial EEPROM Controller
and Autoconfiguration
ROM/Flash Memory Control
Local
Memory
Bus
944 Byte
DMA FIFO
8-Dword SCRIPTS
Prefetch Buffer
8-Kbyte
SCRIPTS RAM
SCSI FIFO and SCSI Control Block
Universal TolerANT
Drivers and Receivers
JTAG
JTAG
Bus
ROM/Flash
Memory
Bus
2 Wire Serial
EEPROM Bus
Ultra160
SCSI Bus
The LSI53C1000 has a wide Ultra160 SCSI channel. The SCSI channel
incorporates an independent DMA FIFO and a separate internal 8 KByte
SCRIPTS RAM.
2-2
Functional Description
2.1 PCI Functional Description
The LSI53C1000 is a PCI to Ultra160 SCSI Controller.
2.1.1 PCI Addressing
There are three physical address spaces defined in the PCI specification:
•
PCI Configuration space
•
I/O space for operating registers
•
Memory space for operating registers
2.1.1.1 Configuration Space
The host processor uses this configuration space to initialize the
LSI53C1000. A configuration space register is defined for the SCSI
function. The configuration register is initialized by the system BIOS
using PCI configuration cycles. The configuration space is a contiguous
256 x 8-bit set of addresses. Decoding C_BE[3:0]/ determines if a PCI
cycle is intended to access the configuration register space. The IDSEL
bus signal is a “chip select” that allows access to the configuration
register space only. A configuration read/write cycle without IDSEL is
ignored. The host processor uses the eight lower order address bits
(AD[7:0]) to select a specific 8-bit register. Bits AD[10:8] decode the
SCSI function configuration register (AD[10:8] = 0b000). Table 4.1 on
page 4-2 is an illustration of the PCI Configuration Register Map.
At initialization time, each PCI device is assigned a base address for
memory and I/O accesses. In the LSI53C1000, the upper 24 bits of the
address are selected. On every access, the LSI53C1000 compares its
assigned base addresses with the value on the Address/Data bus during
the PCI address phase. If the upper 24 bits match, the access is
designated for the LSI53C1000. The low order eight bits define the
register to be accessed. A decode of C_BE[3:0]/ determines which
register and what type of access is performed.
PCI Functional Description
2-3
2.1.1.2 I/O Space
The PCI specification defines I/O space as a contiguous 32-bit I/O
address that is shared by all system resources, including the
LSI53C1000. Base Address Register Zero (BAR0) (I/O) determines
which 256-byte I/O area this device occupies.
2.1.1.3 Memory Space
The PCI specification defines memory space as a contiguous 64-bit
memory address that is shared by all system resources. Base Address
Register One (BAR1) (MEMORY) determines which 1-Kbyte memory
area this device occupies. The SCSI function uses an 8-Kbyte SCRIPTS
RAM memory space. Base Address Register Two (BAR2) (MEMORY)
determines the 8-Kbyte memory area the SCRIPTS RAM occupies.
2.1.2 PCI Bus Commands and Functions Supported
Bus commands indicate to the target the type of transaction the master
is requesting. Bus commands are encoded on the C_BE[3:0]/ lines
during the address phase. PCI bus commands and encoding types
appear in Table 2.1.
Table 2.1
PCI Bus Commands and Encoding Types
C_BE[3:0]/ Command Type
2-4
Supported
as Master
Supported
as Slave
0000
Interrupt Acknowledge
No
No
0001
Special Cycle
No
No
0010
I/O Read
Yes
Yes
0011
I/O Write
Yes
Yes
0100
Reserved
N/A
N/A
0101
Reserved
N/A
N/A
0110
Memory Read
Yes
Yes
0111
Memory Write
Yes
Yes
1000
Reserved
N/A
N/A
Functional Description
Table 2.1
PCI Bus Commands and Encoding Types (Cont.)
C_BE[3:0]/ Command Type
Supported
as Master
Supported
as Slave
1001
Reserved
N/A
N/A
1010
Configuration Read
No
Yes
1011
Configuration Write
No
Yes
1100
Memory Read Multiple
Yes1
Yes (defaults to 0110)
1101
Dual Address Cycle (DAC)
Yes
Yes
1110
Memory Read Line
Yes1
Yes (defaults to 0110)
1111
Memory Write and
Invalidate
Yes2
Yes (defaults to 0111)
1. See the DMA Mode (DMODE) register.
2. See the Chip Test Three (CTEST3) register.
2.1.2.1 Interrupt Acknowledge Command
The LSI53C1000 does not respond to this command as a slave and it
never generates this command as a master.
2.1.2.2 Special Cycle Command
The LSI53C1000 does not respond to this command as a slave and it
never generates this command as a master.
2.1.2.3 I/O Read Command
The LSI53C1000 uses the I/O Read command to read data from an
agent mapped in the I/O address space. When decoding I/O cycles, the
LSI53C1000 decodes the lower 32 address bits and ignores the
upper 32 address bits.
2.1.2.4 I/O Write Command
The LSI53C1000 uses the I/O Write command to write data to an agent
mapped in the I/O address space. When decoding I/O cycles, the
LSI53C1000 decodes the lower 32 address bits and ignores the
upper 32 address bits.
PCI Functional Description
2-5
2.1.2.5 Reserved Command
The given bus encoding is reserved.
2.1.2.6 Memory Read Command
The LSI53C1000 uses the Memory Read command to read data from an
agent mapped in the Memory Address Space. The target may perform
an anticipatory read if such a read produces no side effects.
2.1.2.7 Memory Write Command
The LSI53C1000 uses the Memory Write command to write data to an
agent mapped in the Memory Address Space. When the target returns
“ready”, it assumes responsibility for data coherency, which includes
ordering.
2.1.2.8 Configuration Read Command
The Configuration Read command reads the configuration space of a
device. The LSI53C1000 never generates this command as a master, but
does respond to it as a slave. A device on the PCI bus selects the
LSI53C1000 by asserting its IDSEL signal when AD[1:0] are 0b00.
During the address phase of a configuration cycle, AD[7:2] address one
of the 64 Dword registers in the configuration space of each device.
C_BE[3:0]/ address the individual bytes within each Dword. AD[10:8]
indicate which device on the LSI53C1000 is being addressed. The
LSI53C1000 treats AD[63:11] as logical don’t cares.
2.1.2.9 Configuration Write Command
The Configuration Write command writes the configuration space of a
device. The LSI53C1000 never generates this command as a master, but
does respond to it as a slave. A device on the PCI bus selects the
LSI53C1000 by asserting its IDSEL signal when AD[1:0] are 0b00.
During the address phase of a configuration cycle, AD[7:2] address one
of the 64 Dword registers in the configuration space of each device.
C_BE[3:0]/ address the individual bytes within each Dword. AD[10:8]
indicate which device on the LSI53C1000 is being addressed. The
LSI53C1000 treats AD[63:11] as logical don’t cares.
2-6
Functional Description
2.1.2.10 Memory Read Multiple Command
This command is identical to the Memory Read command, except it
additionally indicates that the master intends to fetch multiple cache lines
before disconnecting. The LSI53C1000 supports PCI Memory Read
Multiple functionality and issues Memory Read Multiple commands on
the PCI bus when the Read Multiple mode is enabled. This mode is
enabled by setting bit 2 (ERMP) of the DMA Mode (DMODE) register. If
the cache mode is enabled, a Memory Read Multiple command is issued
on all read cycles, except opcode fetches, when the following conditions
are met:
•
The CLSE bit (Cache Line Size Enable, bit 7, DMA Control (DCNTL)
register) is set.
•
The ERMP bit (Enable Read Multiple, bit 2, DMA Mode (DMODE)
register) is set.
•
The Cache Line Size (CLS) register contains a legal burst size value
(8, 16, 32, 64, or 128 Dwords) that is less than or equal to the
DMODE burst size.
•
The transfer crosses a cache line boundary.
When these conditions are met, the chip issues a Memory Read Multiple
command instead of a Memory Read during all PCI read cycles.
Burst Size Selection – The Read Multiple command reads in multiple
cache lines of data during a single bus ownership. Revision 2.2 of the
PCI specification specifies the number of cache lines to read as a
multiple of the cache line size. The logic selects the largest multiple of
the cache line size based on the amount of data to transfer. The
maximum allowable burst size is determined from the DMA Mode
(DMODE) burst size bits and the Chip Test Five (CTEST5) register, bit 2.
2.1.2.11 Dual Address Cycles (DAC) Command
When 64-bit addressing is required, the LSI53C1000 performs DAC, per
the PCI 2.2 specification. If any of the selector registers contain a
nonzero value, a DAC is generated.
PCI Functional Description
2-7
2.1.2.12 Memory Read Line Command
This command is identical to the Memory Read command, except it
additionally indicates that the master intends to fetch a complete cache
line. This command is intended for use with bulk sequential data
transfers where the memory system and the requesting master might
gain some performance advantage by reading to a cache line boundary
rather than a single memory cycle. The Read Line function in the
LSI53C1000 takes advantage of the PCI 2.2 specification regarding
issuance of this command.
If the cache mode is disabled, no Read Line commands are issued.
If the cache mode is enabled, a Read Line command is issued on all
read cycles, except nonprefetch opcode fetches, when the following
conditions are met:
•
The CLSE bit (Cache Line Size Enable, bit 7, of the DMA Control
(DCNTL) register) is set.
•
The ERL bit (Enable Read Line, bit 3, of the DMA Mode (DMODE)
register) is set.
•
The Cache Line Size (CLS) register must contain a legal burst size
value (8, 16, 32, 64, or 128 Dwords) that is less than or equal to the
DMODE burst size.
•
The transfer crosses a Dword boundary, but not a cache line
boundary.
When these conditions are met, the chip issues a Read Line command
instead of a Memory Read during all PCI read cycles. Otherwise, it
issues a normal Memory Read command.
Read Multiple with Read Line Enabled – When both the Read
Multiple and Read Line modes are enabled, the Read Line command is
not issued if the above conditions are met. Instead, a Read Multiple
command is issued.
If the Read Multiple mode is enabled, Read Multiple commands are
issued if the Read Multiple conditions are met.
2-8
Functional Description
2.1.2.13 Memory Write and Invalidate Command
The Memory Write and Invalidate command is identical to the Memory
Write command, except it additionally guarantees a minimum transfer of
one complete cache line. That is, the master intends to write all bytes
within the addressed cache line in a single PCI transaction unless
interrupted by the target. This command requires implementation of the
PCI Cache Line Size (CLS) register. The LSI53C1000 enables Memory
Write and Invalidate cycles when bit 0 (WRIE), in the Chip Test Three
(CTEST3) register, and bit 4 (WIE), in the PCI Command register, are
set.
When the following conditions are met, Memory Write and Invalidate
commands are issued:
•
The following bits are set:
–
The CLSE bit (Cache Line Size Enable, bit 7, of the DMA Control
(DCNTL) register),
–
The WRIE bit (Write and Invalidate Enable, bit 0, of the Chip Test
Three (CTEST3) register),
–
Bit 4 of the PCI Configuration Command register.
•
The Cache Line Size (CLS) register contains a legal burst size value
(8, 16, 32, 64, or 128 Dwords) that is less than or equal to the DMA
Mode (DMODE) burst size.
•
The chip has enough bytes in the DMA FIFO to complete at least
one full cache line burst.
•
The chip is aligned to a cache line boundary.
When these conditions are met, the LSI53C1000 issues a Write and
Invalidate command instead of a Memory Write command during all PCI
write cycles.
Multiple Cache Line Transfers – The Memory Write and Invalidate
command can write multiple cache lines of data in a single bus
ownership. The chip issues a burst transfer as soon as it reaches a
cache line boundary. The transfer size is not automatically the cache line
size, but rather a multiple of the cache line size specified in Revision 2.2
of the PCI specification. The logic selects the largest multiple of the
cache line size based on the transfer size. The maximum allowable burst
size is determined from the DMA Mode (DMODE) burst size bits, and
PCI Functional Description
2-9
bit 2 of the Chip Test Five (CTEST5) register. If multiple cache line size
transfers are not desired, set the DMODE burst size to exactly the cache
line size and the chip will only issue single cache line transfers.
After each data transfer, the chip re-evaluates the burst size based on
the amount of remaining data to transfer. It again selects the highest
possible multiple of the cache line size, and no larger than the DMA
Mode (DMODE) burst size. Usually, the chip selects the DMODE burst
size after alignment and issues bursts of this size. The burst size is, in
effect, throttled down toward the end of a long Memory Move or Block
Move transfer until only the cache line size left is burst size. The chip
finishes the transfer with this burst size.
Latency – In accordance with the PCI specification, the latency timer is
ignored when issuing a Memory Write and Invalidate command.
Therefore, when a latency time-out occurs, the LSI53C1000 continues to
transfer up to a cache line boundary. At that point, the chip relinquishes
the bus, and finishes the transfer at a later time using another bus
ownership. If the chip is transferring multiple cache lines it continues to
transfer until the next cache boundary is reached.
PCI Target Retry – A retry is defined as a STOP with no TRDY/,
indicating that no data was transferred. If the target issues a retry during
a Memory Write and Invalidate transfer, the chip relinquishes the bus and
immediately tries to finish the transfer on another bus ownership. The
chip issues another Memory Write and Invalidate command on the next
ownership, in accordance with the PCI specification.
PCI Target Disconnect – If the target device issues a disconnect during
a Memory Write and Invalidate transfer, the LSI53C1000 relinquishes the
bus and immediately tries to finish the transfer on another bus ownership.
The chip does not issue another Memory Write and Invalidate command
on the next ownership unless the address is aligned.
2.1.3 PCI Cache Mode
The LSI53C1000 supports the PCI specification for an 8-bit Cache Line
Size (CLS) register located in the PCI configuration space. The Cache
Line Size (CLS) register provides the ability to sense and react to
nonaligned addresses corresponding to cache line boundaries. In
conjunction with the Cache Line Size (CLS) register, the PCI commands
2-10
Functional Description
Memory Read Line (MRL), Memory Read Multiple (MRM), and Memory
Write and Invalidate (MWI) are individually software enabled or disabled.
Table 2.2 provides information on the PCI cache mode alignment.
Table 2.2
PCI Cache Mode Alignment
Host Memory
A
0x00
B
0x04
0x08
C
0x0C
D
0x10
0x14
0x18
0x1C
E
0x20
0x24
0x28
0x2C
F
0x30
0x34
0x38
0x3C
G
0x40
0x44
0x48
0x4C
H
0x50
0x54
0x58
0x5C
0x60
PCI Functional Description
2-11
2.1.3.1 Enabling Cache Mode
To enable the cache logic to issue PCI cache commands (Memory Read
Line, Memory Read Multiple, and Memory Write and Invalidate) on any
PCI master operation, the following conditions must be met:
•
The Cache Line Size Enable bit in the DMA Control (DCNTL) register
must be set.
•
The PCI Cache Line Size (CLS) register must contain a valid binary
cache size, i.e., 8, 16, 32, 64, or 128 Dwords. These values are the
only valid cache sizes.
•
The programmed burst size (in Dwords) must be equal to or greater
than the cache line size register. The DMA Mode (DMODE) register,
bits [7:6], and the Chip Test Five (CTEST5) register, bit 2, denote the
burst length.
•
The device must be performing a PCI Master transfer. The following
PCI Master transactions do not utilize the PCI cache logic, so no PCI
cache commands are issued during these types of cycles: a
nonprefetch SCRIPTS fetch, a Load/Store data transfer, and a data
flush operation. All other types of PCI Master transactions utilize the
PCI cache logic.
Not only must the above four conditions be met in order for the cache
logic to control the type of PCI cache command that is issued, proper
alignment is also necessary during write operations. If these conditions
are not met for any given PCI Master transaction, a Memory Read or
Memory Write is issued and no cache write alignment is done.
2.1.3.2 Issuing Cache Commands
In order to issue each type of PCI cache command, the corresponding
enable bit(s) must be set.
2-12
•
To issue Memory Read Line commands, the Enable Read Line
(ERL) bit in the DMA Mode (DMODE) register must be set.
•
To issue Memory Read Multiples, the Enable Read Multiple (ERMP)
bit in the DMA Mode (DMODE) register must be set.
•
To issue Memory Write and Invalidates, both the Write and Invalidate
Enable (WRIE) bit in the Chip Test Three (CTEST3) register and the
Write and Invalidate Enable (WIE) bit in the PCI configuration
Command register must be set.
Functional Description
If the corresponding cache command is not enabled, the cache logic falls
back to the next command enabled. For example, if the Memory Read
Multiple command is not enabled and the Memory Read Line command
is, Memory Read Line command is issued in place of Memory Read
Multiple command. If no cache commands are enabled, cache write
alignment still occurs but no cache commands are issued; only Memory
Reads and Memory Writes are issued.
2.1.3.3 Memory Read Caching
The type of Memory Read command issued depends on the starting
location of the transfer and the number of bytes to be transferred. During
reads, no cache alignment is done, as it is neither required nor optional
according to PCI 2.2 specification. Reads are a programmed burst length
in size, as set in the DMA Mode (DMODE) and Chip Test Five (CTEST5)
registers. In the case of a transfer that is smaller than the burst length,
all bytes for that transfer are read in one PCI burst transaction. If the
transfer crosses a Dword boundary (A[1:0] = 0b00), a Memory Read Line
command is issued. If the transfer crosses a cache boundary, as
specified by the cache line size programmed into the PCI configuration
register, a Memory Read Multiple command is issued. If a transfer does
not cross a Dword or cache boundary or if cache mode is not enabled a
Memory Read command is issued.
2.1.3.4 Memory Write Caching
Memory Writes are aligned in a single burst transfer to reach a cache
boundary. At that point, Memory Write and Invalidate commands are
issued and continue at the burst length programmed into the DMA Mode
(DMODE) register. Memory Write and Invalidate commands continue to
be issued as long as the remaining byte count is greater than the
Memory Write and Invalidate threshold. When the remaining byte count
drops below this threshold, a single Memory Write burst is issued to
complete the transfer.
In summary, the general pattern for PCI writes is:
•
A single Memory Write to align to a cache boundary
•
Multiple Memory Write and Invalidates
•
A single data residual Memory Write to complete the transfer
PCI Functional Description
2-13
2.1.3.5 Examples
The examples in this section employ the following abbreviations:
MR = Memory Read, MRL = Memory Read Line, MRM = Memory Read
Multiple, MW = Memory Write, MWI = Memory Write and Invalidate.
Read Example 1 – Burst = 4 Dwords, Cache Line Size = 4 Dwords:
2-14
A to B:
MRL (6 bytes)
A to C:
MRL (13 bytes)
A to D:
MRM (16 bytes)
MR (1 byte)
C to D:
MRM (5 bytes)
C to E:
MRM (16 bytes)
MRM (5 bytes)
D to F:
MRM (16 bytes)
MRM (16 bytes)
A to H:
MRM (16 bytes)
MRM (16 bytes)
MRM (16 bytes)
MRM (16 bytes)
MRM (16 bytes)
MR (1 byte)
A to G:
MRM (16 bytes)
MRM (16 bytes)
MRM (16 bytes)
MRM (16 bytes)
MR (2 bytes)
Functional Description
Read Example 2 – Burst = 8 Dwords, Cache Line Size = 4 Dwords:
A to B:
MRL (6 bytes)
A to C:
MRL (13 bytes)
A to D:
MRM (17 bytes)
C to D:
MRM (5 bytes)
C to E:
MRM (21 bytes)
D to F:
MRM (32 bytes)
A to H:
MRM (32 bytes)
MRM (32 bytes)
MRM (17 bytes)
A to G:
MRM (32 bytes)
MRM (32 bytes)
MR (2 bytes)
Read Example 3 – Burst = 16 Dwords, Cache Line Size = 8 Dwords:
A to B:
MRL (6 bytes)
A to C:
MRL (13 bytes)
A to D:
MRL (17 bytes)
C to D:
MRL (5 bytes)
C to E:
MRM (21 bytes)
D to F:
MRM (32 bytes)
A to H:
MRM (64 bytes)
MRL (17 bytes)
A to G:
MRM (64 bytes)
MR (2 bytes)
PCI Functional Description
2-15
Write Example 1 – Burst = 4 Dwords, Cache Line Size = 4 Dwords:
2-16
A to B:
MW (6 bytes)
A to C:
MW (13 bytes)
A to D:
MW (17 bytes)
C to D:
MW (5 bytes)
C to E:
MW (3 bytes)
MWI (16 bytes)
MW (2 bytes)
D to F:
MW (15 bytes)
MWI (16 bytes)
MW (1 byte)
A to H:
MW (15 bytes)
MWI (16 bytes)
MWI (16 bytes)
MWI (16 bytes)
MWI (16 bytes)
MW (2 bytes)
A to G:
MW (15 bytes)
MWI (16 bytes)
MWI (16 bytes)
MWI (16 bytes)
MW (3 bytes)
Functional Description
Write Example 2 – Burst = 8 Dwords, Cache Line Size = 4 Dwords:
A to B:
MW (6 bytes)
A to C:
MW (13 bytes)
A to D:
MW (17 bytes)
C to D:
MW (5 bytes)
C to E:
MW (3 bytes)
MWI (16 bytes)
MW (2 bytes)
D to F:
MW (15 bytes)
MWI (16 bytes)
MW (1 byte)
A to H:
MW (15 bytes)
MWI (32 bytes)
MWI (32 bytes)
MW (2 bytes)
A to G:
MW (15 bytes)
MWI (32 bytes)
MWI (16 bytes)
MW (3 bytes)
Write Example 3 – Burst = 16 Dwords, Cache Line Size = 8 Dwords:
A to B:
MW (6 bytes)
A to C:
MW (13 bytes)
A to D:
MW (17 bytes)
C to D:
MW (5 bytes)
C to E:
MW (21 bytes)
D to F:
MW (32 bytes)
A to H:
MW (31 bytes)
MWI (32 bytes)
MW (18 bytes)
A to G:
MW (31 bytes)
MWI (32 bytes)
MW (3 bytes)
PCI Functional Description
2-17
2.1.3.6 Memory-to-Memory Moves
Memory-to-Memory moves also support PCI cache commands, as
described above, with one limitation: Memory Write and Invalidate on
Memory-to-Memory Move writes are only supported if the source and
destination address are quad word aligned. If the source and destination
are not quad word aligned, i.e., Source Address[2:0] == Destination
Address[2:0], write alignment is not performed and Memory Write and
Invalidates are not issued.
The LSI53C1000 is little endian. This mode assigns the least significant
byte to bits [7:0].
2.2 SCSI Functional Description
The Ultra160 SCSI controller on the LSI53C1000 supports either an 8-bit
or 16-bit SCSI bus. The controller supports Wide Ultra160 SCSI
synchronous transfer rates up to 160 Mbytes/s on an LVD SCSI bus. The
LSI53C1000 can be programmed with SCSI SCRIPTS, making it easy to
“fine tune” the system for specific mass storage devices or Ultra160 SCSI
requirements. Figure 2.1 on page 2-2 illustrates the relationship between
the LSI53C1000 modules.
The LSI53C1000 offers low level register access or a high level control
interface. Like first generation SCSI devices, the LSI53C1000 is
accessed as a register-oriented device. The ability to sample and/or
assert any signal on the SCSI bus is used in error recovery and
diagnostic procedures.
The LSI53C1000 is controlled by the integrated SCRIPTS processor
through a high level logical interface. Commands controlling the SCSI
function are fetched out of the main host memory or local memory. These
commands instruct the SCSI function to Select, Reselect, Disconnect,
Wait for a Disconnect, Transfer Information, Change Bus Phases, and
implement all other aspects of the SCSI protocol. The SCRIPTS
processor is a special high-speed processor optimized for SCSI protocol.
2-18
Functional Description
2.2.1 SCRIPTS Processor
The SCSI SCRIPTS processor allows fetches of both DMA and SCSI
commands from host memory or internal SCRIPTS RAM. Algorithms
written in SCSI SCRIPTS control the actions of the SCSI and DMA
cores. The SCRIPTS processor, running off of the PCI clock, executes
complex SCSI bus sequences independently of the host CPU.
Algorithms can be designed to tune SCSI bus performance to adjust to
new bus device types, such as scanners, communication gateways, etc.
They can also incorporate changes in the SCSI logical bus definitions
without sacrificing I/O performance. SCSI SCRIPTS are hardware
independent, so they can be used interchangeably on any host or CPU
system bus. SCSI SCRIPTS handle conditions such as Phase Mismatch.
2.2.1.1 Phase Mismatch Handling in SCRIPTS
The LSI53C1000 can handle phase mismatches due to drive disconnects
without needing to interrupt the processor. The primary goal of this logic
is to completely eliminate the need for CPU intervention during an I/O
disconnect/reselect sequence.
SCRIPTS control the storage of appropriate information needed to
restart the I/O state, eliminating the need for processor intervention
during an I/O disconnect/reselect sequence. Calculations are performed
such that the appropriate information is available to SCRIPTS so that an
I/O state can be properly stored for restart later.
The Phase Mismatch Jump logic is disabled at power-up. To enable the
phase mismatch jump logic, set the Phase Mismatch Jump Enable bit
(ENPMJ, bit 7 in the Chip Control Zero (CCNTL0) register). Utilizing the
information supplied in the Phase Mismatch Jump Address registers
allows all overhead involved in a disconnect/reselect sequence to be
handled with a modest amount of SCRIPTS instructions. These registers
are described in detail in Chapter 4, “Registers.”
2.2.2 Internal SCRIPTS RAM
The LSI53C1000 has 8 Kbytes (2048 x 32 bits) of internal, general
purpose RAM. The RAM is designed for SCRIPTS program storage, but
is not limited to this type of information. When the chip fetches SCRIPTS
instructions or Table Indirect information from the internal RAM, these
SCSI Functional Description
2-19
fetches remain internal to the chip and do not use the PCI bus. In
addition, any SCRIPTS instruction that contains a source or destination
address residing in SCRIPTS RAM memory space remains internal to
the chip and does not generate PCI cycles. SCRIPTS instructions able
to access SCRIPTS RAM memory space in this manner include
Memory-to-Memory Moves, Load/Stores, and Block Moves. While an
internal cycle is occurring, any external PCI slave cycle is retried on the
PCI bus. Setting the DISRC (Disable Internal SCRIPTS RAM Cycles) bit
in the Chip Control Zero (CCNTL0) register disables this feature.
SCRIPTS RAM should be initialized before it is read. Reading SCRIPTS
RAM before initialization sets the SCRIPTS RAM parity bit, bit 7, in the
Shadowed SCSI SGE Status 0 register.
PCI system BIOS can relocate the RAM anywhere in the 64-bit address
space. Base Address Register Three (BAR3) (SCRIPTS RAM) and Base
Address Register Four (BAR4) (SCRIPTS RAM), in the PCI configuration
space, contain the base address of the internal RAM. To simplify
SCRIPTS instruction loading, the base address of the RAM appears in
the Scratch Register B (SCRATCHB) register when bit 3 of the Chip Test
Two (CTEST2) register is set. The upper 32 bits of a 64-bit base address
are in the SCRIPT Fetch Selector (SFS) register. The RAM is
byte-accessible from the PCI bus and is visible to any bus mastering
device on the bus. External, CPU accesses to the RAM follow the same
timing sequence as a standard slave register access, except that the
required target wait states drop from 5 to 3. SCRIPTS RAM must first be
written before being read in order to initialize SCRIPTS RAM parity. If a
SCRIPTS RAM parity error is encountered, a SCSI Gross Error interrupt
will be signaled.
A complete set of development tools is available for writing custom
drivers with SCSI SCRIPTS. For more information on the SCSI SCRIPTS
instructions supported by the LSI53C1000, see Chapter 5, “SCSI
SCRIPTS Instruction Set.”
2.2.3 64-Bit Addressing in SCRIPTS
The PCI interface for the LSI53C1000 provides 64-bit address and data
capability in the initiator mode. The chip can also respond to 64-bit
addressing in the target mode.
2-20
Functional Description
DACs can be generated for all SCRIPTS operations. There are six
selector registers which hold the upper Dword of a 64-bit address. All but
one of these is static and requires manual loading using a CPU access,
a Load and Store instruction, or a memory move instruction. One of the
selector registers is dynamic and is used during 64-bit direct block moves
only. All selectors will default to zero, meaning the LSI53C1000 will
power-up in a state where only Single Address Cycles (SACs) are
generated. When any of the selector registers are written to a nonzero
value, DACs are generated.
Direct, Table Indirect and Indirect Block Moves, Memory-to-Memory
Moves, Load/Stores, and Jumps are all instructions with 64-bit address
capability.
Note:
Crossing the 4 Gbyte boundary on any one SCRIPTS
operation is not permitted. Therefore, software must handle
all such transactions.
2.2.4 Hardware Control of SCSI Activity LED
The LSI53C1000 controls an LED through the GPIO_0 pin to indicate
that it is connected to the SCSI bus. This function was previously
handled by a software driver.
Bit 3 (CON), in the Interrupt Status Zero (ISTAT0) register, is presented
at the GPIO_0 pin when the following occurs:
•
Bit 5 (LED_CNTL) in the General Purpose Pin Control (GPCNTL)
register is set,
•
Bit 6 (Fetch Enable) in the General Purpose Pin Control (GPCNTL)
register is cleared,
•
the LSI53C1000 is not performing an EEPROM autodownload.
The CON (Connected) bit in Interrupt Status Zero (ISTAT0) is set anytime
the LSI53C1000 is connected to the SCSI bus either as an initiator or a
target. This happens after the LSI53C1000 has successfully completed
a selection or when it has successfully responded to a selection or
reselection. The CON bit is also set when the LSI53C1000 wins
arbitration in low level mode.
SCSI Functional Description
2-21
2.2.5 Designing an Ultra160 SCSI System
Software modifications are needed to take advantage of the Ultra160
speed in the LSI53C1000. Since Ultra160 SCSI is based on existing
SCSI standards, it can use existing drivers if they are able to negotiate
for Ultra160 synchronous transfer rates. Also, the target device must be
able to communicate at Ultra160 speed. The LSI53C1000 uses Domain
Validation to determine whether or not the system is capable of Ultra160
SCSI before activating DT clocking. Refer to Section 2.2.5.1, “Ultra160
Features,” for more information on DT clocking.
LVD SCSI fulfills the hardware requirements for Ultra160 SCSI transfer
rates, increased cable lengths, and additional devices on the bus. All
devices on the bus must have LVD SCSI capabilities to guarantee
Ultra160 SCSI transfer rates. For additional information on Ultra160
SCSI, refer to the SCSI Parallel Interface-3 (SPI-3) working document
that is available on the world wide web at the T10 Home Page,
http://www.t10.org. Also, check the SCSI Trade Association web site at
http://www.scsita.org/. Chapter 6, “Specifications,” contains Ultra160
SCSI timing information. In addition to the guidelines in the draft
standard, make the following software adjustments to accommodate
Ultra160 SCSI transfers.
2.2.5.1 Ultra160 Features
Domain Validation – Domain Validation is a procedure in which a host
queries a device to determine its ability to communicate at the negotiated
Ultra160 data rate. In software, the following steps are performed to
ensure the selected device can successfully transfer data at the
negotiated speed.
Step 1. Select a device.
Step 2. Issue Inquiry command.
Step 3. Issue Parallel Protocol Request (PPR) message.
Step 4. Issue Write Buffer command.
Step 5. Issue Read Buffer command.
Step 6. Examine the data pattern to ensure validity.
If the commands complete successfully with no CRC errors, bus hangs,
or data pattern errors, then the negotiated speed is valid.
2-22
Functional Description
CRC – CRC is the error detecting code used in Ultra160 SCSI. Four
bytes are transferred with data to increase the reliability of data transfers.
CRC is used in the DT Data-In and DT Data-Out phases only. Because
CRC is implied with DT mode and only works with DT mode, the DT
setting can be used for CRC.
DT Clocking – Ultra160 SCSI implements DT clocking to provide
speeds up to 80 megatransfers/s. DT clocking means that the data is
sampled on both the asserting and deasserting edge of REQ/ACK.
DT clocking is only valid using a LVD SCSI bus.
In order to support DT clocking, there are two new phases for the SCSI
bus. The old Data-In and Data-Out phases are now called ST Data-In
and ST Data-Out. The new phases are DT Data-In and DT Data-Out.
The use of DT and ST phases implies that the SCRIPTS engine may use
a different jump point for DT or ST. Table 2.3 illustrates SCSI signal
configuration for these phases.
Table 2.3
Phase
New Phases on SCSI Bus
MSG
C/D
I/O
Description
ST Data-Out
0
0
0
–
ST Data-In
0
0
1
–
DT Data-Out
1
0
0
Previously reserved
DT Data-In
1
0
1
Previously reserved
To indicate DT or ST mode, a bit is set in the current “selection” data
reserved byte. BMOVE instructions identify the current BMOVE as either
DT or ST through the phase bits.
SCSI Functional Description
2-23
2.2.5.2 Parallel Protocol Request
CRC, Sync/Wide, DT, Quick Arbitration and Selection (QAS), and
“information units” are negotiated with a new SCSI extended message:
Byte 0
0x01
Extended message
Byte 1
0x06
Length
Byte 2
0x04
Parallel Protocol Request (PPR)
Byte 3
0xXX
Transfer Period Factor
Byte 4
0x00
Reserved
Byte 5
0xXX
Req/Ack Offset
Byte 6
0xXX
Transfer Width Exponent
Byte 7
0x0X
Protocol options
Transfer Period Factor (Byte 3) – Transfer Period Factor is the old
Synchronous Period value. These are the same with one addition for the
80 megatransfers/s rate:
0x09
=
12.5 ns (Ultra160 SCSI) only valid when using DT
0x0A
=
25 ns (Ultra2 SCSI)
0x0B
=
30.3 ns
0x0C
=
50 ns (Ultra SCSI)
0x0D–0xFF
=
value × 4 = Period (in ns)
The transfer period depends on the data transfer speed, NOT the clock
period. So, in DT mode, 0x09 means 12.5 ns between clock edges which
really means a 25 ns clock period. In DT mode, 0x0A would mean a
clock period of 50 ns but a data rate of 40 megatransfers/s (25 ns). In
ST mode, 0x0A would mean a clock period of 25 ns and a data rate of
40 megatransfers/s.
Req/Ack Offset (Byte 5) – Req/Ack Offset is the maximum SCSI offset.
Transfer Width Exponent (Byte 6) – Transfer Width Exponent is the
old width value. It is set to 0 (8-bit SCSI width) or 1 (16-bit SCSI width).
2-24
Functional Description
Note:
For DT mode or when the Protocol Options field is nonzero,
the Transfer Width Exponent must be one indicating a SCSI
width of 16 bits.
Note:
The Table Indirect data (used during selection/reselection)
must be updated to enable certain control bits in the
SCNTL4 register. Specific bits to look at include: bit 7,
U3EN (Ultra160 Transfer Enable); bit 6, AIPEN
(Asynchronous Information Protection Enable); and
bits [3:0] (Extra Clock Setup/Hold).
Protocol Options (Byte 7) – A bus or device reset, power cycle, or
change between LVD/SE modes invalidates these settings. A
renegotiation resets the Protocol Options.
QAS_REQ
DT_REQ
IU_REQ
Description
0
0
0
Use ST Data-In and ST Data-Out phase
to transfer data
0
1
0
Use DT Data-In and DT Data-Out phase
to transfer data with CRC
0
1
1
Use DT Data-In and DT Data-Out phase
to transfer data with information units
1
1
0
Use DT Data-In and DT Data-Out phase
to transfer data with CRC and use the
QAS method for arbitration
1
1
1
Use DT Data-In and DT Data-Out phase
to transfer data with information units and
use the QAS method for arbitration
2.2.5.3 Asynchronous Information Protection (AIP)
The AIP feature provides error checking for asynchronous, nondata
phases through BCH encoding. During the command, status, message
in/out phases, the BCH code is transferred on the upper SCSI data bus.
For details on the BCH code, see T10 119 document "Protection for the
Asynchronous Phases".
SCSI Functional Description
2-25
The AIP error status and the live AIP code values are captured in the
AIP Control Zero (AIPCNTL0) register for debug purposes. AIP checking
is enabled by setting bit 6 in the SCSI Control Four (SCNTL4) register.
AIP generation occurs by default and may be disabled by setting bit 3,
Disable AIP Code Generation, in AIP Control One (AIPCNTL1).
The sequence ID is reset on any phase change, chip reset, bus free, or
synchronous phase. It is also reset by writing the RSQAIP bit in the AIP
Control One (AIPCNTL1) register. The AIP sequence value can be read
using this register (SEQAIP).
All AIP errors are treated in the same fashion as parity errors. Bit 0 of
the SCSI Interrupt Status Zero (SIST0) register indicates if SCSI parity,
CRC, or AIP errors are present. The AIPERR bit in the AIP Control Zero
(AIPCNTL0) register indicates if the error is an AIP error.
2.2.5.4 Register Considerations
The following is a summary of the registers and bits required to enable
Ultra160 SCSI on the LSI53C1000.
•
The PCI Device ID register value must be 0x21.
•
The PCI Max_Lat (ML) register contains a value of 0x12, indicating
it requires the bus every 4.5 µs.
•
The SCSI Control Zero (SCNTL0) register:
•
–
Bit 3, EPC (Enable Parity/CRC/AIP Checking) is set to enable
the CRC feature.
–
Bit 1, AAP (Assert SATN/ on Parity/CRC/AIP Error), is set in the
initiator mode to automatically assert SATN/ on the detection of
an error.
The SCSI Control One (SCNTL1) register:
–
•
The SCSI Control Three (SCNTL3) register:
–
2-26
Bit 5, DHP (Disable Halt on Parity/CRC/AIP Error or ATN) (Target
Only), is set in accordance with user requirements. When bit 5
is cleared, a SCSI transfer halts if an error occurs. When bit 5 is
set, a SCSI transfer continues if an error occurs.
Bit 7 is now reserved. It was previously the Ultra Enable bit.
Functional Description
•
•
–
Bits [6:4], SCF[2:0] (Synchronous Clock Conversion Factor),
select the divisor of the SCLK frequency. The SCLK is divided
before its presentation to the synchronous SCSI control logic.
–
Bit 3, EWS (Enable Wide SCSI), is set to enable wide SCSI.
Ultra160 requires wide SCSI. Therefore, this bit must be set
during these transfers.
–
Bits [2:0] are reserved.
The SCSI Transfer (SXFER) register:
–
Bits [7:6] are reserved.
–
Bits [5:0], MO[5:0] (Max SCSI synchronous offset), are set for
the maximum offset.
The SCSI Status Two (SSTAT2) register:
–
•
The SCSI Interrupt Enable Zero (SIEN0) register:
–
•
•
Bit 2 is reserved. HVD SCSI is not supported.
Bit 0, PAR (SCSI Parity/CRC/AIP Error), is set to detect a
parity/CRC/AIP error while receiving or sending SCSI data. For
more information, see SCSI Control One (SCNTL1), bit 5.
The Chip Control Three (CCNTL3) register:
–
Bit 4, ENDSKEW (Enable REQ/ACK to Data skew control) is set
to enable control of the relative skew between the SCSI
REQ/ACK signal and the data signals.
–
Bits [3:2], DSKEW[1:0] (REQ/ACK - Data skew control), control
the amount of skew between the SCSI REQ/ACK signal and the
SCSI data signals. These bits are used for Ultra160 SCSI
Domain Validation only and control the skew only if bit 4 is set.
–
Bits [1:0], LVDDL[1:0] (LVD Drive strength select), control the
drive level of the LVD pad drivers. This feature is intended for use
in Ultra160 SCSI Domain Validation testing environments only.
Set these bits to 0b00 during normal operation.
The SCSI Control Four (SCNTL4) register:
–
Bit 7, U3EN (Ultra160 Transfer Enable) is set to enable Ultra160
transfers.
SCSI Functional Description
2-27
–
Bit 6, AIPCKEN (AIP Checking Enable), is set to enable checking
of the upper byte lane of protection information during
Command, Status, and Message Phases.
–
Bits [5:4] are reserved.
–
Bit 3, XCLKH_DT (Extra Clock of Data Hold on DT Transfer
Edge) is set to add a clock of data hold to synchronous DT SCSI
transfers on the DT edge.
–
Bit 2, XCLKH_ST (Extra Clock of Data Hold on ST Transfer
Edge) is set to add a clock of data hold to synchronous DT or
ST SCSI transfers on the ST edge. This bit impacts both ST and
DT transfers as it affects data hold to the ST edge.
–
Bit 1, XCLKS_DT (Extra Clock of Data Setup on DT Transfer
Edge) is set to add a clock of data setup to synchronous DT
SCSI transfers on the DT edge. This bit only impacts DT
transfers as it affects data setup to the DT edge.
–
Bit 0, XCLKS_ST (Extra Clock of Data Setup on ST Transfer
Edge) is set to add a clock of data setup to synchronous DT or
ST SCSI transfers on the ST edge. This bit impacts both ST and
DT transfers as it affects data setup to the ST edge.
Note:
•
•
2-28
The XCLKH_DT, XCLKH_ST, XCLKS_DT, and XCLKS_ST
bits do not affect CRC timings.
The AIP Control Zero (AIPCNTL0) register:
–
Bits [7:3] are reserved.
–
Bit 2, AIPERR_LIVE (AIP Error Status Live), represents the live
error status for the AIP checking logic. This is not a latched
value. Use this value for diagnostic purposes only.
–
Bit 1, AIPERR (AIP Error Status), represents the error status for
the AIP checking logic. Use this bit only when AIP checking is
enabled.
–
Bit 0, PARITYERR (Parity Error), represents the error status for
the parity error.
The AIP Control One (AIPCNTL1) register:
–
Bits [7:4] are reserved.
–
Bit 3, DISAIP (Disable AIP Code Generation), disables the AIP
code generation on the SCSI bus.
Functional Description
•
–
Bit 2, RAIPERR (Reset AIP Error), allows an AIP error condition
to be reset manually.
–
Bit 1, FBAIP (Force Bad AIP Value), causes bad AIP values to
be sent over the SCSI bus.
–
Bit 0, RSQ (Reset AIP Sequence Value), causes the sequence
value used in the calculation of the protection code to be reset.
The CRC Pad Byte Value (CRCPAD) register:
–
•
•
Bits [15:0], the CRC Pad byte value, contain the value placed
onto the bus for the CRC pad bytes.
The CRC Control Zero (CRCCNTL0) register:
–
Bit 7, DCRCC (Disable CRC Checking), is set to cause the
internal logic to not check or report CRC errors during Ultra160
transfers. The device continues to calculate and send CRCs as
requested by the target per SPI-3 specification.
–
Bit 6, DCRCPC (Disable CRC Protocol Checking) causes the
LSI53C1000 to not check for a CRC request prior to a phase
change on the SCSI bus. This condition creates a SCSI error
condition and makes the device noncompliant with the SPI-3
specification. Do not set these bits under normal operating
conditions.
–
Bit 5, RSTCRCINT (Reset CRC Interval Counter) resets the
internal CRC interval counter to zero.
–
Bit 4 is reserved.
–
Bits [3:0], CRCINT[3:0] (CRC Request Interval (Target Mode
only)), determine when a CRC request is sent by the device
when operating in target mode and transferring data in the DT
Data-In or DT-Data Out phases.
The CRC Control One (CRCCNTL1) register:
–
Bit 7, CRCERR (CRC Error), indicates whether or not a CRC
error has been detected during a DT Data In SCSI transfer. This
bit is independent of the DCRCC bit setting. To clear this
condition, either write this bit to a one or read the SIST0 and
SIST1 registers. When CRC checking and the Parity/CRC/AIP
Error interrupt are both enabled, CRCERR is mirrored in the
SIST0 register, bit 0, as a Parity/CRC/AIP error.
–
Bit 6 is reserved.
SCSI Functional Description
2-29
•
–
Bit 5, ENAS (Enable CRC Auto Seed), is set to cause the CRC
logic to automatically reseed itself after every CRC check
performed during DT Data In SCSI transfers. When this bit is
cleared, the SCSI control logic controls when the CRC logic is
reseeded.
–
Bit 4, TSTSD (Test CRC Seed), is set to cause the CRC logic to
immediately reseed itself. Do not set this bit during normal
operation as it may cause corrupt CRCs to be generated.
–
Bit 3, TSTCHK (Test CRC Check), is set to cause the CRC logic
to initiate a CRC check. Do not set this bit during normal
operation as it creates spurious CRC errors.
–
Bit 2, TSTADD (Test CRC Accumulate), is set to cause the CRC
block to include the value present in the input register in the
current CRC calculation. A new output CRC value results. Do not
set this bit during normal operation as corrupt CRC values result.
–
Bits [1:0], CRCDSEL[1:0] (CRC Data Register Selector), control
the data visible in the CRC Data register.
The CRC Data (CRCD) register:
–
Bits [31:0] CRCDATA (CRC Data). The value in this register is
dependent upon the setting of the CRCDSEL bits.
2.2.5.5 Using the SCSI Clock Quadrupler
The LSI53C1000 can quadruple the frequency of a 40 MHz SCSI clock,
allowing the system to perform Ultra160 SCSI transfers. This option is
user-selectable with bit settings in the SCSI Test One (STEST1), SCSI
Test Three (STEST3), and SCSI Control Three (SCNTL3) registers. At
power-on or reset, the quadrupler is disabled and powered down. Follow
these steps to use the clock quadrupler:
1. Set the SCLK Quadrupler Enable bit (SCSI Test One (STEST1)
register, bit 3).
2. Do not poll bit 5 of the SCSI Test Four (STEST4) register. Bit 5 is
reserved. Use a delay of 50 µs after the quadrupler enable bit is set
in step 1.
3. Halt the SCSI clock by setting the Halt SCSI Clock bit (SCSI Test
Three (STEST3) register, bit 5).
2-30
Functional Description
4. Set the clock conversion factor using the SCF (Synchronous clock
Conversion Factor) field in the SCSI Control Three (SCNTL3)
register.
5. Set the SCLK Quadrupler Select bit (SCSI Test One (STEST1),
bit 2).
6. Clear the Halt SCSI Clock bit.
2.2.6 Prefetching SCRIPTS Instructions
The prefetch logic in the LSI53C1000 fetches 8 Dwords of instructions
when enabled by setting the Prefetch Enable bit (bit 5) in the DMA
Control (DCNTL) register. The maximum burst size that can be
performed is automatically determined using the burst length values in
the DMA Mode (DMODE) register. If the unit cannot perform bursts of at
least 4 Dwords, it disables itself. While the chip is prefetching SCRIPTS
instructions, it uses the PCI cache commands Memory Read Line and
Memory Read Multiple, if PCI caching is enabled.
Note:
This feature is only useful when fetching SCRIPTS
instructions from main memory. Due to the short access
time of SCRIPTS RAM, prefetching is not necessary when
fetching instructions from SCRIPTS RAM.
To ensure the LSI53C1000 always operates from the current version of
the SCRIPTS instruction, the contents of the prefetch unit may be
flushed under certain conditions. The contents of the prefetch unit are
automatically flushed under the following conditions:
•
On every Memory Move instruction
The Memory Move instruction is used to place modified code into
memory. To assure the device executes recent modifications, the
prefetch unit flushes its contents and reloads the code each time an
instruction is issued. To avoid inadvertently flushing the prefetch unit
contents, use the No Flush option for all Memory Move operations
that do not modify code within the next 8 Dwords. For more
information refer to Chapter 5, “SCSI SCRIPTS Instruction Set.”
SCSI Functional Description
2-31
•
On every Store instruction
The Store instruction may also be used to place modified code
directly into memory. To avoid inadvertently flushing the prefetch unit
contents, use the No Flush option for all Store operations that do not
modify code within the next 8 Dwords.
•
On every write to the DMA SCRIPTS Pointer (DSP) register.
•
On all Transfer Control instructions, when the transfer conditions are
met.
This is necessary since the next instruction to be executed is not the
sequential next instruction in the prefetch unit.
•
When the Prefetch Flush bit (DMA Control (DCNTL) register, bit 6)
is set.
The unit flushes whenever this bit is set. This bit is self-clearing.
2.2.7 Opcode Fetch Burst Capability
Setting the Burst Opcode Fetch Enable bit (bit 1) in the DMA Mode
(DMODE) register (0x38) causes the LSI53C1000 to burst in the first two
Dwords of all instruction fetches. If the instruction is a Memory-toMemory Move, the third Dword is accessed in a separate ownership. If
the instruction is an indirect type, the additional Dword is accessed in a
subsequent bus ownership. If the instruction is a Table Indirect Block
Move, the device uses two accesses, each a two Dword burst, to obtain
the four Dwords required.
Note:
This feature is only useful if Prefetching is disabled.
This feature is only useful if fetching SCRIPTS instructions
from main memory. Due to the short access time of
SCRIPTS RAM, burst opcode fetching is not necessary
when fetching instructions from SCRIPTS RAM.
2.2.8 Load and Store Instructions
The LSI53C1000 supports the Load and Store instruction type, which
simplifies data movement between memory and the internal registers. It
also enables the chip to transfer bytes to addresses relative to the Data
Structure Address (DSA) register. Load/Store data transfers to or from
the SCRIPTS RAM remain internal to the chip and do not generate PCI
bus cycles. While a Load/Store to or from SCRIPTS RAM is occurring,
2-32
Functional Description
any external PCI slave cycles that occur are retried on the PCI bus.
Setting the DISRC (Disable Internal SCRIPTS RAM Cycles) bit in the
Chip Control Zero (CCNTL0) register disables this feature. For more
information on the Load and Store instructions, refer to Chapter 5, “SCSI
SCRIPTS Instruction Set.”
2.2.9 JTAG Boundary Scan Testing
With one exception, the LSI53C1000 includes support for JTAG
boundary scan testing in accordance with the IEEE 1149.1 specification.
The exception concerns the TST_RSTN pin. This pin must not be
toggled as it will reset the JTAG TAP controller. For more information,
refer to the BSDL (Boundary Scan Descriptor Language) file.
This device accepts all required boundary scan instructions including the
optional CLAMP, HIGH-Z, and IDCODE instructions. The optional JTAG
pin TRST is not implemented. Reset of the JTAG logic through the TAP
controller occurs when TMS is held high for at least 5 TCK clock cycles.
The LSI53C1000 uses an 8-bit instruction register to support all
boundary scan instructions. The data registers included in the device are
the Boundary Data register, the IDCODE register, and the Bypass
register. This device can handle a 20 MHz TCK frequency with all TAP
pins having a 50% duty cycle.
2.2.10 Parity/CRC/AIP Options
The LSI53C1000 implements a flexible parity scheme that permits
control of the parity sense, allows parity checking to be turned on or off,
and can deliberately send a byte with bad parity over the SCSI bus.
Table 2.4 defines the bits that are involved in parity control and
observation. Table 2.5 describes the parity control function of the Enable
Parity Checking and Assert SCSI Even Parity bits in the SCSI Control
One (SCNTL1) register, bit 2, and the options available when a parity
error occurs.
SCRIPTS RAM must first be written before being read in order to
initialize SCRIPTS RAM parity. If a SCRIPTS RAM parity error is
encountered, a SCSI Gross Error interrupt is signaled.
The LSI53C1000 supports CRC checking and generation in DT phases
and CRC checking and generation during DT Data Transfers.
SCSI Functional Description
2-33
The new CRC registers are: CRC Pad Byte Value (CRCPAD); CRC
Control Zero (CRCCNTL0); CRC Control One (CRCCNTL1); CRC Data
(CRCD); SCSI Control Zero (SCNTL0), bit 3, EPC and bit 1, AAP; Chip
Control One (CCNTL1), bit 5, DHP; and, SCSI Interrupt Enable Zero
(SIEN0), bit 0, (SCSI Parity/CRC/AIP Error).
The new AIP registers are: SCSI Control Zero (SCNTL0), AIP Control
Zero (AIPCNTL0), and AIP Control One (AIPCNTL1).
Table 2.4
Bits Used for Parity/CRC/AIP Control and Generation
Bit Name
Location
Description
AAP (Assert SATN/ on SCSI Control Zero
Parity/CRC/AIP Errors) (SCNTL0), Bit 1
When this bit is set, the LSI53C1000 automatically
asserts the SATN/ signal upon detection of a parity,
CRC, or AIP error. SATN/ is only asserted in initiator
mode.
EPC (Enable
Parity/CRC/AIP
Checking)
SCSI Control Zero
(SCNTL0), Bit 3
When set, this bit enables parity checking on the
LSI53C1000. The LSI53C1000 checks for odd parity.
Assert Even SCSI
Parity
SCSI Control One
(SCNTL1), Bit 2
When set, this bit forces even SCSI parity on each byte
sent to the SCSI bus from the LSI53C1000.
Disable Halt on SATN/ SCSI Control One
or Parity/CRC/AIP Error (SCNTL1), Bit 5
(Target Mode Only)
This bit determines if the LSI53C1000 halts operations
when a parity error is detected in target mode.
Enable Parity/CRC/AIP SCSI Interrupt
Error Interrupt
Enable Zero
(SIEN0), Bit 0
This bit determines whether the LSI53C1000 generates
an interrupt when it detects a SCSI parity/CRC/AIP
error.
Parity Error
SCSI Interrupt
This status bit is set whenever the LSI53C1000 detects
Status Zero (SIST0), a parity/CRC/AIP error on the SCSI bus.
Bit 0
Status of SCSI Parity
Signal
SCSI Status Zero
(SSTAT0), Bit 0
This status bit represents the active HIGH current state
of the SCSI SDP0 parity signal.
SCSI SDP1 Signal
SCSI Status Two
(SSTAT2), Bit 0
This bit represents the active HIGH current state of the
SCSI SDP1 parity signal.
Latched SCSI Parity
SCSI Status Two
(SSTAT2), Bit 3
SCSI Status One
(SSTAT1), Bit 3
These bits reflect the SCSI odd parity signal
corresponding to the data latched into the SCSI Input
Data Latch (SIDL) register.
Master Parity Error
Enable
Chip Test Four
(CTEST4), Bit 3
This bit enables parity checking during PCI master data
phases.
Master Data Parity
Error
DMA Status
(DSTAT), Bit 6
This bit is set when the LSI53C1000, as a PCI master,
detects a target device signaling a parity error during a
data phase.
2-34
Functional Description
Table 2.4
Bits Used for Parity/CRC/AIP Control and Generation (Cont.)
Bit Name
Location
Description
Master Data Parity
Error Interrupt Enable
DMA Interrupt
By clearing this bit, a Master Data Parity Error does not
Enable (DIEN), Bit 6 cause assertion of INTA/, but the status bit is set in the
DMA Status (DSTAT) register.
AIP Checking Enable
SCSI Control Four
(SCNTL4), Bit 6
Setting this bit enables the AIP checking of the upper
byte lane of protection information during command,
status, and message phases.
CRC Request OK
SCSI Control Zero
(SCNTL0), Bit 2
This bit indicates that it is acceptable to force a CRC
request. This bit is set only if a CRC request has been
sent and no data has been transferred since that
request. This bit can be used to determine if it is
necessary to send a CRC request at the end of a data
transfer prior to changing phases in target mode. Use
this bit to prevent back to back CRC conditions.
Disable CRC Checking CRC Control Zero
(CRCCNTL0), Bit 7
This bit is set to cause internal logic not to check or
report CRC errors during Ultra160 transfers.
Disable CRC Protocol
Checking
This bit is set to cause the device not to check for a
CRC request prior to a phase change on the SCSI bus.
This condition normally causes a SCSI error condition.
Note: Setting this bit makes the LSI53C1000
noncompliant to the SPI-3 specification. Do not set this
bit under normal operating conditions.
Table 2.5
CRC Control Zero
(CRCCNTL0), Bit 6
SCSI Parity Errors and Interrupts
DHP1
PAR2
Description
0
0
Halts when a parity error occurs in the target or initiator mode and
does NOT generate an interrupt.
0
1
Halts when a parity error occurs in the target mode and generates
an interrupt in the target or initiator mode.
1
0
Does not halt in target mode when a parity error occurs until the
end of the transfer. An interrupt is not generated.
1
1
Does not halt in target mode when a parity error occurs until the
end of the transfer. An interrupt is generated.
1. DHP = Disable Halt on SATN/ or Parity Error (bit 5 SCSI Control One (SCNTL1)).
2. PAR = Parity Error (bit 0 SCSI Interrupt Enable One (SIEN1)).
SCSI Functional Description
2-35
2.2.11 DMA FIFO
The DMA FIFO is 8 bytes wide by 112–115 transfers deep depending on
the type and direction of data transfer. The DMA FIFO is illustrated in
Figure 2.2. The small FIFO mode (112 bytes) is not supported by the
LSI53C1000.
Figure 2.2
DMA FIFO Sections
8 Bytes Wide
.
.
.
.
.
.
112–115
Transfers
Deep
Byte Lane 7 Byte Lane 6 Byte Lane 5 Byte Lane 4 Byte Lane 3 Byte Lane 2 Byte Lane 1 Byte Lane 0
The LSI53C1000 supports 64-bit memory and automatically supports
misaligned DMA transfers. The FIFO allows the LSI53C1000 to support
4, 8, 16, 32, 64, or 128 Dword bursts across the PCI bus interface.
2-36
Functional Description
2.2.12 SCSI Data Paths
The data path through the LSI53C1000 is dependent on whether data is
moved into or out of the chip and whether the SCSI data transfer is
asynchronous or synchronous. Figure 2.3 illustrates how data is moved
to and from the SCSI bus in each of the different modes. The following
sections determine if any bytes remain in the data path when the device
halts an operation.
Figure 2.3
LSI53C1000 Host Interface SCSI Data Paths
Asynchronous
SCSI Send
Asynchronous
SCSI Receive
Synchronous
SCSI Send
Synchronous
SCSI Receive
PCI Interface
PCI Interface
PCI Interface
PCI Interface
DMA FIFO
DMA FIFO
DMA FIFO
DMA FIFO
SWIDE Register
SWIDE Register
SODL Register
SIDL Register
Chain Byte
Holding Register
SCSI Interface
SCSI Interface
SCSI Interface
SCSI FIFO
SCSI Interface
2.2.12.1 Asynchronous SCSI Send
To determine the number of bytes remaining in the DMA FIFO when a
phase mismatch occurs, read the DMA FIFO Byte Count (DFBC)
register. This 16-bit read only register contains the actual number of
bytes remaining in the DMA FIFO. In addition, the SCSI Output Data
Latch (SODL) register must be checked to determine if it contains any
remaining bytes. If bit 5 (OLF) in the SCSI Status Zero (SSTAT0) register
is set, then the least significant byte in the SODL register contains data.
If bit 5 (OLF1) in the SCSI Status Two (SSTAT2) register is set, then the
most significant byte in the SODL register contains data. Checking these
bits also reveals bytes left in the SODL register from a Chained Move
SCSI Functional Description
2-37
operation with an odd byte count. To recover from all other error
conditions, clear the DMA FIFO by setting bit 2 (CLF) in Chip Test Three
(CTEST3) and retry the I/O.
If the Wide SCSI Send (WSS) bit in the SCSI Control Two (SCNTL2)
register is set when a phase mismatch occurs, then adjustments must be
made to the previous block move, not the current block move loaded into
DCMD/DBC. To recover the byte of chain data in the SODL register, set
the previous block move byte count to 1 and set the address to the last
data address for that block move.
2.2.12.2 Synchronous SCSI Send
The DMA FIFO is the only location where data can reside when a phase
mismatch occurs during a synchronous SCSI send transfer. To determine
the number of bytes remaining in the DMA FIFO, read the DMA FIFO
Byte Count (DFBC) register. This 16-bit, read only register contains the
actual number of bytes remaining in the DMA FIFO. To recover from all
other error conditions, clear the DMA FIFO by setting bit 2 (CLF) in Chip
Test Three (CTEST3) and retry the I/O.
If the Wide SCSI Send (WSS) bit in the SCSI Control Two (SCNTL2)
register is set when a phase mismatch occurs, then adjustments must be
made to the previous block move, not the current block move loaded into
DCMD/DBC. To recover the byte of chain data in the outbound chain byte
holding register, set the previous block move byte count to 1 and set the
address to the last data address for that block move.
2.2.12.3 Asynchronous SCSI Receive
When a phase mismatch occurs during an asynchronous SCSI receive,
the only data that may remain in the device is a potential wide residue
byte in the SCSI Wide Residue (SWIDE) register. If bit 0 (WSR) in SCSI
Control Two (SCNTL2) is set, then the SWIDE register contains a
residual byte. This byte can be flushed by executing a block move
instruction with a byte count of one. To recover from all other error
conditions, clear the DMA FIFO by setting bit 2 (CLF) in Chip Test Three
(CTEST3) and retry the I/O.
2-38
Functional Description
2.2.12.4 Synchronous SCSI Receive
When a phase mismatch occurs during a synchronous SCSI receive
transfer no data recover operation is necessary. All data, including chain
bytes from Chained Block Moves, are flushed from the device prior to the
phase mismatch occurring. To recover from all other error conditions,
clear the DMA FIFO by setting bit 2 (CLF) in Chip Test Three (CTEST3),
clear the SCSI FIFO by setting bit 1 (CSF) in SCSI Test Three (STEST3),
and retry the I/O.
2.2.13 SCSI Bus Interface
The LSI53C1000 performs SE and LVD transfers.
2.2.13.1 SCSI Bus Modes
To increase device connectivity and SCSI cable length, the LSI53C1000
features LVDlink technology, the LSI Logic implementation of LVD SCSI.
LVDlink transceivers provide the inherent reliability of differential SCSI
and a long-term migration path for faster SCSI transfer rates.
HVD is not supported by this device. Bit 2 of the SCSI Status Two
(SSTAT2) register and bit 5 of the SCSI Status Two (SSTAT2) register are
now reserved. The A_DIFFSENS or B_DIFFSENS signals still detect the
different input voltages for HVD, LVD, and SE, but the HVD feature is not
present.
2.2.13.2 SCSI Termination
The terminator networks pull signals to an inactive voltage level and
match the impedance seen at the end of the cable with the characteristic
impedance of the cable. Terminators must be installed at the extreme
ends of the SCSI chain, and only at the ends; no system should ever
have more or less than two terminators. SCSI host adapters should
provide a means of accommodating terminators. There should be a
means of disabling the termination.
SE cables can use a 220 Ω pull-up resistor to the terminator power
supply (Term-Power) line and a 330 Ω pull-down resistor to ground.
Because of the high-performance nature of the LSI53C1000, regulated
SCSI Functional Description
2-39
(or active) termination is recommended. Figure 2.4 shows an active
terminator. TolerANT technology active negation can be used with either
termination network.
For information on terminators that support LVD, refer to the SPI-3 draft
standard.
Note:
Figure 2.4
If the LSI53C1000 is used in a design with an 8-bit SCSI
bus, all 16 data lines must be terminated.
Regulated Termination for Ultra160 SCSI
SD0+
SD0−
SD1+
SD1−
SD2+
SD2−
SD3+
SD3−
SD4+
SD4−
4
5
6
7
11
12
13
14
15
16
Line1+
Line1−
Line2+
Line2−
Line3+
Line3−
Line4+
Line4−
Line5+
Line5−
Line9−
Line9+
Line8−
Line8+
Line7−
Line7+
Line6−
Line6+
32
31
30
29
25
24
23
22
SE 33
LVD 34
HVD 35
SDP0−
SDP0+
SD7−
SD7+
SD6−
SD6+
SD5−
SD5+
To LED
Drivers
DIFFSENS 20
17 DISCONNECT
51 K
DIFF B 21
4.7 µF
DIFFSENS connects to the SCSI bus DIFFSENS line to detect what type of devices (SE,
LVD, or HVD) are connected to the SCSI bus.
DISCONNECT shuts down the terminator when it is not at the end of the bus. The
disconnect pin low enables the terminator.
2.2.14 Select/Reselect During Selection/Reselection
In multithreaded SCSI I/O environments, it is not uncommon to be
selected or reselected while trying to perform selection/reselection. This
situation may occur when a SCSI controller (operating in the initiator
mode) tries to select a target and is reselected by another. The Select
2-40
Functional Description
SCRIPTS instruction has an alternate address to which the SCRIPTS will
jump when this situation occurs. The analogous situation for target
devices is being selected while trying to perform a reselection.
Once a change in operating mode occurs, either the initiator SCRIPTS
issues a Set Initiator instruction or the target SCRIPTS issues a Set
Target instruction. The Selection and Reselection Enable bits (SCSI Chip
ID (SCID) bits 5 and 6, respectively) should both be asserted, enabling
the LSI53C1000 to respond as an initiator or as a target. If only selection
is enabled, the LSI53C1000 cannot be reselected as an initiator. Status
bits, in the SCSI Interrupt Status Zero (SIST0) register, and interrupt bits,
in the SCSI Interrupt Enable Zero (SIEN0) register, indicate if the
LSI53C1000 has been selected or reselected.
2.2.15 Synchronous Operation
The LSI53C1000 can transfer synchronous SCSI data in both the initiator
and target modes. The LSI53C1000’s SCLK input must be connected to
a 40 MHz oscillator. The SCSI Transfer (SXFER) register controls the
synchronous offset while the SCSI Control Three (SCNTL3) register
controls the synchronous clock converters. These registers may be
loaded by the CPU before SCRIPTS execution begins, from within
SCRIPTS, with a Table Indirect I/O instruction, or with a Read-ModifyWrite instruction.
The LSI53C1000 can receive data from the SCSI bus at a synchronous
transfer period as short as 12.5 ns, regardless of the transfer period used
to send data. The LSI53C1000 can receive data at one-fourth of the
divided SCLK frequency. Depending on the SCLK frequency, the
negotiated transfer period, and the synchronous clock divider, the
LSI53C1000 can send synchronous data at intervals as short as
12.5 ns for Ultra160 SCSI, 25 ns for Ultra2 SCSI, 50 ns for Ultra SCSI,
100 ns for Fast SCSI, and 200 ns for SCSI-1.
Synchronous data transfer rates are controlled by bits in two different
registers of the LSI53C1000. Following is a brief description of these bits
and the method used to determine the data transfer rate.
SCSI Functional Description
2-41
2.2.15.1 SCSI Control Three (SCNTL3) Register, Bits [6:4] (SCF[2:0]) Description
The SCF[2:0] bits select the factor by which the frequency of SCLK is
divided before its presentation to the synchronous SCSI control logic.
The synchronous transfer speed is determined by the combination of the
divided clock and the setting of the XCLKS_ST, XCLKS_DT, XCLKH_ST,
and XCLKH_DT bits in the SCSI Control Four (SCNTL4) register.
Table 2.6 provides the clock dividers available. Refer to Table 4.4, "DT
Transfer Rates," and Table 4.5, "Single Transition Transfer Rates,"
located in the SCSI Control Four (SCNTL4) register description, for a full
list of available synchronous transfer rates.
Table 2.6
SCF Divisor Values
SCF2
SCF1
SCF0
SCLK Divisor
0
0
0
SCLK/3
0
0
1
SCLK/1
0
1
0
SCLK/1.5
0
1
1
SCLK/2
1
0
0
SCLK/3
1
0
1
SCLK/4
1
1
0
SCLK/6
1
1
1
SCLK/8
2.2.15.2 SCSI Control Four (SCNTL4) Register, Bits [3:0] Description
The following extra clock bits add an extra clock of setup or hold to a ST
or DT transaction.
Bit 3, XCLKH_DT (Extra Clock of Data Hold on DT transfer edge), adds
a clock of data hold to synchronous DT SCSI transfers on the DT edge.
This bit only impacts DT transfers as it only affects data hold to the DT
edge. Setting this bit reduces the synchronous transfer send rate but
does not reduce the rate at which the LSI53C1000 receives outbound
REQs, ACKs, or data.
2-42
Functional Description
Bit 2, XCLKH_ST (Extra Clock of Data Hold on ST transfer edge), adds
a clock of data hold to synchronous DT or ST SCSI transfers on the ST
edge. This bit impacts DT and ST transfers as it affects data hold to the
ST edge. Setting this bit reduces the synchronous transfer send rate but
does not reduce the rate at which the LSI53C1000 receives outbound
REQs, ACKs, or data.
Bit 1, XCLKS_DT (Extra Clock of Data Setup on DT transfer edge), adds
a clock of data setup to synchronous DT SCSI transfers on the DT edge.
This bit only impacts DT transfers as it only affects data hold to the DT
edge. Setting this bit reduces the synchronous transfer send rate but
does not reduce the rate at which the LSI53C1000 receives outbound
REQs, ACKs, or data.
Bit 0, XCLKS_ST (Extra Clock of Data Setup on ST transfer edge), adds
a clock of data setup to synchronous DT or ST SCSI transfers on the ST
edge. This bit impacts DT and ST transfers as it affects data hold to the
ST edge. Setting this bit reduces the synchronous transfer send rate but
does not reduce the rate at which the LSI53C1000 receives outbound
REQs, ACKs, or data.
2.2.15.3 Determining the Data Transfer Rate
The synchronous receive rate can be calculated using the following
formula:
Input Clock Rate
Receive Rate (DT) = ---------------------------------------------- (Megatransfers/s)
( SCF Divisor × 2 )
Input Clock Rate
Receive Rate (ST) = ---------------------------------------------- (Megatransfers/s)
( SCF Divisor × 4 )
Note :
The receive rate is independent of the settings of the
XCLKS_DT, XCLKS_ST, XCLKH_DT, XCLKH_ST bits.
The synchronous send rate, in units of megatransfers/s, can be
calculated using the following formula:
Input Clock Rate
Send Rate (DT) = -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------XCLKS_DT+XCLKS_ST+XCLKH_DT+XCLKH_ST
SCF Divisor ×  2 + --------------------------------------------------------------------------------------------------------------------------------------


2
Input Clock Rate
Send Rate (ST) = ---------------------------------------------------------------------------------------------------------------------SCF Divisor × ( 4 + XCLKS_ST+XCLKH_ST )
SCSI Functional Description
2-43
To configure the LSI53C1000 for Ultra160 DT transfers, perform the
following steps:
Step 1. Enable the SCSI Clock Quadrupler – The LSI53C1000 can
quadruple the frequency of a 40 MHz SCSI clock, allowing the
system to perform Ultra160 SCSI transfers. This option is
user-selectable through bit settings in the SCSI Test One
(STEST1) register. At power-up or reset, the quadrupler is
disabled and powered down. Follow the steps in the bit
description to enable the clock quadrupler.
Step 2. Program the Transfer Rate – Using SCNTL3 and SCNTL4,
program the register to 160 Mbytes/s transfer rate.
Step 3. Program the Maximum SCSI Offset – Using SXFER, program
the maximum SCSI DT Synchronous offset to 0x3E.
Step 4. Enable TolerANT – Set the TolerANT Enable bit, SCSI Test
Three (STEST3), bit 7. Active negation must be enabled for the
LSI53C1000 to perform Ultra160 SCSI transfers.
Figure 2.5 illustrates the clock division factors used in each register as
well as the role of the register bits in determining the transfer rate. An
example of configuring the Ultra160 SCSI transfer speed is:
1. Set SCNTL3 to 0x18.
2. Set SXFER to 0x3E.
3. Set SCNTL4 to 0x80.
These settings program the LSI53C1000 SCSI clock to send and receive
at 160 MHz with a synchronous SCSI offset of 0x3E.
2-44
Functional Description
Figure 2.5
40 MHz
SCLK
Determining the Synchronous Transfer Rate
SCF2
SCF1
SCF0
SCF Divisor
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
3
1
1.5
2
3
4
6
SCF
Divider
Divide by 4 (ST)
Divide by 2 (DT)
Asynchronous
Divider
Asynchronous
SCSI Logic
Receive/Send
Rate
Clock
Quadrupler
Input Clock Rate
Received Rate (DT) = ---------------------------------------------- (Megatransfers/s)
( SCF Divisor × 2 )
Input Clock Rate
Receive Rate (ST) = ---------------------------------------------- (Megatransfers/s)
( SCF Divisor × 4 )
Input Clock Rate
Send Rate (DT) = ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------XCLKS_DT + XCLKS_ST + XCLKH_DT + XCLKH_ST

SCF Divisor × 2 + ----------------------------------------------------------------------------------------------------------------------------------------------

2
Input Clock Rate
Send Rate (ST) = ------------------------------------------------------------------------------------------------------------------------SCF Divisor × ( 4 + XCLKS_ST + XCLKH_ST )
2.2.16 Interrupt Handling
The SCRIPTS processor in the LSI53C1000 performs most functions
independently of the host microprocessor. However, certain interrupt
situations must be handled by the external microprocessor. This section
explains all aspects of interrupts as they apply to the LSI53C1000.
2.2.16.1 Polling and Hardware Interrupts
The external microprocessor is informed of an interrupt condition by
polling or hardware interrupts. Polling means that the microprocessor
must continually loop and read a register until it detects a bit that is set
SCSI Functional Description
2-45
indicating an interrupt. This method is the fastest, but it diverts CPU time
from other system tasks. The preferred method of detecting interrupts in
most systems is hardware interrupts. In this case, the LSI53C1000
asserts the interrupt request (INTA/) line that interrupts the
microprocessor, causing the microprocessor to execute an interrupt
service routine. A hybrid approach uses hardware interrupts for long
waits and polling for short waits.
The SCSI interrupt is routed to PCI Interrupt INTA/.
2.2.16.2 Registers
The registers in the LSI53C1000 used for detecting or defining interrupts
are Interrupt Status Zero (ISTAT0), Interrupt Status One (ISTAT1), SCSI
Interrupt Status Zero (SIST0), SCSI Interrupt Status One (SIST1), DMA
Status (DSTAT), SCSI Interrupt Enable Zero (SIEN0), SCSI Interrupt
Enable One (SIEN1), and DMA Interrupt Enable (DIEN). See the register
descriptions in Chapter 4, “Registers,” for additional information.
ISTAT – The ISTAT register includes the Interrupt Status Zero (ISTAT0),
Interrupt Status One (ISTAT1), Mailbox Zero (MBOX0), and Mailbox One
(MBOX1) registers. It is the only register that can be accessed as a slave
during the SCRIPTS operation. Therefore, it is the register that is polled
when polled interrupts are used. It is also the first register that should be
read after the INTA/ pin is asserted in association with a hardware
interrupt.
The INTF (Interrupt-on-the-Fly) bit should be the first interrupt serviced.
It must be written to one in order to clear it. This interrupt must be
cleared before servicing any other interrupts indicated by SIP or DIP. Do
not attempt to read the other chip status registers if the INTF bit is set,
but SIP or DIP are not set.
If the SIP bit in the Interrupt Status Zero (ISTAT0) register is set, then a
SCSI-type interrupt has occurred and the SCSI Interrupt Status Zero
(SIST0) and SCSI Interrupt Status One (SIST1) registers should be read.
If the DIP bit in the Interrupt Status Zero (ISTAT0) register is set, then a
DMA-type interrupt has occurred and the DMA Status (DSTAT) register
should be read.
2-46
Functional Description
SCSI-type and DMA-type interrupts may occur simultaneously, so in
some cases both SIP and DIP may be set. To avoid missing a SCSI
interrupt the SIST0 and SIST1 registers should be read before the
DSTAT register is read.
When set, the SIRQD bit in ISTAT1 disables the INTA/ pin for the SCSI
function. The interrupt is not lost or ignored but is merely masked at the
pin. If the INTA/ pin is already asserted when SIRQD is set, the INTA/
pin will remain asserted until the interrupt is serviced. Future interrupts
will be masked at the pin until SIRQD is cleared.
Note that the host can read ISTAT as the SCRIPTS code is writing to
ISTAT. In this case the data will be unstable, so the read should be
retried.
SIST0 and SIST1 – The SCSI Interrupt Status Zero (SIST0) and SCSI
Interrupt Status One (SIST1) registers contain the status of SCSI-type
interrupts whether they are enabled in SCSI Interrupt Enable Zero
(SIEN0) and SCSI Interrupt Enable One (SIEN1) or not. Reading these
registers determines the conditions that caused the SCSI-type interrupt,
clears any bits that are set in SIST0 and SIST1, and clears the SIP bit
in Interrupt Status Zero (ISTAT0). Since the LSI53C1000 stacks
interrupts, SIST0 and SIST1 are not necessarily cleared after a read;
additional interrupts may still be pending.
If the LSI53C1000 is receiving data from the SCSI bus and a fatal
interrupt condition occurs, the chip attempts to send the contents of the
DMA FIFO to memory before generating the interrupt. Reading SCSI
Interrupt Status Zero (SIST0) and SCSI Interrupt Status One (SIST1) will
clear the CRC Error bit (bit 7) in the CRC Control One (CRCCNTL1)
register.
If the LSI53C1000 is sending data to the SCSI bus and a fatal SCSI
interrupt condition occurs, data could remain in the DMA FIFO. To
determine if the DMA FIFO is empty, check the DMA FIFO Empty (DFE)
bit in DMA Status (DSTAT) register. If this bit is cleared, set the CLF
(Clear DMA FIFO) and CSF (Clear SCSI FIFO) bits before continuing.
The CLF bit is bit 2 in Chip Test Three (CTEST3) register. The CSF bit
is bit 1 in SCSI Test Three (STEST3) register.
SCSI Functional Description
2-47
DSTAT – The DMA Status (DSTAT) register contains the status of
DMA-type interrupts whether they are enabled in DIEN or not. Reading
this register determines which condition(s) caused the DMA-type
interrupt, clears any interrupt related bits in DSTAT, and clears the DIP
bit in Interrupt Status Zero (ISTAT0). Since the LSI53C1000 stacks
interrupts, reading DSTAT does not necessarily clear the register as
additional interrupts may be pending.
Bit 7 (DFE) in the DMA Status (DSTAT) register, is purely a status bit; it
will not generate an interrupt and will not be cleared when read. DMA
interrupts do not flush the DMA or SCSI FIFOs before generating the
interrupt. Therefore, the DFE bit in the DSTAT register should be checked
after any DMA interrupt. If the DFE bit is cleared, the FIFOs must either
be cleared by setting the CLF (Clear DMA FIFO in CTEST3) and CSF
(Clear SCSI FIFO in STEST3) bits, or flushed by setting the FLF (Flush
DMA FIFO in CTEST3) bit.
SIEN0 and SIEN1 – The SCSI Interrupt Enable Zero (SIEN0) and SCSI
Interrupt Enable One (SIEN1) registers are the interrupt enable registers
for the SCSI interrupts in SCSI Interrupt Status Zero (SIST0) and SCSI
Interrupt Status One (SIST1). Clearing the appropriate mask bit masks
an interrupt.
DIEN – The DMA Interrupt Enable (DIEN) register is the interrupt enable
register for DMA interrupts in DMA Status (DSTAT). Clearing the
appropriate mask bit masks an interrupt.
2.2.16.3 Fatal vs. Nonfatal Interrupts
A fatal interrupt, as the name implies, always causes the SCRIPTS to
stop running. All nonfatal interrupts become fatal when they are enabled
by setting the appropriate interrupt enable bit. Interrupt masking is
discussed in Section 2.2.16.4, “Masking.” All DMA interrupts are fatal.
The DMA interrupts are indicated by the DIP bit in Interrupt Status Zero
(ISTAT0) and one or more bits in DMA Status (DSTAT).
Some SCSI interrupts are nonfatal. The SCSI interrupts are indicated by
the SIP bit in the Interrupt Status Zero (ISTAT0) register and one or more
bits in SCSI Interrupt Status Zero (SIST0) register or SCSI Interrupt
Status One (SIST1) register.
2-48
Functional Description
When the LSI53C1000 is operating in the Initiator mode, Interrupt-on-theFly, Function Complete (CMP), Selected (SEL), Reselected (RSL),
General Purpose Timer Expired (GEN), and Handshake-to-Handshake
Timer Expired (HTH) interrupts are nonfatal.
When operating in the Target mode, Interrupt-on-the-Fly, SATN/ active
(M/A), CMP, SEL, RSL, GEN, and HTH are nonfatal. Refer to the
description for the Disable Halt on a Parity/CRC/AIP Error or SATN/
active (Target Mode Only) bit, DHP, in the SCSI Control One (SCNTL1)
register to configure the chip’s behavior when the SATN/ interrupt is
enabled during Target mode operation.
The reason for nonfatal interrupts is to prevent the SCRIPTS from
stopping when an interrupt occurs that does not require service from the
CPU. This prevents an interrupt when arbitration is complete (CMP set),
when the LSI53C1000 is selected or reselected (SEL or RSL set), when
the initiator asserts ATN (target mode: SATN/ active), or when the
General Purpose or Handshake-to-Handshake timers expire. These
interrupts are not needed for events that occur during high level
SCRIPTS operation.
2.2.16.4 Masking
Masking an interrupt means disabling or ignoring that interrupt. Clearing
bits in the SCSI Interrupt Enable Zero (SIEN0) and SCSI Interrupt Enable
One (SIEN1) registers will mask SCSI interrupts. Clearing bits in the
DMA Interrupt Enable (DIEN) register will mask DMA interrupts. Masking
an interrupt after INTA/ is asserted does not cause INTA/ to be negated.
How the chip responds to masked interrupts depends on: whether polling
or hardware interrupts are being used; whether the interrupt is fatal or
nonfatal; and whether the chip is operating in the Initiator or Target mode.
If a nonfatal interrupt occurs while masked, SCRIPTS continues. The
appropriate bit in the SCSI Interrupt Status Zero (SIST0) or SCSI
Interrupt Status One (SIST1) is still set, the SIP bit in the Interrupt Status
Zero (ISTAT0) is not set, and the INTA/ pin is not asserted.
If a fatal interrupt occurs while masked, SCRIPTS halts. The appropriate
bit in the DMA Status (DSTAT), SCSI Interrupt Status Zero (SIST0), or
SCSI Interrupt Status One (SIST1) register is set, the SIP or DIP bit in
the Interrupt Status Zero (ISTAT0) register is set, but the INTA/ pin is not
asserted.
SCSI Functional Description
2-49
Setting the SIRQD bit in the Interrupt Status One (ISTAT1) register
disables the interrupt pin for the SCSI function. If an interrupt pin is
already asserted and SIRQD is then set, the interrupt pin will remain
asserted until serviced. Further interrupts will be blocked from the
interrupt pin.
When the LSI53C1000 is initialized, enable all fatal interrupts if hardware
interrupts are being used. If a fatal interrupt is disabled and that interrupt
condition occurs, the SCRIPTS halts and the system never knows it
unless it times out and checks the Interrupt Status Zero (ISTAT0),
Interrupt Status One (ISTAT1), Mailbox Zero (MBOX0), and Mailbox One
(MBOX1) registers after a certain period of inactivity.
If ISTAT is being polled instead of using hardware interrupts, then
masking a fatal interrupt makes no difference since the SIP and DIP bits
in the Interrupt Status Zero (ISTAT0) inform the system of interrupts, not
the INTA/ pin.
2.2.16.5 Stacked Interrupts
The LSI53C1000 stacks interrupts, if they occur, one after the other. If
the SIP or DIP bits in the Interrupt Status Zero (ISTAT0) register are set
(first level), then there is already at least one pending interrupt. Any
future interrupts are stacked in extra registers behind the SCSI Interrupt
Status Zero (SIST0), SCSI Interrupt Status One (SIST1), and DMA
Status (DSTAT) registers (second level). When two interrupts have
occurred and the two levels of the stack are full, any further interrupts
set additional bits in the extra registers behind SIST0, SIST1, and DSTAT.
When the first level of interrupts are cleared, all the later interrupts move
into SIST0, SIST1, and DSTAT. After the first interrupt is cleared, the
INTA/ pin is deasserted for a minimum of three CLKs; the stacked
interrupts move into SIST0, SIST1, or DSTAT; and the INTA/ pin is
asserted once again.
Since a masked nonfatal interrupt does not set the SIP or DIP bits,
interrupt stacking does not occur. A masked, nonfatal interrupt still posts
the interrupt in SCSI Interrupt Status Zero (SIST0), but does not assert
the INTA/ pin. Since no interrupt is generated, future interrupts move into
SCSI Interrupt Status Zero (SIST0) or SCSI Interrupt Status One (SIST1)
instead of stacking behind another interrupt. When another interrupt
condition occurs, the bit corresponding to the earlier masked nonfatal
interrupt is set.
2-50
Functional Description
A related situation to interrupt stacking is when two interrupts occur
simultaneously. Since stacking does not occur until the SIP or DIP bits
are set, there is a small timing window in which multiple interrupts can
occur but are not stacked. These could be multiple SCSI interrupts (SIP
set), multiple DMA interrupts (DIP set), or multiple SCSI and multiple
DMA interrupts (both SIP and DIP set).
As previously mentioned, DMA interrupts do not attempt to flush the
FIFOs before generating the interrupt. It is important to set either the
Clear DMA FIFO (CLF) and Clear SCSI FIFO (CSF) bits if a DMA
interrupt occurs and the DMA FIFO Empty (DFE) bit is not set. This is
because any future SCSI interrupts are not posted until the DMA FIFO
is cleared of data. These ‘locked out’ SCSI interrupts are posted as soon
as the DMA FIFO is empty.
2.2.16.6 Halting in an Orderly Fashion
When an interrupt occurs, the LSI53C1000 attempts to halt in an orderly
fashion.
•
If the interrupt occurs in the middle of an instruction fetch, the fetch
is completed, except in the case of a Bus Fault. Execution does not
begin, but the DSP points to the next instruction since it is updated
when the current instruction is fetched.
•
If the DMA direction is a write to memory and a SCSI interrupt
occurs, the LSI53C1000 attempts to flush the DMA FIFO to memory
before halting. Under any other circumstances, only the current cycle
is completed before halting, so the DFE bit in DMA Status (DSTAT)
should be checked to determine if any data remains in the DMA
FIFO.
•
SCSI SREQ/SACK handshakes that are in progress are completed
before halting.
•
The LSI53C1000 attempts to clean up any outstanding synchronous
offset before halting.
•
In the case of Transfer Control Instructions, once instruction
execution begins it continues to completion before halting.
•
In the case of a JUMP/CALL WHEN/IF <phase> instruction, the DMA
SCRIPTS Pointer (DSP) is updated to the transfer address before
halting.
•
All other instructions may halt before completion.
SCSI Functional Description
2-51
2.2.16.7 Sample Interrupt Service Routine
The following is a sample of an interrupt service routine for the
LSI53C1000. It can be repeated if polling is used, or should be called
when the INTA/ pin is asserted if hardware interrupts are used.
1. Read Interrupt Status Zero (ISTAT0).
2. If the INTF bit is set, write it to a one to clear this status.
3. If only the SIP bit is set, read SCSI Interrupt Status Zero (SIST0) and
SCSI Interrupt Status One (SIST1) to clear the SCSI interrupt
condition and get the SCSI interrupt status. The bits in the SIST0
and SIST1 tell which SCSI interrupts occurred and determine what
action is required to service the interrupts.
4. If only the DIP bit is set, read DMA Status (DSTAT) to clear the
interrupt condition and determine the DMA interrupt status. The bits
in the DSTAT register indicate which DMA interrupts occurred and
determine what action is required to service the interrupts.
5. If both the SIP and DIP bits are set, read SCSI Interrupt Status Zero
(SIST0), SCSI Interrupt Status One (SIST1), and DMA Status
(DSTAT) to clear the SCSI and DMA interrupt condition and
determine the interrupt status. If using 8-bit reads of the SIST0,
SIST1, and DSTAT registers to clear interrupts, insert a 12 clock
delay between the consecutive reads to ensure that the interrupts
clear properly. Both the SCSI and DMA interrupt conditions should
be handled before leaving the Interrupt Service Routine (ISR). It is
recommended that the DMA interrupt is serviced before the SCSI
interrupt, because a serious DMA interrupt condition could influence
how the SCSI interrupt is acted upon.
6. When using polled interrupts go back to step 1 before leaving the
ISR in case any stacked interrupts moved in when the first interrupt
was cleared. When using hardware interrupts, the INTA/ pin is
asserted again if there are any stacked interrupts. This should cause
the system to re-enter the interrupt service routine.
2-52
Functional Description
2.2.17 Interrupt Routing
This section documents the recommended approach to RAID ready
interrupt routing for the LSI53C1000. In order to be compatible with RAID
upgrade products and the LSI53C1000, the following requirements must
be met:
•
When a RAID upgrade card is installed in the upgrade slot, interrupts
from the mainboard SCSI controller assigned to the RAID upgrade
card must be routed to INTC/ of the upgrade slot and isolated from
the mainboard interrupt controller. The system processor must not
see interrupts from the SCSI controllers that are serviced by the
RAID upgrade card. An upgrade slot is one that is connected to the
interrupt routing logic for mainboard SCSI device(s). When a PCI
RAID upgrade board is installed into the system, it will be plugged
into this slot if it is to control mainboard SCSI device(s).
•
The TDI pin of the upgrade slot must be connected to the INT_DIR/
pin of the LSI53C1000.
•
When a RAID upgrade card is not installed, interrupts from a SCSI
core must not be presented to the system’s interrupt controller using
multiple interrupt inputs.
Figure 2.6 shows an example configuration. In this example the
LSI53C1000 contains the interrupt routing logic.
The LSI53C1000 supports four different interrupt routing modes.
Additional information for these modes may be found in the register
description of SCSI Test One (STEST1) description in Chapter 4,
“Registers.” The SCSI core within the chip may be configured by
selecting the interrupt routing mode using bits [1:0] in the STEST1
register within the core. Mode 0 is the default mode and is compatible
with RAID upgrade products.
If the implementation shown in Figure 2.6 is used, INTC/ of the PCI RAID
upgrade slot cannot be used when a non-RAID upgrade card is installed
in the slot. If this restriction is not acceptable, additional buffer logic must
be implemented on the mainboard. As long as the interrupt routing
requirements stated above are satisfied, a mainboard designer could
implement this design with external logic.
SCSI Functional Description
2-53
Figure 2.6
Interrupt Routing Hardware Using the LSI53C1000
+5V
PCI RAID UPGRADE SLOT
INT_DIR
10 K
+5V
LSI53C1000
2.7 K
ALT_INTA/
A4 TDI
A6 INTA/
INTC/
A7
PCI RAID
Upgrade
Slot INTA/
SCSI Core
INTA/
MB SCSI INTA/
These interrupt lines are
connected to the other PCI
slot interrupt lines as
determined by the
mainboard interrupt
routing scheme.
There can only be one entity controlling a mainboard SCSI core or
conflicts will occur. Typically a SCSI core is controlled by the SCSI BIOS
and an operating system driver. When a SCSI core is allocated to a RAID
adapter, however, a mechanism must be implemented to prevent the
SCSI BIOS and operating system driver from trying to access the SCSI
core. The mainboard designer has several options to choose from for
doing this.
2-54
•
The first option is to have the SCSI core load its PCI Subsystem ID
using a serial EPROM on power-up. If bit 15 in this ID is set, the LSI
Logic BIOS and operating system drivers will ignore the chip. This
makes it possible to control the assignment of the mainboard SCSI
cores using a configuration utility.
•
The second option is to provide mainboard and system BIOS
support for Nonvolative Storage (NVS). The SCSI core may then be
enabled or disabled using the SCSI BIOS configuration utility. Not all
versions of the drivers support this capability.
Functional Description
•
The third option is to have the system BIOS not report the existence
of the SCSI controller chips when the SCSI BIOS and operating
systems make PCI BIOS calls. This approach requires modifications
to the system BIOS and assumes the operating system uses PCI
BIOS calls when searching for PCI devices.
2.2.18 Chained Block Moves
Since the LSI53C1000 has the capability to transfer 16-bit wide SCSI
data, a unique situation occurs when dealing with odd bytes. The
Chained Move (CHMOV) SCRIPTS instruction along with the Wide SCSI
Send (WSS) and Wide SCSI Receive (WSR) bits in the SCSI Control
Two (SCNTL2) register are used to facilitate these situations. The
Chained Block Move instruction is illustrated in Figure 2.7.
Figure 2.7
Chained Block Move Instruction
Host Memory
SCSI Bus
0x03
0x02
0x01
0x00
0x00
0x04
0x03
0x07
0x06
0x05
0x04
0x04
0x06
0x05
0x0B 0x0A 0x09
0x08
0x08
0x0F 0x0E 0x0D 0x0C
0x0C
0x13
0x10
0x09
0x07
0x12
0x11
0x10
0x0B 0x0A
0x0D 0x0C
32 Bits
16 Bits
CHMOV 5, 3 when Data-Out
Moves five bytes from address 0x03 in the host memory to the SCSI bus.
Bytes 0x03, 0x04, 0x05, and 0x06 are moved and byte 0x07 remains in
the SCSI core (in the lower byte of the SODL register for asynchronous
SCSI Functional Description
2-55
transfers, in the chain byte holding register for synchronous transfers).
The stored byte is combined with the first byte of the following CHMOV
instruction.
CHMOV 0x5, 0x9 when Data-In
Moves five bytes from address 0x09 in the host memory to the SCSI bus.
The data in address 0x09 is married with the stored data (0x07) and
transferred to the SCSI bus.
2.2.18.1 Wide SCSI Send Bit
The WSS bit is set following a wide SCSI send operation (Data-Out for
initiator mode or Data-In for target mode) when the SCSI core is holding
a byte of chain data. The SCSI core holds the byte when the controller
detects a partial transfer at the end of a Chained Block Move SCRIPTS
instruction. This flag is not set if a normal Block Move instruction is used.
Under this condition, the SCSI controller does not send the low-order
byte of the last partial memory transfer across the SCSI bus. Instead, the
low-order byte is temporarily stored in the lower byte of the SCSI Output
Data Latch (SODL) register for asynchronous transfers or in the chain
byte holding register for synchronous transfers, and the WSS flag is set.
The hardware uses the WSS bit to determine what behavior must occur
at the start of the next data send transfer. If the WSS bit is set at the
start of the next transfer, the first byte (the high-order byte) of the next
data send transfer is “married” with the byte of chain data. The two bytes
are sent out across the bus regardless of the type of Block Move
instruction (normal or chained). The WSS bit is automatically cleared
when the “married” word is sent. Performing either a SCSI receive
operation or any narrow transfer also clears the bit. In addition, SCRIPTS
and the microprocessor can clear the WSS bit as well as use it for error
detection and recovery purposes.
2.2.18.2 Wide SCSI Receive Bit
The WSR bit is set following a wide SCSI receive operation (Data-In for
initiator mode or Data-Out for target mode) when the SCSI core is
holding a byte of chain data. The SCSI core holds the byte when the
controller detects a partial transfer at the end of a Chained Block Move
2-56
Functional Description
instruction. Under this condition the high-order byte is not transferred out
the DMA channel to memory. Instead, it is stored in the SCSI Wide
Residue (SWIDE) register and the WSR flag is set.
The hardware uses the WSR bit to determine what behavior must occur
at the start of the next data receive transfer. If set the stored high-order
byte may be residual data, valid data for a subsequent data transfer, or
overrun data. The byte may be read as normal by starting a data receive
transfer. The WSR bit is automatically cleared at the start of the next data
receive transfer. Performing either a SCSI send operation or any narrow
transfer also clears the bit. In addition, SCRIPTS and the microprocessor
can clear the WSR bit as well as use it for error detection and recovery
purposes.
2.2.18.3 SWIDE Register
For wide asynchronous receive data transfers, the SCSI Wide Residue
(SWIDE) register holds the high-order byte of a partial SCSI transfer
which has not yet been transferred to memory. This stored data may be
a residue byte (and therefore ignored) or it may be valid data that is
transferred to memory at the beginning of the next data receive Block
Move instruction.
2.2.18.4 SODL Register
For wide asynchronous send data transfers, the low-order byte of the
SCSI Output Data Latch (SODL) register holds the low-order byte of a
partial memory transfer which has not yet been transferred across the
SCSI bus. This stored data is usually “married” with the first byte of the
next data send transfer, and both bytes are sent across the SCSI bus at
the start of the next data send Block Move instruction.
2.2.18.5 Chained Block Move SCRIPTS Instruction
A Chained Block Move SCRIPTS instruction is primarily used to transfer
consecutive data send or data receive blocks. Using the Chained Block
Move instruction facilitates partial receive transfers and allows correct
partial send behavior without additional opcode overhead. The behavior
of the Chained Block Move instruction varies slightly for sending and
receiving data.
SCSI Functional Description
2-57
For receive data (Data-In for the initiator or Data-Out for the target), a
Chained Block Move instruction indicates that if a partial transfer
occurred at the end of the instruction the WSR flag is set. The high-order
byte of the last SCSI transfer is stored in the SCSI Wide Residue
(SWIDE) register rather than transferred to memory. The stored byte
should be the first byte transferred to memory at the start of the Chained
Block Move or regular Block Move data stream. Since the byte count
always represents data transfers to/from memory (as opposed to/from
the SCSI bus), the stored byte transferred out is one of the bytes in the
count. If the WSR bit is cleared when a receive data Chained Block Move
instruction is executed, the data transfer occurs similar to that of the
regular Block Move instruction. It is recommended that all Block Move
instructions be Chained Block Moves.
For send data (Data-Out for the initiator or Data-In for the target), a
Chained Block Move instruction indicates that if a partial transfer
terminates the Chained Block Move the WSS flag is set. The low-order
byte should be stored in the lower byte of the SCSI Output Data Latch
(SODL) register for asynchronous transfers or in the chain byte holding
register for synchronous transfers and not sent across the SCSI bus.
Without the Chained Block Move instruction, the last low-order byte
would be sent across the SCSI bus. The starting byte count represents
data bytes transferred from memory but not to the SCSI bus when a
partial transfer exists. For example, if the instruction is an initiator
Chained Block Move Data Out of five bytes (and WSS is not previously
set), five bytes are transferred out of memory to the SCSI controller. Four
bytes are transferred from the SCSI controller across the SCSI bus and
one byte is temporarily stored as described above, waiting to be married
with the first byte of the next Chained Block Move instruction. If the WSS
bit is set at the start of a data send command the first byte of the transfer
is assumed to be the high-order byte and is “married” with the stored
byte (which will be the low-order byte) before the two bytes are sent
across the SCSI bus. It is recommended that all Block Move instructions
be Chained Block Moves.
2-58
Functional Description
2.3 Parallel ROM Interface
The LSI53C1000 supports up to 1 Mbyte of external memory in binary
increments from 16 Kbytes to allow the use of expansion ROM for
add-in PCI cards. This interface is designed for low-speed operations
such as downloading instruction code from ROM; it is not intended for
dynamic activities such as executing instructions.
System requirements include the LSI53C1000, two or three external 8-bit
address holding registers (HCT273 or HCT374), and the appropriate
memory device. The 4.7 KΩ pull-up resistors on the MAD bus require HC
or HCT external components to be used. Pull-up resistors on the 8-bit
bidirectional memory bus at power-up determine the memory size and
speed. The LSI53C1000 senses this bus shortly after the release of the
Reset signal and configures the Expansion ROM Base Address register
and the memory cycle state machines for the appropriate conditions.
The LSI53C1000 supports a variety of sizes and speeds of expansion
ROM. An example set of interface drawings is in Appendix B, “External
Memory Interface Diagram Examples.” The encoding of pins MAD[3:1]
allows the user to define how much external memory is available to the
LSI53C1000. Table 2.7 shows the memory space associated with the
possible values of MAD[3:1]. The MAD[3:1] pins are fully described in
Chapter 3, “Signal Descriptions.”
Parallel ROM Interface
2-59
Table 2.7
Parallel ROM Support
MAD[3:1]
Available Memory Space
000
16 Kbytes
001
32 Kbytes
010
64 Kbytes
011
128 Kbytes
100
256 Kbytes
101
512 Kbytes
110
1024 Kbytes
111
No external memory present,
ROM interface disabled
To use one of the configurations mentioned above in a host adapter
board design, put 4.7 KΩ pull-up resistors on the MAD pins
corresponding to the available memory space. Each MAD pin has an
internal static pull-down; therefore, no external pull-down resistors are
needed. For example, to connect to a 64 Kbytes external ROM use a
pull-up on MAD[2]. If the external memory interface is not used,
MAD[3:1] should be pulled HIGH.
The LSI53C1000 allows the system to determine the size of the available
external memory using the Expansion ROM Base Address register in the
PCI configuration space. For more information on how this works, refer
to the PCI specification or the Expansion ROM Base Address register
description in Chapter 4, “Registers.”
MAD[0] is the slow ROM pin. When pulled up it enables two extra clock
cycles of data access time to allow use of slower memory devices. The
external memory interface also supports updates to flash memory.
2-60
Functional Description
2.4 Serial EEPROM Interface
The LSI53C1000 implements an interface permitting attachment of a
serial EEPROM device to the GPIO[0] and GPIO[1] pins. There are two
modes of operation relating to the serial EEPROM, the Subsystem ID
register, and the Subsystem Vendor ID register. These modes are
programmable through the MAD[7] pin, which is sampled at power-up.
2.4.1 Default Download Mode
In this mode, MAD[7] is pulled down internally, GPIO[0] is the serial data
signal (SDA), and GPIO[1] is the serial clock signal (SCL). Certain data
in the serial EEPROM is automatically loaded into chip registers at
power-up.
The format of the serial EEPROM data is defined in Table 2.8. If the
download is enabled and an EEPROM is not present or the checksum
fails, the Subsystem ID and Subsystem Vendor ID registers read back all
zeros. At power-up five bytes are loaded into the chip from locations
0xFB through 0xFF.
The Subsystem ID and Subsystem Vendor ID registers are read only in
accordance with the PCI specification, with a default value of all zeros if
the download fails.
Note:
Table 2.8
The speed of the serial EEPROM must be 400 Kbits/s.
Default Download Mode Serial EEPROM Data Format
Byte
Name
Description
0xFB
SVID(0)
Subsystem Vendor ID (SVID), LSB. This byte is loaded
into the least significant byte of the Subsystem Vendor
ID register in the appropriate PCI configuration space at
chip power-up.
0xFC
SVID(1)
Subsystem Vendor ID (SVID), MSB. This byte is loaded
into the most significant byte of the Subsystem Vendor
ID register in the appropriate PCI configuration space at
chip power-up.
Serial EEPROM Interface
2-61
Table 2.8
Default Download Mode Serial EEPROM Data Format
(Cont.)
Byte
Name
Description
0xFD
SID(0)
Subsystem ID (SID), LSB. This byte is loaded into the
least significant byte of the Subsystem ID register in the
appropriate PCI configuration space at chip power-up.
0xFE
SID(1)
Subsystem ID (SID), MSB. This byte is loaded into the
most significant byte of the Subsystem ID register in the
appropriate PCI configuration space at chip power-up.
0xFF
CKSUM
Checksum (CKSUM). This 8-bit checksum is formed by
adding, bytewise, each byte contained in locations
0xFB–0xFE to the seed value (0x55) and then taking the
2’s complement of the result.
2.4.2 No Download Mode
When MAD[7] is pulled up through an external resistor, the automatic
download is disabled and data is not automatically loaded into chip
registers at power-up. The Subsystem ID and Subsystem Vendor ID
registers are read only, per the PCI specification, with a default value of
0x1000 and 0x1000 respectively.
2.5 Power Management
The LSI53C1000 complies with the PCI Bus Power Management
Interface Specification, Revision 1.1, in which the D0, D1, D2, and D3
are defined.
D0 is the maximum powered state, and D3 is the minimum powered
state. Power state D3 is further categorized as D3hot or D3cold. A device
that is powered off is in the D3cold power state.
The LSI53C1000 power states are independently controlled through two
power state bits that are located in the PCI Configuration Space Power
Management Control/Status (PMCSR) register, 0x44–0x45. The power
state bit settings are provided in Table 2.9.
2-62
Functional Description
Table 2.9
Power States
Configuration Register (0x44),
Bits [1:0]
Power State
00
D0
Maximum Power
01
D1
Disables SCSI clock
10
D2
Coma Mode
11
D3
Minimum Power
Function
Although the PCI Bus Power Management Interface Specification does
not allow power state transitions D2 to D1, D3 to D2, or D3 to D1, the
LSI53C1000 hardware places no restriction on transitions between
power states. The PCI Function Power States D0, D1, D2, and D3 are
described below.
As the device transitions from one power level to a lower one, the
attributes that occur from the higher power state level are carried over
into the lower power state level. For example, D1 disables the SCSI CLK.
Therefore, D2 includes this attribute as well as the attributes defined in
the Power State D2 section. The PCI Function Power States - D0, D1,
D2, and D3 are described below.
2.5.1 Power State D0
Power state D0 is the maximum power state and is the power-up default
state. The LSI53C1000 is fully functional in this state.
2.5.2 Power State D1
Power state D1 is a lower power state than D0. In this state the
LSI53C1000 core is in the snooze mode and the SCSI clock is disabled.
In the snooze mode, a SCSI reset does not generate an INT/ signal.
Power Management
2-63
2.5.3 Power State D2
Power state D2 is a lower power state than D1. In this state the
LSI53C1000 core is in the coma mode. The following PCI Configuration
Space Command register enable bits are suppressed:
•
I/O Space Enable
•
Memory Space Enable
•
Bus Mastering Enable
•
SERR/Enable
•
Enable Parity Error Response
Thus, the function's memory and I/O spaces cannot be accessed, and
the function cannot be a PCI bus master. Furthermore, SCSI and DMA
interrupts are disabled when the function is in power state D2. If the
function is changed from power state D2 to power state D1 or D0, the
previous values of the PCI Command register are restored. Also, any
pending interrupts before the function entered power state D2 are
asserted.
2.5.4 Power State D3
Power state D3 is the minimum power state, which includes settings
called D3hot and D3cold. D3hot allows the device to transition to D0
using software. The LSI53C1000 is considered to be in power state
D3cold when power is removed from the device. D3cold can transition to
D0 by applying VCC and resetting the device.
Power state D3 is a lower power level than power state D2. In this state
the LSI53C1000 core is in the coma mode. Furthermore, soft reset is
continually asserted while in power state D3, which clears all pending
interrupts and 3-states the SCSI bus. In addition, the PCI Command
register is cleared. If the LSI53C1000 is placed in power state D3, the
Clock Quadrupler is disabled, which results in additional power savings.
2-64
Functional Description
Chapter 3
Signal Descriptions
This chapter describes the input and output signals of the LSI53C1000.
The chapter consists of the following sections:
•
Section 3.1, “Signal Organization”
•
Section 3.2, “Internal Pull-ups and Pull-downs on LSI53C1000
Signals”
•
Section 3.3, “PCI Bus Interface Signals”
•
Section 3.4, “SCSI Bus Interface Signals”
•
Section 3.5, “General Purpose I/O (GPIO) Signals”
•
Section 3.6, “Flash ROM and Memory Interface Signals”
•
Section 3.7, “Test Interface Signals”
•
Section 3.8, “Power and Ground Signals”
•
Section 3.9, “MAD Bus Programming”
3.1 Signal Organization
The LSI53C1000 has five major interfaces:
•
PCI Interface
•
SCSI Bus Interface
•
General Purpose I/O (GPIO) Interface
•
Memory Interface
•
Test Interface
Figure 3.1 illustrates the signals, their grouping, and their I/O direction. A
slash (/) at the end of a signal name indicates that it is an active LOW
signal. When the slash is absent, the signal is active at a HIGH voltage.
LSI53C1000 PCI to Ultra160 SCSI Controller
3-1
The PCI Interface contains several functional groups of signals. The
SCSI Bus Interface contains one functional group of signals, as
illustrated in Figure 3.1.
There are five signal type definitions:
I
Input, a standard input-only signal.
O
Output, a standard output driver (typically a Totem Pole output).
I/O
Input and output (bidirectional).
T/S
3-state, a bidirectional, 3-state input/output signal.
S/T/S
Sustained 3-state, an active LOW 3-state signal owned and driven by
one and only one agent at a time.
Figure 3.1 illustrates the signal groupings. Pinout information and
package drawings are available in Section 6.6, “Package Drawings.”
3-2
Signal Descriptions
Figure 3.1
PCI
Bus
Interface
LSI53C1000 Signal Grouping
System
CLK
ENABLE66
M66EN
RST/
Address
and
Data
AD[63:0]
C_BE[7:0]/
PAR
PAR64
Interface
Control
LSI53C1000
ACK64/
REQ64/
FRAME/
TRDY/
IRDY/
STOP/
DEVSEL/
IDSEL
Arbitration
REQ/
GNT/
Error
Reporting
PERR/
SERR/
Interrupt
INTA/
ALT_INTA/
INT_DIR
GPIO
Interface
GPIO0_FETCH/
GPIO1_MASTER/
GPIO2
GPIO3
GPIO4
Flash
ROM
and
Memory
Interface
MWE/
MCE/
MOE/_TESTOUT
MAS0/
MAS1/
MAD[7:0]
Signal Organization
SCLK
SD[15:0]/
SDP[1:0]/
DIFFSENS
SC_D/
SI_O/
SMSG/
SREQ/
SACK/
SBSY/
SATN/
SRST/
SSEL/
SCAN_MODE
TEST_HSC
TEST_PD
TEST_RST/
MOE/_TESTOUT
TCK
TMS
TDI
TDO
SCSI
Bus
Interface
Test
Interface
3-3
3.2 Internal Pull-ups and Pull-downs on LSI53C1000 Signals
Several LSI53C1000 signals use internal pull-ups or pull-downs.
Table 3.1 describes the conditions that enable these pull-ups and
pull-downs.
Table 3.1
LSI53C1000 Internal Pull-ups and Pull-downs
Pull-up
Current
Pin Name
Conditions for Pull-up
INTA/, ALT_INTA/
25 µA
Pull-up enabled when the “AND-tree” mode is enabled by
driving TEST_RST/ LOW or when the IRQ Mode bit (bit 3
of the DMA Control (DCNTL) register) is cleared.1
ENABLE66, INT_DIR,
M66EN, TCK, TDI,
TEST_RST/, TMS
25 µA
Pulled up internally.
AD[63:32], C_BE[7:4]/,
PAR64
25 µA
Pulled down internally.
GPIO[4:0]
25 µA
Pulled up internally.
MAD[7:0]
25 µA
Pulled down internally.
TEST_PD, TEST_HSC,
SCAN_MODE
25 µA
Pulled down internally.
1. When bit 3 of the DMA Control (DCNTL) register is set, the pad becomes a totem pole output pad
and drives both HIGH and LOW.
3.3 PCI Bus Interface Signals
The PCI Bus Interface Signals section contains tables describing the
signals for the following signal groups: System Signals, Address and
Data Signals, Interface Control Signals, Arbitration Signals, Error
Reporting Signals, Interrupt Signals, and GPIO Signals.
3-4
Signal Descriptions
3.3.1 System Signals
Table 3.2 describes the signals for the System Signals group.
Table 3.2
System Signals
Name
Bump
Type
Strength
CLK
Description
H3
I
N/A
Clock provides timing for all transactions on the PCI bus
and is an input to every PCI device. All other PCI signals
are sampled on the rising edge of CLK and other timing
parameters are defined with respect to this edge.
ENABLE66 B3
I
N/A
Enable66 controls the 66C bit in the PCI Configuration
Space. This bit indicates whether or not the chip is 66 MHz
capable. This pin has a static pull-up.
M66EN
B1
I
N/A
M66EN is used to enable the 66 MHz PCI mode. This pin
is connected to the M66EN PCI signal on the PCI bus. This
pin has a static pull-up.
RST/
G1
I
N/A
Reset forces the PCI sequencer of each device to a known
state. All T/S and S/T/S signals are forced to a high
impedance state, and all internal logic is reset. The RST/
input is synchronized internally to the rising edge of CLK.
To properly reset the device, the CLK input must be active
while RST/ is active.
PCI Bus Interface Signals
3-5
3.3.2 Address and Data Signals
Table 3.3 describes the Address and Data Signals group.
Table 3.3
Address and Data Signals
Name
Bump
Type
AD[63:0]
Y5, AB5, AC5, AA6,
Y6, AB6, AC6, AA7,
AB7, AC7, AA8, Y8,
AB8, AC8, AA9, Y9,
AB9, AC9, AA10, Y11,
AB10, AC10, AA11,
AC11, AB11, AC12,
AA12, AB12, AB13,
AC13, AA13, AC14,
H1, J3, J4, J2, J1, K3,
L4, K2, L1, L2, M1, M3,
M2, N2, N1, N3, T4,
T3, U1–U3, V1, V2,
V4, W1, W2, W4, W3,
Y1, Y2, AA1, Y3
Strength
Description
T/S
8 mA PCI Physical longword Address and Data are
multiplexed on the same PCI pins. A bus
transaction consists of an address phase
followed by one or more data phases. During
the first clock of a transaction, AD[63:0]
contain a 64-bit physical byte address. If the
command is a DAC, implying a 64-bit
address, AD[31:0] will contain the upper
32 bits of the address during the second
clock of the transaction. During subsequent
clocks, AD[63:0] contain data. PCI supports
both read and write bursts. AD[7:0] define
the least significant byte, and AD[63:56]
define the most significant byte.
C_BE[7:0]/ AA4, AC3, AB4, AC4,
K1, P1, T2, V3
T/S
8 mA PCI Bus Command and Byte Enables are
multiplexed on the same PCI pins. During
the address phase of a transaction,
C_BE[3:0]/ define the bus command. If the
transaction is a DAC, C_BE[3:0]/ contain the
DAC command and C_BE[7:4]/ define the
bus command. C_BE[3:0]/ define the bus
command during the second clock of the
transaction. During the data phase,
C_BE[7:0]/ are used as byte enables. The
byte enables determine which byte lanes
carry meaningful data: C_BE[0]/ applies to
byte 0 and C_BE[7] applies to byte 7.
PAR
T1
T/S
8 mA PCI Parity is the even parity bit that protects the
AD[31:0] and C_BE[3:0]/ lines. During the
address phase, both the address and
command bits are covered. During the data
phase, both the data and byte enables are
covered.
PAR64
AA5
T/S
8 mA PCI Parity64 is the even parity bit that protects
the AD[63:32] and C_BE[7:4]/ lines. During
the address phase, the address and
command bits are covered. During the data
phase, both data and byte enables are
covered.
3-6
Signal Descriptions
3.3.3 Interface Control Signals
Table 3.4 describes the Interface Control Signals group.
Table 3.4
Interface Control Signals
Name
Bump
Type
ACK64/
AB1
S/T/S 8 mA PCI Acknowledge 64-bit transfer is driven by the current bus
target to indicate its ability to transfer 64-bit data.
REQ64/
AA2
S/T/S 8 mA PCI Request 64-bit transfer is driven by the current bus master
to indicate a request to transfer 64-bit data.
FRAME/
P2
S/T/S 8 mA PCI Cycle Frame is driven by the current master to indicate the
beginning and duration of an access. FRAME/ is asserted
to indicate that a bus transaction is beginning. While
FRAME/ is deasserted, either the transaction is in the final
data phase or the bus is idle.
TRDY/
P3
S/T/S 8 mA PCI Target Ready indicates the target’s ability to complete the
current data phase of the transaction. TRDY/ is used with
IRDY/. A data phase is completed on any clock when both
TRDY/ and IRDY/ are sampled asserted. During a read,
TRDY/ indicates that valid data is present on the AD bus.
During a write, it indicates that the target is prepared to
accept data.
IRDY/
N4
S/T/S 8 mA PCI Initiator Ready indicates the initiator’s ability to complete
the current data phase of the transaction. IRDY/ is used with
TRDY/. A data phase is completed on any clock when both
IRDY/ and TRDY/ are sampled asserted. During a write,
IRDY/ indicates that valid data is present on the AD bus.
During a read, it indicates that the master is prepared to
accept data.
STOP/
R2
S/T/S 8 mA PCI Stop indicates that the selected target is requesting the
master to stop the current transaction.
DEVSEL/
R1
S/T/S 8 mA PCI Device Select indicates that the driving device has
decoded its address as the target of the current access. As
an input, it indicates to a master whether any device on the
bus has been selected.
IDSEL
L3
I
Strength
N/A
Description
Initialization Device Select is used as a chip select, in
place of the upper 24 address lines, during configuration
read and write transactions.
PCI Bus Interface Signals
3-7
3.3.4 Arbitration Signals
Table 3.5 describes the Arbitration Signals group.
Table 3.5
Arbitration Signals
Name
Bump
Type
REQ/
H2
O
GNT/
H4
I
Strength
Description
8 mA PCI Request indicates to the system arbiter that this agent
requests use of the PCI bus. This is a point-to-point signal.
Every master has its own REQ/ signal.
N/A
Grant indicates to a specific agent that access to the PCI bus
has been granted. This is a point-to-point signal. Every
master has its own GNT/ signal.
3.3.5 Error Reporting Signals
Table 3.6 describes the Error Reporting Signals group.
Table 3.6
Error Reporting Signals
Name
Bump
Type
PERR/
R4
S/T/S 8 mA PCI Parity Error may be pulsed active by an agent that detects
a data parity error. PERR/ can be used by any agent to
signal data corruption. On detection of a PERR/ pulse, the
central resource may generate a nonmaskable interrupt to
the host CPU, which often implies the system is unable to
continue operation once error processing is complete.
SERR/
R3
3-8
O
Strength
Description
8 mA PCI System Error is an open drain output used to report
address parity errors as well as critical errors other than
parity.
Signal Descriptions
3.3.6 Interrupt Signals
Table 3.7 describes the Interrupt Signals group.
Table 3.7
Interrupt Signals
Name
Bump
Type
Strength
INTA/
F4
O
8 mA PCI Interrupt. This signal, when asserted LOW, indicates that
an interrupt condition requires service from the host CPU.
The output drive of this pin is an open drain. See SCSI Test
One (STEST1), bits [1:0], for additional information about
disabling this interrupt in a RAID environment. This
interrupt pin is disabled if INT_DIR is driven LOW.
ALT_INTA/
F1
O
8 mA PCI Alt Interrupt. This signal, when asserted LOW, indicates
that an interrupt condition requires service from the host
CPU. The output drive of this pin is an open drain. See
SCSI Test One (STEST1), bits [1:0], for additional
information about disabling this interrupt in a RAID
environment.
INT_DIR
G2
I
N/A
Description
Interrupt Direction. This input signal indicates whether
internally generated interrupts are presented on INTA/. If
INT_DIR is HIGH, internal interrupts are generated on the
INTA/ and ALT_INTA/ pins. If INT_DIR is LOW, the internal
interrupts are generated only on the ALT_INTA/ pin. This
pin has no effect if either bit 0 or 1 in SCSI Test One
(STEST1) is set. This pin has a static pull-up.
3.4 SCSI Bus Interface Signals
Table 3.8 contains tables describing the SCSI Bus Interface Signal group.
Table 3.8
SCSI Bus Interface Signals
Name
Bump
SCLK
A21
Type
Strength
I
N/A
Description
SCSI Clock is used to derive all SCSI-related timings.
The speed of this clock must be 40 MHz. The clock
frequency can be quadrupled to create the 160 MHz clock
required internally for Ultra160 transfers.
SCSI Bus Interface Signals
3-9
The following tables describe the SCSI signals. Table 3.9 describes the
SCSI Signals and Table 3.10 describes the SCSI Control Signals.
Table 3.9
SCSI Signals
Name
Bump
SD[15:0]−
B5, C5, B4, C4,
D19, A19, D18,
A18, D11, A9, D9,
A8, D8, A7, C7, B6
Type
Strength
Description
I/O
SE:
48 mA
SCSI
SCSI Data.
LVD:
12 mA
UniLVD
SD[15:0]+
A5, D5, A4, A3,
C19, B19, C18,
B18, B10, C10, B9,
C9, B8, C8, B7, A6
I/O
SE:
48 mA
SCSI
LVD:
12 mA
UniLVD
SDP[1:0]−
C6, A10.
I/O
SE:
48 mA
SCSI
LVD:
12 mA
UniLVD
SDP[1:0]+
D6, C11
I/O
SE:
48 mA
SCSI
LVD:
12 mA
UniLVD
3-10
Signal Descriptions
LVD Mode: Negative half of LVDlink pair for
SCSI data. SD[15:0]− form the 16-bit SCSI
data bus.
SE Mode: SD[15:0]− form the 16-bit SCSI
data bus.
SCSI Data.
LVD Mode: Positive half of LVDlink pair for
SCSI data lines. SD[15:0]+ form the 16-bit
data bus.
SE Mode: SD[15:0]+ are at 0 V.
SCSI Parity.
LVD Mode: Negative half of LVDlink pair for
SCSI parity lines. SDP[1:0]− are the SCSI
data parity lines.
SE Mode: SDP[1:0]− are the SCSI data
parity lines.
SCSI Parity.
LVD Mode: Positive half of LVDlink pair for
the SCSI parity lines. SDP[1:0]+ are the
SCSI data parity lines.
SE Mode: SDP[1:0]+ are at 0 V.
Table 3.9
SCSI Signals (Cont.)
Name
Bump
DIFFSENS
A20
Type
Strength
I
N/A
Description
SCSI Differential Sense pin detects the
present mode of the SCSI bus when
connected to the DIFFSENS signal on the
physical SCSI bus.
LVD Mode: If a voltage between 0.7 V and
1.9 V is present, the SCSI bus operates in
the LVD mode.
SE Mode: When this pin is driven LOW
(below 0.5 V), the SCSI bus operates in
the SE mode.
HVD Mode: When this pin is detected
HIGH (above 2.0 V) HVD operation is
indicated. The SCSI bus is driven to the
high impedance state. This pin is 5 V
tolerant. The HVD Mode is not supported.
SCSI Bus Interface Signals
3-11
Table 3.10
Name1
SCSI Control Signals
Bump
Type
Strength
Description
SCSI Control includes the following signals:
I/O
SE:
48 mA
SCSI
SCSI phase line, command/data.
SC_D−
SC_D+
C15
A16
SI_O−
SI_O+
B17
C17
SMSG−
SMSG+
C14
A15
SREQ−
SREQ+
C16
A17
Data handshake line from target device.
SACK−
SACK+
C13
A14
Data handshake signal from the initiator device.
SBSY−
SBSY+
C12
A12
SCSI bus arbitration signal, busy.
SATN−
SATN+
B11
B12
SCSI Attention, the initiator is requesting a message out
phase.
SRST−
SRST+
B14
D13
SCSI bus reset.
SSEL−
SSEL+
B15
D15
SCSI bus arbitration signal, select.
SCSI phase line, input/output.
LVD:
12 mA
UniLVD
SCSI phase line, message.
1. LVD Mode: The negative and positive halves of LVD link signal pairs are shown for SCSI Control.
SE Mode: The SCSI Control signals are shown. All positive (+) signals are at 0 Volts.
3-12
Signal Descriptions
3.5 General Purpose I/O (GPIO) Signals
Table 3.11 describes the GPIO Signals group.
Table 3.11
GPIO Signals
Name
Bump
Type
Strength
Description
GPIO0_
FETCH/
AB16
I/O
8 mA
General Purpose I/O pin 0. This pin is programmable at
power-up, through the MAD7 pin, to serve as the data
signal for the serial EEPROM interface. When GPIO_0 is
not in the process of downloading EEPROM data it can
be used to drive a SCSI Activity LED, if bit 5 in the
General Purpose Pin Control (GPCNTL) register is set.
Or, it can be used to indicate that the next bus request
will be an opcode fetch if bit 6 in the General Purpose Pin
Control (GPCNTL) register is set, it indicates if the next
bus request is an opcode fetch.
GPIO1_
MASTER/
Y16
I/O
8 mA
General Purpose I/O pin 1. This pin is programmable at
power-up, through the MAD7 pin, to serve as the clock
signal for the serial EEPROM interface. If bit 7 of the
General Purpose Pin Control (GPCNTL) register is set,
this pin drives LOW when the LSI53C1000 is the bus
master.
GPIO2
AA16
I/O
8 mA
General Purpose I/O pin 2. This pin powers up as an
input.
GPIO3
AC17
I/O
8 mA
General Purpose I/O pin 3. This pin powers up as an
input.
GPIO4
AB17
I/O
8 mA
General Purpose I/O pin 4. This pin powers up as an
output. It can be used as the enable line for VPP, the 12 V
power supply to the external flash memory interface.
General Purpose I/O (GPIO) Signals
3-13
3.6 Flash ROM and Memory Interface Signals
Table 3.12 describes the Flash ROM and Memory Interface Signal
groups.
Table 3.12
Flash ROM and Memory Interface Signals
Name
Bump
Type
MWE/
AC19
O
4 mA
Memory Write Enable. This pin is a write enable
signal to an external flash memory.
MCE/
AA18
O
4 mA
Memory Chip Enable. This pin is a chip enable
signal to an external EPROM or flash memory
device.
MOE/_
TESTOUT
Y18
O
4 mA
Memory Output Enable. This pin is an output
enable signal to an external EPROM or flash
memory during read operations. It is also used to
test the connectivity of the LSI53C1000 signals in
the “AND-tree” test mode.
MAS0/
AC18
O
4 mA
Memory Address Strobe 0. This pin latches in the
least significant address byte (bits [7:0]) of an
external EPROM or flash memory. Since the
LSI53C1000 moves addresses eight bits at a time,
this pin connects to the clock of an external bank of
flip-flops that assemble up to a 20-bit address for
the external memory.
MAS1/
AA17
O
4 mA
Memory Address Strobe 1. This pin latches in the
most significant address byte (bits [15:8]) of an
external EPROM or flash memory. Since the
LSI53C1000 moves addresses eight bits at a time,
this pin connects to the clock of an external bank of
flip-flops that assemble up to a 20-bit address for
the external memory.
MAD[7:0]
Y19, AA19,
AC20, AB20,
AA20, AC22,
AB21, AC23
I/O
4 mA
Memory Address/Data Bus. This bus, in
conjunction with the memory address strobe pins
and external address latches, assembles up to a
20-bit address for an external EPROM or flash
memory. This bus first issues the least significant
byte and finishes with the most significant bits. It is
also used to write data to a flash memory or read
data into the chip from external EPROM/flash
memory. These pins have static pull-downs.
3-14
Strength Description
Signal Descriptions
3.7 Test Interface Signals
Table 3.13 describes the Test Interface Signal group. The table is divided
into Internal Test signals and JTAG signals.
Table 3.13
Test Interface Signals
Name
Bump
Type
Strength
Description
Internal Test Signals:
SCAN_MODE
C22
I
N/A
Scan Mode. For LSI Logic test purposes only. This
pin has a static pull-down.
TEST_HSC
C23
I
N/A
Test Halt SCSI Clock. For LSI Logic test purposes
only. Pulled LOW internally. This signal can also
cause a full chip reset.
TEST_PD
A2
I
N/A
Test Power Down. For LSI Logic test purposes
only. This pin has a static pull-down.
TEST_RST/
C1
I
N/A
Test Reset. For LSI Logic test purposes only.
Pulled HIGH internally.
MOE/_
TESTOUT
Y18
O
4 mA
TCK
D1
I
N/A
Test Clock. This pin provides the clock for the
JTAG test logic. This pin has a static pull-up.
TMS
E3
I
N/A
Test Mode Select (TMS). The signal received at
TMS is decoded by the Test Access Port (TAP)
controller to control JTAG test operations. This pin
has a static pull-up.
TDI
E2
I
N/A
Test Data In. This pin receives the serial test
instructions for the JTAG test logic. This pin has a
static pull-up.
TDO
E1
O
4 mA
Test Data Out. This pin is the serial output for test
instructions and data from the JTAG test logic.
Reserved
AB14
N/A
N/A
Memory Output Enable. This pin is used as an
output enable signal to an external EPROM or
flash memory during read operations. It is also
used to test the connectivity of the LSI53C1000
signals in the “AND-tree” test mode.
JTAG Signals:
Test Interface Signals
Reserved. Not Used.
3-15
3.8 Power and Ground Signals
Table 3.14 describes the Power and Ground Signal group.
Table 3.14
Power and Ground Signals
Name1
Bump
VSS_IO
VDD_IO
Type
Strength
C3, C21, D4, D12, D20,
K10–14, L10–14, M4, M10–14,
M20, N10–14, P10–14, Y4,
Y12, Y20, AA3, AA21
G
N/A
Ground for PCI bus
drivers/receivers, SCSI bus
drivers/receivers, local memory
interface drivers, and other I/O
pins.
D7, D10, D14, D17, G4, G20,
K4, K20, P4, P20, U4, U20,
Y7, Y10, Y14, Y17
P
N/A
Power for PCI bus
drivers/receivers, SCSI bus
drivers/receivers, local memory
interface drivers/receivers, and
other I/O pins.
VDD_CORE B22, B23, D3, E4, Y13, AB3,
AB18, AB23, AC1
P
N/A
Power for core logic.
VSS_CORE A22, D2, D21, F3, Y15, AA22,
AB19, AB2, AC2, AC21
G
N/A
Ground for core logic.
VDD_A2
B2, C20
P
N/A
Power for analog cells (clock
quadrupler and DIFFSENS logic).
VSS_A2
B20, C2
G
N/A
Ground for analog cells (clock
quadrupler and DIFFSENS logic).
VDD_Bias
A11, M22
P
N/A
Power for the RBIAS circuit.
RBIAS
M21
I
N/A
Used to connect an external
resistor to generate the bias
current used by LVDlink pads.
Resistor value should be 10.0 kΩ.
Connect the other end of the
resistor to VDD.
3-16
Signal Descriptions
Description
Table 3.14
Power and Ground Signals (Cont.)
Name1
Bump
Type
Strength
Description
NC
A1, A13, A23, AA14, AA15,
AA23, AB15, AB22, AC15,
AC16, B13, B16, B21, D16,
D22, D23, E20, E21, E22, E23,
F2, F20, F21, F22, F23, G3,
G21, G22, G23, H20, H21,
H22, H23, J20, J21, J22, J23,
K21, K22, K23, L20, L21, L22,
L23, M23, N20, N21, N22,
N23, P21, P22, P23, R20,
R21, R22, R23, T20, T21, T22,
T23, U21, U22, U23, V20, V21,
V22, V23, W20, W21, W22,
W23, Y21, Y22, Y23
N/A
N/A
These pins are reserved or have
no internal connection.
1. The I/O driver pad rows and digital core have isolated power supplies as indicated by the “I/O” and
“CORE” extensions on their respective VSS and VDD names. Connect the power and ground pins
directly to the primary power and ground planes of the circuit board. Apply bypass capacitors of
0.01 µF between adjacent VSS and VDD pairs wherever possible. Do not connect bypass capacitors
between VSS and VDD pairs that cross power and ground bus boundaries.
2. To reduce signal noise that can affect Frequency Synthesizer (FSN) functionality, place a ferrite bead
in series with the VDD_A and VSS_A pins. The recommended rating of the bead is 150 Ω at
100 MHz.
3.9 MAD Bus Programming
The MAD[7:0] pins, in addition to serving as the address/data bus for the
local memory interface, also are used to program power-up options for
the chip. A particular option is programmed allowing the internal
pull-down current sink to pull the pin LOW at reset or by connecting a
4.7 kΩ resistor between the appropriate MAD[x] pin and VDD. The
pull-down resistors require that HC or HCT external components are
used for the memory interface. A description of the MAD bus pins
follows:
•
MAD[7], Serial EEPROM programmable option – When pulled
LOW by the internal pull-down current sink, the automatic data
download is enabled. When pulled HIGH by an external resistor, the
automatic data download is disabled. See Section 2.4, “Serial
EEPROM Interface,” and the Subsystem ID (SID) and Subsystem
Vendor ID (SVID) register descriptions.
MAD Bus Programming
3-17
•
MAD[6] – Reserved.
•
MAD[5] – Reserved.
•
MAD[4] – Reserved.
•
MAD[3:1] – These pins set the size of the external expansion ROM
device attached. Table 3.15 provides the encoding for these pins. A
“0” indicates a pull-down resistor is attached while a “1” indicates a
pull-up resistor attached.
Table 3.15
MAD[3:1]
•
Available Memory Space
000
16 Kbytes
001
32 Kbytes
010
64 Kbytes
011
128 Kbytes
100
256 Kbytes
101
512 Kbytes
110
1024 Kbytes
111
no external memory present
MAD[0], slow ROM – When pulled up, this pin enables use of slower
memory devices by including two extra data access cycles.
Note:
3-18
MAD[3:1] Pin Decoding
All MAD pins have internal pull-down resistors.
Signal Descriptions
Chapter 4
Registers
This section contains descriptions of all LSI53C1000 registers. The term
“set” refers to bits programmed to a binary one. Similarly, the term
“cleared” refers to bits programmed to a binary zero. Do not access
reserved bits. Reserved bit functions may change at any time. Unless
otherwise indicated, all bits in the registers are active high; the feature is
enabled by setting the bit. The bottom row of every register diagram
presents the default register values, which are enabled after the chip is
powered on or reset.
This chapter contains the following sections:
•
Section 4.1, “PCI Configuration Registers”
•
Section 4.2, “SCSI Registers”
•
Section 4.3, “SCSI Shadow Registers”
4.1 PCI Configuration Registers
To access the PCI Configuration registers, perform a configuration read
or write to a device with its IDSEL pin asserted. The appropriate address
value is in AD[10:8] during the address phase of the transaction. The
SCSI function is identified by a binary value of 0b000. Table 4.1 shows
the PCI configuration registers implemented in the LSI53C1000.
All PCI-compliant devices, such as the LSI53C1000, support Vendor ID,
Device ID, Command, and Status registers. Support of other
PCI-compliant registers is optional. In the LSI53C1000, registers that are
not supported are not writable and return all zeros when read. Only those
registers and bits that are currently supported by the LSI53C1000 are
described in this chapter. Do not access bits marked as Reserved.
LSI53C1000 PCI to Ultra160 SCSI Controller
4-1
Table 4.1
31
PCI Configuration Register Map
16 15
0 Address Page
Vendor ID
0x00
4-2
Command
0x04
4-3
Class Code (CC)
Revision ID (RID)
0x08
4-6
Reserved
Header Type (HT)
Latency Timer (LT)
Cache Line Size (CLS)
0x0C
4-7
Base Address Register Zero (BAR0) (I/O)
0x10
4-9
Base Address Register One (BAR1) (MEMORY) bits [31:0]
0x14
4-10
Base Address Register Two (BAR2) (MEMORY) bits [31:0]
0x18
4-10
Base Address Register Three (BAR3) (SCRIPTS RAM) bits [31:0]
0x1C
4-11
Base Address Register Four (BAR4) (SCRIPTS RAM)) bits [31:0]
0x20
4-11
Reserved
0x24
4-12
Reserved
0x28
4-12
Subsystem ID (SID)
Subsystem Vendor ID (SVID)
0x2C
4-12
Expansion ROM Base Address (ERBA)
0x30
4-14
Reserved
Capabilities Pointer (CP)
0x34
4-15
Reserved
0x38
4-15
Max_Lat (ML)
Min_Gnt (MG)
Interrupt Pin (IP)
Interrupt Line (IL)
0x3C
4-16
Power Management Capabilities (PMC)
Next Item Pointer (NIP)
Capability ID (CID)
0x40
4-18
Bridge Support ExtenData
Power Management Control/Status (PMCSR)
0x44
4-19
sions (PMCSR_BSE)
Device ID
Status
Registers: 0x00–0x01
Vendor ID
Read Only
15
0
VID
0
0
VID
4-2
Registers
0
1
0
0
0
0
0
0
0
0
0
0
0
0
Vendor ID
[15:0]
This 16-bit register identifies the manufacturer of the
device. The Vendor ID is 0x1000.
Registers: 0x02–0x03
Device ID
Read Only
15
0
DID
0
0
0
0
DID
0
0
0
0
0
0
1
0
0
0
0
1
Device ID
[15:0]
This 16-bit register identifies the particular device. The
LSI53C1000 Device ID is 0x0021.
Registers: 0x04–0x05
Command
Read/Write
15
9
R
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
SE
R
EPER
R
WIE
R
EBM
EMS
EIS
0
0
0
0
0
0
0
0
0
The SCSI Command register provides coarse control over a device’s
ability to generate and respond to PCI cycles. When a zero is written to
this register, the LSI53C1000 is logically disconnected from the PCI bus
for all accesses except configuration accesses.
R
Reserved
SE
SERR/Enable
8
When this bit is set, the LSI53C1000 enables the SERR/
driver. SERR/ is disabled when this bit is cleared. The
default value of this bit is zero. This bit and bit 6 must be
set to report address parity errors.
R
Reserved
EPER
Enable Parity Error Response
6
When this bit is set, the LSI53C1000 detects parity errors
on the PCI bus and reports these errors to the system.
Only data parity checking is affected with this bit. The
LSI53C1000 always generates parity for the PCI bus.
PCI Configuration Registers
[15:9]
7
4-3
4-4
R
Reserved
WIE
Write and Invalidate Enable
4
When this bit is set, the LSI53C1000 can generate write
and invalidate commands on the PCI bus. The WRIE bit
in the Chip Test Three (CTEST3) register must also be
set for the device to generate write and invalidate
commands.
R
Reserved
EBM
Enable Bus Mastering
2
This bit controls the ability of the LSI53C1000 to act as a
master on the PCI bus. A value of zero disables this
device from generating PCI bus master accesses. A
value of one allows the LSI53C1000 to behave as a bus
master. The device must be a bus master to fetch
SCRIPTS instructions and transfer data.
EMS
Enable Memory Space
1
This bit controls the ability of the LSI53C1000 to respond
to Memory space accesses. A value of zero disables the
device response. A value of one allows the LSI53C1000
to respond to Memory Space accesses at the address
range specified by the Base Address Register One
(BAR1) (MEMORY), Base Address Register Two (BAR2)
(MEMORY), Base Address Register Three (BAR3)
(SCRIPTS RAM), and the Base Address Register Four
(BAR4) (SCRIPTS RAM) registers in the PCI
configuration space.
EIS
Enable I/O Space
0
This bit controls the LSI53C1000 response to I/O space
accesses. A value of zero disables the device response.
A value of one allows the LSI53C1000 to respond to I/O
Space accesses at the address range specified by the
Base Address Register Zero (BAR0) (I/O) register in the
PCI configuration space.
Registers
5
3
Registers: 0x06–0x07
Status
Read/Write
15
14
13
12
DPE SSE RMA RTA
0
0
0
0
11
10
9
R
DT[1:0]
0
0
1
8
7
DPR FBBC
0
0
6
R
0
5
4
3
0
66C NC
1
1
R
0
0
0
0
Reads to this register behave normally. Writes are slightly different in that
bits can be cleared, but not set. A bit is cleared whenever the register is
written, and the data in the corresponding bit location is a one. For
example, to clear bit 15 and not affect any other bits, write the value
0x8000 to the register.
DPE
Detected Parity Error (from Slave)
15
This bit is set by the LSI53C1000 upon the detection of
a data parity error, even if data parity error handling is
disabled.
SSE
Signaled System Error
14
This bit is set whenever the device asserts the SERR/
signal.
RMA
Received Master Abort (from Master)
13
A master device should set this bit when its transaction
(except for Special Cycle) is terminated with Master
Abort.
RTA
Received Target Abort (from Master)
A master device should set this bit whenever its
transaction is terminated by Target Abort.
12
R
Reserved
11
DT[1:0]
DEVSEL/ Timing
[10:9]
These bits encode the timing of DEVSEL/. The timings
are encoded as:
0b00
0b01
0b10
0b11
PCI Configuration Registers
fast
medium
slow
reserved
4-5
These bits are read only and indicate the slowest time
that a device asserts DEVSEL/ for any bus command
except Configuration Read and Configuration Write. The
LSI53C1000 only supports medium DEVSEL/ timing.
DPR
Data Parity Error Reported
This bit is set when the following conditions are met:
8
• The bus agent asserts PERR/ itself or observes
PERR/ asserted and;
• The agent setting this bit acted as the bus master for
the errant operation and;
• The Parity Error Response bit in the Command
register is set.
FBBC
Fast Back to Back Capable
This bit is zero.
7
R
Reserved
6
66C
66 MHz Capable
5
When set, this bit indicates that the LSI53C1000 is
capable of 66 MHz PCI operation. This bit is controlled
by the ENABLE66 pin, which has a static pull-up.
NC
New Capabilities
4
This bit is set to indicate a list of extended capabilities
such as PCI Power Management. This bit is read only.
R
Reserved
[3:0]
Register: 0x08
Revision ID (RID)
Read Only
7
0
RID
x
RID
4-6
Registers
x
x
x
x
x
x
x
Revision ID
[7:0]
This register indicates the current revision level of the
device.
Registers: 0x09–0x0B
Class Code (CC)
Read Only
23
0
CC
0
0
0
0
0
0
0
1
0
CC
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Class Code
[23:0]
This 24-bit register identifies the generic function of the
device. The upper byte of this register is a base class
code, the middle byte is a subclass code, and the lower
byte identifies a specific register-level programming
interface. The value of this register is 0x010000, which
identifies a SCSI controller.
Register: 0x0C
Cache Line Size (CLS)
Read/Write
7
0
CLS
0
CLS
0
0
0
0
0
0
0
Cache Line Size
[7:0]
This register specifies the system cache line size in units
of 32-bit words. The value in this register is used by the
device to determine whether to use Write and Invalidate
or Write commands for performing write cycles, and
whether to use Read, Read Line, or Read Multiple
commands for performing read cycles as a bus master.
Devices participating in the caching protocol use this field
to determine when to retry burst accesses at cache line
boundaries. These devices can ignore the PCI cache
support lines (SDONE and SB0/) if this register is set
to 0. If this register is programmed to a number which is
not a power of 2, the device does not use PCI
performance commands to execute data transfers.
PCI Configuration Registers
4-7
Register: 0x0D
Latency Timer (LT)
Read/Write
7
0
LT
0
0
LT
0
0
0
0
0
0
Latency Timer
[7:0]
The Latency Timer register specifies, in units of PCI bus
clocks, the value of the Latency Timer for this PCI bus
master. The LSI53C1000 supports this timer. All eight
bits are writable, allowing latency values of 0–255 PCI
clocks. Use the following equation to calculate an
optimum latency value for the SCSI function.
Latency = 2 + (Burst Size * (typical wait states + 1))
Values greater than optimum are also acceptable.
Register: 0x0E
Header Type (HT)
Read Only
7
0
HT
0
HT
4-8
Registers
0
0
0
0
0
0
0
Header Type
[7:0]
This 8-bit register identifies the layout of bytes 0x10
through 0x3F in configuration space and also whether or
not the device contains multiple functions. Since the
LSI53C1000 is not a multifunction controller, the value of
this register is 0x00.
Register: 0x0F
Reserved
7
0
R
0
0
0
0
0
0
0
0
This register is reserved.
Registers: 0x10–0x13
Base Address Register Zero (BAR0) (I/O)
Read/Write
31
0
BAR0
0
0
0
0
0
0
0
0
0
BAR0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Base Address Register Zero - I/O
[31:0]
This base address register is used to map the operating
register set into I/O space. The LSI53C1000 requires
256 bytes of I/O space for this base address register.
Bit 0 is hardwired to one. Bit 1 is reserved and returns a
zero on all reads. All other bits are used to map the
device into I/O space. For detailed information on the
operation of this register, refer to the PCI 2.2
specification.
PCI Configuration Registers
4-9
Registers: 0x14–0x17
Base Address Register One (BAR1) (MEMORY)
Read/Write
31
0
BAR1
0
0
0
0
0
0
0
0
0
0
0
0
BAR1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
Base Address Register One
[31:0]
This base address register, in conjunction with Base
Address Register Two (BAR2) (MEMORY), maps SCSI
operating registers into memory space and represents
the lower 32 bits of the memory address. Bits [9:0] are
hardwired to 0b0000000100. The default value of this
register is 0x00000004. The LSI53C1000 requires
1024 bytes of memory space. For detailed information on
the operation of this register, refer to the PCI 2.2
specification.
Registers: 0x18–0x1B
Base Address Register Two (BAR2) (MEMORY)
Read/Write
31
0
BAR2
0
0
0
0
0
0
0
0
0
0
BAR2
4-10
Registers
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Base Address Register Two
[31:0]
This base address register, in conjunction with Base
Address Register One (BAR1) (MEMORY), maps SCSI
operating registers into memory space and represents
the upper 32 bits of the memory address. The default
value of this register is 0x00000000. The LSI53C1000
requires 1024 bytes of memory space. For detailed
information on the operation of this register, refer to the
PCI 2.2 specification.
Registers: 0x1C–0x1F
Base Address Register Three (BAR3) (SCRIPTS RAM)
Read/Write
31
0
BAR3
0
0
0
0
0
0
0
0
0
0
0
0
BAR3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
Base Address Register Three
[31:0]
This base address register, in conjunction with Base
Address Register Four (BAR4) (SCRIPTS RAM), is used
to map the SCRIPTS RAM into memory space and
represents the lower 32 bits of the memory address.
Bits [12:0] are hardwired to 0b0000000000100. The
default value of this register is 0x00000004. The
LSI53C1000 requires 8192 bytes of memory space for
SCRIPTS RAM. For detailed information on the operation
of this register, refer to the PCI 2.2 specification.
Registers: 0x20–0x23
Base Address Register Four (BAR4) (SCRIPTS RAM)
Read/Write
31
0
BAR4
0
0
0
0
0
0
0
0
0
BAR4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Base Address Register Four
[31:0]
This base address register, in conjunction with Base
Address Register Three (BAR3) (SCRIPTS RAM), is
used to map the SCRIPTS RAM into memory space and
represents the upper 32 bits of the memory address. The
default value of this register is 0x00000000. The
LSI53C1000 requires 8192 bytes of memory space for
SCRIPTS RAM. For detailed information on the operation
of this register, refer to the PCI 2.2 specification.
PCI Configuration Registers
4-11
Registers: 0x24–0x27
Reserved
31
0
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
This register is reserved.
Registers: 0x28–0x2B
Reserved
31
0
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
This register is reserved.
Registers: 0x2C–0x2D
Subsystem Vendor ID (SVID)
Read Only
15
0
SVID
If MAD7 is HIGH
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
x
x
x
x
x
x
If MAD7 is LOW
x
x
SVID
4-12
Registers
x
x
x
x
x
x
x
x
Subsystem Vendor ID
[15:0]
This 16-bit register is used to uniquely identify the vendor
manufacturing the add-in board or subsystem where this
PCI device resides. It provides a mechanism for an
add-in card vendor to distinguish its cards from another
vendor’s cards, even if the cards have the same PCI
controller installed on them (and therefore the same
Vendor ID and Device ID).
If the external serial EEPROM interface is enabled
(MAD[7] LOW), this register is automatically loaded at
power-up from the external serial EEPROM and contains
the value downloaded from the serial EEPROM or, if the
download fails, a value of 0x0000.
If the external serial EEPROM interface is disabled
(MAD[7] HIGH), this register returns a value of 0x1000.
The 16-bit value that should be stored in the external
serial EEPROM for this register is the vendor’s PCI
Vendor ID. This value must be obtained from the PCI
Special Interest Group (SIG). Please see Section 2.4,
“Serial EEPROM Interface,” for more information on
downloading a value for this register.
Registers: 0x2E–0x2F
Subsystem ID (SID)
Read Only
15
0
SID
If MAD[7] is HIGH
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
x
x
x
x
x
x
If MAD[7] is LOW
x
SID
x
x
x
x
x
x
x
x
x
Subsystem ID
[15:0]
This 16-bit register is used to uniquely identify the add-in
board or subsystem where this PCI device resides. It
provides a mechanism for an add-in card vendor to
distinguish its cards from one another even if the cards
have the same PCI controller installed on them (and
therefore the same Vendor ID and Device ID).
If the external serial EEPROM interface is enabled
(MAD[7] is LOW), this register is automatically loaded at
power-up from the external serial EEPROM and contains
the value downloaded from the serial EEPROM or, if the
download fails, a value of 0x0000.
If the external serial EEPROM is disabled (MAD[7] pulled
HIGH), the register returns a value of 0x1000. The 16-bit
value stored in the external serial EEPROM is
PCI Configuration Registers
4-13
vendor-specific. Please see Section 2.4, “Serial
EEPROM Interface,” for additional information on
downloading a value for this register.
Registers: 0x30–0x33
Expansion ROM Base Address (ERBA)
Read/Write
31
11 10
1
ERBA
0
0
0
0
0
0
0
0
0
0
0
0
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
EREN
0
0
0
0
0
0
This four-byte register handles the base address and size information for
the expansion ROM.
ERBA
Expansion ROM Base Address
[31:11]
Bits [31:11] correspond to the upper 21 bits of the
expansion ROM base address. The host system detects
the size of the external memory by first writing the
Expansion ROM Base Address (ERBA) register with all
ones and then reading back the register. The
LSI53C1000 responds with zeros in all don’t care
locations. The least significant one (1) that remains
represents the binary version of the external memory
size. For example, to indicate an external memory size of
32 Kbytes, this register, when written with ones and read
back, returns ones in the upper 17 bits.
The size of the external memory is set through MAD[3:1].
Please see Section 3.9, “MAD Bus Programming,” for the
possible size encodings available.
R
Reserved
EREN
Expansion ROM Enable
0
The expansion ROM Enable bit, bit 0, is the only bit
defined in this register. This bit is used to control whether
or not the device accepts accesses to its expansion
ROM. When the bit is set, address decoding is enabled,
and a device is used with or without an expansion ROM
depending on the system configuration.
Note:
4-14
Registers
[10:1]
To access the external memory interface, also set the
Memory Space bit in the Command register.
Register: 0x34
Capabilities Pointer (CP)
Read Only
7
0
CP
0
1
CP
0
0
0
0
0
0
Capabilities Pointer
[7:0]
This register indicates that the first extended capability
register is located at offset 0x40 in PCI Configuration
Space.
Registers: 0x35–0x37
Reserved
23
0
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
This register is reserved.
Registers: 0x38–0x3B
Reserved
31
0
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
This register is reserved.
PCI Configuration Registers
4-15
Register: 0x3C
Interrupt Line (IL)
Read/Write
7
0
IL
0
0
IL
0
0
0
0
0
0
Interrupt Line
[7:0]
This register is used to communicate interrupt line routing
information. POST software writes the routing information
into this register as it configures the system. The value in
this register tells which input of the system interrupt
controller(s) the device’s interrupt pin is connected to.
Values in this register are specified by system
architecture.
Register: 0x3D
Interrupt Pin (IP)
Read Only
7
0
IP
SCSI Function
0
IP
0
0
0
0
0
1
Interrupt Pin
[7:0]
This register tells which interrupt pin the device uses. Its
value is set to 0x01 for the SCSI (INTA/) signal.
Note:
4-16
0
Registers
Please see Section 3.9, “MAD Bus Programming,” for
additional information.
Register: 0x3E
Min_Gnt (MG)
Read Only
7
0
MG
0
0
MG
0
1
0
0
0
1
Min_Gnt
[7:0]
This register is used to specify the desired settings for
latency timer values. Min_Gnt is used to specify how long
a burst period the device needs. The value specified in
these registers is in units of 0.25 µs. The LSI53C1000
sets this register to 0x11.
Register: 0x3F
Max_Lat (ML)
Read Only
7
0
ML
0
ML
0
0
1
0
0
1
0
Max_Lat
[7:0]
This register is used to specify the desired settings for
latency timer values. Max_Lat is used to specify how
often the device needs to gain access to the PCI bus.
The value specified in this register is in units of 0.25 µs.
The LSI53C1000 sets this register to 0x12 indicating it
needs the bus every 4.5 µs to maintain a data stream of
160 Mbytes/s.
PCI Configuration Registers
4-17
Register: 0x40
Capability ID (CID)
Read Only
7
0
CID
0
0
CID
0
0
0
0
0
1
Capability ID
[7:0]
This register indicates the type of data structure currently
being used. It is set to 0x01, indicating the Power
Management Data Structure.
Register: 0x41
Next Item Pointer (NIP)
Read Only
7
0
NIP
0
0
NIP
0
0
0
0
0
0
Next Item Pointer
[7:0]
Bits [7:0] contain the offset location of the next item in the
function’s capabilities list. The LSI53C1000 has these bits
set to zero indicating no further extended capabilities
registers exist.
Registers: 0x42–0x43
Power Management Capabilities (PMC)
Read Only
15
11
PMES
0
0
PMES
4-18
Registers
0
10
9
8
D2S D1S
0
0
1
1
6
AUX_C
0
0
0
5
4
3
DSI
R
PMEC
0
0
0
2
0
VER[2:0]
0
1
0
PME_Support
[15:11]
Bits [15:11] define the power management states in
which the LSI53C1000 will assert the PME pin. These
bits are all set to zero because the LSI53C1000 does not
provide a PME signal.
D2S
D2_Support
10
The LSI53C1000 sets this bit to indicate support for
power management state D2. Bits 9 and 10 are set to
one indicating support for the D1 and D2 power states.
D1S
D1_Support
9
The LSI53C1000 sets this bit to indicate support for
power management state D1. Bits 9 and 10 are set to
indicate support for the D1 and D2 power states.
AUX_C
Aux_Current
[8:6]
The LSI53C1000 always returns zeros. This feature is not
supported.
DSI
Device Specific Initialization
5
This bit is cleared to indicate that the LSI53C1000
requires no special initialization before the generic class
device driver is able to use it.
R
Reserved
4
PMEC
PME Clock
Bit 3 is cleared because the LSI53C1000 does not
provide a PME pin.
3
VER[2:0]
Version
[2:0]
These three bits are set to 0b010 to indicate that the
LSI53C1000 complies with Revision 1.1 of the PCI Power
Management Interface Specification.
Registers: 0x44–0x45
Power Management Control/Status (PMCSR)
Read/Write
15
14 13 12
9
PST DSCL
0
PST
0
0
DSLT
0
0
0
8
7
2
PEN
0
0
R
0
0
0
1
0
PWS[1:0]
0
0
0
0
0
PME_Status
15
The LSI53C1000 always returns a zero for this bit,
indicating that PME signal generation is not supported
from D3cold.
PCI Configuration Registers
4-19
DSCL
Data_Scale
[14:13]
The LSI53C1000 does not support the Data register.
Therefore, these two bits are always cleared.
DSLT
Data_Select
[12:9]
The LSI53C1000 does not support the Data register.
Therefore, these four bits are always cleared.
PEN
PME_Enable
The LSI53C1000 always returns zero for this bit to
indicate that PME assertion is disabled.
R
Reserved
PWS[1:0]
Power State
[1:0]
Bits [1:0] are used to determine the current power state
of the LSI53C1000. They are used to place the
LSI53C1000 in a new power state. Power states are
defined as:
8
[7:2]
0b00
D0
0b01
D1
0b10
D2
0b11 D3 hot
See the Section 2.5, “Power Management,” for
descriptions of the Power Management States.
Register: 0x46
Bridge Support Extensions (PMCSR_BSE)
Read Only
7
0
BSE
0
BSE
4-20
Registers
0
0
0
0
0
0
0
Bridge Support Extensions
[7:0]
This register indicates PCI Bridge specific functionality.
The LSI53C1000 always returns 0x00.
Register: 0x47
Data
Read Only
7
0
DATA
0
0
DATA
0
0
0
0
0
0
Data
[7:0]
This register provides an optional mechanism for the
function to report state-dependent operating data. The
LSI53C1000 always returns 0x00.
4.2 SCSI Registers
The control registers for the SCSI core are directly accessible from the
PCI bus using Memory or I/O mapping. The address map of the SCSI
registers is shown in Table 4.2.
The eight, 32-bit, phase mismatch registers contain the byte count and
addressing information required to update the Direct, Indirect, or Table
Indirect BMOV instructions with new byte counts and addresses. The
phase mismatch registers are the Phase Mismatch Jump Address One
(PMJAD1), Phase Mismatch Jump Address Two (PMJAD2), Remaining
Byte Count (RBC), Updated Address (UA), Entry Storage Address
(ESA), Instruction Address (IA), SCSI Byte Count (SBC), and the
Cumulative SCSI Byte Count (CSBC). All the phase mismatch registers
can be read/written using the Load and Store SCRIPTS instructions,
Memory-to-Memory Moves, Read/Write SCRIPTS instructions, or the
CPU with SCRIPTS not running.
Note:
The only registers that the host CPU can access while the
LSI53C1000 is executing SCRIPTS are the Interrupt Status
Zero (ISTAT0), Interrupt Status One (ISTAT1), Mailbox Zero
(MBOX0), and Mailbox One (MBOX1) registers; attempts to
access other registers interfere with the operation of the
chip. However, all operating registers are accessible with
SCRIPTS. All read data is synchronized and stable when
presented to the PCI bus.
Note:
Do not access reserved bits or registers.
SCSI Registers
4-21
Table 4.2
SCSI Register Map
31
SCNTL3
GPREG
SBCL
SSTAT2
16
SCNTL2
SDID
SSID
SSTAT1
MBOX1
CTEST3
MBOX0
CTEST2
CTEST6
DCMD
CTEST5
15
SCNTL1
SXFER
SOCL
SSTAT0
0
SCNTL0
SCID
SFBR
DSTAT
ISTAT1
CTEST1
ISTAT0
CTEST0
CTEST4
DBC
Reserved
DIEN
DMODE
SIEN1
SWIDE
STIME1
STEST1
SIEN0
Reserved
STIME0
STEST0
DSA
TEMP
DNAD
DSP
DSPS
SCRATCH A
DCNTL
SBR
ADDER
SIST1
GPCNTL
RESPID1
STEST3
CSO
CCNTL1
CCNTL3
SIST0
CCNTL2
RESPID0
STEST2
STEST4
CCNTL0
Reserved
SIDL
SODL
SBDL
SCRATCH B
SCRATCH C–SCRATCH R
MMRS
MMWS
SFS
DRS
SBMS
DBMS
DNAD64
AIPCNTL1
AIPCNTL0
Reserved
SCNTL4
PMJAD1
PMJAD2
RBC
UA
ESA
IA
Reserved
SBC
CSBC
CRCCNTL1
CRCCNTL0
CRCPAD
CRCD
Reserved
Reserved
DFBC
Reserved
4-22
Registers
Address
0x00
0x04
0x08
0x0C
0x10
0x14
0x18
0x1C
0x20
0x24
0x28
0x2C
0x30
0x34
0x38
0x3C
0x40
0x44
0x48
0x4C
0x50
0x54
0x58
0x5C
0x60–0x9F
0xA0
0xA4
0xA8
0xAC
0xB0
0xB4
0xB8
0xBC
0xC0
0xC4
0xC8
0xCC
0xD0
0xD4
0xD8
0xDC
0xE0
0xE4
0xE8–0xEF
0xF0
0xF4–0xFF
Page
4-23
4-32
4-36
4-39
4-45
4-46
4-51
4-54
4-55
4-58
4-59
4-60
4-60
4-61
4-61
4-68
4-68
4-76
4-78
4-81
4-87
4-88
4-92
4-94
4-95
4-95
4-96
4-96
4-97
4-97
4-98
4-98
4-99
4-110
4-110
4-111
4-111
4-112
4-113
4-113
4-114
4-115
4-117
4-118
4-118
4-119
Register: 0x00
SCSI Control Zero (SCNTL0)
Read/Write
7
6
ARB[1:0]
1
5
4
3
2
1
0
START
WATN
EPC
CRCOK
AAP
TRG
0
0
0
x
0
0
1
ARB[1:0]
Arbitration Mode Bits 1 and 0
[7:6]
A combination of the ARB bits selects either Simple or
Full arbitration.
ARB1
ARB0
Arbitration Mode
0
0
1
1
0
1
0
1
Simple arbitration
Reserved
Reserved
Full arbitration, selection/reselection
Simple Arbitration
SCSI Registers
1.
The LSI53C1000 waits for a bus free condition to
occur.
2.
It asserts SBSY/ and its SCSI ID, contained in the
SCSI Chip ID (SCID) register, onto the SCSI bus. If
the SSEL/ signal is asserted by another SCSI
device, the LSI53C1000 deasserts SBSY/,
deasserts its ID, and sets the Lost Arbitration bit
(bit 3) in the SCSI Status Zero (SSTAT0) register.
3.
After an arbitration delay, the CPU should read the
SCSI Bus Data Lines (SBDL) register to check if a
higher priority SCSI ID is present. If no higher
priority ID bit is set, and the Lost Arbitration bit is not
set, the LSI53C1000 wins arbitration.
4.
Once the LSI53C1000 wins arbitration, SSEL/ is
asserted using the SCSI Output Control Latch
(SOCL) for a bus clear and a bus settle delay
(1.2 µs). Then, a low level selection is performed.
4-23
Full Arbitration, Selection/Reselection
START
4-24
Registers
1.
The LSI53C1000 waits for a bus free condition.
2.
It asserts SBSY/ and its SCSI ID onto the SCSI bus.
The SCSI ID asserted is the highest priority ID
stored in the SCSI Chip ID (SCID) register.
3.
If the SSEL/ signal is asserted by another SCSI
device or if the LSI53C1000 detects a higher priority
ID, the LSI53C1000 deasserts SBSY/, deasserts its
ID, sets the Lost Arbitration bit, bit 3 in the SCSI
Status Zero (SSTAT0) register, and waits until the
next bus free state to try arbitration again.
4.
The LSI53C1000 repeats arbitration until it wins
control of the SCSI bus. When it wins, the Won
Arbitration bit is set in the SCSI Status Zero
(SSTAT0) register, bit 2.
5.
The LSI53C1000 performs selection by asserting
SSEL/, the target’s ID (stored in the SCSI
Destination ID (SDID) register), and the
LSI53C1000’s ID (stored in the SCSI Chip ID (SCID)
register) onto the SCSI bus.
6.
After a selection is complete, the Function Complete
bit is set in the SCSI Interrupt Status Zero (SIST0)
register, bit 6.
7.
If a selection time-out occurs, the Selection
Time-Out bit is set in the SCSI Interrupt Status One
(SIST1) register, bit 2.
Start Sequence
5
When this bit is set, the LSI53C1000 starts the arbitration
sequence indicated by the Arbitration Mode bits. The
Start Sequence bit is accessed directly in low-level mode;
during SCSI SCRIPTS operations, this bit is controlled by
the SCRIPTS processor. Do not start an arbitration
sequence if the connected (CON) bit in the SCSI Control
One (SCNTL1) register, bit 4, is set. This bit indicates
that the LSI53C1000 is already connected to the SCSI
bus. This bit is automatically cleared when the arbitration
sequence is complete. If a sequence is aborted, check
bit 4 in the SCNTL1 register to verify that the
LSI53C1000 is not connected to the SCSI bus.
WATN
Select with SATN/ on a Start Sequence
4
When this bit is set and the LSI53C1000 is in the initiator
mode, the SATN/ signal is asserted during selection of a
SCSI target device. This is to inform the target that the
LSI53C1000 has a message to send. If a selection
time-out occurs while attempting to select a target device,
SATN/ is deasserted at the same time SSEL/ is
deasserted. When this bit is cleared, the SATN/ signal is
not asserted during selection. When executing SCSI
SCRIPTS, this bit is controlled by the SCRIPTS
processor, but manual setting is possible in the low level
mode.
EPC
Enable Parity/CRC/AIP Checking
3
When this bit is set and the SCSI transfers are
asynchronous or ST synchronous, the SCSI data bus is
checked for odd parity when data is received from the
SCSI bus in either the initiator or the target mode. If a
parity error is detected, bit 0 of the SCSI Interrupt Status
Zero (SIST0) register is set and an interrupt may be
generated.
When SCSI transfers are DT synchronous, the CRC is
checked when the target requests a CRC transfer using
the DP0 signal on the SCSI bus. If a CRC error is
detected, bit 0 of the SCSI Interrupt Status Zero (SIST0)
register is set and an interrupt may be generated.
If the LSI53C1000 SCSI function is operating in the
initiator mode and a parity error or CRC error is detected,
SATN/ can optionally be asserted, but the transfer
continues until the target changes phase or the block
move in which the parity error was detected completes.
When this bit is clear, parity errors are not reported. CRC
errors are reported in bit 0 of the SCSI Interrupt Status
Zero (SIST0). To disable CRC checking and reporting,
set bit 7, Disable CRC Checking, of CRC Control Zero
(CRCCNTL0).
SCSI Registers
4-25
CRCOK
CRC Request OK
2
This bit indicates it is acceptable to force a CRC request.
This bit is set only if a CRC request has been sent and
no data has been transferred since the request. This bit
can be used to determine if it is necessary to send a
CRC request at the end of a data transfer, prior to
changing phases in target mode. This bit may be used to
prevent back-to-back CRC conditions. Back-to-back CRC
requests are illegal.
AAP
Assert SATN/ on Parity/CRC/AIP Error
1
When this bit is set, the LSI53C1000 automatically
asserts the SATN/ signal upon detection of a parity error
or CRC error. SATN/ is only asserted in the initiator
mode. The SATN/ signal is asserted before deasserting
SACK/ during the byte transfer with the parity error. Also
set the Enable Parity/CRC/AIP Checking bit for the
LSI53C1000 to assert SATN/ in this manner. A parity
error or CRC error is detected on data received from the
SCSI bus.
If the Assert SATN/ on Parity/CRC/AIP Error bit is cleared
or the Enable Parity/CRC/AIP Checking bit is cleared,
SATN/ is not automatically asserted on the SCSI bus
when a Parity/CRC/AIP error is received.
TRG
Caution:
4-26
Registers
Target Mode
0
This bit determines the default operating mode of the
LSI53C1000. The user must manually set the target or
initiator mode. This is done using the SCRIPTS language
(SET TARGET or CLEAR TARGET). When this bit is set, the
chip is a target device. When this bit is cleared, the
LSI53C1000 is an initiator device.
Writing this bit while not connected may cause the loss of
a selection or reselection due to the changing of target or
initiator modes.
Register: 0x01
SCSI Control One (SCNTL1)
Read/Write
7
6
5
4
3
2
1
0
R
ADB
DHP
CON
RST
AESP
IARB
R
0
0
0
0
0
0
0
0
R
Reserved
7
ADB
Assert SCSI Data Bus
6
When this bit is set, the LSI53C1000 drives the contents
of the SCSI Output Data Latch (SODL) register onto the
SCSI data bus. When the LSI53C1000 is an initiator, the
SCSI I/O signal must be inactive to assert the SODL
contents onto the SCSI bus. When the LSI53C1000 is a
target, the SCSI I/O signal must be active to assert the
SODL contents onto the SCSI bus. The contents of the
SODL register can be asserted at any time, even before
the LSI53C1000 is connected to the SCSI bus. Clear this
bit when executing SCSI SCRIPTS. It is normally used
only for diagnostics testing or operation in low level mode.
DHP
Disable Halt on Parity/CRC/AIP Error or ATN
(Target Only)
5
The DHP bit is only defined for the target mode. When
this bit is cleared, the LSI53C1000 halts the SCSI data
transfer when a Parity/CRC/AIP error is detected or when
the SATN/ signal is asserted. If SATN/ or a
Parity/CRC/AIP error is received in the middle of a data
transfer, the LSI53C1000 may transfer up to three
additional bytes before halting to synchronize between
internal core cells. During synchronous operation, the
LSI53C1000 transfers data until there are no outstanding
synchronous offsets. If the LSI53C1000 is receiving data,
any data residing in the DMA FIFO is sent to memory
before halting.
When this bit is set, the LSI53C1000 does not halt the
SCSI transfer when SATN/ or a Parity/CRC/AIP error is
received.
SCSI Registers
4-27
CON
Connected
4
This bit is automatically set any time the LSI53C1000 is
connected to the SCSI bus as an initiator or as a target.
It is set after the LSI53C1000 successfully completes
arbitration or when it has responded to a bus-initiated
selection or reselection. This bit is also set after the chip
wins simple arbitration when operating in low level mode.
When this bit is cleared, the LSI53C1000 is not
connected to the SCSI bus.
The CPU can force a connected or disconnected
condition by setting or clearing this bit.
RST
Assert SCSI RST/ Signal
Setting this bit asserts the SRST/ signal. The SRST/
output remains asserted until this bit is cleared. The
25 µs minimum assertion time defined in the SCSI
specification must be timed out by the controlling
microprocessor or a SCRIPTS loop.
3
AESP
Assert Even SCSI Parity (force bad parity)
2
When this bit is set, the LSI53C1000 asserts even parity.
It forces a SCSI parity error on each byte sent to the
SCSI bus from the chip. If parity checking is enabled,
then the LSI53C1000 checks data received for odd parity.
This bit is used for diagnostic testing and is cleared for
normal operation.
IARB
Immediate Arbitration
1
Setting this bit causes the SCSI core to immediately
begin arbitration once a Bus Free phase is detected
following an expected SCSI disconnect. This bit is useful
for multithreaded applications. The ARB[1:0] bits in SCSI
Control Zero (SCNTL0) are set for full arbitration and
selection before setting this bit.
Arbitration is retried until won. At that point, the
LSI53C1000 holds SBSY and SSEL asserted, and waits
for a select or reselect sequence. The Immediate
Arbitration bit is cleared automatically when the selection
or reselection sequence is completed or times out.
4-28
Registers
An unexpected disconnect condition clears IARB with it
attempting arbitration. See the SCSI Disconnect
Unexpected bit (SCSI Control Two (SCNTL2), bit 7) for
more information on expected versus unexpected
disconnects.
It is possible to abort an immediate arbitration sequence.
First, set the Abort bit in the Interrupt Status Zero
(ISTAT0) register. Then one of two things eventually
happens:
• The Won Arbitration bit (SCSI Status Zero (SSTAT0),
bit 2) will be set. In this case, the Immediate
Arbitration bit needs to be cleared. This completes the
abort sequence and disconnects the chip from the
SCSI bus. If it is not acceptable to go to the Bus Free
phase immediately following the arbitration phase, it is
possible to perform a low level selection instead.
• The abort completes because the LSI53C1000 loses
arbitration. This is detected by the clearing of the
Immediate Arbitration bit. Do not use the Lost
Arbitration bit (SCSI Status Zero (SSTAT0),
bit 3) to detect this condition. In this case take no
further action.
R
Reserved
0
Register: 0x02
SCSI Control Two (SCNTL2)
Read/Write
7
6
SDU
CHM
0
0
SDU
SCSI Registers
5
4
R
0
0
3
2
1
0
WSS
VUE0
VUE1
WSR
0
0
0
0
SCSI Disconnect Unexpected
7
This bit is valid in the initiator mode only. When this bit is
set, the SCSI core is not expecting the SCSI bus to enter
the Bus Free phase. If it does, an unexpected disconnect
error is generated (see the Unexpected Disconnect bit in
the SCSI Interrupt Status Zero (SIST0) register, bit 2).
During normal SCRIPTS mode operation, this bit is set
automatically whenever the SCSI core is reselected, or
successfully selects another SCSI device. The SDU bit
4-29
should be cleared with a register write (Move 0x00 To
SCSI Control Two (SCNTL2)) before the SCSI core
expects a disconnect to occur, normally prior to sending
an Abort, Abort Tag, Bus Device Reset, Clear Queue or
Release Recovery message, or before deasserting
SACK/ after receiving a Disconnect command or
Command Complete message.
4-30
CHM
Chained Mode
6
This bit determines whether or not the SCSI core is
programmed for chained SCSI mode. This bit is
automatically set by the Chained Block Move (CHMOV)
SCRIPTS instruction and is automatically cleared by the
Block Move SCRIPTS instruction (MOVE). For more
information, refer to Section 2.2.18, “Chained Block
Moves.”
R
Reserved
WSS
Wide SCSI Send
3
When read, this bit returns the value of the Wide SCSI
Send (WSS) flag. Asserting this bit clears the WSS flag.
This clearing function is self-clearing. For more
information refer to Section 2.2.18, “Chained Block
Moves.”
VUE0
Vendor Unique Enhancements, Bit 0
2
This bit is a read only value indicating whether the group
code field in the SCSI instruction is standard or vendor
unique. If cleared, the bit indicates standard group codes;
if set, the bit indicates vendor unique group codes. The
value in this bit is reloaded at the beginning of all
asynchronous target receives.
VUE1
Vendor Unique Enhancement, Bit 1
1
This bit is used to disable the automatic byte count reload
during Block Move instructions in the Command phase. If
this bit is cleared, the device reloads the Block Move byte
count if the first byte received is one of the standard
group codes. If this bit is set, the device does not reload
the Block Move byte count, regardless of the group code.
Registers
[5:4]
WSR
Wide SCSI Receive
0
When read, this bit returns the value of the Wide SCSI
Receive (WSR) flag. Setting this bit clears the WSR flag.
This bit is self-clearing.
For more information refer to Section 2.2.18, “Chained
Block Moves.”
Register: 0x03
SCSI Control Three (SCNTL3)
Read/Write
7
6
R
0
4
3
SCF[2:0]
0
0
2
EWS
0
0
R
0
0
0
0
This register is automatically loaded when a Table Indirect Select or
Reselect SCRIPTS instruction is executed.
R
Reserved
SCF[2:0]
Synchronous Clock Conversion Factor
[6:4]
These bits select a factor by which the frequency of
SCLK is divided before being presented to the
synchronous SCSI control logic. The synchronous
transfer speed is determined by the combination of the
divided clock and the setting of the XCLKS and XCLKH
bits in the SCSI Control Four (SCNTL4) register. The
table below shows the clock dividers that are available.
See the table in the SCSI Control Four (SCNTL4) register
description for a full list of available transfer rates.
SCSI Registers
7
SCF2
SCF1
SCF0
Factor
Frequency
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
SCLK/3
SCLK/1
SCLK/1.5
SCLK/2
SCLK/3
SCLK/4
SCLK/6
SCLK/8
4-31
EWS
Enable Wide SCSI
3
When this bit is cleared, all information transfer phases
are assumed to be eight bits, transmitted on SD[7:0]/ and
SDP0/. When this bit is asserted, data transfers are
performed 16 bits at a time; the least significant byte is
on SD[7:0]/ and SDP0/, and the most significant byte is
on SD[15:8]/ and SDP1/. Command, Status, and
Message phases are not affected by this bit. Because
Ultra160 DT SCSI transfers are always wide, this bit must
be set. If it is not set, a SGE interrupt will occur.
R
Reserved
[2:0]
Register: 0x04
SCSI Chip ID (SCID)
Read/Write
4-32
7
6
5
4
R
RRE
SRE
R
x
0
0
x
3
0
ENC[3:0]
0
0
0
0
R
Reserved
RRE
Enable Response to Reselection
6
When this bit is set, the LSI53C1000 is enabled to
respond to bus-initiated reselection at the chip ID in the
Response ID Zero (RESPID0) and Response ID One
(RESPID1) registers. Note that the chip does not
automatically reconfigure itself to the initiator mode as a
result of being reselected.
SRE
Enable Response to Selection
5
When this bit is set, the LSI53C1000 is able to respond
to bus-initiated selection at the chip ID in the Response
ID Zero (RESPID0) and Response ID One (RESPID1)
registers. Note that the chip does not automatically
reconfigure itself to target mode as a result of being
selected.
R
Reserved
ENC[3:0]
Encoded Chip SCSI ID
[3:0]
These bits are used to store the LSI53C1000 encoded
SCSI ID. This is the ID which the chip asserts when
Registers
7
4
arbitrating for the SCSI bus. The IDs that the LSI53C1000
responds to when selected or reselected are configured
in the Response ID Zero (RESPID0) and Response ID
One (RESPID1) registers. The priority of the 16 possible
IDs, in descending order is:
Highest
7
6
5
4
3
Lowest
2
1
0 15 14 13 12 11 10 9
8
Register: 0x05
SCSI Transfer (SXFER)
Read/Write
7
6
5
0
R
0
MO[5:0]
0
0
0
0
0
0
0
This register is automatically loaded when a Table Indirect Select or
Reselect SCRIPTS instruction is executed.
R
Reserved
[7:6]
MO[5:0]
Max SCSI Synchronous Offset
[5:0]
These bits describe the maximum SCSI synchronous
offset used by the LSI53C1000 when transferring
synchronous SCSI data in either the initiator or target
mode. Table 4.3 describes the possible combinations and
their relationship to the synchronous data offset used by
the LSI53C1000. These bits determine the LSI53C1000
method of transfer for ST/DT Data-In and ST/DT
Data-Out phases only; all other information transfers
occur asynchronously. Please note that the SCSI offset
for Ultra160 transfers is counted as the maximum number
of data transfers allowed to be outstanding, not the
maximum REQ pulses allowed to be outstanding.
During ST Data-In or ST Data-Out transfers the
maximum supported offset is 31 (MO[5:0] = 0x1F).
During DT Data-In or DT Data-Out transfers the
maximum supported offset is 62 (MO[5:0] = 0x3E).
Setting offset values outside the allowable range will
result in data corruption.
SCSI Registers
4-33
A value of 0 in these bits program the device to perform
asynchronous transfers. A value of 1 during DT transfers
is illegal and will result in data corruption.
Table 4.3
MO5
0
0
0
0
...
...
...
1
1
1
1
1
1
1
Maximum Synchronous Offset
MO4
0
0
0
0
...
...
...
1
1
1
1
1
1
1
MO3
0
0
0
0
...
...
...
1
1
1
1
1
1
1
MO2
0
0
0
0
...
...
...
0
0
0
1
1
1
1
MO1
0
0
1
1
...
...
...
0
1
1
0
0
1
1
MO0
0
1
0
1
...
...
...
1
0
1
0
1
0
1
Synchronous Offset
0-Asynchronous
Reserved
2
3
...
...
...
57
58
59
60
61
62
Reserved
Register: 0x06
SCSI Destination ID (SDID)
Read/Write
7
4
3
x
0
0
R
x
ENC
x
x
0
0
R
Reserved
[7:4]
ENC
Encoded Destination SCSI ID
[3:0]
Writing these bits sets the SCSI ID of the intended
initiator or target during SCSI reselection or selection
phases, respectively. When executing SCRIPTS, the
SCRIPTS processor writes the destination SCSI ID to
this register. The SCSI ID is defined by the user in a
SCRIPTS Select or Reselect instruction. The value
written is the binary-encoded ID. The priority of the
16 possible IDs, in descending order, is:
Highest
7
4-34
0
Registers
6
5
4
3
Lowest
2
1
0 15 14 13 12 11 10 9
8
Register: 0x07
General Purpose (GPREG)
Read/Write
7
5
4
0
R
x
x
GPIO
x
0
x
x
x
x
A write to this register will cause the data written to be output to the
appropriate GPIO pin if it is set to output mode in the General Purpose
Pin Control (GPCNTL) register.
R
Reserved
[7:5]
GPIO
General Purpose I/O
[4:0]
These bits are programmed through the General Purpose
Pin Control (GPCNTL) register as inputs, outputs, or to
perform special functions. As an output, these pins can
be used to enable or disable external terminators. It is
also possible to program these signals as live inputs and
sense them through a SCRIPTS register to register Move
Instruction. GPIO[3:0] default as inputs and GPIO4
defaults as an output pin. When configured as inputs, an
internal pull-up is enabled.
LSI Logic software uses the GPIO[1:0] signals to access
serial EEPROM. GPIO1 is used as a clock, with the
GPIO0 pin serving as data.
LSI Logic software also reserves the use of GPIO[4:2]. If
there is a need to use GPIO[4:2], please check with
LSI Logic for additional information.
SCSI Registers
4-35
Register: 0x08
SCSI First Byte Received (SFBR)
Read/Write
7
0
SFBR
0
SFBR
0
0
0
0
0
0
0
SCSI First Byte Received
[7:0]
This register contains the first byte received in any
asynchronous information transfer phase. For example,
when a LSI53C1000 is operating in the initiator mode,
this register contains the first byte received in the
Message-In, Status, and Data-In phases.
When a Block Move instruction is executed for a
particular phase, the first byte received is stored in this
register, even if the present phase is the same as the last
phase. The first byte received value for a particular input
phase is not valid until after a MOVE instruction is
executed.
This register is also the accumulator for register
read-modify-writes with the SCSI First Byte Received
(SFBR) as the destination. This allows bit testing after an
operation.
The SCSI First Byte Received (SFBR) is not writable
using the CPU, and therefore not by a Memory Move.
However, it can be loaded using SCRIPTS Read/Write
operations. To load the SFBR with a byte stored in
system memory, the byte must first be moved to an
intermediate LSI53C1000 register (such as the
SCRATCH register), and then to the SFBR.
This register also contains the state of the lower eight bits
of the SCSI data bus during the Selection phase if the
COM bit in the DMA Control (DCNTL) register is clear.
If the COM bit is cleared, do not access this register
using SCRIPTS operations, as indeterminate operations
may occur. (This includes SCRIPTS Read/Write
operations and conditional transfer control instructions
that initialize the SCSI First Byte Received (SFBR)
register.)
4-36
Registers
Register: 0x09
SCSI Output Control Latch (SOCL)
Read/Write
7
6
5
4
3
2
1
0
REQ
ACK
BSY
SEL
ATN
MSG
C_D
I_O
0
0
0
0
0
0
0
0
This register is used primarily for diagnostic testing or programmed I/O
operation. It is controlled by the SCRIPTS processor when executing
SCSI SCRIPTS. SCSI Output Control Latch (SOCL) is used only when
transferring data using programmed I/O. Some bits are set or cleared
when executing SCSI SCRIPTS. Do not write to the register once the
LSI53C1000 starts executing normal SCSI SCRIPTS.
REQ
Assert SCSI REQ/ Signal
7
ACK
Assert SCSI ACK/ Signal
6
BSY
Assert SCSI BSY/ Signal
5
SEL
Assert SCSI SEL/ Signal
4
ATN
Assert SCSI ATN/ Signal
3
MSG
Assert SCSI MSG/ Signal
2
C_D
Assert SCSI C_D/ Signal
1
I_O
Assert SCSI I_O/ Signal
0
SCSI Registers
4-37
Register: 0x0A
SCSI Selector ID (SSID)
Read Only
7
6
4
VAL
0
3
0
R
x
x
ENID
x
0
0
0
0
VAL
SCSI Valid
7
If VAL is asserted, then the two SCSI IDs are detected
on the bus during a bus-initiated selection or reselection,
and the encoded destination SCSI ID bits below are valid.
If VAL is deasserted, only one ID is present and the
contents of the encoded destination ID are meaningless.
R
Reserved
ENID
Encoded Destination SCSI ID
[3:0]
Reading the SSID register immediately after the
LSI53C1000 is selected or reselected returns the
binary-encoded SCSI ID of the device that performed the
operation. These bits are invalid for targets that are
selected under the single initiator option of the SCSI-1
specification. This condition is detected by examining the
VAL bit above.
[6:4]
Register: 0x0B
SCSI Bus Control Lines (SBCL)
Read Only
7
6
5
4
3
2
1
0
REQ
ACK
BSY
SEL
ATN
MSG
C_D
I_O
x
x
x
x
x
x
x
x
This register returns the SCSI control line status. A bit is set when the
corresponding SCSI control line is asserted. These bits are not latched;
they are a true representation of what is on the SCSI bus at the time the
register is read. The resulting read data is synchronized before being
presented to the PCI bus to prevent parity errors from being passed to
the system. This register is only used for diagnostics testing or operation
in the low level mode.
4-38
Registers
REQ
Assert SCSI REQ/ Signal
7
ACK
Assert SCSI ACK/ Signal
6
BSY
Assert SCSI BSY/ Signal
5
SEL
Assert SCSI SEL/ Signal
4
ATN
Assert SCSI ATN/ Signal
3
MSG
Assert SCSI MSG/ Signal
2
C_D
Assert SCSI C_D/ Signal
1
I_O
Assert SCSI I_O/ Signal
0
Register: 0x0C
DMA Status (DSTAT)
Read Only
7
6
5
4
3
2
1
0
DFE
MDPE
BF
ABRT
SSI
SIR
R
IID
1
0
0
0
0
0
x
0
Reading this register clears any bits that are set at the time the register
is read, but does not necessarily clear the register in case additional
interrupts are pending (the LSI53C1000 stacks interrupts). The DIP bit in
the Interrupt Status Zero (ISTAT0) register is also cleared. It is possible
to mask DMA interrupt conditions individually through the DMA Interrupt
Enable (DIEN) register.
When performing consecutive 8-bit reads of the DMA Status (DSTAT),
SCSI Interrupt Status Zero (SIST0) and SCSI Interrupt Status One
(SIST1) registers (in any order), insert a delay equivalent to 12 clock
periods between the reads to ensure that the interrupts clear properly.
See Chapter 2, “Functional Description,” for more information on
interrupts.
DFE
SCSI Registers
DMA FIFO Empty
7
This status bit is set when the DMA FIFO is empty. It is
possible to use it to determine if any data resides in the
FIFO when an error occurs and an interrupt is generated.
This bit is a pure status bit and does not cause an
interrupt.
4-39
MDPE
Master Data Parity Error
6
This bit is set when the LSI53C1000, acting as a PCI
master, detects a data parity error, or, when acting as a
target device, signals a parity error during a data phase.
This bit is completely disabled by the Master Parity Error
Enable bit (bit 3 of Chip Test Four (CTEST4)).
BF
Bus Fault
5
This bit is set when a PCI bus fault condition is detected.
A PCI bus fault can only occur when the LSI53C1000 is
bus master, and is defined as a cycle that ends with a
Bad Address or Target Abort Condition.
ABRT
Aborted
4
This bit is set when an abort condition occurs. An abort
condition occurs when a software abort command is
issued by setting bit 7 of the Interrupt Status Zero
(ISTAT0) register.
SSI
Single Step Interrupt
3
If the Single-Step Mode bit in the DMA Control (DCNTL)
register is set, this bit is set and an interrupt generated
after successful execution of each SCRIPTS instruction.
SIR
SCRIPTS Interrupt Instruction Received
2
This status bit is set whenever an interrupt instruction is
evaluated as true.
R
Reserved
IID
Illegal Instruction Detected
0
This status bit is set any time an illegal or reserved
instruction opcode is detected, whether the LSI53C1000
is operating in single-step mode or automatically
executing SCSI SCRIPTS.
1
Any of the following conditions during instruction
execution also sets this bit:
• The LSI53C1000 is executing a Wait Disconnect
instruction and the SCSI REQ line is asserted without
a disconnect occurring.
• A Block Move instruction is executed as an initiator
with 0x000000 loaded into the DMA Byte Counter
(DBC) register, indicating there are zero bytes to
move.
4-40
Registers
• During a Transfer Control instruction, the Compare
Data (bit 18) and Compare Phase (bit 17) bits are set
in the DMA Byte Counter (DBC) register while the
LSI53C1000 is in target mode.
• During a Transfer Control instruction, the Carry Test
bit (bit 21) is set and either the Compare Data (bit 18)
or Compare Phase (bit 17) bit is set.
• A Transfer Control instruction is executed with the
Wait for Valid phase bit (bit 16) set while the chip is in
the target mode.
• A Load and Store instruction is issued with the
memory address mapped to the operating registers of
the chip, not including ROM or RAM.
• A Load and Store instruction is issued when the
register address is not aligned with the memory
address.
• A Load and Store instruction is issued with bit 5 in the
DMA Command (DCMD) register cleared or bits 3 or
2 set.
• A Load and Store instruction is issued when the count
value in the DMA Byte Counter (DBC) register is not
set at 1, 2, 3, or 4.
• A Load and Store instruction attempts to cross a
Dword boundary.
• A Memory Move instruction is executed with one of
the reserved bits in the DMA Command (DCMD)
register set.
• A Memory Move instruction is executed with the
source and destination addresses not aligned.
• A 64-bit Table Indirect Block Move instruction is
executed with a selector index value greater than
0x16.
• If the Select with ATN/ bit, bit 24, is set for any I/O
instruction other than a Select instruction.
SCSI Registers
4-41
Register: 0x0D
SCSI Status Zero (SSTAT0)
Read Only
4-42
7
6
5
4
3
2
1
0
ILF
R
OLF
ARBIP
LOA
WOA
RST
SDP0
0
0
0
0
0
0
0
0
ILF
SIDL Least Significant Byte Full
7
This bit is set when the least significant byte in the SCSI
Input Data Latch (SIDL) contains data. Data is transferred
from the SCSI bus to the SCSI Input Data Latch register
before being sent to the DMA FIFO and then to the host
bus. The SCSI Input Data Latch (SIDL) register contains
SCSI data received asynchronously. Synchronous data
received does not flow through this register.
R
Reserved
OLF
SODL Least Significant Byte Full
5
This bit is set when the least significant byte in the SCSI
Output Data Latch (SODL) contains data. The SODL
register is the interface between the DMA logic and the
SCSI bus for asynchronous send operations. In the
asynchronous mode, data is transferred from the host
bus to the SODL register, and then to the SCSI bus. It is
possible to use this bit to determine how many bytes
reside in the device when an error occurs.
ARBIP
Arbitration in Progress
4
Arbitration in Progress (ARBIP = 1) indicates that the
LSI53C1000 has detected a Bus Free condition, asserted
SBSY, and asserted its SCSI ID onto the SCSI bus.
LOA
Lost Arbitration
3
When set, LOA indicates that the LSI53C1000 has
detected a bus free condition, arbitrated for the SCSI bus,
and lost arbitration due to another SCSI device asserting
the SSEL/ signal.
Registers
6
WOA
Won Arbitration
2
When set, WOA indicates that the LSI53C1000 has
detected a Bus Free condition, arbitrated for the SCSI
bus and won arbitration. The arbitration mode selected in
the SCSI Control Zero (SCNTL0) register must be full
arbitration and selection to set this bit.
RST
SCSI RST/ Signal
1
This bit reports the current status of the SCSI RST/
signal, and the RST signal (bit 3) in the SCSI Control
One (SCNTL1) register. This bit is not latched and may
change as it is read.
SDP0
SCSI SDP0 Parity Signal
0
This bit represents the present state of the SCSI SDP0/
parity signal. This signal is not latched and may change
as it is read.
Register: 0x0E
SCSI Status One (SSTAT1)
Read Only
7
4
R
0
0
0
0
3
2
1
0
SDP0L
MSG
C_D
I_O
x
x
x
x
R
Reserved
SDP0L
Latched SCSI Parity
3
This bit reflects the SCSI parity signal (SDP0/) that
corresponds to the data latched in the SCSI Input Data
Latch (SIDL). It changes when a new byte is latched into
the least significant byte of the SIDL register. This bit is
active HIGH, in other words, it is set when the parity
signal is active.
MSG
SCSI MSG/ Signal
2
This SCSI phase status bit is latched on the asserting
edge of SREQ/ when operating in either the initiator or
target mode. This bit is set when the corresponding
signal is active. This bit is useful when operating in the
low-level mode.
SCSI Registers
[7:4]
4-43
C_D
SCSI C_D/ Signal
1
This SCSI phase status bit is latched on the asserting
edge of SREQ/ when operating in either the initiator or
target mode. This bit is set when the corresponding
signal is active. This bit is useful when operating in the
low-level mode.
I_O
SCSI I_O/ Signal
0
This SCSI phase status bit is latched on the asserting
edge of SREQ/ when operating in either the initiator or
target mode. This bit is set when the corresponding
signal is active. This bit is useful when operating in the
low-level mode.
Register:
0x0F
SCSI Status Two (SSTAT2)
Read Only
4-44
7
6
5
4
3
2
1
0
ILF1
R
OLF1
R
SPL1
R
LDSC
SDP1
0
0
0
0
x
0
1
x
ILF1
SIDL Most Significant Byte Full
7
This bit is set when the most significant byte in the SCSI
Input Data Latch (SIDL) contains data. Data is transferred
from the SCSI bus to the SCSI Input Data Latch register
before being sent to the DMA FIFO. The data is then sent
to the host bus. The SIDL register contains SCSI data
received asynchronously. Synchronous data received
does not flow through this register.
R
Reserved
OLF1
SODL Most Significant Byte Full
5
This bit is set when the most significant byte in the SCSI
Output Data Latch (SODL) contains data. The SODL
register is the interface between the DMA logic and the
SCSI bus for asynchronous send operations. In the
asynchronous mode, data is transferred from the host
bus to the SCSI Output Data Latch (SODL) register, and
then to the SCSI bus. This bit can be used to determine
how many bytes reside in the device when an error
occurs.
Registers
6
R
Reserved
4
SPL1
Latched SCSI parity for SD[15:8]
3
This active HIGH bit reflects the SCSI odd parity signal
corresponding to the data latched into the most
significant byte in the SCSI Input Data Latch (SIDL)
register.
R
Reserved
LDSC
Last Disconnect
1
This bit is used in conjunction with the Connected (CON)
bit in SCSI Control One (SCNTL1). It allows the user to
detect the case in which a target device disconnects, and
then a SCSI device selects or reselects the LSI53C1000.
If the Connected bit and the LDSC bit are asserted, a
disconnect is indicated. This bit is set when the
Connected bit in SCNTL1 is off. This bit is cleared when
a Block Move instruction is executed while the Connected
bit in SCNTL1 is set.
SDP1
SCSI SDP1 Parity Signal
0
This bit represents the present state of the SCSI SDP1/
parity signal. It is not latched and may change as it is
read.
2
Registers: 0x10–0x13
Data Structure Address (DSA)
Read/Write
31
0
DSA
0
0
0
0
0
0
0
0
0
0
0
0
DSA
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Data Structure Address
[31:0]
This 32-bit register contains the base address used for all
Table Indirect calculations. The DSA register is usually
loaded prior to starting an I/O, but it is possible for a
SCRIPTS Memory Move to load the DSA during the I/O.
During any Memory-to-Memory Move operation, the
contents of this register are preserved. The power-up
value of this register is indeterminate.
SCSI Registers
4-45
Register: 0x14
Interrupt Status Zero (ISTAT0)
Read/Write
7
6
5
4
3
2
1
0
ABRT
SRST
SIGP
SEM
CON
INTF
SIP
DIP
0
0
0
0
0
0
0
0
This is the only register that is accessible by the host CPU while a
LSI53C1000 is executing SCRIPTS (without interfering in the operation
of the function). It is used to poll for interrupts if hardware interrupts are
disabled. Read this register after servicing an interrupt to check for
stacked interrupts.
ABRT
SRST
4-46
Registers
Abort Operation
7
Setting this bit aborts the current operation under
execution by the LSI53C1000. If this bit is set and an
interrupt is received, clear this bit before reading the DMA
Status (DSTAT) register to prevent further aborted
interrupts from being generated. The sequence to abort
any operation is:
1.
Set this bit.
2.
Wait for an interrupt.
3.
Read the Interrupt Status Zero (ISTAT0) register.
4.
If the SCSI Interrupt Pending bit is set, read the
SCSI Interrupt Status Zero (SIST0) or SCSI Interrupt
Status One (SIST1) register to determine the cause
of the SCSI Interrupt and return to step 2.
5.
If the SCSI Interrupt Pending bit is cleared and the
DMA Interrupt Pending bit is set, write 0x00 to this
register.
6.
Read the DMA Status (DSTAT) register to verify the
aborted interrupt and to determine if any other
interrupting conditions have occurred.
Software Reset
6
Setting this bit resets the LSI53C1000. All operating
registers are cleared to their respective default values
and all SCSI signals are deasserted. Setting this bit does
not assert the SCSI RST/ signal. This reset does not
clear the ID Mode bit or any of the PCI configuration
registers. This bit is not self-clearing; it must be cleared
to clear the reset condition. A hardware reset also clears
this bit.
Note:
If SCRIPTS are running, then the ABRT bit (bit 7) must be
set prior to setting the SRST bit.
SIGP
Signal Process
5
SIGP is a R/W bit that is writable at any time. It is polled
and reset using Chip Test Two (CTEST2). The SIGP bit
is used in various ways to pass a flag to or from a running
SCRIPTS instruction.
The only SCRIPTS instruction directly affected by the
SIGP bit is Wait For Selection/Reselection. Setting the
SIGP bit causes this instruction to jump to the alternate
address immediately. The instructions at the alternate
jump address should check the status of SIGP to
determine the cause of the jump. The SIGP bit is usable
at any time and is not restricted to the wait for
selection/reselection condition.
SEM
Semaphore
4
The SCRIPTS processor may set this bit using a
SCRIPTS register write instruction. An external processor
may also set it while the LSI53C1000 is executing a
SCRIPTS operation. This bit enables the LSI53C1000 to
notify an external processor of a predefined condition
while SCRIPTS are running. The external processor may
also notify the LSI53C1000 of a predefined condition and
the SCRIPTS processor may take action while SCRIPTS
are executing.
CON
Connected
3
This bit is automatically set any time the LSI53C1000 is
connected to the SCSI bus as an initiator or as a target.
It is set after successfully completing selection or when
the LSI53C1000 responds to a bus-initiated selection or
reselection. It is also set after the chip wins arbitration
when operating in the low level mode. When this bit is
cleared, the LSI53C1000 is not connected to the SCSI
bus.
SCSI Registers
4-47
INTF
Note:
Interrupt-on-the-Fly
2
This bit is asserted by an INTFLY instruction during
SCRIPTS execution. SCRIPTS programs do not halt
when the interrupt occurs. This bit can be used to notify
a service routine, running on the main processor while
the SCRIPTS processor is still executing a SCRIPTS
program. If this bit is set, when the Interrupt Status Zero
(ISTAT0) register is read it is not automatically cleared. To
clear this bit, write a one to it. The reset operation is
self-clearing.
If the INTF bit is set but SIP or DIP is not set, do not
attempt to read the other chip status registers. An
interrupt-on-the-fly must be cleared before servicing any
other interrupts indicated by SIP or DIP.
After it has been set, this bit must be written to one to clear
it.
SIP
SCSI Interrupt Pending
1
This status bit is set when an interrupt condition is
detected in the SCSI portion of the LSI53C1000. The
following conditions cause a SCSI interrupt to occur:
• A phase mismatch (initiator mode) or SATN/ becomes
active (target mode)
• An arbitration sequence completes
• A selection or reselection time-out occurs
• The LSI53C1000 is selected
• The LSI53C1000 is reselected
• A SCSI gross error occurs
• An unexpected disconnect occurs
• A SCSI reset occurs
• A parity error is detected
• The handshake-to-handshake timer expires
• The general purpose timer expires
To determine which condition(s) caused the
interrupt, read the SCSI Interrupt Status Zero (SIST0)
and SCSI Interrupt Status One (SIST1) registers.
4-48
Registers
DIP
DMA Interrupt Pending
0
This status bit is set when an interrupt condition is
detected in the DMA portion of the LSI53C1000. The
following conditions cause a DMA interrupt to occur:
• A PCI parity error is detected
• A bus fault is detected
• An abort condition is detected
• A SCRIPTS instruction is executed in the single-step
mode
• A SCRIPTS interrupt instruction is executed
• An illegal instruction is detected
To determine exactly which condition(s) caused the
interrupt, read the DMA Status (DSTAT) register.
Register: 0x15
Interrupt Status One (ISTAT1)
Read/Write
7
3
R
0
0
0
0
0
2
1
0
FLSH
SRUN
SI
0
0
0
R
Reserved
FLSH
Flushing
2
If this bit is set, the chip is flushing data from the DMA
FIFO. If cleared, no flushing is occurring. This bit is read
only. Writes do not affect the value of this bit.
SRUN
SCRIPTS Running
1
If this bit is set, the SCRIPTS engine is currently fetching
and executing SCRIPTS instructions. If it is cleared, the
SCRIPTS engine is not active. This bit is read only.
Writes do not affect the value of this bit.
SI
SYNC_IRQD
0
Setting this bit disables the INTA/ pin for the LSI53C1000,
except for the SCSI gross error, bus fault, residual data
in SCSI FIFO, and data underflow interrupts. Clearing
this bit enables normal operation of the INTA/ pin. If the
INTA/ is already asserted and this bit is set, INTA/
SCSI Registers
[7:3]
4-49
remains asserted until the interrupt is serviced. At this
point the interrupt line is blocked for future interrupts until
this bit is cleared. In addition, this bit may be read and
written while SCRIPTS are executing.
Register: 0x16
Mailbox Zero (MBOX0)
Read/Write
7
0
MBOX0
0
0
MBOX0
Note:
0
0
0
0
0
0
Mailbox Zero
[7:0]
These are general purpose bits that may be read or
written while SCRIPTS are running. They also may be
read or written by the SCRIPTS processor.
The host and the SCRIPTS processor code could access
the same mailbox byte at the same time. Using one mailbox
register as read only and the other as write only prevents
this conflict.
Register: 0x17
Mailbox One (MBOX1)
Read/Write
7
0
MBOX1
0
MBOX1
Note:
4-50
Registers
0
0
0
0
0
0
0
Mailbox One
[7:0]
These are general purpose bits that may be read or
written while SCRIPTS are running. They also may be
read or written by the SCRIPTS processor.
The host and the SCRIPTS processor code could access
the same mailbox byte at the same time. Using one mailbox
register as read only and the other as write only prevents
this conflict.
Register: 0x18
Chip Test Zero (CTEST0)
Read/Write
7
0
FMT
1
1
FMT
1
1
1
1
1
1
Byte Empty in DMA FIFO
[7:0]
These bits identify the lower bytes in the DMA FIFO that
are empty. Each bit corresponds to a byte lane in the
DMA FIFO. For example, if byte lane three is empty, then
FMT bit 3 is set. The FMT flags indicate the status of
bytes at the bottom of the FIFO. Therefore, if all FMT bits
are set, the DMA FIFO is empty.
Register: 0x19
Chip Test One (CTEST1)
Read Only
7
0
FFL
0
0
FFL
SCSI Registers
0
0
0
0
0
0
Byte Full in DMA FIFO
[7:0]
These status bits identify the upper bytes in the DMA
FIFO that are full. Each bit corresponds to a byte lane in
the DMA FIFO. For example, if byte lane three is full then
FFL bit 3 is set. The FFL flags indicate the status of bytes
at the top of the FIFO. Therefore, if all FFL bits are set,
the DMA FIFO is full.
4-51
Register: 0x1A
Chip Test Two (CTEST2)
Read Only (bit 3 write)
7
6
5
4
3
R
SIGP
CIO
CM
PCICIE
x
0
x
x
0
2
0
R
x
x
x
R
Reserved
SIGP
Signal Process
6
This bit is a copy of the SIGP bit in the Interrupt Status
Zero (ISTAT0) register (bit 5). The SIGP bit is used to
signal a running SCRIPTS instruction. When this register
is read, the SIGP bit in the ISTAT0 register is cleared.
CIO
Configured as I/O
5
This bit is defined as the Configuration I/O Enable Status
bit. This read only bit indicates if the chip is currently
enabled as I/O space.
CM
Configured as Memory
4
This bit is defined as the configuration memory enable
status bit. This read only bit indicates if the chip is
currently enabled as memory space.
Note:
PCICIE
7
Bits 4 and 5 may be set if the chip is mapped in both I/O
and memory space. Also, bits 4 and 5 may be set if the
chip is dual-mapped.
PCI Configuration Info Enable
3
This bit controls the shadowing of the PCI Base Address
Register One (BAR1) (MEMORY), PCI Base Address
Register Two (BAR2) (MEMORY), PCI Base Address
Register Three (BAR3) (SCRIPTS RAM), PCI Base
Address Register Four (BAR4) (SCRIPTS RAM), PCI
Device ID, and PCI Revision ID (RID) into the Scratch
Register A (SCRATCHA), Memory Move Read Selector
(MMRS), Scratch Register B (SCRATCHB), Memory
Move Write Selector (MMWS), and SCRIPT Fetch Selector (SFS) registers.
When it is set, MMWS contains bits [63:32] and
SCRATCH B contains bits [31:0] of the RAM Base
Address value from the PCI Configuration Base Address
4-52
Registers
Register Three (BAR3) (SCRIPTS RAM) and Base
Address Register Four (BAR4) (SCRIPTS RAM). This is
the base address for the 8 Kbytes of internal RAM.
Memory Move Read Selector (MMRS) contains
bits [63:32] and Scratch Register A (SCRATCHA)
contains bits [31:0] of the memory mapped operating
register base address. Bits [23:16] of SCRIPT Fetch
Selector (SFS) contain the PCI Revision ID (RID) register
value and bits [15:0] contain the PCI Device ID register
value. When this bit is set, only reads to the registers are
affected, writes occur normally.
When this bit is cleared, the SCRATCH A, MMRS,
SCRATCH B, MMWS, and SFS registers return to normal
operation.
Note:
Bit 3 is the only writable bit in this register. All other bits are
read only. When modifying this register, all other bits must
be written to zero. Do not execute a Read-Modify-Write to
this register.
R
Reserved
[2:0]
Register: 0x1B
Chip Test Three (CTEST3)
Read/Write
7
4
R
0
0
0
0
3
2
1
0
FLF
CLF
R
WRIE
0
0
0
0
R
Reserved
FLF
Flush DMA FIFO
3
When this bit is set, data residing in the DMA FIFO is
transferred to memory, starting at the address in the DMA
Next Address (DNAD) register. This bit is not
self-clearing; clear it once the data is successfully
transferred by the LSI53C1000.
Note:
[7:4]
Polling of FIFO flags is allowed during flush operations.
SCSI Registers
4-53
CLF
Clear DMA FIFO
2
When this bit is set, all data pointers for the DMA FIFO
are cleared. Any data in the FIFO is lost. After the
LSI53C1000 successfully clears the appropriate FIFO
pointers and registers, this bit automatically clears.
Note:
This bit does not clear the data visible at the bottom of the
FIFO.
R
Reserved
1
WRIE
Write and Invalidate Enable
0
This bit, when set, causes the issuing of Write and
Invalidate commands on the PCI bus whenever legal.
The Write and Invalidate Enable bit in the PCI
Configuration Command register must also be set for the
chip to generate Write and Invalidate commands.
Registers: 0x1C–0x1F
Temporary (TEMP)
Read/Write
31
0
TEMP
0
0
0
0
0
0
0
0
0
0
TEMP
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Temporary
[31:0]
This 32-bit register stores the Return instruction address
pointer from the Call instruction. The address pointer
stored in this register is loaded into the DMA SCRIPTS
Pointer (DSP) register when a Return instruction is
executed. This address points to the next instruction to
execute. Do not write to this register while the
LSI53C1000 is executing SCRIPTS.
During any Memory-to-Memory Moves operation, the
contents of this register are preserved. The power-up
value of this register is indeterminate.
4-54
Registers
0
Register: 0x20
Reserved
7
0
R
x
x
x
x
x
x
3
2
x
x
This register is reserved.
Register: 0x21
Chip Test Four (CTEST4)
Read/Write
7
6
R
FBL3
5
0
0
4
R
0
MPEE
0
0
0
FBL[2:0]
0
0
0
R
Reserved
FBL3
FIFO Byte Control 3
6
This bit is used with FBL[2:0]. See Bits [2:0] description
in this register.
R
Reserved
MPEE
Master Parity Error Enable
3
Setting this bit enables parity checking during master
data phases. A parity error during a bus master read is
detected by the LSI53C1000. A parity error during a bus
master write is detected by the target, and the
LSI53C1000 is informed of the error by the PERR/ pin
being asserted by the target. When this bit is cleared, the
LSI53C1000 does not interrupt if a master parity error
occurs. This bit is cleared at power-up.
FBL[2:0]
FIFO Byte Control
SCSI Registers
7
[5:4]
[2:0]
FBL3
FBL2
FBL1
FBL0
DMA FIFO
Byte Lane
Pins
0
1
1
1
1
X
0
0
0
0
X
0
0
1
1
X
0
1
0
1
Disabled
0
1
2
3
N/A
D[7:0]
D[15:8]
D[23:16]
D[31:24]
4-55
FBL3
FBL2
FBL1
FBL0
DMA FIFO
Byte Lane
Pins
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
4
5
6
7
D[39:32]
D[47:40]
D[53:48]
D[63:54]
These bits steer the contents of the Chip Test Six
(CTEST6) register to the appropriate byte lane of the
64-bit DMA FIFO. If the FBL3 bit is set, then FBL2
through FBL0 determine which of eight byte lanes can be
read or written. When cleared, the byte lane read or
written is determined by the current contents of the DMA
Next Address (DNAD) and DMA Byte Counter (DBC)
registers. Each of the eight bytes that make up the 64-bit
DMA FIFO is accessed by writing these bits to the proper
value. For normal operation, FBL3 must equal zero.
Register: 0x22
Chip Test Five (CTEST5)
Read/Write
4-56
7
6
5
ADCK
BBCK
0
0
3
R
0
0
2
1
BL2
0
0
0
R
0
0
ADCK
Clock Address Incrementor
7
Setting this bit increments the address pointer contained
in the DMA Next Address (DNAD) register. The DNAD
register is incremented based on the DNAD contents and
the current DMA Byte Counter (DBC) value. This bit
automatically clears itself after incrementing the DNAD
register.
BBCK
Clock Byte Counter
6
Setting this bit decrements the byte count contained in
the 24-bit DMA Byte Counter (DBC) register. It is
decremented based on the DBC contents and the current
DMA Next Address (DNAD) value. This bit automatically
clears itself after decrementing the DBC register.
Registers
R
Reserved
[5:3]
BL2
Burst Length Bit 2
2
This bit works with bits 6 and 7 (BL[1:0]) in the DMA
Mode (DMODE) register to determine the burst length.
For complete definitions of this field, refer to the
descriptions of DMODE bits 6 and 7.
R
Reserved
[1:0]
Register: 0x23
Chip Test Six (CTEST6)
Read/Write
7
0
DF
0
0
DF
SCSI Registers
0
0
0
0
0
0
DMA FIFO
[7:0]
Writing to this register writes data to the appropriate byte
lane of the DMA FIFO, as determined by the FBL bits in
the Chip Test Four (CTEST4) register. Reading this
register unloads data from the appropriate byte lane of
the DMA FIFO, as determined by the FBL bits in the
CTEST4 register. Data written to the FIFO is loaded into
the top of the FIFO. Data read out of the FIFO is taken
from the bottom. To prevent DMA data from being
corrupted, this register should not be accessed before
starting or restarting SCRIPTS operations. This register
should be the last register read when performing register
dumps because of its effects on other registers. Write to
this register only when testing the DMA FIFO using the
CTEST4 register. Writing to this register while the test
mode is not enabled produces unexpected results.
4-57
Registers: 0x24–0x26
DMA Byte Counter (DBC)
Read/Write
23
0
DBC
0
0
0
0
0
0
0
0
DBC
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DMA Byte Counter
[23:0]
This 24-bit register determines the number of bytes
transferred in a Block Move instruction. While sending
data to the SCSI bus, the counter is decremented as data
is moved into the DMA FIFO from memory. While
receiving data from the SCSI bus, the counter is
decremented as data is written to memory from the
LSI53C1000. The DBC counter is decremented each
time data is transferred on the PCI bus. It is decremented
by an amount equal to the number of bytes transferred.
The maximum number of bytes transferred in any one
Block Move command is 16,777,215 bytes. The
maximum value that can be loaded into the DMA Byte
Counter (DBC) register is 0xFFFFFF. If the instruction is
a Block Move and a value of 0x000000 is loaded into the
DBC register, an illegal instruction interrupt occurs if the
LSI53C1000 is not in the target mode, Command phase.
The DMA Byte Counter (DBC) register is also used to
hold the least significant 24 bits of the first Dword of a
SCRIPTS fetch, and to hold the offset value during Table
Indirect I/O SCRIPTS. For a complete description see
Chapter 5, “SCSI SCRIPTS Instruction Set.” The
power-up value of this register is indeterminate.
4-58
Registers
Register: 0x27
DMA Command (DCMD)
Read/Write
7
0
DCMD
0
0
DCMD
0
0
0
0
0
0
DMA Command
[7:0]
This 8-bit register determines the instruction for the
LSI53C1000 to execute. This register has a different
format for each instruction. For a complete description
see Chapter 5, “SCSI SCRIPTS Instruction Set.”
Registers: 0x28–0x2B
DMA Next Address (DNAD)
Read/Write
31
0
DNAD
0
0
0
0
0
0
0
0
0
0
0
0
DNAD
SCSI Registers
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DMA Next Address
[31:0]
This 32-bit register contains the general purpose address
pointer. At the start of some SCRIPTS operations, its
value is copied from the DMA SCRIPTS Pointer Save
(DSPS) register. Its value may not be valid except in
certain abort conditions. The default value of this register
is zero.
4-59
Registers: 0x2C–0x2F
DMA SCRIPTS Pointer (DSP)
Read/Write
31
0
DSP
0
0
0
0
0
0
0
0
0
0
0
0
DSP
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DMA SCRIPTS Pointer
[31:0]
To execute SCSI SCRIPTS, the address of the first
SCRIPTS instruction must be written to this register. In
normal SCRIPTS operation, once the starting address of
the SCRIPT is written to this register, SCRIPTS are
automatically fetched and executed until an interrupt
condition occurs.
In the single-step mode, there is a single step interrupt
after each instruction is executed. The DMA SCRIPTS
Pointer (DSP) register does not need to be written with
the next address. However, to fetch and execute the next
SCRIPTS command, the Start DMA bit (bit 2, DMA Control (DCNTL) register) must be set each time the step
interrupt occurs. When writing this register eight bits at a
time, writing the upper eight bits begins execution of
SCSI SCRIPTS. The default value of this register is zero.
Registers: 0x30–0x33
DMA SCRIPTS Pointer Save (DSPS)
Read/Write
31
0
DSPS
0
0
0
0
0
0
0
0
0
0
DSPS
4-60
Registers
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DMA SCRIPTS Pointer Save
[31:0]
This register contains the second Dword of a SCRIPTS
instruction. It is overwritten each time a SCRIPTS
instruction is fetched. When a SCRIPTS interrupt
instruction is executed, this register holds the interrupt
vector. The power-up value of this register is
indeterminate.
Registers: 0x34–0x37
Scratch Register A (SCRATCHA)
Read/Write
31
0
SCRATCHA
0
0
0
0
0
0
0
0
0
0
0
0
SCRATCHA
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Scratch Register A
[31:0]
This is a general purpose, user-definable scratch pad
register. Apart from CPU access, only register read/write
and Memory Moves into the SCRATCH register alter its
contents. The power-up value of this register is
indeterminate.
A special mode of this register is enabled by setting the
PCI Configuration Info Enable bit in the Chip Test Two
(CTEST2) register. If this bit is set, Scratch Register A
(SCRATCHA) returns bits [31:10] of the PCI Base
Address Register One (BAR1) (MEMORY) in bits [31:10].
Bits [9:0] of SCRATCH A will always return zero in this
mode. Writes to the SCRATCHA register are unaffected.
Clearing the PCI Configuration Info Enable bit causes the
SCRATCH A register to return to normal operation.
Register: 0x38
DMA Mode (DMODE)
Read/Write
7
6
BL[1:0]
0
0
BL[1:0]
SCSI Registers
5
4
3
2
1
0
SIOM
DIOM
ERL
ERMP
BOF
MAN
0
0
0
0
0
0
Burst Length
[7:6]
These bits control the maximum number of Dwords
transferred per bus ownership, regardless of whether the
transfers are back-to-back, burst, or a combination of
both. This value is also independent of the width (64-bit
or 32-bit) of the data transfer on the PCI bus. The
LSI53C1000 asserts the Bus Request (PCIREQ/) output
when the DMA FIFO can accommodate a transfer of at
least one burst threshold of data. Bus Request
(PCIREQ/) is also asserted during start-of-transfer and
4-61
end-of-transfer cleanup and alignment, even if less than
a full burst of transfers is performed. The LSI53C1000
inserts a “fairness delay” of four CLKs between burst
transfers (set in BL[2:0]) during normal operation. The
fairness delay is not inserted during PCI retry cycles. This
gives the CPU and other bus master devices the
opportunity to access the PCI bus between bursts.
SIOM
BL2
(CTEST5 bit 2)
BL1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
BL0
Number
of 64-bit
Transfers
Number
of 32-bit
Transfers
0
1
0
1
0
1
0
1
4
4
8
16
32
64
64
Reserved
8
8
16
32
64
128
128
Reserved
Source I/O-Memory Enable
5
This bit is defined as an I/O Memory Enable bit for the
source address of a Memory Move or Block Move
Command. If this bit is set, then the source address is in
I/O space; if cleared, the source address is in memory
space.
This function is useful for register-to-memory operations
using the Memory Move instruction when a LSI53C1000
is I/O mapped. Bits 4 and 5 of the Chip Test Two
(CTEST2) register are used to determine the
configuration status of the LSI53C1000.
DIOM
Destination I/O-Memory Enable
4
This bit is defined as an I/O Memory Enable bit for the
destination address of a Memory Move or Block Move
Command. If this bit is set, then the destination address
is in I/O space; if cleared, the destination address is in
memory space.
This function is useful for memory-to-register operations
using the Memory Move instruction when a LSI53C1000
is I/O mapped. Bits 4 and 5 of the Chip Test Two
(CTEST2) register are used to determine the
configuration status of the LSI53C1000.
4-62
Registers
ERL
Enable Read Line
3
This bit enables a PCI Read Line command. If this bit is
set and the chip is about to execute a read cycle (other
than an opcode fetch), the command is 0b1110.
ERMP
Enable Read Multiple
2
If this bit is set and cache mode is enabled, a Read
Multiple command is used on all read cycles when it is
legal.
BOF
Burst Opcode Fetch Enable
1
Setting this bit causes the LSI53C1000 to fetch
instructions in burst mode. Specifically, the chip bursts in
the first two Dwords of all instructions using a single bus
ownership. If the instruction is a Memory-to-Memory
Moves type, the third Dword is accessed in a subsequent
bus ownership. If the instruction is an indirect type, the
additional Dword is accessed in a subsequent bus
ownership. If the instruction is a table indirect block move
type, the chip accesses the remaining two Dwords in a
subsequent bus ownership, thereby fetching the four
Dwords required in two bursts of two Dwords each. If
prefetch is enabled, this bit has no affect. This bit also
has no affect on fetches out of SCRIPTS RAM.
MAN
Manual Start Mode
0
Setting this bit prevents the LSI53C1000 from
automatically fetching and executing SCSI SCRIPTS
when the DMA SCRIPTS Pointer (DSP) register is
written. When this bit is set, the Start DMA bit in the DMA
Control (DCNTL) register must be set to begin SCRIPTS
execution. Clearing this bit causes the LSI53C1000 to
automatically begin fetching and executing SCSI
SCRIPTS when the DMA SCRIPTS Pointer (DSP)
register is written. This bit normally is not used for SCSI
SCRIPTS operations.
SCSI Registers
4-63
Register: 0x39
DMA Interrupt Enable (DIEN)
Read/Write
7
6
5
4
3
2
1
0
R
MDPE
BF
ABRT
SSI
SIR
R
IID
x
0
0
0
0
0
x
0
This register contains the interrupt mask bits corresponding to the
interrupting conditions described in the DMA Status (DSTAT) register. An
interrupt is masked by clearing the appropriate mask bit. Masking an
interrupt prevents INTA/ from being asserted for the corresponding
interrupt, but the status bit is still set in the DMA Status (DSTAT) register.
Masking an interrupt does not prevent setting the Interrupt Status Zero
(ISTAT0) DIP. All DMA interrupts are considered fatal. Therefore,
SCRIPTS halts when this condition occurs, whether or not the interrupt
is masked. Setting a mask bit enables the assertion of INTA/ for the
corresponding interrupt. A masked nonfatal interrupt does not prevent
unmasked or fatal interrupts from getting through; interrupt stacking
begins when either the Interrupt Status Zero (ISTAT0) SIP or DIP bit is
set.
The INTA/ output is latched. Once asserted, it remains asserted until the
interrupt is cleared by reading the appropriate status register. Masking
an interrupt after the INTA/ output is asserted does not cause
deassertion of INTA/. For more information on interrupts, see Chapter 2,
“Functional Description.”
4-64
R
Reserved
7
MDPE
Master Data Parity Error
6
BF
Bus Fault
5
ABRT
Aborted
4
SSI
Single Step Interrupt
3
SIR
SCRIPTS Interrupt Instruction Received
2
R
Reserved
1
IID
Illegal Instruction Detected
0
Registers
Register: 0x3A
Scratch Byte Register (SBR)
Read/Write
7
0
SBR
0
0
SBR
0
0
0
0
0
0
Scratch Byte Register
[7:0]
This is a general purpose register. Apart from CPU
access, only register Read/Write and Memory Moves into
this register alter its contents. The default value of this
register is zero. This register is called the DMA Watchdog
Timer on previous LSI53C8XX family products.
Register: 0x3B
DMA Control (DCNTL)
Read/Write
7
6
5
4
3
2
1
0
CLSE
PFF
PFEN
SSM
IRQM
STD
R
COM
0
0
0
0
0
0
0
0
CLSE
Cache Line Size Enable
7
Setting this bit enables the LSI53C1000 to sense and
react to cache line boundaries set up by the DMA Mode
(DMODE) or PCI Cache Line Size (CLS) register,
whichever contains the smaller value. Clearing this bit
disables the cache line size logic.
PFF
Prefetch Flush
Setting this bit causes the prefetch unit to flush its
contents. This bit clears after the flush is complete.
PFEN
Prefetch Enable
5
Setting this bit enables an 8-Dword SCRIPTS instruction
prefetch unit. The prefetch unit, when enabled, fetches
8 Dwords of instructions and instruction operands in
bursts of 4 or 8 Dwords. Prefetching instructions allows
the LSI53C1000 to make more efficient use of the system
PCI bus, thus improving overall system performance. A
flush occurs whenever the PFF bit is set, on all transfer
control instructions (when the transfer conditions are
SCSI Registers
6
4-65
met), on writes to the DMA SCRIPTS Pointer (DSP), on
regular MMOV instructions, and when an interrupt is
generated. Based on the burst length as determined by
the values in the DMA Mode (DMODE) register, the unit
automatically determines the maximum burst size that it
is capable of performing. If the burst threshold is set to
8 Dwords, the prefetch unit fetches instructions in two
bursts of 4 Dwords. If the burst threshold is set to
16 Dwords, or greater, the prefetch unit fetches
instructions in one burst of 8 Dwords. Burst thresholds of
less than 8 Dwords cause the prefetch unit to be
disabled. PCI Cache commands (Read Line and Read
Multiple) are issued if PCI caching is enabled.
Prefetching from SCRIPTS RAM is not supported and is
unnecessary due to the speed of the fetches. When
fetching from SCRIPTS RAM, the setting of this bit has
no effect on the fetch mechanism from SCRIPTS RAM.
The prefetch unit does not support 64-bit data instruction
fetches across the PCI bus. Prefetches of SCRIPTS
instructions are 32-bits in width.
4-66
SSM
Single-Step Mode
4
Setting this bit causes the LSI53C1000 to stop after
executing each SCRIPTS instruction and to generate a
single step interrupt. When this bit is cleared the
LSI53C1000 does not stop after each instruction. It
continues fetching and executing instructions until an
interrupt condition occurs. For normal SCSI SCRIPTS
operation, keep this bit cleared. To restart the
LSI53C1000 after it generates a SCRIPTS Step interrupt,
read the Interrupt Status Zero (ISTAT0) and DMA Status
(DSTAT) registers to recognize and clear the interrupt.
Then set the START DMA bit in this register.
IRQM
IRQ Mode
3
When set, this bit enables a totem pole driver for the
INTA/ pin. When cleared, this bit enables an open drain
driver for the INTA/ pin with an internal weak pull-up. The
bit should remain cleared to retain full PCI compliance.
Registers
STD
Start DMA Operation
2
The LSI53C1000 fetches a SCSI SCRIPTS instruction
from the address contained in the DMA SCRIPTS Pointer
(DSP) register when this bit is set. This bit is required if
the LSI53C1000 is in one of the following modes:
• Manual start mode – Bit 0 in the DMA Mode
(DMODE) register is set
• Single-step mode – Bit 4 in the DMA Control (DCNTL)
register is set
When the LSI53C1000 is executing SCRIPTS in manual
start mode, the Start DMA bit must be set to start
instruction fetches, but need not be set again until an
interrupt occurs. When the LSI53C1000 is in the
single-step mode, set the Start DMA bit to restart
execution of SCRIPTS after a single-step interrupt.
R
Reserved
1
COM
LSI53C700 Family Compatibility
0
When the COM bit is cleared, the LSI53C1000 behaves
in a manner compatible with the LSI53C700 family;
selection/reselection IDs are stored in both the SCSI
Selector ID (SSID) and SCSI First Byte Received (SFBR)
registers. This bit is not affected by a software reset.
If the COM bit is cleared, do not access this register
using SCRIPTS operation as indeterminate operations
may occur. This includes SCRIPTS Read/Write
operations and conditional transfer control instructions
that initialize the SCSI First Byte Received (SFBR)
register.
When the COM bit is set, the ID is stored only in the
SCSI Selector ID (SSID) register, protecting the SCSI
First Byte Received (SFBR) from being overwritten if a
selection/reselection occurs during a DMA register-toregister operation.
SCSI Registers
4-67
Registers: 0x3C–0x3F
Adder Sum Output (ADDER)
Read Only
31
0
ADDER
0
0
0
0
0
0
0
0
0
0
0
0
ADDER
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Adder Sum Output
[31:0]
This register contains the output of the internal adder,
and is used primarily for test purposes. The power-up
value for this register is indeterminate.
Register: 0x40
SCSI Interrupt Enable Zero (SIEN0)
Read/Write
7
6
5
4
3
2
1
0
M/A
CMP
SEL
RSL
SGE
UDC
RST
PAR
0
0
0
0
0
0
0
0
This register contains the interrupt mask bits corresponding to the
interrupting conditions described in the SCSI Interrupt Status Zero
(SIST0) register. An interrupt is masked by clearing the appropriate mask
bit. For more information on interrupts see Chapter 2, “Functional
Description.”
4-68
M/A
SCSI Phase Mismatch - Initiator Mode;
SCSI ATN Condition - Target Mode
7
In the initiator mode, this bit is set when the SCSI phase
asserted by the target and sampled during SREQ/ does
not match the expected phase in the SCSI Output Control
Latch (SOCL) register. This expected phase is
automatically written by SCSI SCRIPTS. In the target
mode, this bit is set when the initiator asserts SATN/. See
the Disable Halt on Parity Error or SATN/ Condition bit in
the SCSI Control One (SCNTL1) register for more
information on when this status is actually raised.
CMP
Function Complete
When set, this bit indicates the full arbitration and
selection sequence is completed.
Registers
6
SEL
Selected
5
When set, this bit indicates the LSI53C1000 is selected
by a SCSI initiator device. For this to occur, set the
Enable Response to Selection bit in the SCSI Chip ID
(SCID) register.
RSL
Reselected
4
When set, this bit indicates the LSI53C1000 is reselected
by a SCSI target device. For this to occur, set the Enable
Response to Reselection bit in the SCSI Chip ID (SCID)
register.
SGE
SCSI Gross Error
The following conditions are considered SCSI Gross
Errors:
3
• Offset Underflow occurs in target mode when a
SACK/ signal is received before the corresponding
SREQ/ signal has been sent.
• Offset Overflow occurs in initiator mode when an
SREQ/ signal is received and causes the maximum
offset, as defined by the MO[5:0] bits in the SXFER
register, to be exceeded.
• In initiator mode, a phase change occurs with an
outstanding SREQ/SACK offset.
• Residual Data in SCSI FIFO occurs when a transfer
other than Synchronous Data Received is started with
data left in the SCSI Synchronous Receive FIFO.
• Multiple CRC Requests occur when, during a
synchronous DT transfer, multiple CRC requests are
received within the same offset.
• A request for a Pad CRC word is received without the
subsequent CRC word requests.
• A phase change occurs without a CRC Request.
Note:
Checking for this condition can be disabled by setting the
DISCRC bit in the CRCCNTL0 register.
• An illegal Force CRC Request Block Move is
executed.
• A SCRIPTS RAM parity error.
SCSI Registers
4-69
Note:
The Shadowed SCSI SGE Status 0 register indicates which
condition caused an SGE SCSI interrupt. This register is
shadowed behind the SCSI Interrupt Status Zero (SIST0)
register. It can be accessed by setting bit 7, the Enable
Shadowed SGE Register (ShSGE) bit, in the Chip Control
Two (CCNTL2) register.
UDC
Unexpected Disconnect
2
This condition only occurs in the initiator mode. It
happens when the target, which the LSI53C1000 is
connected to, unexpectedly disconnects from the SCSI
bus. See the SCSI Disconnect Unexpected bit in the
SCSI Control Two (SCNTL2) register for more information
on expected versus unexpected disconnects. Any
disconnect in the low level mode causes this condition.
RST
SCSI Reset Condition
1
This bit indicates assertion of the SRST/ signal by the
LSI53C1000 or any other SCSI device. This condition is
edge-triggered, so multiple interrupts cannot occur
because of a single SRST/ pulse.
PAR
SCSI Parity/CRC/AIP Error
0
This bit indicates the LSI53C1000 detected a
Parity/CRC/AIP error while receiving or sending SCSI
data. See the Disable Halt on Parity/CRC/AIP error or
SATN/ Condition bits in the SCNTL1 register for more
information about when this condition is raised.
Register: 0x41
SCSI Interrupt Enable One (SIEN1)
Read/Write
7
5
R
x
x
x
4
3
2
1
0
SBMC
R
STO
GEN
HTH
0
x
0
0
0
This register contains the interrupt mask bits corresponding to the
interrupting conditions described in the SCSI Interrupt Status One
(SIST1) register. An interrupt is masked by clearing the appropriate mask
bit. For more information on interrupts refer to Chapter 2, “Functional
Description.”
4-70
Registers
R
Reserved
SBMC
SCSI Bus Mode Change
4
Setting this bit allows the LSI53C1000 to generate an
interrupt when the DIFFSENS pin detects a change in
voltage level that indicates the SCSI bus has changed
between SE, LVD, or HVD modes. For example, when
this bit is cleared and the SCSI bus changes modes, INT/
does not assert and the SIP bit in the Interrupt Status
Zero (ISTAT0) register is not set. However, bit 4 in the
SCSI Interrupt Status One (SIST1) register is set. Setting
this bit allows the interrupt to occur.
R
Reserved
STO
Selection or Reselection Time-out
2
This bit is set when the SCSI device which the
LSI53C1000 is attempting to select or reselect does not
respond within the programmed time-out period. See the
description of the SCSI Timer Zero (STIME0) register,
bits [3:0], for more information on the time-out timer.
GEN
General Purpose Timer Expired
1
This bit is set when the general purpose timer expires.
The time measured is the time between enabling and
disabling of the timer. See the description of the SCSI
Timer One (STIME1) register, bits [3:0], for more
information on the general purpose timer.
HTH
Handshake-to-Handshake Timer Expired
0
This bit is set when the handshake-to-handshake timer
expires. The time measured is the SCSI Request-toRequest (target) or Acknowledge-to-Acknowledge
(initiator) period. See the description of the SCSI Timer
Zero (STIME0) register, bits [7:4], for more information on
the handshake-to-handshake timer.
SCSI Registers
[7:5]
3
4-71
Register: 0x42
SCSI Interrupt Status Zero (SIST0)
Read Only
7
6
5
4
3
2
1
0
M/A
CMP
SEL
RSL
SGE
UDC
RST
PAR
0
0
0
0
0
0
0
0
Reading the SCSI Interrupt Status Zero (SIST0) register returns the
status of the various interrupt conditions, whether they are enabled in the
SCSI Interrupt Enable Zero (SIEN0) register or not. Each bit set indicates
occurrence of the corresponding condition. Reading the SIST0 clears the
interrupt status.
Reading this register clears any bits that are set at the time the register
is read, but does not necessarily clear the register because additional
interrupts may be pending; the LSI53C1000 stacks interrupts. SCSI
interrupt conditions are individually masked through the SCSI Interrupt
Enable Zero (SIEN0) register.
When performing consecutive 8-bit reads of the DMA Status (DSTAT),
SCSI Interrupt Status Zero (SIST0), and SCSI Interrupt Status One
(SIST1) registers (in any order), insert a delay equivalent to 12 clock
periods between the reads to ensure the interrupts clear properly. Also,
if reading the registers when both the Interrupt Status Zero (ISTAT0) SIP
and DIP bits may not be set, read the SIST0 and SIST1 registers before
the DSTAT register to avoid missing a SCSI interrupt. For more
information on interrupts refer to Chapter 2, “Functional Description.”
4-72
M/A
Initiator Mode: Phase Mismatch; Target Mode:
SATN/ Active
7
In the initiator mode, this bit is set if the SCSI phase
asserted by the target does not match the instruction.
The phase is sampled when SREQ/ is asserted by the
target. In the target mode, this bit is set when the SATN/
signal is asserted by the initiator.
CMP
Function Complete
6
This bit is set when an arbitration only or full arbitration
sequence is completed.
Registers
SEL
Selected
5
This bit is set when the LSI53C1000 is selected by
another SCSI device. For the LSI53C1000 to respond to
selection attempts, the Enable Response to Selection bit
must be set in the SCSI Chip ID (SCID) register. The
Response ID Zero (RESPID0) and Response ID One
(RESPID1) registers must hold the chip’s ID.
RSL
Reselected
4
This bit is set when the LSI53C1000 is reselected by
another SCSI device. The Enable Response to
Reselection bit must be set in the SCSI Chip ID (SCID)
register (and the Response ID Zero (RESPID0) and
Response ID One (RESPID1) registers must hold the
chip’s ID) for the LSI53C1000 to respond to reselection
attempts.
SGE
SCSI Gross Error
3
This bit is set when the LSI53C1000 encounters a SCSI
Gross Error condition. The following conditions can result
in a SCSI Gross Error:
• Offset Underflow occurs in target mode when a
SACK/ signal is received before the corresponding
SREQ/ signal has been sent.
• Offset Overflow occurs in initiator mode when an
SREQ/ signal is received and causes the maximum
offset, as defined by the MO[5:0] bits in the SXFER
register, to be exceeded.
• In initiator mode, a phase change occurs with an
outstanding SREQ/SACK offset.
• Residual Data in SCSI FIFO occurs when a transfer
other than Synchronous Data Received is started with
data left in the SCSI Synchronous Receive FIFO.
• Multiple CRC Requests occur when, during a
synchronous DT transfer, multiple CRC requests are
received within the same offset.
• A request for a Pad CRC word is received without the
subsequent CRC word requests.
• A phase change occurs without a CRC Request.
Note:
Checking for this condition can be disabled by setting the
DCRC bit in the CRCCNTL0 register.
SCSI Registers
4-73
• An illegal Force CRC Request Block Move is
executed.
• A SCRIPTS RAM parity error.
Note:
4-74
The Shadowed SCSI SGE Status 0 register indicates which
condition caused an SGE SCSI interrupt. This register is
shadowed behind the SCSI Interrupt Status Zero (SIST0)
register. It can be accessed by setting bit 7, the Enable
Shadowed SGE Register (ShSGE) bit, in the Chip Control
Two (CCNTL2) register.
UDC
Unexpected Disconnect
2
This bit is set when the LSI53C1000 is operating in the
initiator mode and the target device unexpectedly
disconnects from the SCSI bus. This bit is only valid
when the LSI53C1000 operates in the initiator mode.
When the LSI53C1000 operates in the low level mode,
any disconnect causes an interrupt, even a valid SCSI
disconnect. This bit is also set if a selection time-out
occurs. Since a selection time-out is not considered an
expected disconnect, an unexpected disconnect may
occur before, at the same time, or stacked after the STO
interrupt.
RST
SCSI RST/ Received
1
This bit is set when the LSI53C1000 detects an active
SRST/ signal, whether the reset is generated external to
the chip or caused by the Assert SRST/ bit in the SCSI
Control One (SCNTL1) register. This SCSI reset
detection logic is edge-sensitive, so that multiple
interrupts are not generated for a single assertion of the
SRST/ signal.
PAR
Parity/CRC/AIP Error
0
This bit indicates the LSI53C1000 detected a
Parity/CRC/AIP error while receiving or sending SCSI
data. See the Disable Halt on Parity/CRC/AIP Error or
ATN/ condition bit in the SCSI Control One (SCNTL1)
register for more information about when this condition
will actually be raised.
Registers
Register: 0x43
SCSI Interrupt Status One (SIST1)
Read Only
7
5
R
0
0
0
4
3
2
1
0
SBMC
R
STO
GEN
HTH
0
0
0
0
0
Reading the SIST1 register returns the status of the various interrupt
conditions, whether they are enabled in the SCSI Interrupt Enable One
(SIEN1) register or not. Each bit set indicates an occurrence of the
corresponding condition. Reading the SIST1 clears the interrupt
condition.
R
Reserved
SBMC
SCSI Bus Mode Change
4
This bit is set when the DIFFSENS pin detects a change
in voltage level indicating the SCSI bus has switched
between SE, LVD, or HVD modes. HVD is not supported.
R
Reserved
STO
Selection or Reselection Time-Out
2
This bit is set when the SCSI device which the
LSI53C1000 is attempting to select or reselect does not
respond within the programmed time-out period. See the
description of the SCSI Timer Zero (STIME0) register,
bits [3:0], for more information on the time-out timer.
GEN
General Purpose Timer Expired
1
This bit is set when the general purpose timer expires.
The time measured is the time between enabling and
disabling of the timer. See the description of the SCSI
Timer One (STIME1) register, bits [3:0], for more
information on the general purpose timer.
HTH
Handshake-to-Handshake Timer Expired
0
This bit is set when the handshake-to-handshake timer
expires. The time measured is the SCSI Request-toRequest (target) or Acknowledge-to-Acknowledge
(initiator) period. See the description of the SCSI Timer
Zero (STIME0) register, bits [7:4], for more information on
the handshake-to-handshake timer.
SCSI Registers
[7:5]
3
4-75
Register: 0x44
Reserved
7
0
R
x
x
x
x
x
x
x
x
This register is reserved.
Register: 0x45
SCSI Wide Residue (SWIDE)
Read/Write
7
0
SWIDE
0
0
SWIDE
0
0
0
0
0
0
SCSI Wide Residue
[7:0]
After a wide SCSI data receive operation, this register
contains a residual data byte if the last byte received was
never sent across the DMA bus. It represents either the
first data byte of a subsequent data transfer, a residue
byte which should be cleared when an Ignore Wide
Residue message is received, or an overrun data byte.
The power-up value of this register is indeterminate.
Register: 0x46
Reserved
7
0
R
x
x
x
This register is reserved.
4-76
Registers
x
x
x
x
x
Register: 0x47
General Purpose Pin Control (GPCNTL)
Read/Write
7
6
5
ME
FE
LEDC
0
0
x
4
2
1
GPIO[4:2]
0
1
0
GPIO[1:0]
1
1
1
This register is used to determine if the pins controlled by the General
Purpose (GPREG) register are inputs or outputs. Bits [4:0] in GPCNTL
correspond to bits [4:0] in the GPREG register. When the bits are
enabled as inputs, an internal pull-up is also enabled.
ME
Master Enable
7
When the ME bit is set, the bus master state of the
device is presented on GPIO1. GPIO1 goes low when the
part is a bus master. When set, the ME bit is independent
of the setting of bit 1 (GPIO1). If the GPIO1 is configured
as an input while the ME bit is set, the Master bit will still
toggle the GPIO1 pin.
FE
Fetch Enable
6
If the FE bit is set, GPIO0 reflects when an internal
opcode fetch is being performed. GPIO0 goes low when
an opcode fetch is performed. When set, the FE bit is
independent of the setting of bit 0 (GPIO0). If GPIO0 is
configured as an input, the Fetch bit still toggles GPIO0.
LEDC
LED_CNTL
5
If the LED_CNTL bit is set GPIO0 reflects the state of the
SCSI bus, connected (GIO0 is low) or not connected
(GPIO0 is high). This occurs if bit 6 (FE) is not set and
the chip is not currently performing an EEPROM
autodownload. This bit provides a hardware solution for
driving an external SCSI activity LED.
GPIO[4:2]
GPIO Enable
[4:2]
The general purpose control corresponds to bits [4:2] in
the General Purpose (GPREG) register and to the
GPIO4–GPIO2 pins. GPIO4 powers-up as a general
purpose output. GPIO[3:2] power-up as general purpose
inputs.
SCSI Registers
4-77
GPIO[1:0]
GPIO Enable
[1:0]
These bits are set at power-up causing the GPIO1 and
GPIO0 pins to become inputs. Clearing these bits cause
GPIO[1:0] to become outputs.
Register: 0x48
SCSI Timer Zero (STIME0)
Read/Write
7
4
3
0
HTH[3:0]
0
HTH[3:0]
4-78
Registers
0
SEL[3:0]
0
0
0
0
0
0
Handshake-to-Handshake Timer Period
[7:4]
These bits select the handshake-to-handshake time-out
period, which is the maximum time between SCSI
handshakes (SREQ/ to SREQ/ in target mode; or, SACK/
to SACK/ in the initiator mode). When this timing is
exceeded, an interrupt is generated and the HTH bit in
the SCSI Interrupt Status One (SIST1) register is set.
The following table contains time-out periods for the
Handshake-to-Handshake Timer, the
Selection/Reselection Timer (bits [3:0]), and the General
Purpose Timer (SCSI Timer One (STIME1) bits [3:0]).
For a more detailed explanation of interrupts, refer to
Chapter 2, “Functional Description.”
HTH[3:0], SEL[3:0]
Minimum Time-Out
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Disabled
125 µs
250 µs
500 µs
1 ms
2 ms
4 ms
8 ms
16 ms
32 ms
64 ms
128 ms
256 ms
512 ms
1.024 s
2.048 s
SEL[3:0]
Selection Time-Out
[3:0]
These bits select the SCSI selection/reselection time-out
period. When this timing (plus the 200 µs selection abort
time) is exceeded, the STO bit in the SCSI Interrupt
Status One (SIST1) register is set. For a more detailed
explanation of interrupts, refer to Chapter 2, “Functional
Description.”
Register: 0x49
SCSI Timer One (STIME1)
Read/Write
7
6
5
4
R
HTHBA
GENSF
HTHSF
x
0
0
0
3
0
GEN[3:0]
0
0
0
0
R
Reserved
7
HTHBA
Handshake-to-Handshake Timer Bus Activity
Enable
6
Setting this bit causes this timer to begin testing for SCSI
REQ/ and ACK/ activity as soon as SBSY/ is asserted,
regardless of the agents participating in the transfer.
GENSF
General Purpose Timer Scale Factor
5
Setting this bit causes this timer to shift by a factor of 16.
Refer to the SCSI Timer Zero (STIME0) register
description for details.
Minimum Time-out
SCSI Registers
HTH[3:0], SEL[3:0], GEN[3:0]
HTHSF = 0,
GENSF = 0
HTHSF = 1,
GENSF = 1
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
Disabled
125 µs
250 µs
500 µs
1 µs
2 ms
4 ms
8 ms
16 ms
32 ms
64 ms
Disabled
2 ms
4 ms
8 ms
16 ms
32 ms
64 ms
128 ms
256 ms
512 ms
1s
4-79
Minimum Time-out
HTH[3:0], SEL[3:0], GEN[3:0]
HTHSF = 0,
GENSF = 0
HTHSF = 1,
GENSF = 1
1011
1100
1101
1110
1111
128 ms
256 ms
512 ms
1.024 s
2.048 s
2s
4.1 s
8.2 s
16.4 s
32.8 s
HTHSF
Handshake to Handshake Timer Scale Factor
4
Setting this bit causes this timer to shift by a factor of 16.
Refer to the SCSI Timer Zero (STIME0) register
description for details.
GEN[3:0]
General Purpose Timer Period
[3:0]
These bits select the period of the general purpose timer.
The time measured is the time between enabling and
disabling of the timer. When this timing is exceeded, the
GEN bit in the SCSI Interrupt Status One (SIST1) register
is set. Refer to the table under SCSI Timer Zero
(STIME0), bits [3:0], for the available time-out periods.
Note:
To reset a timer before it expires and obtain repeatable
delays, the time value must be written to zero first, and then
written back to the desired value. This is also required
when changing from one time value to another.
Register: 0x4A
Response ID Zero (RESPID0)
Read/Write
7
0
RESPID0
x
RESPID0
4-80
Registers
x
x
x
x
x
x
x
Response ID Zero
[7:0]
RESPID0 and Response ID One (RESPID1) contain the
selection or reselection IDs. These two 8-bit registers
contain the SCSI ID that the chip responds to on the
SCSI bus. Each bit represents one possible ID; the most
significant bit of Response ID One (RESPID1) represents
ID 15, and the least significant bit of RESPID0 represents
ID 0. The SCSI Chip ID (SCID) register still contains the
chip ID used during arbitration. The chip can respond to
more than one ID because more than one bit can be set
in the RESPID1 and RESPID0 registers. However, the
chip can arbitrate with only one ID value in the SCSI Chip
ID (SCID) register.
Register: 0x4B
Response ID One (RESPID1)
Read/Write
7
0
RESPID1
x
x
RESPID1
x
x
x
x
x
x
Response ID One
[7:0]
Response ID Zero (RESPID0) and RESPID1 contain the
selection or reselection IDs. These two 8-bit registers
contain the SCSI ID that the chip responds to on the
SCSI bus. Each bit represents one possible ID; the most
significant bit of RESPID1 represents ID 15, and the least
significant bit of RESPID0 represents ID 0. The SCID
register still contains the chip ID used during arbitration.
The chip can respond to more than one ID because more
than one bit can be set in the RESPID1 and RESPID0
registers. However, the chip can arbitrate with only one
ID value in the SCSI Chip ID (SCID) register.
Register: 0x4C
SCSI Test Zero (STEST0)
Read Only
7
4
SSAID[3:0]
0
0
SSAID[3:0]
SCSI Registers
0
0
3
2
1
0
SLT
ART
SOZ
SOM
0
x
1
1
SCSI Selected As ID
[7:4]
These bits contain the encoded value of the SCSI ID that
the LSI53C1000 is selected or reselected as during a
SCSI Selection or Reselection phase. These bits are
read only and contain the encoded value of 16 possible
IDs that could be used to select the LSI53C1000. During
a SCSI Selection or Reselection phase when a valid ID
4-81
is put on the bus, and the LSI53C1000 responds to that
ID, the “selected as” ID is written into these bits. These
bits are used with Response ID Zero (RESPID0) and
Response ID One (RESPID1) registers to allow response
to multiple IDs on the bus.
4-82
SLT
Selection Response Logic Test
3
This bit is set when the LSI53C1000 is ready to be
selected or reselected. This does not take into account
the bus settle delay of 400 ns. This bit is used for
functional test and fault purposes.
ART
Arbitration Priority Encoder Test
2
This bit is always set when the LSI53C1000 exhibits the
highest priority ID asserted on the SCSI bus during
arbitration. It is primarily used for chip level testing. It may
be used during low level mode operation to determine if
the LSI53C1000 won arbitration.
SOZ
SCSI Synchronous Offset Zero
1
This bit indicates that the current synchronous SREQ/,
SACK/ offset is zero. This bit is not latched and may
change at any time. It is used in low level synchronous
SCSI operations. When this bit is set and if the
LSI53C1000 is functioning as an initiator, then it is waiting for the target to request data transfers. When this bit
is set and if the LSI53C1000 is functioning as a target,
then the initiator has sent the offset number of acknowledges.
SOM
SCSI Synchronous Offset Maximum
0
This bit indicates that the current synchronous SREQ/,
SACK/ offset is the maximum specified by bits [5:0] in the
SCSI Transfer (SXFER) register. This bit is not latched
and may change at any time. It is used in low level
synchronous SCSI operations. If this bit is set, and if the
LSI53C1000 is functioning as a target, it is waiting for the
initiator to acknowledge the data transfers. If the
LSI53C1000 is functioning as an initiator, the target has
sent the offset number of requests.
Registers
Register: 0x4D
SCSI Test One (STEST1)
Read/Write
7
6
R
0
0
5
4
3
2
DOSGE
DISGE
QEN
QSEL
0
0
0
0
1
0
IRM[1:0]
0
0
R
Reserved
DOSGE
Disable Outbound SCSI Gross Errors
5
When set, this bit disables all SCSI gross errors related
to outbound data transfers.
DISGE
Disable Inbound SCSI Gross Errors
4
When set, this bit disables all SCSI gross errors related
to inbound data transfers.
QEN
SCLK Quadrupler Enable
3
This bit, when set, powers up the internal clock
quadrupler circuit, which quadruples the SCLK 40 MHz
clock to the internal 160 MHz SCSI clock required for
Ultra2 and Ultra160 SCSI operation. When cleared, this
bit powers down the internal quadrupler circuit. Refer to
Chapter 2, “Functional Description,” for information
concerning the operation of the quadrupler.
QSEL
SCLK Quadrupler Select
2
This bit, when set, selects the output of the internal clock
quadrupler as the internal SCSI clock. When cleared, this
bit selects the clock presented on SCLK as the internal
SCSI clock. Refer to Chapter 2, “Functional Description,”
for information concerning the operation of the
quadrupler.
IRM[1:0]
Interrupt Routing Mode
[1:0]
The LSI53C1000 supports four different interrupt routing
modes. These modes are described in the following table.
Mode 0, the default mode, is compatible with RAID
upgrade products.
SCSI Registers
[7:6]
4-83
Mode
Bits [1:0]
Operation
0
00
If the INT_DIR/ input pin is low,
interrupts are signaled on ALT_INTA/.
Otherwise, interrupts are signaled on
both INTA/ and ALT_INTA/.
1
01
Interrupts are only signaled on INTA/,
not ALT_INTA/. The INT_DIR/ input
pin is ignored.
2
10
Interrupts are only signaled on
ALT_INTA/. The INT_DIR/ input pin is
ignored.
3
11
Interrupts are signaled on both INTA/
and ALT_INTA/. The INT_DIR input
pin is ignored.
Register: 0x4E
SCSI Test Two (STEST2)
Read/Write
7
6
SCE
ROF
0
0
SCE
4
R
0
3
2
SZM
0
0
1
R
0
0
LOW
0
0
SCSI Control Enable
7
Setting this bit allows assertion of all SCSI control and
data lines through the SCSI Output Control Latch (SOCL)
and SCSI Output Data Latch (SODL) registers regardless
of whether the LSI53C1000 is configured as a target or
initiator.
Note:
ROF
4-84
5
Registers
Do not set this bit during normal operation, since it could
cause contention on the SCSI bus. It is included for
diagnostic purposes only.
Reset SCSI Offset
6
Setting this bit clears any outstanding synchronous
SREQ/SACK offset. If a SCSI gross error occurs, set this
bit. This bit automatically clears itself after resetting the
synchronous offset.
R
Reserved
SZM
SCSI High Impedance Mode
3
Setting this bit places all the open drain 48 mA SCSI
drivers into a high impedance state.
R
Reserved
LOW
SCSI Low Level Mode
0
Setting this bit places the LSI53C1000 in the low level
mode. In this mode, no DMA operations occur and no
SCRIPTS execute. Arbitration and selection may be
performed by setting the start sequence bit as described
in the SCSI Control Zero (SCNTL0) register. SCSI bus
transfers are performed by manually asserting and polling
SCSI signals. Clearing this bit allows instructions to be
executed in the SCSI SCRIPTS mode.
Note:
[5:4]
[2:1]
It is not necessary to set this bit for access to the SCSI
bit-level registers (SCSI Output Data Latch (SODL), SCSI
Bus Control Lines (SBCL), and input registers).
Register: 0x4F
SCSI Test Three (STEST3)
Read/Write
7
6
5
4
3
2
1
0
TE
R
HSC
DSI
R
TTM
CSF
R
0
0
0
0
0
0
0
0
TE
SCSI Registers
TolerANT Enable
7
Setting this bit enables the active negation portion of
LSI Logic TolerANT technology. Active negation causes
the SCSI Request, Acknowledge, Data, and Parity
signals to be actively deasserted, instead of relying on
external pull-ups, when the LSI53C1000 is driving these
signals. Active deassertion of these signals occurs only
when the LSI53C1000 is in an information transfer phase.
When performing synchronous transfers, TolerANT
should be enabled to improve setup and deassertion
times. Active negation is disabled after reset or when this
bit is cleared. For more information on LSI Logic
TolerANT technology, see Chapter 1, “Introduction.”
4-85
4-86
R
Reserved
HSC
Halt SCSI Clock
5
Asserting this bit causes the internal divided SCSI clock
to come to a stop in a glitchless manner. This bit is used
for test purposes or to lower IDD during a power-down
mode. Refer to Chapter 2, “Functional Description,” for
operation of the SCSI clock quadrupler.
DSI
Disable Single Initiator Response
4
If this bit is set, the LSI53C1000 ignores all bus-initiated
selection attempts that employ the single-initiator option
from SCSI-1. In order to select the LSI53C1000 while this
bit is set, the LSI53C1000 SCSI ID and the initiator’s
SCSI ID must both be asserted. Assert this bit in SCSI-2
systems so that a single bit error on the SCSI bus is not
interpreted as a single initiator response.
R
Reserved
TTM
Timer Test Mode
2
Asserting this bit facilitates testing of the selection
time-out, general purpose, and handshake-to-handshake
timers by greatly reducing all three time-out periods.
Setting this bit starts all three timers. If the respective bits
in the SCSI Interrupt Enable One (SIEN1) register are
asserted, the LSI53C1000 generates interrupts at
time-out. This bit is intended for internal manufacturing
diagnosis and should not be used in normal operation.
CSF
Clear SCSI FIFO
1
Setting this bit causes the “full flags” for the SCSI FIFO
to be cleared. This empties the FIFO. This bit is
self-clearing. In addition to the SCSI FIFO pointers, the
SIDL, SODL, and SODR full bits in the SCSI Status Zero
(SSTAT0) and SCSI Status Two (SSTAT2) are cleared.
R
Reserved
Registers
6
3
0
Registers: 0x50–0x51
SCSI Input Data Latch (SIDL)
Read Only
15
0
SIDL
x
x
x
x
x
x
x
SIDL
x
x
x
x
x
x
x
x
x
SCSI Input Data Latch
[15:0]
This register is used primarily for diagnostic testing,
programmed I/O operation, or error recovery.
Asynchronous Data received from the SCSI bus can be
read from this register. When receiving asynchronous
SCSI data, the data flows into this register and out to the
host FIFO. This register differs from the SCSI Bus Data
Lines (SBDL) register; the SCSI Input Data Latch (SIDL)
contains latched data and the SCSI Bus Data Lines
(SBDL) always contains exactly what is currently on the
SCSI data bus. Reading this register causes the SCSI
parity bit to be checked, and causes a parity error
interrupt if the data is invalid. The power-up values are
indeterminate.
Register: 0x52
SCSI Test Four (STEST4)
Read Only
7
6
5
0
SMODE[1:0]
x
x
SMODE[1:0]
SCSI Registers
R
0
0
0
0
0
0
SCSI Mode
[7:6]
These bits contain the encoded value of the SCSI
operating mode that is indicated by the voltage level
sensed at the DIFFSENS pin. The incoming SCSI signal
goes to a pair of analog comparators that determine the
voltage window of the DIFFSENS signal. These voltage
windows indicate LVD, SE, or HVD operation. The bit
values are defined in the following table. When the HVD
mode is detected, all of the LSI53C1000 3-state outputs
go to the high impedance state.
4-87
SMODE [1:0]
Operating Mode
00
01
10
11
R
Reserved
High Impedance State
SE
LVD SCSI
Reserved
[5:0]
Register: 0x53
Current Inbound SCSI Offset (CSO)
Read Only
7
6
R
0
0
5
4
3
2
1
0
CSO5
CSO4
CSO3
CSO2
CSO1
CSO0
0
0
0
0
0
0
R
Reserved
[7:6]
CSO[5:0]
Current SCSI Offset
[5:0]
These bits indicate the SCSI offset for synchronous
inbound transfers. This also represents the number of
data bytes in the SCSI FIFO in narrow transfer modes
and half the number of bytes in wide transfer mode. This
does not include any CRC or PAD bytes that may be in
the FIFO.
Registers: 0x54–0x55
SCSI Output Data Latch (SODL)
Read/Write
15
0
SODL
x
x
x
x
x
SODL
4-88
Registers
x
x
x
x
x
x
x
x
x
x
x
SCSI Output Data Latch
[15:0]
This register is used primarily for diagnostic testing and
programmed I/O operations. Data written to this register
is asserted on the SCSI data bus by setting the Assert
Data Bus bit in the SCSI Control One (SCNTL1) register.
This register is used to send data using programmed I/O.
Data flows through this register when sending data in
asynchronous mode. It is also used to write to the
synchronous data FIFO when testing the chip. The
power-up value of this register is indeterminate.
Register: 0x56
Chip Control Zero (CCNTL0)
Read/Write
7
6
5
4
ENPMJ
PMJCTL
ENNDJ
DISFC
0
0
0
0
ENPMJ
3
2
R
x
x
1
0
DISRC
R
0
x
Enable Phase Mismatch Jump
7
Upon setting this bit, any phase mismatches do not
interrupt but force a jump to an alternate location to
handle the phase mismatch. Prior to actually taking the
jump, the appropriate remaining byte counts and
addresses are calculated to facilitate storage.
In the case of a SCSI send, any data in the part will be
automatically cleared after being accounted for. In the
case of a SCSI receive, all data will be flushed out of the
part and accounted for prior to taking the jump. This
feature does not cover, however, the byte that may
appear in SCSI Wide Residue (SWIDE). This byte must
be flushed manually.
This bit also enables the flushing mechanism to flush
data during a Data-In phase mismatch in a more efficient
manner.
PMJCTL
SCSI Registers
Jump Control
6
This bit controls which decision mechanism is used when
jumping on phase mismatch. When this bit is cleared, the
LSI53C1000 will use Phase Mismatch Jump Address
One (PMJAD1) when the WSR bit is cleared and Phase
Mismatch Jump Address Two (PMJAD2) when the WSR
bit is set. When this bit is set, the LSI53C1000 will use
Phase Mismatch Jump Address One (PMJAD1) on
Data-Out (Data-Out, Command, Message-Out) transfers
and Phase Mismatch Jump Address Two (PMJAD2) on
Data-In (Data-In, Status, Message-In) transfers. The
4-89
phase referred to here is the phase encoded in the block
move SCRIPTS instruction, not the phase on the SCSI
bus that caused the phase mismatch.
ENNDJ
Enable Jump On Nondata Phase Mismatches
5
This bit controls whether or not a jump is taken during a
nondata phase mismatch (Message-In, Message-Out,
Status, or Command). When this bit is cleared, jumps will
only be taken on Data-In or Data-Out phases, and a
phase mismatch interrupt will be generated for all other
phases. When this bit is set, jumps will be taken
regardless of the phase in the block move. Note that the
phase referred to here is the phase encoded in the block
move SCRIPTS instruction, not the phase on the SCSI
bus that caused the phase mismatch.
DISFC
Disable Auto FIFO Clear
4
This bit controls whether or not the FIFO is automatically
cleared during a Data-Out phase mismatch. When set,
data in the DMA FIFO and data in the SCSI Output Data
Latch (SODL) and SODR (a hidden buffer register which
is not accessible) registers are not cleared after
calculations on them are complete. When cleared, the
DMA FIFO, SODL, and SODR are automatically cleared.
This bit also disables the enhanced flushing mechanism.
R
Reserved
DISRC
Disable Internal SCRIPTS RAM Cycles
1
This bit controls whether or not data transfers, for which
the source/destination is located in SCRIPTS RAM,
generate external PCI cycles.
[3:2]
If cleared, data transfers of this type do NOT generate
PCI cycles and stay internal to the chip. If set, data
transfers of this type generate PCI cycles. This does not
affect SCRIPTS Fetch operations from SCRIPTS RAM,
including Table Indirect and Indirect opcode fetches.
R
4-90
Registers
Reserved
0
Register: 0x57
Chip Control One (CCNTL1)
Read/Write
7
6
5
4
PULLDIS PULLEN DIS64MAS DIS64SLV
0
0
0
0
3
DDAC
x
2
1
0
64TIMOD EN64TIBMV EN64DBMV
x
0
0
PULLDIS
Pull Disable
7
Setting this bit causes all internal pulls to be disabled on
all pins. This bit is intended for manufacturing test only
and should NOT be set for normal operation. PULLDIS
has precedence over PULLEN if both bits are set.
PULLEN
Pull Enable
6
Setting this bit causes all internal pulls to be enabled on
all pins. This bit is intended for manufacturing test only
and should NOT be set for normal operation.
DIS64MAS
Disable 64-bit Master Operation
Setting this bit causes the LSI53C1000 to no longer
request 64-bit master data transfers. If this bit is set,
64-bit data transfers will be disabled for all master
transactions.
DIS64SLV
Disable 64-bit Slave Cycles
4
Setting this bit disables 64-bit slave data transfers to the
SCRIPT RAM. This causes only 32-bit data transfers to
occur.
DDAC
Disable Dual Address Cycle
3
When this bit is set, all 64-bit addressing as a master is
disabled. No dual address cycles will be generated by the
LSI53C1000.
5
When this bit is cleared, the LSI53C1000 generates dual
address cycles based on the master operation performed
and the value of its associated selector register.
64TIMOD
SCSI Registers
64-bit Table Indirect Indexing Mode
2
When this bit is cleared, bits [28:24] of the first table entry
Dword will select one of 22 possible selectors to be used
in a BMOV operation. When this bit is set, bits [31:24] of
the first table entry Dword will be copied directly into
4-91
DMA Next Address 64 (DNAD64) to provide 40-bit
addressing capability. This bit will only function if the
EN64TIBMV bit is set.
Index Mode 0 (64TIMOD clear) table entry format:
[31:29]
[28:24]
[23:0]
Reserved
Sel Index
Byte Count
Source/Destination Address [31:0]
Index Mode 1 (64TIMOD set) table entry format:
[31:24]
[23:0]
Src/Dest Addr [39:32]
Byte Count
Source/Destination Address [31:0]
EN64TIBMV
Enable 64-bit Table Indirect BMOV
1
Setting this bit enables 64-bit addressing for Table
Indirect BMOVs using the upper byte (bits [31:24]) of the
first Dword of the table entry. When this bit is cleared,
Table Indirect BMOVs use the Static Block Move Selector
(SBMS) register to obtain the upper 32 bits of the data
address.
EN64DBMV
Enable 64-bit Direct BMOV
0
Setting this bit enables the 64-bit version of a direct
BMOV. When this bit is cleared, direct BMOVs use the
Static Block Move Selector (SBMS) register to obtain the
upper 32 bits of the data address.
Registers: 0x58–0x59
SCSI Bus Data Lines (SBDL)
Read Only
15
0
SBDL
0
0
0
0
0
SBDL
4-92
Registers
0
0
0
0
0
0
0
0
0
0
0
SCSI Bus Data Lines
[15:0]
This register contains the SCSI data bus status. Even
though the SCSI data bus is active low, these bits are
active high. The signal status is not latched and is a true
representation of exactly what is on the data bus at the
time the register is read. This register is used when
receiving data using programmed I/O. This register can
also be used for diagnostic testing or in the low level
mode. The power-up value of this register is
indeterminate.
If the chip is in wide mode (SCSI Control Three
(SCNTL3), bit 3 is set) and SCSI Bus Data Lines (SBDL)
register is read, both byte lanes are checked for parity
regardless of phase. When in a nondata phase, this will
cause a parity error interrupt to be generated because
the upper byte lane parity is invalid.
Register: 0x5A
Chip Control Two (CCNTL2)
Read/Write
7
6
0
ShSGE
R
0
x
x
x
x
x
x
x
ShSGE
Enable Shadowed SGE Register
7
Setting this bit allows access to the SGE Status registers
shadowed behind SIST0 and SIST1.
R
Reserved
[6:0]
Register: 0x5B
Chip Control Three (CCNTL3)
Read/Write
7
5
R
0
0
4
ENDSKEW
0
0
3
2
DSKEW[1:0]
0
0
1
0
LVDDL[1:0]
0
0
R
Reserved
ENDSKEW
Enable REQ/ACK to Data Skew Control
4
Setting this bit enables the control of the relative skew
between the SCSI REQ/ACK signals and the data
signals. The actual amount of skew time is controlled by
DSKEW[1:0] in this register.
SCSI Registers
[7:5]
4-93
DSKEW[1:0]
Note:
Setup Data Skew Control
[3:2]
These bits control the amount of skew between the SCSI
REQ/ACK signal and the SCSI data signals during setup.
The skew is affected only if the ENDSKEW bit is set.
These bits are used for Ultra160 SCSI Domain Validation
only and should not be set during normal data transfer
operations.
LVDDL[1:0]
Note:
LVD Drive Strength Select
[1:0]
These bits control the drive level of the LVD pad drivers.
This feature is for Ultra160 SCSI Domain Validation testing
environments only and should not be set during normal
data transfer operations.
The table below shows the relative strength increase or
decrease based on the LVDDL values.
LVDDL
Drive Level
00
01
10
11
Nominal
−20% Nominal
+20% Nominal
Reserved
Registers: 0x5C–0x5F
Scratch Register B (SCRATCHB)
Read/Write
31
0
SCRATCHB
0
0
0
0
0
0
0
0
0
0
0
SCRATCHB
4-94
Registers
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Scratch Register B
[31:0]
This is a general purpose user definable scratch pad
register. Apart from CPU access, only register
Read/Write and Memory Moves directed at the
SCRATCH register will alter its contents. The power-up
values are indeterminate. A special mode of this register
can be enabled by setting the PCI Configuration Info
Enable bit in the Chip Test Two (CTEST2) register. If this
bit is set, bits [31:13] of the Scratch Register B
(SCRATCHB) register return bits [31:13] of the PCI Base
Address Register Three (BAR3) (SCRIPTS RAM). In this
mode, bits [12:0] of SCRATCH B will always return zeros.
Writes to the SCRATCH B register have no effect.
Resetting the PCI Configuration Info Enable bit causes
the SCRATCH B register to return to normal operation.
Registers: 0x60–0x9F
Scratch Registers C–R (SCRATCHC–SCRATCHR)
Read/Write
These are general purpose user definable scratch pad registers. Apart
from CPU access, only register Read/Write, Memory Moves, and
Load/Stores directed at a SCRATCH register alter its contents. The
power-up values are indeterminate.
Registers: 0xA0–0xA3
Memory Move Read Selector (MMRS)
Read/Write
31
0
MMRS
0
0
0
0
0
0
0
0
0
0
0
0
MMRS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Memory Move Read Selector
[31:0]
This register supplies AD[63:32] for data read operations
during Memory-to-Memory Moves and absolute address
LOAD operations.
A special mode of this register can be enabled by setting
the PCI Configuration Info Enable bit in the Chip Test Two
(CTEST2) register. If this bit is set, the Memory Move
Read Selector (MMRS) register returns bits [31:0] of the
memory mapped operating register, PCI Base Address
Register Two (BAR2) (MEMORY), when read. In this
mode, writes to the MMRS register affect no change.
Clearing the PCI Configuration Info Enable bit causes the
MMRS register to return to normal operation.
SCSI Registers
4-95
Registers: 0xA4–0xA7
Memory Move Write Selector (MMWS)
Read/Write
31
0
MMWS
0
0
0
0
0
0
0
0
0
0
0
0
MMWS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Memory Move Write Selector
[31:0]
This register supplies AD[63:32] during data write
operations during Memory-to-Memory Moves and
absolute address STORE operations.
A special mode of this register can be enabled by setting
the PCI Configuration Info Enable bit in the Chip Test Two
(CTEST2) register. If this bit is set, the MMWS register
returns bits [31:0] of the SCRIPT RAM PCI Base Address
Register Four (BAR4) (SCRIPTS RAM) in bits [31:0] of
the MMWS register when read. In this mode, writes to the
MMWS register affect no change. Clearing the PCI
Configuration Info Enable bit causes the MMWS register
to return to normal operation.
Registers: 0xA8–0xAB
SCRIPT Fetch Selector (SFS)
Read/Write
31
0
SFS
0
0
0
0
0
0
0
0
0
0
SFS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SCRIPT Fetch Selector
[31:0]
This register supplies AD[63:32] during SCRIPT Fetches
and Indirect Fetches (excluding Table Indirect Fetches).
This register can be loaded automatically using a 64-bit
jump instruction.
A special mode of this register can be enabled by setting
the PCI Configuration Info Enable bit in the Chip Test Two
(CTEST2) register. If this bit is set, bits [23:16] of this
register return the PCI Revision ID (RID) register value
and bits [15:0] return the PCI Device ID register value
when read.
4-96
Registers
Writes to the SCRIPT Fetch Selector (SFS) register are
unaffected. Clearing the PCI Configuration Info Enable bit
causes the SFS register to return to normal operation.
Registers: 0xAC–0xAF
DSA Relative Selector (DRS)
Read/Write
31
0
DRS
0
0
0
0
0
0
0
0
0
0
0
0
DRS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DSA Relative Selector
[31:0]
This register supplies AD[63:32] during Table Indirect
Fetches and Load and Store Data Structure Address
(DSA) relative operations.
Registers: 0xB0–0xB3
Static Block Move Selector (SBMS)
Read/Write
31
0
SBMS
0
0
0
0
0
0
0
0
0
0
0
0
SBMS
SCSI Registers
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Static Block Move Selector
[31:0]
This register supplies AD[63:32] during block move
operations, reads, or writes. This register is static and is
not changed when a 64-bit direct BMOV is used.
4-97
Registers: 0xB4–0xB7
Dynamic Block Move Selector (DBMS)
Read/Write
31
0
DBMS
0
0
0
0
0
0
0
0
0
0
0
0
DBMS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Dynamic Block Move Selector
[31:0]
This register supplies AD[63:32] during block move
operations, reads, or writes. This register is used only
during 64-bit direct BMOV instructions. It is reloaded with
the upper 32-bit data address upon execution of 64-bit
direct BMOVs.
Registers: 0xB8–0xBB
DMA Next Address 64 (DNAD64)
Read/Write
31
0
DNAD64
0
0
0
0
0
0
0
0
0
0
0
DNAD64
Note:
4-98
Registers
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DMA Next Address 64
[31:0]
This register holds the current selector being used in a
host transaction. The appropriate selector is copied to
this register prior to beginning the host transaction.
The crossing of selector boundaries in one memory
operation is not supported.
Register: 0xBC
SCSI Control Four (SCNTL4)
Read/Write
7
6
5
U3EN
AIPCKEN
0
0
4
R
0
3
2
1
0
XCLKH_DT XCLKH_ST XCLKS_DT XCLKS_ST
0
0
0
0
0
This register is automatically loaded when a Table Indirect Select or
Reselect SCRIPTS instruction is executed.
U3EN
Ultra160 Transfer Enable
7
Setting this bit enables Ultra160 transfers. This bit will
force all SCSI Block Move SCRIPTS instructions for ST
Data-In or ST Data-Out phases to become DT Data-In or
DT Data-Out phases.
AIPCKEN
AIP Checking Enable
6
Setting this bit enables the AIP (Asynchronous
Information Protection) checking of the upper byte lane of
protection information during Command, Status, and
Message phases. By default, AIP codes are generated
on the SCSI bus during all asynchronous transfers. To
disable this feature set bit 3, the Disable AIP Code
Generation bit, in AIP Control One (AIPCNTL1).
R
Reserved
XCLKH_DT
Extra Clock of Data Hold on DT Transfer Edge
3
Setting this bit adds a clock of data hold to synchronous
DT SCSI transfers on the DT edge. This bit only impacts
DT transfers as it affects data hold to the DT edge.
Setting this bit reduces the synchronous transfer send
rate but does not reduce the transfer rate at which the
LSI53C1000 can receive inbound REQs, ACKs or data.
Refer to Table 4.4 and Table 4.5 for a summary of
available transfer rates and to Figure 4.1 through
Figure 4.3 for examples of how the XCLKH bits function.
Note:
[5:4]
This bit does not affect CRC timings.
XCLKH_ST
SCSI Registers
Extra Clock of Data Hold on ST Transfer Edge
2
Setting this bit adds a clock of data hold to synchronous
DT or ST SCSI transfers on the ST edge. This bit impacts
4-99
both ST and DT transfers as it affects data hold to the ST
edge. Setting this bit reduces the synchronous send
transfer rate but does not reduce the transfer rate at
which the LSI53C1000 can receive inbound REQs, ACKs
or data. Refer to Table 4.4 and Table 4.5 for a summary
of available transfer rates and to Figure 4.1 through
Figure 4.3 for examples of how the XCLKH bits function.
Note:
XCLKS_DT
Note:
XCLKS_ST
Note:
This bit does not affect CRC timings.
Extra Clock of Data Setup on DT Transfer Edge
1
Setting this bit adds a clock of data setup to synchronous
DT SCSI transfers on the DT edge. This bit only impacts
DT transfers as it only affects data setup to the DT edge.
Setting this bit reduces the synchronous transfer send
rate but does not reduce the transfer rate at which the
LSI53C1000 can receive inbound REQs, ACKs or data.
Refer to Table 4.4 and Table 4.5 for a summary of
available transfer rates and to Figure 4.1 through
Figure 4.3 for examples of how the XCLKS bits function.
This bit does not affect CRC timings.
Extra Clock of Data Setup on ST Transfer Edge
0
Setting this bit adds a clock of data setup to synchronous
DT or ST SCSI transfers on the ST edge. This bit impacts
both ST and DT transfers as it affects data setup to the
ST edge. Setting this bit reduces the synchronous send
transfer rate but does not reduce the transfer rate at
which the LSI53C1000 can receive inbound REQs, ACKs
or data. Refer to Table 4.4 and Table 4.5 for a summary
of available transfer rates and to Figure 4.1 through
Figure 4.3 for examples of how the XCLKS bits function.
This bit does not affect CRC timings.
Synchronous Receive Rate Calculation
The synchronous receive rate, in megatransfers/s, can be
calculated using the following formula:
Input Clock Rate
Receive Rate (DT) = -------------------------------------------SCF Divisor × 2
Input Clock Rate
Receive Rate (ST) = -------------------------------------------SCF Divisor × 4
4-100
Registers
Note:
The receive rate is independent of the settings of the
XCLKS_DT, XCLKS_ST, XCLKH_DT, and XCLKH_ST bits.
Synchronous Send Rate Calculation
The synchronous send rate, in megatransfers/s, can be
calculated using the following formula:
Input Clock Rate
Send Rate (DT) = -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
XCLKS_DT + XCLKS_ST+XCLKH_DT+XCLKH_ST
 SCFDivisor ×  2 + ------------------------------------------------------------------------------------------------------------------------------------------  
2

Input Clock Rate
Send Rate (ST) = -----------------------------------------------------------------------------------------------------------------------SCFDivisor × ( 4 + XCLKS_ST + XCLKH_ST )
SCSI Registers
4-101
Figure 4.1
Single Transition Transfer Waveforms
CLK1
REQ/ACK
DATA
XCLKS_ST = 0
XCLKH_ST = 0
CLK1
REQ/ACK
DATA
XCLKS_ST = 1
XCLKH_ST = 0
CLK1
REQ/ACK
DATA
XCLKS_ST = 0
XCLKH_ST = 1
CLK1
REQ/ACK
DATA
1. CLK = SCLK/SCF Divisor
4-102
Registers
XCLKS_ST = 1
XCLKH_ST = 1
Figure 4.2
DT Transfer Waveforms (XCLKS Examples)
CLK1
REQ/ACK
DATA
XCLKS_DT = 0/XCLKS_ST = 0
XCLKH_DT = 0/XCLKH_ST = 0
CLK1
REQ/ACK
DATA
XCLKS_DT = 0/XCLKS_ST = 1
XCLKH_DT = 0/XCLKH_ST = 0
CLK1
REQ/ACK
DATA
XCLKS_DT = 1/XCLKS_ST = 0
XCLKH_DT = 0/XCLKH_ST = 0
CLK1
REQ/ACK
DATA
XCLKS_DT = 1/XCLKS_ST = 1
XCLKH_DT = 0/XCLKH_ST = 0
1. CLK = SCLK/SCF Divisor
SCSI Registers
4-103
Figure 4.3
DT Transfer Waveforms (XCLKH Examples)
CLK1
REQ/ACK
DATA
XCLKS_DT = 0 / XCLKS_ST = 0
XCLKH_DT = 1 / XCLKH_ST = 0
CLK1
REQ/ACK
DATA
XCLKS_DT = 0 / XCLKS_ST = 0
XCLKH_DT = 0 / XCLKH_ST = 1
CLK1
REQ/ACK
DATA
XCLKS_DT = 0 / XCLKS_ST = 0
XCLKH_DT = 1 / XCLKH_ST = 1
CLK1
REQ/ACK
DATA
XCLKS_DT = 1 / XCLKS_ST = 1
XCLKH_DT = 1 / XCLKH_ST = 1
1. CLK = SCLK/SCF Divisor
4-104
Registers
Table 4.4
DT Transfer Rates
Clock Diviso Number Base Period
Receive Rate
Send Rate
(MHz)
r
Xclks1
(ns)
(Megatransfers/s) (Megatransfers/s)
160
160
160
160
160
160
160
160
160
160
160
160
160
160
160
160
160
160
160
160
160
160
160
160
160
160
160
160
160
160
160
160
160
160
160
40
40
40
40
1
1
1
1
1
1.5
1.5
1.5
1.5
1.5
2
2
2
2
2
3
3
3
3
3
4
4
4
4
4
6
6
6
6
6
8
8
8
8
8
1
1
1
1
SCSI Registers
0
1
2
3
4
0
1
2
3
4
0
1
2
3
4
0
1
2
3
4
0
1
2
3
4
0
1
2
3
4
0
1
2
3
4
0
1
2
3
6.25
6.25
6.25
6.25
6.25
9.38
9.38
9.38
9.38
9.38
12.50
12.50
12.50
12.50
12.50
18.75
18.75
18.75
18.75
18.75
25.00
25.00
25.00
25.00
25.00
37.50
37.50
37.50
37.50
37.50
50.00
50.00
50.00
50.00
50.00
25.00
25.00
25.00
25.00
80.00
80.00
80.00
80.00
80.00
53.33
53.33
53.33
53.33
53.33
40.00
40.00
40.00
40.00
40.00
26.67
26.67
26.67
26.67
26.67
20.00
20.00
20.00
20.00
20.00
13.33
13.33
13.33
13.33
13.33
10.00
10.00
10.00
10.00
10.00
20.00
20.00
20.00
20.00
80.00
64.00
53.33
45.71
40.00
53.33
42.67
35.56
30.48
26.67
40.00
32.00
26.67
22.86
20.00
26.67
21.33
17.78
15.24
13.33
20.00
16.00
13.33
11.43
10.00
13.33
10.67
8.89
7.62
6.67
10.00
8.00
6.67
5.71
5.00
20.00
16.00
13.33
11.43
4-105
Table 4.4
DT Transfer Rates (Cont.)
Clock Diviso Number Base Period
Receive Rate
Send Rate
(MHz)
r
Xclks1
(ns)
(Megatransfers/s) (Megatransfers/s)
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
1
1.5
1.5
1.5
1.5
1.5
2
2
2
2
2
3
3
3
3
3
4
4
4
4
4
8
8
8
8
8
4
0
1
2
3
4
0
1
2
3
4
0
1
2
3
4
0
1
2
3
4
0
1
2
3
4
25.00
37.50
37.50
37.50
37.50
37.50
50.00
50.00
50.00
50.00
50.00
75.00
75.00
75.00
75.00
75.00
100.00
100.00
100.00
100.00
100.00
200.00
200.00
200.00
200.00
200.00
20.00
13.33
13.33
13.33
13.33
13.33
10.00
10.00
10.00
10.00
10.00
6.67
6.67
6.67
6.67
6.67
5.00
5.00
5.00
5.00
5.00
2.50
2.50
2.50
2.50
2.50
10.00
13.33
10.67
8.89
7.62
6.67
10.00
8.00
6.67
5.71
5.00
6.67
5.33
4.44
3.81
3.33
5.00
4.00
3.33
2.86
2.50
2.50
2.00
1.67
1.43
1.25
1. Number Xclks = XCLKS_DT + XCLKS_ST + XCLKH_DT + XCLKH_ST
Table 4.5
Single Transition Transfer Rates
Clock Diviso Number Base Period
Receive Rate
Send Rate
(MHz)
r
Xclks1
(ns)
(Megatransfers/s) (Megatransfers/s)
160
160
160
160
160
160
160
4-106
Registers
1
1
1
1.5
1.5
1.5
2
0
1
2
0
1
2
0
6.25
6.25
6.25
9.38
9.38
9.38
12.50
40.00
40.00
40.00
26.67
26.67
26.67
20.00
40.00
32.00
26.67
26.67
21.33
17.78
20.00
Table 4.5
Single Transition Transfer Rates (Cont.)
Clock Diviso Number Base Period
Receive Rate
Send Rate
(MHz)
r
Xclks1
(ns)
(Megatransfers/s) (Megatransfers/s)
160
160
160
160
160
160
160
160
160
160
160
160
160
160
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
2
2
3
3
3
4
4
4
6
6
6
8
8
8
1
1
1
1.5
1.5
1.5
2
2
2
3
3
3
4
4
4
6
6
6
8
8
8
1
2
0
1
2
0
1
2
0
1
2
0
1
2
0
1
2
0
1
2
0
1
2
0
1
2
0
1
2
0
1
2
0
1
2
12.50
12.50
18.75
18.75
18.75
25.00
25.00
25.00
37.50
37.50
37.50
50.00
50.00
50.00
25.00
25.00
25.00
37.50
37.50
37.50
50.00
50.00
50.00
75.00
75.00
75.00
100.00
100.00
100.00
150.00
150.00
150.00
200.00
200.00
200.00
20.00
20.00
13.33
13.33
13.33
10.00
10.00
10.00
6.67
6.67
6.67
5.00
5.00
5.00
10.00
10.00
10.00
6.67
6.67
6.67
5.00
5.00
5.00
3.33
3.33
3.33
2.50
2.50
2.50
1.67
1.67
1.67
1.25
1.25
1.25
16.00
13.33
13.33
10.67
8.89
10.00
8.00
6.67
6.67
5.33
4.44
5.00
4.00
3.33
10.00
8.00
6.67
6.67
5.33
4.44
5.00
4.00
3.33
3.33
2.67
2.22
2.50
2.00
1.67
1.67
1.33
1.11
1.25
1.00
0.83
1. Number Xclks = XCLKS_ST + XCLKH_ST
SCSI Registers
4-107
Register: 0xBD
Reserved
7
0
R
x
x
x
x
x
x
x
x
This register is reserved.
Register: 0xBE
AIP Control Zero (AIPCNTL0)
Read Only
7
3
R
0
0
R
0
Reserved
0
0
2
1
0
AIPERR_LIVE
AIPERR
PARITYERR
0
0
0
[7:3]
AIPERR_LIVE
AIP Error Status Live
2
This bit represents the live error status for the AIP
checking logic. A high indicates an error while low
indicates no error. This is not a latched value; therefore,
an error could have occurred previously and not be
indicated by this bit.
This bit indicates the AIP error status whether or not AIP
checking is enabled. This bit may indicate false errors
and should not be used except for diagnostic purposes
and when AIP Checking is enabled.
AIPERR
AIP Error Status
1
This bit represents the error status for the AIP checking
logic. This bit is set upon an AIP error and cleared either
when the interrupt is cleared or the RAIPER bit is set in
the AIP Control One (AIPCNTL1) register.
This bit indicates the AIP error status whether or not AIP
checking is enabled. Therefore, only use this bit when
AIP checking is enabled.
4-108
Registers
PARITYERR
Parity Error Status
0
This bit represents the error status for the parity error.
This bit is set upon a parity error and clears when the
interrupt clears.
Register: 0xBF
AIP Control One (AIPCNTL1)
Read/Write
7
4
R
0
0
0
0
3
2
1
0
DISAIP
RAIPERR
FBAIP
RSQ
0
0
0
0
R
Reserved
DISAIP
Disable AIP Code Generation
3
When set, this bit disables AIP code generation on the
SCSI bus. By default, AIP codes are generated on the
SCSI bus during all asynchronous transfers.
RAIPERR
Reset AIP Error
2
This bit allows an AIP error condition to be reset
manually. Setting this bit clears the AIP error status in
bit 1 of AIP Control Zero (AIPCNTL0). Setting this bit
does not clear the live AIP error status in bit 0 of AIP
Control Zero (AIPCNTL0). The RAIPERR bit is not
self-clearing. It must be written back to zero.
FBAIP
Force Bad AIP Value
1
When set, this bit causes bad AIP values to be sent over
the SCSI bus.
RSQ
Reset AIP Sequence Value
0
When set, this bit causes the sequence value used in the
calculation of the protection code to be reset.
SCSI Registers
[7:4]
4-109
Registers: 0xC0–0xC3
Phase Mismatch Jump Address One (PMJAD1)
Read/Write
31
0
PMJAD1
0
0
0
0
0
0
0
0
0
0
0
0
PMJAD1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Phase Mismatch Jump Address One
[31:0]
This register contains the 32-bit address that is jumped
to upon a phase mismatch. Depending upon the state of
the PMJCTL bit, this address is either used during an
outbound (Data-Out, Command, Message-Out) phase
mismatch (PMJCTL = 0) or when the WSR bit is cleared
(PMJCTL = 1). This register is loaded with the address of
a SCRIPTS routine that updates the memory data
structures of the BMOV that was executing when the
phase mismatch occurred.
Registers: 0xC4–0xC7
Phase Mismatch Jump Address Two (PMJAD2)
Read/Write
31
0
PMJAD2
0
0
0
0
0
0
0
0
0
0
PMJAD2
4-110
Registers
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Phase Mismatch Jump Address Two
[31:0]
This register contains the 32-bit address that is jumped
to upon a phase mismatch. Depending upon the state of
the PMJCTL bit, this address is either used during an
inbound (Data-In, Status, Message-In) phase mismatch
(PMJCTL = 0) or when the WSR bit is set (PMJCTL = 1).
This register is loaded with the address of a SCRIPTS
routine that updates the memory data structures of the
BMOV that was executing when the phase mismatch
occurred.
Registers: 0xC8–0xCB
Remaining Byte Count (RBC)
Read/Write
31
0
RBC
0
0
0
0
0
0
0
0
0
0
0
0
RBC
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Remaining Byte Count
[31:0]
This register contains the byte count that remains for the
BMOV that was executing when the phase mismatch
occurred. In the case of Direct or Indirect BMOV
instructions, the upper byte of this register also contains
the opcode of the BMOV that was executing. In the case
of a Table Indirect BMOV instruction, the upper byte
contains the upper byte of the Table Indirect entry that
was fetched.
In the case of a SCSI data receive, this byte count
reflects all data received from the SCSI bus, including
any byte in SCSI Wide Residue (SWIDE). There is no
data remaining in the part that must be flushed to
memory with the exception of a possible byte in the
SWIDE register. That byte must be flushed to memory
manually in SCRIPTS.
In the case of a SCSI data send, this byte count reflects
all data sent out onto the SCSI bus. Any data left in the
part from the phase mismatch is ignored and
automatically cleared from the FIFOs.
Registers: 0xCC–0xCF
Updated Address (UA)
Read/Write
31
0
UA
0
0
0
0
0
0
0
0
0
0
0
0
UA
SCSI Registers
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Updated Address
[31:0]
This register contains the updated data address for the
BMOV that was executing when the phase mismatch
occurred.
4-111
In the case of a SCSI data receive, if there is a byte in
the SCSI Wide Residue (SWIDE) register then this
address points to the location where that byte must be
stored. The SWIDE byte must be manually written to
memory and this address must be incremented prior to
updating any scatter/gather entry.
In the case of a SCSI data receive, if there is not a byte
in the SWIDE register then this address is the next
location that should be written to when this I/O restarts.
No manual flushing will be necessary.
In the case of a SCSI data send, all data sent to the SCSI
bus will be accounted for and any data left in the part is
ignored and is automatically cleared from the FIFOs.
Registers: 0xD0–0xD3
Entry Storage Address (ESA)
Read/Write
31
0
ESA
0
0
0
0
0
0
0
0
0
0
0
0
ESA
4-112
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Entry Storage Address
[31:0]
This register's value depends on the type of BMOV being
executed. The three types of BMOVs are.
Direct BMOV:
In the case of a direct BMOV, this register contains
the address the BMOV was fetched from when the
phase mismatch occurred.
Indirect BMOV:
In the case of an indirect BMOV, this register contains
the address the BMOV was fetched from when the
phase mismatch occurred.
Table Indirect BMOV:
In the case of a Table Indirect BMOV, this register
contains the address of the Table Indirect entry being
used when the phase mismatch occurred.
Registers
Registers: 0xD4–0xD7
Instruction Address (IA)
Read/Write
31
0
IA
0
0
0
0
0
0
0
0
0
0
0
0
IA
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Instruction Address
[31:0]
This register always contains the address of the BMOV
instruction that was executing when the phase mismatch
occurred. This value will always match the value in the
Entry Storage Address (ESA) except in the case of a
Table Indirect BMOV in which case the ESA will have the
address of the Table Indirect entry and this register points
to the address of the BMOV instruction.
Registers: 0xD8–0xDA
SCSI Byte Count (SBC)
Read Only
23
0
SBC
0
0
0
0
0
0
0
0
0
SBC
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SCSI Byte Count
[23:0]
This register contains the count of the number of bytes
transferred to or from the SCSI bus during any given
BMOV. This value is used in calculating the information
placed into the Remaining Byte Count (RBC) and
Updated Address (UA) registers and should not need to
be used in normal operations.
There are several conditions for which the byte count
does not match the number of bytes transferred. If a
BMOV transfers an odd number of bytes across a wide
bus, the byte count at the end of the BMOV is one byte
greater than the number of bytes sent. This also occurs
in an odd byte count wide receive case. Lastly, when a
wide send occurs and a chain byte from a previous
transfer is present, the byte count does not reflect the
chain byte sent across the bus during that BMOV. To
SCSI Registers
4-113
determine the correct address to start fetching data from
after a phase mismatch, this byte is not counted for this
BMOV. It is included in the previous BMOV’s byte count.
Register: 0xDB
Reserved
7
0
R
x
x
x
x
x
x
x
x
This register is reserved.
Registers: 0xDC–0xDF
Cumulative SCSI Byte Count (CSBC)
Read/Write
31
0
CSBC
0
0
0
0
0
0
0
0
0
0
CSBC
4-114
Registers
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Cumulative SCSI Byte Count
[31:0]
This loadable register contains a cumulative count of the
number of bytes transferred across the SCSI bus during
data phases. It does not count bytes sent in command,
status, Message-In or Message-Out phases. It counts
bytes as long as the phase mismatch enable bit (ENPMJ)
in the Chip Control Zero (CCNTL0) register is set. Unlike
the SCSI Byte Count (SBC), this count is not cleared on
each BMOV instruction but continues to count across
multiple BMOV instructions. This register can be loaded
with any arbitrary start value.
Registers: 0xE0–0xE1
CRC Pad Byte Value (CRCPAD)
Read/Write
15
0
CRCPBV
0
0
0
0
CRCPBV
0
0
0
0
0
0
0
0
0
0
0
0
CRC Pad Byte Value
[15:0]
This register contains the value placed onto the bus for
the CRC pad bytes.
Register: 0xE2
CRC Control Zero (CRCCNTL0)
Read/Write
7
6
DCRCC
DCRCPC
5
0
0
0
R
0
0
0
0
0
0
DCRCC
Disable CRC Checking
7
Setting this bit causes the internal logic not to check or
report CRC errors during Ultra160 transfers. The
LSI53C1000 continues to calculate and send CRCs as
requested by the target according to the SPI-3
specification.
DCRCPC
Disable CRC Protocol Checking
6
Setting this bit causes the internal logic to neither check
nor report CRC protocol errors during Ultra160 transfers.
The LSI53C1000 continues to calculate and send CRCs
as requested by the target according to the SPI-3
specification but does not set a SGE interrupt if a CRC
protocol error occurs. This bit should not be set in normal
operations.
R
Reserved
SCSI Registers
[5:0]
4-115
Register: 0xE3
CRC Control One (CRCCNTL1)
Read/Write
4-116
7
6
5
4
3
2
CRCERR
R
ENAS
TSTSD
TSTCHK
TSTADD
0
0
0
0
0
0
1
0
CRCDSEL
0
0
CRCERR
CRC Error
7
This bit indicates whether or not a CRC error has been
detected during a DT Data-In SCSI transfer. This bit is set
independent of the DCRCC bit. To clear this condition,
either write this bit to a 1 or read the SIST0 and SIST1
registers. When CRC Checking and the Parity/CRC/AIP
Error Interrupt are enabled, this error condition is also
indicated as a Parity/CRC/AIP error (bit 0 of the SIST0
register).
R
Reserved
ENAS
Enable CRC Auto Seed
5
Setting this bit causes the CRC logic to automatically
reseed after every CRC check performed during DT
Data-In SCSI transfers. When this bit is cleared, the SCSI
control logic controls when the reseeding occurs.
TSTSD
Test CRC Seed
4
Setting this bit causes the CRC logic to immediately
reseed itself. This bit should never be set during normal
operation as it may cause corrupt CRCs to be generated.
TSTCHK
Test CRC Check
3
Setting this bit causes the CRC logic to initiate a CRC
check. This bit should never be set during normal
operation as it results in spurious CRC errors.
TSTADD
Test CRC Accumulate
2
Setting this bit causes the CRC block to take the value in
its input register and add it into the current CRC
calculation, resulting in a new output CRC value. This bit
should not be set during normal operation as it results in
corrupt CRC values.
Registers
6
CRCDSEL
CRC Data Register Selector
[1:0]
These bits control the data that is visible in the CRC Data
(CRCD) register.
Registers: 0xE4–0xE7
CRC Data (CRCD)
Read/Write
31
0
CRCD
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
The value in this register is dependent on the setting of the CRCDSEL
bits in the CRC Control One (CRCCNTL1) register.
Note:
Data written to this register may not be available for
immediate read back due to synchronization between the
PCI and SCSI clock domains. After a write, wait at least
16 PCI clock cycles before reading this register.
CRCD
CRC Data
[31:0]
If CRCDSEL = 0b00, this register represents the current
CRC value. After sending data during the DT Data-Out
phase, this register contains the CRC calculation for that
data, if no CRC request occurred during the transfer. In
this mode, this register is read only.
If CRCDSEL = 0b01, this register represents the CRC
Input register and contains its current value. It normally
contains the SCSI data transferred to or from the SCSI
bus during a DT transfer phase. In this mode, this register
can be written to in order to manually alter the input data
used for CRC calculation. For normal operations, this
register should never be written to.
If CRCDSEL = 0b10, this register represents the CRC
Accumulator and contains its current value. In this mode,
this register can be written to in order to manually modify
the value in the accumulator. This register should not be
written to during normal operation as corrupt CRC values
result.
SCSI Registers
4-117
If CRCDSEL = 0b11, this register contains the saved bad
CRC value that was calculated when a CRC error was
detected. After a CRC error is detected, this register is
not overwritten until the error condition is cleared.
Registers: 0xE8–0xEF
Reserved
31
0
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
This register is reserved.
Registers: 0xF0–0xF1
DMA FIFO Byte Count (DFBC)
Read Only
15
0
DFBC
x
x
x
DFBC
x
x
x
x
x
x
x
x
x
x
x
x
x
DMA FIFO Byte Count
[15:0]
This 16-bit read only register contains the actual number
of bytes contained in the DMA FIFO. This register is not
stable while data is actually being transferred. This
register can be used during error recovery.
Registers: 0xF2–0xF3
Reserved
15
0
R
0
0
0
0
0
0
This register is reserved.
4-118
Registers
0
0
0
0
0
0
0
0
0
0
Registers: 0xF4–0xFF
Reserved
31
0
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
This register is reserved.
4.3 SCSI Shadow Registers
Note:
For more information concerning shadow registers, refer to
the Chip Test Four (CTEST4), Scratch Register A
(SCRATCHA), Chip Control Two (CCNTL2), Scratch Register B (SCRATCHB), Memory Move Read Selector (MMRS),
Memory Move Write Selector (MMWS), and SCRIPT Fetch
Selector (SFS) register descriptions.
Registers: 0x34–0x37
Shadowed Scratch Register A (SCRATCHA)
Read/Write
31
0
SCRATCHA
0
0
0
0
0
0
0
0
0
0
0
SCRATCHA
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Scratch Register A
[31:0]
When the Configuration Info Enable bit in the Chip Test
Two (CTEST2) register is set, SCRATCH Register A is
placed in the shadowed mode and returns bits [31:10] of
the PCI Base Address Register One (BAR1) (MEMORY)
in bits [31:10]. Bits [9:0] of SCRATCH A will always return
zero in this mode. Writes to the SCRATCHA register have
no effect. Clearing the PCI Configuration Info Enable bit
causes the SCRATCH A register to return to normal
operation.
SCSI Shadow Registers
4-119
Register: 0x42
Shadowed SCSI SGE Status 0
Read/Write
7
6
5
4
3
2
1
0
SRP
DFP
RD
PCO
OO
OU
DO
DU
0
0
0
0
0
0
0
0
This register contains the individual status bits which cause a SGE SCSI
interrupt. These bits correspond to the SGE conditions described in the
SIST0 register description. Unlike the other registers in the device, these
bits must be set to one to clear the condition. This register is shadowed
behind the SCSI Interrupt Status Zero (SIST0) register. It can be
accessed by setting bit 7, the Enable Shadowed SGE Register (ShSGE)
bit, in the Chip Control Two (CCNTL2) register.
SRP
SCRIPTS RAM Parity
7
DFP
DMA FIFO Parity
6
RD
Residual Data in SCSI FIFO
5
PCO
Phase Change with Outstanding Offset
4
OO
Offset Overflow
3
OU
Offset Underflow
2
DO
Data Overflow
1
DU
Data Underflow
0
Register: 0x43
Shadowed SCSI Interrupt Status One (SIST1)
Read Only
7
6
R
0
0
5
4
3
2
1
0
PNCRC
FCRC
DTST
NFCRC
MCRC
R
0
0
0
0
0
0
This register contains the individual status bits which cause a SGE SCSI
interrupt. These bits correspond to the SGE conditions described in the
SIST0 register description. Unlike the other registers in the device, these
bits must be set to one to clear the condition. This register is shadowed
4-120
Registers
behind the SCSI Interrupt Status One (SIST1) register. It can be
accessed by setting bit 7, the Enable Shadowed SGE Register (ShSGE)
bit, in the Chip Control Two (CCNTL2) register.
R
Reserved
[7:6]
PNCRC
Pad Request with no CRC Request Following
5
FCRC
Force CRC
4
DTST
Switch from DT to ST Timings During a Transfer
3
NFCRC
Phase Change with no Final CRC Request
2
MCRC
Multiple CRC Requests with the Same Offset
1
R
Reserved
0
Registers: 0x5C–0x5F
Shadowed Scratch Register B (SCRATCHB)
Read/Write
31
0
SCRATCHB
0
0
0
0
0
0
0
0
0
0
0
SCRATCHB
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Scratch Register B
[31:0]
When the PCI Configuration Info Enable bit in the Chip
Test Two (CTEST2) register is set, SCRATCH Register B
is placed in the shadow mode. In this mode, bits [31:13]
of the Scratch Register B (SCRATCHB) register return
bits [31:13] of the PCI Base Address Register Three
(BAR3) (SCRIPTS RAM). Bits [12:0] of SCRATCH B will
always return zeros. Writes to the SCRATCH B register
have no effect. Resetting the PCI Configuration Info
Enable bit causes the SCRATCH B register to return to
normal operation.
SCSI Shadow Registers
4-121
Registers: 0xA0–0xA3
Shadowed Memory Move Read Selector (MMRS)
Read/Write
31
0
MMRS
0
0
0
0
0
0
0
0
0
0
0
0
MMRS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Shadowed Memory Move Read Selector
[31:0]
When the PCI Configuration Info Enable bit in the Chip
Test Two (CTEST2) register is set, the MMRS register is
placed in the shadow mode. In this mode, the Memory
Move Read Selector (MMRS) register returns bits [31:0]
of the memory mapped operating register, PCI Base
Address Register Two (BAR2) (MEMORY), when read.
Writes to the MMRS register have no effect. Clearing the
PCI Configuration Info Enable bit causes the MMRS
register to return to normal operation.
Registers: 0xA4–0xA7
Shadowed Memory Move Write Selector (MMWS)
Read/Write
31
0
MMWS
0
0
0
0
0
0
0
0
0
0
MMWS
4-122
Registers
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Shadowed Memory Move Write Selector
[31:0]
When the PCI Configuration Info Enable bit in the Chip
Test Two (CTEST2) register is set, the MMWS register is
placed in the shadow mode. In this mode, the MMWS
register returns bits [31:0] of the SCRIPT RAM PCI Base
Address Register Four (BAR4) (SCRIPTS RAM) in
bits [31:0] of the MMWS register when read. Writes to the
MMWS register have no effect. Clearing the PCI
Configuration Info Enable bit causes the MMWS register
to return to normal operation.
Registers: 0xA8–0xAB
Shadowed SCRIPT Fetch Selector (SFS)
Read/Write
31
0
SFS
0
0
0
0
0
0
0
0
0
SFS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Shadowed SCRIPT Fetch Selector
[31:0]
When the PCI Configuration Info Enable bit in the Chip
Test Two (CTEST2) register is set, the SCRIPT Fetch
Selector register is placed in shadow mode. In this mode,
bits [23:16] of this register return the PCI Revision ID
(RID) register value and bits [15:0] return the PCI Device
ID register value when read. Writes to the SCRIPT Fetch
Selector (SFS) register have no effect. Clearing the PCI
Configuration Info Enable bit causes the SFS register to
return to normal operation.
SCSI Shadow Registers
4-123
4-124
Registers
Chapter 5
SCSI SCRIPTS
Instruction Set
After power-up and initialization, the LSI53C1000 can operate in the low
level register interface mode, or use SCSI SCRIPTS.
With the low level register interface, the user has access to the DMA
control logic and the SCSI bus control logic. An external processor has
access to the SCSI bus signals and the low level DMA signals, which
allow creation of complicated board level test algorithms. The low level
interface is useful for backward compatibility with SCSI devices that
require certain unique timings or bus sequences to operate properly.
The following sections describe the benefits and use of SCSI SCRIPTS.
•
Section 5.1, “SCSI SCRIPTS”
•
Section 5.2, “Block Move Instructions”
•
Section 5.3, “I/O Instructions”
•
Section 5.4, “Read/Write Instructions”
•
Section 5.5, “Transfer Control Instructions”
•
Section 5.6, “Memory Move Instructions”
•
Section 5.7, “Load and Store Instructions”
5.1 SCSI SCRIPTS
To operate in the SCSI SCRIPTS mode, the LSI53C1000 requires only
a SCRIPTS start address. The start address must be at a Dword (four
byte) boundary. This aligns all the following SCRIPTS at a Dword
boundary since all SCRIPTS are 8 or 12 bytes long. Instructions are
fetched until an interrupt instruction is encountered, or until an
unexpected event (such as a hardware error) causes an interrupt to the
external processor.
LSI53C1000 PCI to Ultra160 SCSI Controller
5-1
Once an interrupt is generated, the LSI53C1000 halts all operations until
the interrupt is serviced. Then, the start address of the next SCRIPTS
instruction is written to the DMA SCRIPTS Pointer (DSP) register to
restart the automatic fetching and execution of instructions.
In the SCSI SCRIPTS mode the LSI53C1000 is allowed to make
decisions based on the status of the SCSI bus, which frees the
microprocessor from servicing the numerous interrupts inherent in I/O
operations.
Given the rich set of SCSI oriented features included in the instruction
set, and the ability to re-enter the SCSI algorithm at any point, this high
level interface is all that is required for both normal and exception
conditions. Switching to the low level mode for error recovery is not
required.
The following types of SCRIPTS instructions are implemented in the
LSI53C1000:
•
Block Move—used to move data between the SCSI bus and memory.
•
I/O or Read/Write—causes the LSI53C1000 to trigger common SCSI
hardware sequences, or to move registers.
•
Transfer Control—allows SCRIPTS instructions to make decisions
based on real time SCSI bus conditions.
•
Memory Move—causes the LSI53C1000 to execute block moves
between different parts of main memory.
•
Load/Store—provides a more efficient way to move data to/from
memory from/to an internal register in the chip without using the
Memory Move instruction.
Each instruction consists of two or three 32-bit words. The first 32-bit
word is always loaded into the DMA Command (DCMD) and DMA Byte
Counter (DBC) registers, the second into the DMA SCRIPTS Pointer
Save (DSPS) register. The third word, used only by Memory Move
instructions, is loaded into the Temporary (TEMP) shadow register. In an
indirect I/O or Move instruction, the first two 32-bit opcode fetches are
followed by one or two more 32-bit fetch cycles.
5-2
SCSI SCRIPTS Instruction Set
5.1.1 Sample Operation
The following example describes execution of a SCRIPTS Block Move
instruction.
•
The host CPU, through programmed I/O, gives the DMA SCRIPTS
Pointer (DSP) register (in the Operating register file) the starting
address in main memory that points to a SCSI SCRIPTS program
for execution.
•
Loading the DMA SCRIPTS Pointer (DSP) register causes the
LSI53C1000 to fetch its first instruction at the address just loaded.
This fetch is from main memory or the internal RAM, depending on
the address.
•
The LSI53C1000 typically fetches two Dwords (64 bits) and decodes
the high order byte of the first Dword as a SCRIPTS instruction. If
the instruction is a Block Move, the lower three bytes of the first
Dword are stored and interpreted as the number of bytes to move.
The second Dword is stored and interpreted as the 32-bit beginning
address in main memory to which the move is directed.
•
For a SCSI send operation, the LSI53C1000 waits until there is
enough space in the DMA FIFO to transfer a programmable size
block of data. For a SCSI receive operation, it waits until enough data
is collected in the DMA FIFO for transfer to memory. At this point,
the LSI53C1000 requests use of the PCI bus again to transfer the
data.
•
When the LSI53C1000 is granted the PCI bus, it executes (as a bus
master) a burst transfer (programmable size) of data, decrements the
internally stored remaining byte count, increments the address
pointer, and then releases the PCI bus. The LSI53C1000 stays off
the PCI bus until the FIFO can again hold (for a write) or has
collected (for a read) enough data to repeat the process.
The process repeats until the internally stored byte count has reached
zero. The LSI53C1000 releases the PCI bus and then performs another
SCRIPTS instruction fetch cycle, using the incremented stored address
maintained in the DMA SCRIPTS Pointer (DSP) register. Execution of
SCRIPTS instructions continues until an error condition occurs or an
interrupt SCRIPTS instruction is received. At this point, the LSI53C1000
interrupts the host CPU and waits for further servicing by the host
system. It can execute independent Block Move instructions specifying
SCSI SCRIPTS
5-3
new byte counts and starting locations in main memory. In this manner,
the LSI53C1000 performs scatter/gather operations on data without
requiring help from the host program, generating a host interrupt, or
programming of an external DMA controller.
Figure 5.1 provides an overview of SCRIPTS operation.
Figure 5.1
SCRIPTS Overview
System Processor
System Memory
(or Internal RAM)
SCSI Initiator Write Example
select ATN0, alt_addr
move 1, identify_msg_buf, when MSG_OUT
move 6, cmd_buf, when CMD
move 512, data_buf, when DATA_OUT
move 1, stat_in_buf, when STATUS
move 1, msg_in_buf, when MSG_IN
move SCNTL2 & 7F to SCNTL2
clear ACK
wait disconnect alt2
int 10
S
y
s
t
e
m
B
u
s
Write DSP
Fetch
SCRIPTS
LSI53C1000
SCSI
Bus
Data
Data Structure
Message Buffer
Command Buffer
Data Buffer
Status Buffer
(Data is not fetched across system bus if
internal RAM is enabled.)
5.2 Block Move Instructions
For Block Move instructions, bits 5 and 4 (SIOM and DIOM) in the DMA
Mode (DMODE) register determine whether the source/destination
address resides in memory or I/O space. When data is moved onto the
5-4
SCSI SCRIPTS Instruction Set
SCSI bus, SIOM controls whether that data comes from the I/O or
memory space. When data is moved off of the SCSI bus, DIOM controls
whether that data goes to the I/O or memory space.
5.2.1 First Dword
This section describes the structure of the first SCSI SCRIPTS Dword.
Bits [31:24] are loaded into the DMA Command register while bits [23:0]
are loaded into the DBC Register.
Figure 5.2
31
30
Block Move Instruction - First Dword
29
28
27
26
24
23
0
DCMD Register
IT[1:0]
IA
TIA OPC
DBC Register
SCSIP[2:0]
TC[23:0]
IT[1:0]
Instruction Type - Block Move
[31:30]
The configuration of these two bits define the SCRIPTS
instruction type. The Block Move Instruction is 0b00.
IA
Indirect Addressing
29
When this bit is cleared, user data is moved to or from
the 32-bit data start address for the Block Move
instruction. The value is loaded into the chip’s address
register and incremented as data is transferred. The
address of the data to move is in the second Dword of
this instruction.
When the EN64DBMV bit in Chip Control One (CCNTL1)
is set, a third Dword is fetched to provide the upper
Dword of a 64-bit address. The upper Dword address is
fetched along with the instruction and loaded into the
Dynamic Block Move Selector (DBMS) register.
If the EN64DBMV bit is cleared, the upper Dword
address is copied from the Static Block Move Selector
(SBMS) register.
Direct Addressing
The byte count and absolute address are as follows:
Command
Byte Count
Lower Dword Address of Data
Upper Dword address of data (EN64DBMV = 1)
Block Move Instructions
5-5
Indirect
When set, the 32-bit user data start address for the Block
Move is the address of a pointer to the actual data buffer
address. The value at the 32-bit start address is loaded
into the chip’s DMA Next Address (DNAD) register using
a third Dword fetch (4-byte transfer across the host
computer bus).
Use the fetched byte count, but fetch the data address
from the address in the instruction.
If 64-bit addressing is desired, the upper Dword of the
address is stored in the Static Block Move Selector
(SBMS) register. When the value in SBMS is 0x0, 32-bit
addressing is assumed.
Command
Byte Count
Address of Pointer to Data
Once the data pointer address is loaded, it is executed
as when the chip operates in the direct mode. This
indirect feature allows specification of a table of data
buffer addresses. Using the SCSI SCRIPTS compiler, the
table offset is placed in the SCRIPT at compile time.
Then at the actual data transfer time, the offsets are
added to the base address of the data address table by
the external processor. The logical I/O driver builds a
structure of addresses for an I/O rather than treating each
address individually.
Note:
TIA
Using indirect and table indirect addressing simultaneously
is not permitted; use only one addressing method at a time.
Table Indirect
32-Bit Addressing
28
When this bit is set, the 24-bit signed value in the start
address of the move is treated as a relative displacement
from the value in the Data Structure Address (DSA)
register. Both the transfer count and the source/
destination address are fetched from this location.
Use the signed integer offset in bits [23:0] of the second
four bytes of the instruction, added to the value in the
Data Structure Address (DSA) register, to fetch first the
byte count and then the data address. The signed value
5-6
SCSI SCRIPTS Instruction Set
is combined with the data structure base address to
generate the physical address used to fetch values from
the data structure. Sign-extended values of all ones for
negative values are allowed, but bits [31:24] are ignored.
Note:
Command
Not Used
Don’t Care
Table Offset
Using indirect and table indirect addressing simultaneously
is not permitted; use only one addressing method at a time.
Prior to the start of an I/O, load the Data Structure
Address (DSA) register with the base address of the I/O
data structure. Any address on a Dword boundary is
allowed.
After a Table Indirect opcode is fetched, the Data
Structure Address (DSA) is added to the 24-bit signed
offset value from the opcode to generate the address of
the required data; both positive and negative offsets are
allowed. A subsequent fetch from that address brings the
data values into the chip.
For a MOVE instruction, the 24-bit byte count is fetched
from system memory. Then the 32-bit physical address is
brought into the LSI53C1000. Execution of the move
begins at this point.
SCRIPTS can directly execute operating system I/O data
structures, saving time at the beginning of an I/O
operation. The I/O data structure can begin on any Dword
boundary and may cross system segment boundaries.
There are two restrictions on the placement of pointer
data in system memory:
• The eight bytes of data in the MOVE instruction must
be contiguous.
• Indirect data fetches are not available during
execution of a Memory-to-Memory DMA operation.
00
Byte Count
Physical Data Address
Block Move Instructions
5-7
64-Bit Addressing
If the Enable 64-bit Table Indirect Block Move
(EN64TIBMV) bit is cleared, table indirect block moves
remain as 2 Dword opcodes plus a 2 Dword table entry.
The upper 32 bits of the address are copied from the
Static Block Move Selector (SBMS) when performing
data transfers during block move operations. The SBMS
register must be loaded manually.
If the Enable 64-bit Table Indirect Block Move
(EN64TIBMV) bit is set and the 64-bit Table Indirect Index
Mode (64TIMOD) bit is cleared, bits [28:24] of the first
Dword of the table entry (where the byte count is located)
select one of the 16 scratch registers or any of the six
64-bit selector registers as a selector for the upper 32 bit
address. Please see the Table Indirect Index mode
mapping table for a breakdown of index values and the
corresponding registers selected. The selected address
is automatically loaded into the DMA Next Address 64
(DNAD64) register.
Note:
If EN64TIBMV is set and 64TIMOD is set, bits [31:24] of the
first Dword of the table entry (where the byte count is
located) are loaded directly into DMA Next Address 64
(DNAD64) to provide a 40-bit address.
The format for the table indirect entries for each mode is
shown below. The table for Table Indirect block moves
upper 32-bit address locations summarizes the available
modes for table indirect block moves.
Index Mode 0 (64TIMOD clear) table entry format:
31
29 28
R
24 23
0
Sel Index
Byte Count
Source/Destination Address [31:0]
Index Mode 1 (64TIMOD set) table entry format:
31
24 23
0
Src/Dest Addr [39:32]
Byte Count
Source/Destination Address [31:0]
5-8
SCSI SCRIPTS Instruction Set
Table Indirect block moves upper 32-bit address
locations:
Upper 32-Bit Data
Address Comes From
EN64TIBMV 64TIMOD
0
0
SBMS
0
1
SBMS
1
0
ScratchC–J, MMWS, MMRS, SFS,
DRS, SBMS, DBMS
1
1
1st Table Entry Dword bits [31:24]
(40-bit addressing only)
Table Indirect Index mode mapping:
OPC
Index Value
Selector Used
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16–0x1F
Scratch C
Scratch D
Scratch E
Scratch F
Scratch G
Scratch H
Scratch I
Scratch J
Scratch K
Scratch L
Scratch M
Scratch N
Scratch O
Scratch P
Scratch Q
Scratch R
MMRS
MMWS
SFS
DRS
SBMS
SBMS
Illegal (Results in an IID interrupt)
Opcode
27
This 1-bit field defines the instruction to execute as a
block move (MOVE).
Block Move Instructions
5-9
Target Mode
OPC
Instruction Defined
0
MOVE/MOVE64
1
CHMOV/CHMOV64
The LSI53C1000 verifies that it is connected to the SCSI
bus as a target before executing this instruction.
The LSI53C1000 asserts the SCSI phase signals
(SMSG/, SC_D/, and SI_O/) as defined by the Phase
Field bits in the instruction.
If the instruction is for the command phase, the
LSI53C1000 receives the first command byte and
decodes its SCSI Group Code.
• If the SCSI Group Code is either Group 0,
Group 1, Group 2, or Group 5, then the LSI53C1000
overwrites the DMA Byte Counter (DBC) register with
the length of the Command Descriptor Block: 6, 10, or
12 bytes.
• If the Vendor Unique Enhancement 0 (VUE0) bit
(SCSI Control Two (SCNTL2), bit 1) is cleared and the
SCSI group code is a vendor unique code, the
LSI53C1000 overwrites the DMA Byte Counter (DBC)
register with the length of the Command Descriptor
Block: 6, 10, or 12 bytes. If the VUE0 bit is set, the
LSI53C1000 receives the number of bytes in the byte
count regardless of the group code.
• If any other Group Code is received, the DMA Byte
Counter (DBC) register is not modified and the
LSI53C1000 requests the number of bytes specified
in the DMA Byte Counter (DBC) register. If the DBC
register contains 0x000000, an illegal instruction
interrupt is generated.
The LSI53C1000 transfers the number of bytes specified
in the DMA Byte Counter (DBC) register starting at the
address specified in the DMA Next Address (DNAD)
register. If the Opcode bit is set and a data transfer ends
on an odd byte boundary, the LSI53C1000 stores the last
byte in the SCSI Wide Residue (SWIDE) register during
5-10
SCSI SCRIPTS Instruction Set
a receive operation. This byte is combined with the first
byte from the subsequent transfer so that a wide transfer
can complete.
If the SATN/ signal is asserted by the initiator or a parity
error occurred during the transfer, it is possible to halt the
transfer and generate an interrupt. The Disable Halt on
Parity Error or ATN bit in the SCSI Control One (SCNTL1)
register controls whether the LSI53C1000 halts on these
conditions immediately, or waits until completion of the
current Move.
Initiator Mode
OPC
Instruction Defined
0
CHMOV/CHMOV64
1
MOVE/MOVE64
The LSI53C1000 verifies that it is connected to the SCSI
bus as an initiator before executing this instruction.
The LSI53C1000 waits for an unserviced phase to occur.
An unserviced phase is defined as any phase (with
SREQ/ asserted) for which the LSI53C1000 has not yet
transferred data by responding with a SACK/.
The LSI53C1000 compares the SCSI phase bits in the
DMA Command (DCMD) register with the latched SCSI
phase lines stored in the SCSI Status One (SSTAT1)
register. These phase lines are latched when SREQ/ is
asserted.
If the SCSI phase bits match the value stored in the SCSI
Status One (SSTAT1) register, the LSI53C1000 transfers
the number of bytes specified in the DMA Byte Counter
(DBC) register starting at the address pointed to by the
DMA Next Address (DNAD) register. If the opcode bit is
cleared and a data transfer ends on an odd byte
boundary, the LSI53C1000 stores the last byte in the
SCSI Wide Residue (SWIDE) register during a receive
operation, or in the SCSI Output Data Latch (SODL)
register during a send operation. This byte is combined
with the first byte from the subsequent transfer so that a
wide transfer can complete.
Block Move Instructions
5-11
If the SCSI phase bits do not match the value stored in
the SCSI Status One (SSTAT1) register, the LSI53C1000
generates a phase mismatch interrupt and the instruction
is not executed.
During a Message-Out phase, after the LSI53C1000 has
performed a select with Attention (or SATN/ is manually
asserted with a Set ATN instruction), the LSI53C1000
deasserts SATN/ during the final SREQ/SACK/
handshake.
When the LSI53C1000 is performing a block move for
Message-In phase, it does not deassert the SACK/ signal
for the last SREQ/SACK/ handshake. Clear the SACK/
signal using the Clear SACK I/O instruction.
SCSIP[2:0]
SCSI Phase
[26:24]
This field defines the desired SCSI information transfer
phase. When the LSI53C1000 operates in the initiator
mode, these bits are compared with the latched SCSI
phase bits in the SCSI Status One (SSTAT1) register.
When the LSI53C1000 operates in the target mode, it
asserts the phase defined in this field. The following table
describes the possible combinations and the
corresponding SCSI phase.
MSG C_D
TC[23:0]
5-12
I_O SCSI Phase
0
0
0
ST Data-Out
0
0
1
ST Data-In
0
1
0
Command
0
1
1
Status
1
0
0
DT Data-Out
1
0
1
DT Data-In
1
1
0
Message-Out
1
1
1
Message-In
Transfer Counter
[23:0]
This 24-bit field specifies the number of data bytes to be
moved between the LSI53C1000 and system memory.
The field is stored in the DMA Byte Counter (DBC)
register. When the LSI53C1000 transfers data to/from
memory, the DBC register is decremented by the number
of bytes transferred. In addition, the DMA Next Address
SCSI SCRIPTS Instruction Set
(DNAD) register is incremented by the number of bytes
transferred. This process is repeated until the DBC
register is decremented to zero. At this time, the
LSI53C1000 fetches the next instruction.
If bit 28 is set, indicating table indirect addressing, this
field is not used. The byte count is instead fetched from
a table pointed to by the Data Structure Address (DSA)
register.
5.2.2 Second Dword
This section describes the structure of the second SCSI SCRIPTS block
move instruction Dword.
Figure 5.3
31
Block Move Instruction - Second Dword
24 23
16 15
8
7
0
DSPS Register
Start Address
[31:0]
This 32-bit field specifies the starting address of the data
to move to/from memory. This field is copied to the DMA
Next Address (DNAD) register. When the LSI53C1000
transfers data to or from memory, the DNAD register is
incremented by the number of bytes transferred.
When bit 29 is set, indicating indirect addressing, this
address is a pointer to an address in memory that points
to the data location. When bit 28 is set, indicating table
indirect addressing, the value in this field is an offset into
a table pointed to by the Data Structure Address (DSA).
The table entry contains byte count and address
information.
Block Move Instructions
5-13
5.2.3 Third Dword
This section describes the structure of the third SCSI SCRIPTS Dword.
Figure 5.4
Block Move Instruction - Third Dword
31
24 23
16 15
8
7
0
DBMS Register
Start Address
[63:32]
This 32-bit field specifies the upper Dword of a 64-bit
starting address of data to move to/from memory. This
field is copied to the Dynamic Block Move Selector
(DBMS) register. The EN64DBMV bit in the Chip
Control One (CCNTL1) register must be set for this
Dword to be fetched.
5.3 I/O Instructions
This section contains information about the I/O Instruction register. It is
divided into First Dword and Second Dword.
5.3.1 First Dword
This section describes the first Dword of the I/O Instruction register.
Figure 5.5
31 30 29
First 32-bit Word of the I/O Instruction
27 26 25 24 23
20 19
16 15
DCMD Register
IT[1:0] OPC[2:0] RA TI Sel
0
1
5-14
x
x
x
x
11 10
9
8 7 6 5 4
3
2
0
DBC Register
x
x
R
0
0
ENDID[3:0]
0
0
x
x
x
R
x 0 0 0 0 0
CA TM
x
x
R
A
R
0 0 x 0 0
ATN
R
x
0 0 0
IT[1:0]
Instruction Type - I/O Instruction
OPC[2:0]
Opcode
[29:27]
The following Opcode bits have different meanings,
depending on whether the LSI53C1000 is operating in
the initiator or target mode. Opcode selections 0b101–
0b111 are considered Read/Write instructions, and are
described in Section 5.4, “Read/Write Instructions.”
SCSI SCRIPTS Instruction Set
[31:30]
Target Mode
OPC2 OPC1 OPC0 Instruction Defined
0
0
0
Reselect
0
0
1
Disconnect
0
1
0
Wait Select
0
1
1
Set
1
0
0
Clear
Reselect Instruction
The LSI53C1000 arbitrates for the SCSI bus by asserting
the SCSI ID stored in the SCSI Chip ID (SCID) register.
If it loses arbitration, it tries again during the next
available arbitration cycle without reporting any lost
arbitration status.
If the LSI53C1000 wins arbitration, it attempts to reselect
the SCSI device whose ID is defined in the destination ID
field of the instruction. Once the LSI53C1000 wins
arbitration, it fetches the next instruction from the address
pointed to by the DMA SCRIPTS Pointer (DSP) register.
This way the SCRIPTS can move on to the next
instruction before the reselection completes. It continues
executing SCRIPTS until a SCRIPT that requires a
response from the initiator is encountered.
If the LSI53C1000 is selected or reselected before
winning arbitration, it fetches the next instruction from the
address pointed to by the 32-bit jump address field stored
in the DMA Next Address (DNAD) register. Manually set
the LSI53C1000 to the initiator mode if it is reselected, or
to the target mode if it is selected.
Disconnect Instruction
The LSI53C1000 disconnects from the SCSI bus by
deasserting all SCSI signal outputs.
Wait Select Instruction
If the LSI53C1000 is selected, it fetches the next
instruction from the address pointed to by the DMA
SCRIPTS Pointer (DSP) register.
I/O Instructions
5-15
If reselected, the LSI53C1000 fetches the next instruction
from the address pointed to by the 32-bit jump address
field stored in the DMA Next Address (DNAD) register.
Manually set the LSI53C1000 to the initiator mode when
it is reselected.
If the CPU sets the SIGP bit in the Interrupt Status Zero
(ISTAT0) register, the LSI53C1000 aborts the Wait Select
instruction and fetches the next instruction from the
address pointed to by the 32-bit jump address field stored
in the DMA Next Address (DNAD) register.
Set Instruction
When the SACK/ or SATN/ bits are set, the
corresponding bits in the SCSI Output Control Latch
(SOCL) register are set. Do not set SACK/ or SATN/
except for testing purposes. When the target bit is set,
the corresponding bit in the SCSI Control Zero (SCNTL0)
register is also set. When the carry bit is set, the
corresponding bit in the Arithmetic Logic Unit (ALU) is
set.
Note:
None of the signals are set on the SCSI bus in target mode.
Clear Instruction
When the SACK/ or SATN/ bits are cleared, the
corresponding bits are cleared in the SCSI Output
Control Latch (SOCL) register. Do not set SACK/ or
SATN/ except for testing purposes. When the target bit is
cleared, the corresponding bit in the SCSI Control Zero
(SCNTL0) register is cleared. When the carry bit is
cleared, the corresponding bit in the ALU is cleared.
Note:
None of the signals are cleared on the SCSI bus in the
target mode.
Initiator Mode
5-16
OPC2
OPC1
0
0
0
Select
0
0
1
Wait Disconnect
0
1
0
Wait Reselect
0
1
1
Set
1
0
0
Clear
SCSI SCRIPTS Instruction Set
OPC0 Instruction Defined
Select Instruction
The LSI53C1000 arbitrates for the SCSI bus by asserting
the SCSI ID stored in the SCSI Chip ID (SCID) register.
If it loses arbitration, it tries again during the next
available arbitration cycle without reporting any lost
arbitration status.
If the LSI53C1000 wins arbitration, it attempts to select
the SCSI device whose ID is defined in the destination ID
field of the instruction. Once the LSI53C1000 wins
arbitration, it fetches the next instruction from the address
pointed to by the DMA SCRIPTS Pointer (DSP) register.
This way the SCRIPTS can move to the next instruction
before the selection completes. It continues executing
SCRIPTS until a SCRIPT that requires a response from
the target is encountered.
If the LSI53C1000 is selected or reselected before
winning arbitration, it fetches the next instruction from the
address pointed to by the 32-bit jump address field stored
in the DMA Next Address (DNAD) register. Manually set
the LSI53C1000 to the initiator mode if it is reselected, or
to the target mode if it is selected.
If the Select with SATN/ field is set, the SATN/ signal is
asserted during the selection phase.
Wait Disconnect Instruction
The LSI53C1000 waits for the target to perform a “legal”
disconnect from the SCSI bus. A “legal” disconnect
occurs when SBSY/ and SSEL/ are inactive for a
minimum of one Bus Free delay (400 ns), after the
LSI53C1000 receives a Disconnect Message or a
Command Complete Message.
Wait Reselect Instruction
If the LSI53C1000 is selected before being reselected, it
fetches the next instruction from the address pointed to
by the 32-bit jump address field stored in the DMA Next
Address (DNAD) register. Manually set the LSI53C1000
to the target mode when it is selected.
If the LSI53C1000 is reselected, it fetches the next
instruction from the address pointed to by the DMA
SCRIPTS Pointer (DSP) register.
I/O Instructions
5-17
If the CPU sets the SIGP bit in the Interrupt Status Zero
(ISTAT0) register, the LSI53C1000 aborts the Wait
Reselect instruction and fetches the next instruction from
the address pointed to by the 32-bit jump address field
stored in the DMA Next Address (DNAD) register.
Set Instruction
When the SACK/ or SATN/ bits are set, the
corresponding bits in the SCSI Output Control Latch
(SOCL) register are set. When the target bit is set, the
corresponding bit in the SCSI Control Zero (SCNTL0)
register is also set. When the carry bit is set, the
corresponding bit in the ALU is set.
Clear Instruction
When the SACK/ or SATN/ bits are cleared, the
corresponding bits are cleared in the SCSI Output
Control Latch (SOCL) register. When the target bit is
cleared, the corresponding bit in the SCSI Control Zero
(SCNTL0) register is cleared. When the carry bit is
cleared, the corresponding bit in the ALU is cleared.
5-18
RA
Relative Addressing Mode
26
When this bit is set, the 24-bit signed value in the DMA
Next Address (DNAD) register is used as a relative
displacement from the current DMA SCRIPTS Pointer
(DSP) address. Use this bit only in conjunction with the
Select, Reselect, Wait Select, and Wait Reselect
instructions. The Select and Reselect instructions can
contain an absolute alternate jump address or a relative
transfer address.
TI
Table Indirect Mode
25
When this bit is set, the 24-bit signed value in the DMA
Byte Counter (DBC) register is added to the value in the
Data Structure Address (DSA) register, and used as an
offset relative to the value in the Data Structure Address
(DSA) register. The SCSI Control Three (SCNTL3) value,
SCSI ID, synchronous offset and synchronous period are
loaded from this address. Prior to the start of an I/O, load
the Data Structure Address (DSA) with the base address
of the I/O data structure. Any address on a Dword
boundary is allowed. After a Table Indirect opcode is
fetched, the Data Structure Address (DSA) is added to
the 24-bit signed offset value from the opcode to
SCSI SCRIPTS Instruction Set
generate the address of the required data. Both positive
and negative offsets are allowed. A subsequent fetch
from that address brings the data values into the chip.
SCRIPTS can directly execute operating system I/O data
structures, saving time at the beginning of an I/O
operation. The I/O data structure can begin on any Dword
boundary and may cross system segment boundaries.
There are two restrictions on the placement of data in
system memory:
• The I/O data structure must lie within the 8 Mbytes
above or below the base address.
• An I/O command structure must have all four bytes
contiguous in system memory, as shown below. The
offset/period bits are ordered as in the SCSI Transfer
(SXFER) register. The configuration bits are ordered
as in the SCSI Control Three (SCNTL3) register.
Config
ID
Offset/period
00
Use this bit only in conjunction with the Select, Reselect,
Wait Select, and Wait Reselect instructions. It is allowable
to set bits 25 and 26 individually or in combination:
Bit 25
Bit 26
Direct
0
0
Table Indirect
0
1
Relative
1
0
Table Relative
1
1
Direct
Uses the device ID and physical address in the
instruction.
Command
ID
Not Used
Not Used
Absolute Alternate Address
Table Indirect
Uses the physical jump address, but fetches data using
the table indirect method.
I/O Instructions
5-19
Command
Table Offset
Absolute Alternate Address
Relative
Uses the device ID in the instruction, but treats the
alternate address as a relative jump.
Command
ID
Not Used
Not Used
Absolute Jump Offset
Table Relative
Treats the alternate jump address as a relative jump and
fetches the device ID, synchronous offset, and
synchronous period indirectly. The value in bits [23:0] of
the first four bytes of the SCRIPTS instruction is added
to the data structure base address to form the fetch
address.
Command
Table Offset
Absolute Jump Offset
5-20
Sel
Select with ATN/
24
This bit specifies whether SATN/ is asserted during the
selection phase when the LSI53C1000 is executing a
Select instruction. When operating in the initiator mode,
set this bit for the Select instruction. If this bit is set on
any other I/O instruction, an illegal instruction interrupt is
generated.
R
Reserved
ENDID[3:0]
Encoded SCSI Destination ID
[19:16]
This 4-bit field specifies the destination SCSI ID for an I/O
instruction.
SCSI SCRIPTS Instruction Set
[23:20]
R
Reserved
CA
Set/Clear Carry
10
This bit is used in conjunction with a Set or Clear
instruction to set or clear the Carry bit. Setting this bit
with a Set instruction asserts the Carry bit in the ALU.
Clearing this bit with a Clear instruction deasserts the
Carry bit in the ALU.
TM
[15:11]
Set/Clear Target Mode
9
This bit is used in conjunction with a Set or Clear
instruction to set or clear the target mode. Setting this bit
with a Set instruction configures the LSI53C1000 as a
target device (this sets bit 0 of the SCSI Control Zero
(SCNTL0) register). Clearing this bit with a Clear
instruction configures the LSI53C1000 as an initiator
device (this clears bit 0 of the SCNTL0 register).
R
Reserved
A
Set/Clear SACK/
This bit is used in conjunction with a Set or Clear
instruction to assert or deassert SACK/.
[8:7]
6
The Set instruction is used to assert SACK/ on the SCSI
bus. The Clear instruction is used to deassert SACK/ on
the SCSI bus. The corresponding bit in the SCSI Output
Control Latch (SOCL) register is set or cleared depending on the instruction used. Since SACK/ is an initiator
signal, it is not asserted on the SCSI bus unless the
LSI53C1000 is operating as an initiator.
The Set/Clear SCSI ACK/, ATN/ instructions are used
after message phase Block Move operations to give the
initiator the opportunity to assert attention before
acknowledging the last message byte. For example, if the
initiator wishes to reject a message, it issues an Assert
SCSI ATN instruction before a Clear SCSI ACK
instruction.
R
ATN
I/O Instructions
Reserved
Set/Clear SATN/
This bit is used in conjunction with a Set or Clear
instruction to assert or deassert SATN/.
[5:4]
3
5-21
The Set instruction is used to assert SATN/ on the SCSI
bus. The Clear instruction is used to deassert SATN/ on
the SCSI bus. The corresponding bit in the SCSI Output
Control Latch (SOCL) register will be set or cleared
depending on the instruction used. Since SATN/ is an
initiator signal, it is not asserted on the SCSI bus unless
the LSI53C1000 is operating as an initiator.
The Set/Clear SCSI ACK/, ATN/ instructions are used
after message phase Block Move operations to give the
initiator the opportunity to assert attention before
acknowledging the last message byte. For example, if the
initiator wishes to reject a message, it issues an Assert
SCSI ATN instruction before a Clear SCSI ACK
instruction.
R
Reserved
[2:0]
5.3.2 Second Dword
This section describes the second Dword of the I/O Instruction register.
Figure 5.6
31
Second 32-Bit Word of the I/O Instruction
24 23
16 15
8
7
0
DSPS Register
SA
Start Address
[31:0]
This 32-bit field contains the memory address to fetch the
next instruction if the selection or reselection fails.
If relative or table relative addressing is used, this value
is a 24-bit signed offset relative to the current DMA
SCRIPTS Pointer (DSP) register value.
5-22
SCSI SCRIPTS Instruction Set
5.4 Read/Write Instructions
The Read/Write instruction supports addition, subtraction, and
comparison of two separate values within the chip. It performs the
desired operation on the specified register and the SCSI First Byte
Received (SFBR) register and stores the result back to the specified
register or to the SFBR. If the COM bit (DMA Control (DCNTL), bit 0) is
cleared, Read/Write instructions cannot be used.
5.4.1 First Dword
This section describes the first Dword of the Read/Write Instruction
register.
Figure 5.7
31 30 29
Read/Write Instruction - First Dword
27 26
24 23 22
16 15
8
DCMD Register
IT[1:0] OPC[2:0]
0
1
x
x
x
6
0
DBC Register
O[2:0]
x
7
x
D8 Register Address [6:0]
x
x
x
x
x
x
x
x
x
Immediate Data
x
x
x
x
x
x
A7 Reserved - Must be 0
x
x
0
0
0
0
0
0
0
0
IT[1:0]
Instruction Type - Read/Write Instruction
[31:30]
The Read/Write instruction uses operator bits [26:24] in
conjunction with the opcode bits to determine which
instruction is currently selected.
OPC[2:0]
Opcode
[29:27]
These bits determine if the instruction is a Read/Write or
an I/O instruction. Opcodes 0b000 through 0b100 are
considered I/O instructions.
O[2:0]
Operator
[26:24]
The Operator bits are used in conjunction with the
opcode bits to determine which instruction is currently
selected. Refer to Table 5.1 for field definitions.
D8
Use data8/SFBR
23
When this bit is set, SCSI First Byte Received (SFBR) is
used, instead of the data8 value, during a Read-ModifyWrite instruction (see Table 5.1 on page 5-25). This
allows the user to add two register values.
Read/Write Instructions
5-23
A[6:0]
Register Address - A[6:0]
[22:16]
It is possible to change register values from SCRIPTS in
read-modify-write cycles or move to/from SCSI First Byte
Received (SFBR) cycles. A[6:0] selects an 8-bit
source/destination register within the LSI53C1000.
IMMD
Immediate Data
[15:8]
This 8-bit value is used as a second operand in logical
and arithmetic functions.
A7
Upper Register Address Line [A7]
This bit is used to access registers 0x80–0xFF.
R
Reserved
7
[6:0]
5.4.2 Second Dword
This section describes the second Dword of the Read/Write Instruction
register.
Figure 5.8
31
Read/Write Instruction - Second Dword
24 23
16 15
8
7
0
DSPS Register
DA
Destination Address
[31:0]
This field contains the 32-bit destination address where
the data is to move.
5.4.3 Read-Modify-Write Cycles
During these cycles the register is read, the selected operation is
performed, and the result is written back to the source register.
The Add operation is used to increment or decrement register values (or
memory values if used in conjunction with a Memory-to-Register Move
operation) for use as loop counters.
Subtraction is not available when SCSI First Byte Received (SFBR) is
used instead of data8 in the instruction syntax. To subtract one value
from another when using SFBR, first XOR the value to subtract
(subtrahend) with 0xFF, and add 1 to the resulting value. This creates the
2’s complement of the subtrahend. The two values are then added to
obtain the difference.
5-24
SCSI SCRIPTS Instruction Set
5.4.4 Move To/From SFBR Cycles
All operations are read-modify-writes. However, two registers are
involved, one of which is always the SCSI First Byte Received (SFBR).
The possible functions of this instruction are:
Table 5.1
•
Write one byte (value contained within the SCRIPTS instruction) into
any chip register.
•
Move to/from the SCSI First Byte Received (SFBR) from/to any other
register.
•
Alter the value of a register with AND, OR, ADD, XOR, SHIFT LEFT,
or SHIFT RIGHT operators.
•
After moving values to the SCSI First Byte Received (SFBR), the
compare and jump, call, or similar instructions are used to check the
value.
•
A Move-to-SFBR followed by a Move-from-SFBR is used to perform
a register to register move.
Read/Write Instructions1
Opcode 111
Read Modify Write
Opcode 110
Move to SFBR
Opcode 101
Move from SFBR
000
Move data into register.
Syntax: “Move data8 to
RegA”
Move data into SCSI First
Byte Received (SFBR)
register. Syntax: “Move
data8 to SFBR”
Move data into register.
Syntax: “Move data8 to
RegA”
0012
Shift register one bit to the
left and place the result in
the same register. Syntax:
“Move RegA SHL RegA”
Shift register one bit to the
left and place the result in
the SCSI First Byte
Received (SFBR) register.
Syntax: “Move RegA SHL
SFBR”
Shift the SFBR register one
bit to the left and place the
result in the register. Syntax:
“Move SFBR SHL RegA”
010
OR data with register and
place the result in the same
register. Syntax: “Move
RegA | data8 to RegA”
OR data with register and
place the result in the SCSI
First Byte Received (SFBR)
register. Syntax: “Move
RegA | data8 to SFBR”
OR data with SFBR and
place the result in the
register. Syntax: “Move
SFBR | data8 to RegA”
Operator
Read/Write Instructions
5-25
Table 5.1
Read/Write Instructions1 (Cont.)
Opcode 111
Read Modify Write
Opcode 110
Move to SFBR
Opcode 101
Move from SFBR
011
XOR data with register and
place the result in the same
register. Syntax: “Move
RegA XOR data8 to RegA”
XOR data with register and
place the result in the SCSI
First Byte Received (SFBR)
register. Syntax: “Move
RegA XOR data8 to SFBR”
XOR data with SFBR and
place the result in the
register. Syntax: “Move
SFBR XOR data8 to RegA”
100
AND data with register and
place the result in the same
register. Syntax: “Move
RegA & data8 to RegA”
AND data with register and
place the result in the SCSI
First Byte Received (SFBR)
register. Syntax: “Move
RegA & data8 to SFBR”
AND data with SFBR and
place the result in the
register. Syntax: “Move
SFBR & data8 to RegA”
1012
Shift register one bit to the
right and place the result in
the same register. Syntax:
“Move RegA SHR RegA”
Shift register one bit to the
right and place the result in
the SCSI First Byte
Received (SFBR) register.
Syntax: “Move RegA SHR
SFBR”
Shift the SFBR register one
bit to the right and place the
result in the register. Syntax:
“Move SFBR SHR RegA”
110
Add data to register without
carry and place the result
in the same register.
Syntax: “Move RegA +
data8 to RegA”
Add data to register without
carry and place the result in
the SCSI First Byte
Received (SFBR) register.
Syntax: “Move RegA + data8
to SFBR”
Add data to SFBR without
carry and place the result in
the register. Syntax: “Move
SFBR + data8 to RegA”
111
Add data to register with
carry and place the result
in the same register.
Syntax: “Move RegA +
data8 to RegA with carry”
Add data to register with
carry and place the result in
the SCSI First Byte
Received (SFBR) register.
Syntax: “Move RegA + data8
to SFBR with carry”
Add data to SFBR with carry
and place the result in the
register. Syntax: “Move
SFBR + data8 to RegA with
carry”
Operator
1. Substitute the desired register name or address for “RegA” in the syntax examples. data8 indicates
eight bits of data. Use SFBR instead of data8 to add two register values.
2. Data is shifted through the Carry bit and the Carry bit is shifted into the data byte.
5-26
SCSI SCRIPTS Instruction Set
5.5 Transfer Control Instructions
This section describes transfer control instructions for the first Dword,
second Dword, and third Dword.
5.5.1 First Dword
This section describes the first Dword of the Transfer Control Instruction
register.
Figure 5.9
31 30 29
Transfer Control Instructions - First Dword
27 26
24 23 22 21 20 19 18 17 16 15
DCMD Register
8
7
0
DBC Register
IT[1:0] OPC[2:0] SCSIP[2:0] RA J CT IF TF CD CP VP
IT[1:0]
OPC[2:0]
MC
DC
Instruction Type Transfer Control Instruction
[31:30]
Opcode
[29:27]
This 3-bit field specifies the type of transfer control
instruction to execute. All transfer control instructions can
be conditional. They can be dependent on a true/false
comparison of the ALU Carry bit, or a comparison of the
SCSI information transfer phase with the Phase field,
and/or a comparison of the First Byte Received with the
Data Compare field. Each instruction can operate in the
initiator or target mode.
OPC2
OPC1
OPC0
Instruction Defined
0
0
0
Jump
0
0
1
Call
0
1
0
Return
0
1
1
Interrupt
1
x
x
Reserved
Jump Instruction
The LSI53C1000 can do a true/false comparison of the
ALU carry bit, or compare the phase and/or data as
defined by the Phase Compare, Data Compare and
True/False bit fields. If the comparisons are true, it loads
Transfer Control Instructions
5-27
the DMA SCRIPTS Pointer (DSP) register with the
contents of the DMA SCRIPTS Pointer Save (DSPS)
register. The DSP register now contains the address of
the next instruction.
If the comparisons are false, the LSI53C1000 fetches the
next instruction from the address pointed to by the DMA
SCRIPTS Pointer (DSP) register, leaving the instruction
pointer unchanged.
When the JUMP64 instruction is used, a third Dword is
fetched and loaded into the SCRIPT Fetch Selector
(SFS) register. Bit 22 indicates whether the jump is to a
32-bit address (0) or a 64-bit address (1). All
combinations of jumps are still valid for JUMP64.
Call Instruction
The LSI53C1000 can do a true/false comparison of the
ALU carry bit, or compare the phase and/or data as
defined by the Phase Compare, Data Compare, and
True/False bit fields. If the comparisons are true, it loads
the DMA SCRIPTS Pointer (DSP) register with the
contents of the DMA SCRIPTS Pointer Save (DSPS)
register and that address value becomes the address of
the next instruction.
When the LSI53C1000 executes a Call instruction, the
instruction pointer contained in the DMA SCRIPTS
Pointer (DSP) register is stored in the Temporary (TEMP)
register. Since the TEMP register is not a stack and can
only hold one Dword, nested call instructions are not
allowed.
If the comparisons are false, the LSI53C1000 fetches the
next instruction from the address pointed to by the DMA
SCRIPTS Pointer (DSP) register and the instruction
pointer is not modified.
Return Instruction
The LSI53C1000 can do a true/false comparison of the
ALU carry bit, or compare the phase and/or data as
defined by the Phase Compare, Data Compare, and
True/False bit fields. If the comparisons are true, it loads
the DMA SCRIPTS Pointer (DSP) register with the
contents of the DMA SCRIPTS Pointer Save (DSPS)
register. That address value becomes the address of the
next instruction.
5-28
SCSI SCRIPTS Instruction Set
When a Return instruction is executed, the value stored
in the Temporary (TEMP) register is returned to the DMA
SCRIPTS Pointer (DSP) register. The LSI53C1000 does
not check to see whether the Call instruction has already
been executed. It does not generate an interrupt if a
Return instruction is executed without previously
executing a Call instruction.
If the comparisons are false, the LSI53C1000 fetches the
next instruction from the address pointed to by the DMA
SCRIPTS Pointer (DSP) register and the instruction
pointer is not modified.
Interrupt Instruction
The LSI53C1000 can do a true/false comparison of the
ALU carry bit, or compare the phase and/or data as
defined by the Phase Compare, Data Compare, and
True/False bit fields. If the comparisons are true, the
LSI53C1000 generates an interrupt by asserting the INT/
signal.
The 32-bit address field stored in the DMA SCRIPTS
Pointer Save (DSPS) register can contain a unique
interrupt service vector. When servicing the interrupt, this
unique status code allows the Interrupt Service Routine
to quickly identify the point at which the interrupt
occurred.
The LSI53C1000 halts and the DMA SCRIPTS Pointer
(DSP) register must be written to before starting any
further operation.
Interrupt-on-the-Fly Instruction
The LSI53C1000 can do a true/false comparison of the
ALU carry bit or compare the phase and/or data as
defined by the Phase Compare, Data Compare, and
True/False bit fields. If the comparisons are true, and the
Interrupt-on-the-Fly bit Interrupt Status Zero (ISTAT0),
bit 2) is set, the LSI53C1000 asserts the Interrupt-on-theFly bit.
SCSIP[2:0]
SCSI Phase
[26:24]
This 3-bit field corresponds to the three SCSI bus phase
signals that are compared with the phase lines latched
when SREQ/ is asserted. Comparisons can be performed
to determine the SCSI phase actually being driven on the
Transfer Control Instructions
5-29
SCSI bus. The following table describes the possible
combinations and their corresponding SCSI phase.
These bits are only valid when the LSI53C1000 is
operating in the initiator mode. Clear these bits when the
LSI53C1000 is operating in the target mode.
RA
MSG
C/D
I/O SCSI Phase
0
0
0
ST Data-Out
0
0
1
ST Data-In
0
1
0
Command
0
1
1
Status
1
0
0
DT Data-Out
1
0
1
DT Data-In
1
1
0
Message-Out
1
1
1
Message-In
Relative Addressing Mode
23
When this bit is set, the 24-bit signed value in the DMA
SCRIPTS Pointer Save (DSPS) register is used as a
relative offset from the current DMA SCRIPTS Pointer
(DSP) address, which is pointing to the next instruction
and not the one currently executing. The relative mode
does not apply to Return and Interrupt SCRIPTS.
Jump/Call an Absolute Address
Start execution at the new absolute address.
Command
Condition Codes
Absolute Alternate Address
Jump/Call a Relative Address
Start execution at the current address plus (or minus) the
relative offset.
Command
Condition Codes
Don’t Care
Alternate Jump Offset
The SCRIPTS program counter is a 32-bit value pointing
to the SCRIPTS currently under execution by the
LSI53C1000. The next address is formed by adding the
5-30
SCSI SCRIPTS Instruction Set
32-bit program counter to the 24-bit signed value of the
last 24 bits of the Jump or Call instruction. Because it is
signed (2’s complement), the jump can be forward or
backward.
A relative transfer can be to any address within a
16 Mbyte segment. The program counter is combined
with the 24-bit signed offset (using addition or
subtraction) to form the new execution address.
SCRIPTS programs may contain a mixture of direct
jumps and relative jumps to provide maximum versatility
when writing SCRIPTS. For example, major sections of
code can be accessed with far calls using the 32-bit
physical address, then local labels can be called using
relative transfers. If a SCRIPT is written using only
relative transfers it does not require any run time
alteration of physical addresses, and can be stored in and
executed from a PROM.
J
32/64-Bit Jump
22
When this bit is cleared, the jump address is 32-bits wide.
When this bit is set, the jump address is 64-bits wide.
CT
Carry Test
21
When this bit is set, decisions based on the ALU carry bit
can be made. True/False comparisons are legal, but Data
Compare and Phase Compare are illegal.
IF
Interrupt-on-the-Fly
20
When this bit is set, the interrupt instruction does not halt
the SCRIPTS processor. Once the interrupt occurs, the
Interrupt-on-the-Fly bit (Interrupt Status Zero (ISTAT0),
bit 2) is asserted.
TF
Jump If True/False
19
This bit determines whether the LSI53C1000 branches
when a comparison is true or when a comparison is false.
This bit applies to phase compares, data compares, and
carry tests. If both the Phase Compare and Data
Compare bits are set, then both compares must be true
to branch on a true condition. Both compares must be
false to branch on a false condition.
Transfer Control Instructions
5-31
CD
Bit 19
Result of
Compare
0
False
Jump Taken
0
True
No Jump
1
False
No Jump
1
True
Jump Taken
Action
Compare Data
18
When this bit is set, the first byte received from the SCSI
data bus (contained in the SCSI First Byte Received
(SFBR) register) is compared with the Data to be
Compared Field in the Transfer Control instruction. The
Wait for Valid Phase bit controls when this compare
occurs. The Jump if True/False bit determines the
condition (true or false) to branch on.
CP
Compare Phase
17
When the LSI53C1000 is in the initiator mode, this bit
controls phase compare operations. When this bit is set,
the SCSI phase signals (latched by SREQ/) are
compared to the Phase Field in the Transfer Control
instruction. If they match, the comparison is true. The
Wait for Valid Phase bit controls when the compare
occurs. When the LSI53C1000 is operating in the target
mode and this bit is set it, tests for an active SCSI SATN/
signal.
VP
Wait For Valid Phase
16
If the Wait for Valid Phase bit is set, the LSI53C1000
waits for a previously unserviced phase before comparing
the SCSI phase and data.
If the Wait for Valid Phase bit is cleared, the LSI53C1000
compares the SCSI phase and data immediately.
MC
5-32
Data Compare Mask
[15:8]
The Data Compare Mask allows a SCRIPT to test certain
bits within a data byte. During the data compare, if any
mask bits are set, the corresponding bit in the SCSI First
Byte Received (SFBR) data byte is ignored. For instance,
a mask of 0b01111111 and data compare value of
0b1XXXXXXX allows the SCRIPTS processor to
determine whether or not the high order bit is set while
ignoring the remaining bits.
SCSI SCRIPTS Instruction Set
DC
Data Compare Value
[7:0]
This 8-bit field is the data compared against the SCSI
First Byte Received (SFBR) register. These bits are used
in conjunction with the Data Compare Mask Field to test
for a particular data value. If the COM bit (DMA Control
(DCNTL), bit 0) is cleared, the value in the SFBR register
may not be stable. In this case, do not use instructions
using this data compare value.
5.5.2 Second Dword
This section describes the second Dword of the Transfer Control
Instruction register.
Figure 5.10 Transfer Control Instructions - Second Dword
31
24 23
16 15
8
7
0
DSPS Register
Jump Address
[31:0]
This 32-bit field contains the address of the next
instruction to fetch when a jump is taken. Once the
LSI53C1000 fetches the instruction from the address
pointed to by these 32-bits, this address is incremented
by 4, loaded into the DMA SCRIPTS Pointer (DSP)
register and becomes the current instruction pointer.
5.5.3 Third Dword
This section describes the third Dword of the Transfer Control Instruction
register.
Figure 5.11 Transfer Control Instructions - Third Dword
31
24 23
16 15
8
7
0
SFS Register (Used for JUMP64 Instruction)
JUMP64 Address
[31:0]
This 32-bit field contains the upper Dword of a 64-bit
address of the next instruction to fetch when a JUMP64
is taken.
Transfer Control Instructions
5-33
5.6 Memory Move Instructions
For Memory Move instructions, bits 5 and 4 (SIOM and DIOM) in the
DMA Mode (DMODE) register determine whether the source or
destination addresses reside in memory or I/O space. By setting these
bits appropriately, data may be moved within memory space, within I/O
space, or between the two address spaces.
The Memory Move instruction is used to copy the specified number of
bytes from the source address to the destination address.
For memory moves where the data read is from the 64-bit address
space, the upper Dword of the address resides in the Memory Move
Read Selector (MMRS) register. For memory moves where the data is
written to the 64-bit address space, the upper Dword of the address
resides in the Memory Move Write Selector (MMWS) register.
Allowing the LSI53C1000 to perform memory moves frees the system
processor for other tasks and moves data at higher speeds than available
from current DMA controllers. Up to 16 Mbytes may be transferred with
one instruction. There are two restrictions:
•
Both the source and destination addresses must start with the same
address alignment (A[1:0]) must be the same). If the source and
destination are not aligned, then an illegal instruction interrupt
occurs. For the PCI Cache Line Size (CLS) register setting to take
effect, the source and destination must be the same distance from a
cache line boundary.
•
Indirect addresses are not allowed. A burst of data is fetched from
the source address, put into the DMA FIFO and then written out to
the destination address. The move continues until the byte count
decrements to zero, then another SCRIPT is fetched from system
memory.
The DMA SCRIPTS Pointer Save (DSPS) and Data Structure Address
(DSA) registers are additional holding registers used during the Memory
Move. However, the contents of the Data Structure Address (DSA)
register are preserved.
5-34
SCSI SCRIPTS Instruction Set
Figure 5.12 Memory Move Instructions - First Dword
31
29 28
25 24 23
16 15
DCMD Register
IT[2:0]
R
8
7
0
DBC Register
NF
TC[23:0]
IT[2:0]
Instruction Type - Memory Move
R
Reserved
[28:25]
These bits are reserved and must be zero. If any of these
bits are set, an illegal instruction interrupt occurs.
NF
No Flush
24
When this bit is set, the LSI53C1000 performs a Memory
Move without flushing the prefetch unit. When this bit is
cleared, the Memory Move instruction automatically
flushes the prefetch unit. Use the No Flush option if the
source and destination are not within four instructions of
the current Memory Move instruction.
Note:
TC[23:0]
[31:29]
This bit has no effect unless the Prefetch Enable bit in the
DMA Control (DCNTL) register is set. For information on
SCRIPTS instruction prefetching, see Chapter 2, “Functional Description.”
Transfer Count
[23:0]
The number of bytes to transfer is stored in the lower
24 bits of the first instruction word.
5.6.1 Read/Write System Memory from a SCRIPT
By using the Memory Move instruction, single or multiple register values
are transferred to or from system memory.
Because the LSI53C1000 responds to addresses as defined in the Base
Address Register Zero (BAR0) (I/O) or Base Address Register One
(BAR1) (MEMORY) registers, the device can be accessed during a
Memory Move operation if the source or destination address decodes to
within the chip’s register space. If this occurs, the register indicated by
the lower seven bits of the address is taken as the data source or
destination. In this way, register values are saved to system memory and
later restored, and SCRIPTS can make decisions based on data values
in system memory.
Memory Move Instructions
5-35
The SCSI First Byte Received (SFBR) is not writable using the CPU, and
therefore not by a Memory Move. However, it can be loaded using
SCRIPTS Read/Write operations. To load the SFBR with a byte stored
in system memory, first move the byte to an intermediate LSI53C1000
register (for example, a SCRATCH register), and then to the SCSI First
Byte Received (SFBR).
The same address alignment restrictions apply to register access
operations as to normal memory-to-memory transfers.
5.6.2 Second Dword
This section describes the second Dword of the Memory Move
Instruction register.
Figure 5.13 Memory Move Instructions - Second Dword
-
31
24 23
16 15
8
7
0
DSPS Register
DSPS Register
[31:0]
These bits contain the source address of the Memory
Move.
If the source address is in the 64-bit address space, the
bits will be contained in the Memory Move Read Selector
(MMRS) register.
31
24 23
16 15
8
7
0
MMRS Register
5.6.3 Third Dword
This section describes the third Dword of the Memory Move Instruction
register.
5-36
SCSI SCRIPTS Instruction Set
Figure 5.14 Memory Move Instructions - Third Dword
31
24 23
16 15
8
7
0
TEMP Register
TEMP Register
[31:0]
These bits contain the destination address for the
Memory Move.
If the destination address is in the 64-bit address space,
the bits will be contained in the Memory Move Write
Selector (MMWS) register.
31
24 23
16 15
8
7
0
MMWS Register
5.7 Load and Store Instructions
The Load and Store instructions provide a more efficient way to move
data from/to memory to/from an internal register in the chip without using
the normal memory move instruction.
The load and store instructions are represented by two Dword opcodes.
The first Dword contains the DMA Command (DCMD) and DMA Byte
Counter (DBC) register values. The second Dword contains the DMA
SCRIPTS Pointer Save (DSPS) value. This is either the actual memory
location of where to load/store, or the offset from the Data Structure
Address (DSA), depending on the value of bit 28 (DSA Relative).
For load operations where the data is read from the 64-bit address
space, the upper Dword of address resides in the Memory Move Read
Selector (MMRS) register. For store operations where the data is written
to the 64-bit address space, the upper Dword of address resides in the
Memory Move Write Selector (MMWS) register.
A maximum of 4 bytes may be moved with these instructions. The
register address and memory address must have the same byte
alignment, and the count set such that it does not cross Dword
boundaries. The memory address may not map back to the chip,
Load and Store Instructions
5-37
excluding RAM and ROM. If it does, a PCI read/write cycle occurs (the
data does not actually transfer to/from the chip), and the chip issues an
interrupt (Illegal Instruction Detected) immediately following.
Bits A1, A0
Number of Bytes Allowed to Load/Store
00
One, two, three or four
01
One, two, or three
10
One or two
11
One
The SIOM and DIOM bits in the DMA Mode (DMODE) register determine
whether the destination or source address of the instruction is in Memory
space or I/O space, as illustrated in the following table. The Load/Store
utilizes the PCI commands for I/O read and I/O write to access the I/O
space.
Bit
Source
Destination
SIOM (Load)
Memory
Register
DIOM (Store)
Register
Memory
5.7.1 First Dword
This section describes the first Dword of the Load and Store Instruction
register.
Figure 5.15 Load and Store Instruction - First Dword
31
29 28 27 26 25 24 23
16 15
3
DCMD Register
IT[2:0]
1
1
1
DSA
x
R
0
NF LS
0
x
x
A[7:0]
x
IT[2:0]
5-38
2
0
DBC Register
x
x
x
x
R
x
x
x
0
0
0
0
0
0
0
BC
0
0
0
0
0
0
x
x
x
Instruction Type
[31:29]
These bits should be 0b111, indicating the Load and
Store instruction.
SCSI SCRIPTS Instruction Set
DSA
DSA Relative
28
When this bit is cleared, the value in the DMA SCRIPTS
Pointer Save (DSPS) is the actual 32-bit memory address
used to perform the Load/Store to/from. When this bit is
set, the chip determines the memory address to perform
the Load/Store to/from by adding the 24-bit signed offset
value in the DMA SCRIPTS Pointer Save (DSPS) to the
Data Structure Address (DSA).
R
Reserved
NF
No Flush (Store instruction only)
25
When this bit is set, the LSI53C1000 performs a Store
without flushing the prefetch unit. When this bit is cleared,
the Store instruction automatically flushes the prefetch
unit. Use No Flush if the source and destination are not
within four instructions of the current Store instruction.
This bit has no effect on the Load instruction.
Note:
[27:26]
This bit has no effect unless the Prefetch Enable bit in the
DMA Control (DCNTL) register is set. For information on
SCRIPTS instruction prefetching, see Chapter 2, “Functional Description.”
LS
Load/Store
24
When this bit is set, the instruction is a Load. When
cleared, it is a Store.
A[7:0]
Register Address
[23:16]
A[7:0] selects the register to load/store to/from within the
LSI53C1000.
R
Reserved
BC
Byte Count
This value is the number of bytes to load/store.
[15:3]
[2:0]
5.7.2 Second Dword
This section describes the second Dword of the Load and Store
Instruction register.
Load and Store Instructions
5-39
Figure 5.16 Load and Store Instructions - Second Dword
31
24 23
16 15
8
7
0
8
7
0
DSPS Register - Memory I/O Address/DSA Offset
31
24 23
16 15
MMRS/MMWS Register
Memory I/O Address / DSA Offset
[31:0]
This is the actual memory location of where to load/store,
or the offset from the Data Structure Address (DSA)
register value.
5-40
SCSI SCRIPTS Instruction Set
Chapter 6
Specifications
This chapter specifies the LSI53C1000 electrical and mechanical
characteristics. It is divided into the following sections:
•
Section 6.1, “DC Characteristics”
•
Section 6.2, “TolerANT Technology Electrical Characteristics”
•
Section 6.3, “AC Characteristics”
•
Section 6.4, “PCI and External Memory Interface Timing Diagrams”
•
Section 6.5, “SCSI Timing Diagrams”
•
Section 6.6, “Package Drawings”
6.1 DC Characteristics
This section of the manual describes the LSI53C1000 DC characteristics.
Tables 6.1 through 6.12 give current and voltage specifications.
Figures 6.1 and 6.2 are driver schematics.
LSI53C1000 PCI to Ultra160 SCSI Controller
6-1
Table 6.1
Absolute Maximum Stress Ratings
Parameter
Min
Max1
Unit
Test Conditions
TSTG
Storage temperature
−55
150
°C
–
VDD
Supply voltage
−0.5
4.5
V
–
VIN
Input voltage
−0.3
5.55
V
–
Input voltage PCI pins
−5.5
11.0
V
–
Latch-up current
±150
–
mA
–
Lead temperature
–
250
°C
<10 seconds
Electrostatic discharge
–
2K
V
MIL-STD 883C,
Method 3015.7
Symbol
VIN-PCI
ILP2
T
3
ESD
1. Stresses beyond those listed above may cause permanent damage to the device. These are stress
ratings only; functional operation of the device at these or any other conditions beyond those
indicated in the Operating Conditions section of the manual is not implied.
2. −2 V < VPIN < 8 V.
3. SCSI pins only.
Table 6.2
Symbol
VDD
IDD
IDD-SCSI
TA
θJA
Operating Conditions
Parameter
Supply voltage
Min
Max1
Unit
Test Conditions
3.13
3.47
V
–
(dynamic)2
–
800
mA
–
LVD Mode Supply Current
(dynamic)
–
1
A
–
Operating free air
0
70
°C
–
Thermal resistance
(junction to ambient air)
–
20
°C/W
–
Supply current
1. Conditions that exceed the operating limits may cause the device to function incorrectly.
Core and analog supply only.
6-2
Specifications
Table 6.3
Symbol
LVD Driver SCSI Signals1—SD[15:0], SDP[1:0], SREQ/, SACK/, SMSG/,
SIO/, SCD/, SATN/, SBSY/, SSEL/, SRST/
Parameter
Min
Max
Units
Test Conditions
IO+
Source (+) current
−9.6
−14.4
mA
Asserted state
IO−
Sink (−) current
9.6
14.4
mA
Asserted state
IO+
Source (+) current
6.4
9.6
mA
Negated state
IO−
Sink (−) current
−6.4
−9.6
mA
Negated state
IOZ
3-state leakage
–
20
µA
–
1. Note: VCM = 0.7–1.8 V (Common Mode, nominal ~1.2V), RL = 0–110 Ω, Rbias = 10.0 kΩ.
Figure 6.1
LVD Driver
RL
IO+
2
+
+
VCM
−
IO-
RL
2
Table 6.4
Symbol
LVD Receiver SCSI Signals1—SD[15:0], SDP[1:0], SREQ/, SACK/, SMSG/,
SIO/, SCD/, SATN/, SBSY/, SSEL/, SRST/
Parameter
Min
Max
Units
Test Conditions
VI
LVD receiver voltage asserting
60
–
mV
Differential voltage
VI
LVD receiver voltage negating
−60
–
mV
Differential voltage
1. Note: VCM = 0.7–1.8 V (Common Mode Voltage, nominal ~1.2 V.)
DC Characteristics
6-3
Figure 6.2
LVD Receiver
+
VI
+
VCM
−
2
Symbol
+
+
−
VI
2
Table 6.5
−
−
DIFFSENS SCSI Signals
Parameter
Min
Max
Unit
Test Conditions
VIH
HVD sense voltage
2.4
5.05
V
Note 1
VS
LVD sense voltage
0.7
1.9
V
Note 1
VIL
SE sense voltage
VSS −0.35
0.5
V
Note 1
IOZ
3-state leakage
−10
10
µA
0 VDD = 3 Max
1. Functional test specified VIH/VIL for each mode.
Table 6.6
Symbol
Input Capacitance
Min
Max
Unit
Test Conditions
Input capacitance of input pads
–
7
pF
Guaranteed by design
CIO
Input capacitance of I/O pads
–
15
pF
Guaranteed by design
CPCI
Input capacitance of PCI pads
–
8
pF
Guaranteed by design
CLVD
Input capacitance of LVD pads
–
8
pF
6.5 pf Pad
1.5 pf Package
CI
6-4
Parameter
Specifications
Table 6.7
Symbol
8 mA Bidirectional Signals—GPIO0_FETCH/, GPIO1_MASTER/, GPIO2,
GPIO3, GPIO4
Parameter
Min
Max
Unit
Test Conditions
VIH
Input high voltage
2.0
5.55
V
–
VIL
Input low voltage
−0.3
0.8
V
–
VOH
Output high voltage
2.4
VDD
V
−8 mA
VOL
Output low voltage
VSS
0.4
V
8 mA
IOZ
3-state leakage
−10
10
µA
–
Pull down current
25
–
µA
–
IPULL
Table 6.8
Symbol
4 mA Bidirectional Signals—MAD[7:0]
Parameter
Min
Max
Unit
Test Conditions
VIH
Input high voltage
2.0
5.55
V
–
VIL
Input low voltage
−0.3
0.8
V
–
VOH
Output high voltage
2.4
VDD
V
−4 mA
VOL
Output low voltage
VSS
0.4
V
4 mA
IOZ
3-state leakage
−10
10
µA
–
IPULL
Pull up current
25
–
µA
–
Table 6.9
Symbol
4 mA Output Signals—MAS[1:0]/, MCE/, MOE/_TESTOUT1, MWE/, TDO
Parameter
Min
Max
Unit
Test Conditions
VOH
Output high voltage
2.4
VDD
V
−4 mA
VOL
Output low voltage
VSS
0.4
V
4 mA
IOZ
3-state leakage
−10
10
µA
–
1. MOE/_TESTOUT is not tested for 3-state leakage. It cannot be 3-stated.
DC Characteristics
6-5
Table 6.10
Symbol
8 mA PCI Bidirectional Signals—AD[63:0], C_BE[7:0]/, FRAME/, IRDY/,
TRDY/, DEVSEL/, STOP/, PERR/, PAR, PAR64, REQ64/, ACK64/
Parameters
Min
Max
Unit
Test Conditions
VIH
Input high voltage
0.5 VDD
VDD +0.5
V
–
VIL
Input low voltage
−0.5
0.3 VDD
V
–
VOH
Output high voltage
0.9 VDD
VDD
V
−8 mA
VOL
Output low voltage
VSS
0.1 VDD
V
8 mA
IOZ
3-state leakage
−10
10
µA
–
25
–
µA
–
IPULL-DOWN Pull down current1
1. Pull-down text does not apply to AD[31:0] and C_BE[3:0]/.
Table 6.11
Symbol
Input Signals1—CLK, GNT/, IDSEL, INT_DIR, RST/, SCLK, TCK, TDI,
TEST_HSC, TEST_RST/, TEST_PD, TMS
Parameters
Min
Max
Unit
Test Conditions
VIH
Input high voltage
2.0
5.55
V
–
VIL
Input low voltage
−0.3
0.8
V
–
IIN
3-state leakage
−10
10
µA
–
Pull current
25
−
µA
–
IPULL-UP
1. Pull text does not apply to CKL, GNT/, IDSEL, RST/, and SCLK.
Table 6.12
Symbol
8 mA Output Signals1—INTA/, INTB/, ALT_INTA/, ALT_INTB/, REQ/, SERR/
Parameters
Max
Unit
Test Conditions
VOH
Output high voltage
0.9 VDD
VDD
V
−8 mA
VOL
Output low voltage
VDD
0.1 VDD
V
8 mA
IOZ
3-state leakage
−10
10
µA
–
Pull current
25
–
µA
–
IPULL-UP
1. Pull text does not apply to REQ/ and SERR/.
6-6
Min
Specifications
6.2 TolerANT Technology Electrical Characteristics
The LSI53C1000 features TolerANT technology, which includes active
negation on the SCSI drivers and input signal filtering on the SCSI
receivers. Active negation actively drives the SCSI Request,
Acknowledge, Data, and Parity signals HIGH rather than allowing them
to be passively pulled up by terminators. Table 6.13 provides electrical
characteristics for SE SCSI signals. Figures 6.3 through 6.7 provide
reference information for testing SCSI signals.
Table 6.13
Symbol
TolerANT Technology Electrical Characteristics for SE SCSI Signals1
Parameter
Min
Max
Units
Test Conditions
VOH2
Output high voltage
2.2
3.7
V
IOH = 7 mA
VOL
Output low voltage
0.0
0.5
V
IOL = 48 mA
VIH
Input high voltage
2.0
–
V
–
VIL
Input low voltage
–
0.8
V
Referenced to VSS
VIK
Input clamp voltage
−0.66
−0.77
V
Vpp = 4.75 V;
I1 = −20 mA
VTH
Threshold, HIGH to LOW
1.15
1.25
V
–
VTL
Threshold, LOW to HIGH
1.55
1.65
V
–
Hysteresis
300
500
mV
–
VTH-VTL
IOH2
Output high current
0
7
mA
VOH = 2.2 V
IOL
Output low current
48
–
mA
VOL = 0.5 V
IOSH2
Short-circuit output high
current
48
–
mA
Short to VDD3
IOSL
Short-circuit output low
current
22
–
mA
Short to VSS
ILH
Input high leakage
–
20
µA
−0.5<VDD<5.25
VPIN = 2.7 V
ILL
Input low leakage
–
20
µA
−0.5<VDD<5.25
VPIN = 0.5 V
RI
Input resistance
20
–
MΩ
SCSI pins
TolerANT Technology Electrical Characteristics
6-7
Table 6.13
Symbol
TolerANT Technology Electrical Characteristics for SE SCSI Signals1
(Cont.)
Min
Max
Units
Test Conditions
–
8
pF
PQFP
Rise time, 10% to 90%
6.7
14.7
ns
Figure 6.3
Fall time, 90% to 10%
5.7
17.2
ns
Figure 6.3
dVH/dt
Slew rate LOW to HIGH
100
470
mV/ns
Figure 6.3
dVL/dt
Slew rate HIGH to LOW
110
440
mV/ns
Figure 6.3
2
–
KV
MIL-STD-883C;
3015-7
Latch-up
100
–
mA
–
Filter delay
20
30
ns
Figure 6.4
Ultra filter delay
10
15
ns
Figure 6.4
Ultra2 filter delay
5
8
ns
Figure 6.4
Extended filter delay
40
60
ns
Figure 6.4
CP
tR
2
tF
ESD
Parameter
Capacitance per pin
Electrostatic discharge
1. These values are guaranteed by periodic characterization; they are not 100% tested on every
device.
2. Active negation outputs only: Data, Parity, SREQ/, SACK/. SCSI mode only (minus pins).
3. Single pin only; irreversible damage may occur if sustained for one second.
Figure 6.3
Rise and Fall Time Test Condition
47 Ω
20 pF
+
-
Figure 6.4
2.5 V
SCSI Input Filtering
t1
REQ/ or ACK/ Input
VTH
Note: t1 is the input filtering period.
6-8
Specifications
Figure 6.5
Hysteresis of SCSI Receivers
Received Logic Level
1.1
1.3
1
0
1.5
1.7
Input Voltage (Volts)
Figure 6.6
Input Current as a Function of Input Voltage
Input Current (milliAmperes)
+40
+20
14.4 V
8.2 V
0
−0.7 V
HIGH-Z
OUTPUT
−20
ACTIVE
−40
−4
0
4
8
12
16
Input Voltage (Volts)
TolerANT Technology Electrical Characteristics
6-9
Figure 6.7
Output Current as a Function of Output Voltage
100
Output Source Current (milliAmperes)
Output Sink Current (milliAmperes)
0
−200
−400
−600
−800
0
1
2
3
Output Voltage (Volts)
6-10
Specifications
4
5
80
60
40
20
0
0
1
2
3
4
Output Voltage (Volts)
5
6.3 AC Characteristics
The AC characteristics described in this section apply over the entire
range of operating conditions (refer to Section 6.1, “DC Characteristics”).
Chip timing is based on simulation at worst case voltage, temperature,
and processing. Timing was developed with a load capacitance of 50 pF.
Table 6.14 and Figure 6.8 provide external clock timing data.
Table 6.14
External Clock
66 MHz PCI
Symbol
t1
t2
t3
t4
Parameter
33 MHz PCI1
Min
Max
Min
Max
Units
PCI Bus clock period
15
30
30
250
ns
SCSI clock period
25
25
25
25
ns
6
–
11
–
ns
SCLK LOW time
10
15
10
15
ns
PCI CLK HIGH time
6
–
11
–
ns
SCLK HIGH time
10
15
10
15
ns
PCI CLK slew rate
1.5
4
1
4
V/ns
PCI CLK LOW
time2
1. The minimum PCI Clock frequency is 33 MHz.
2. Duty cycle not to exceed 60/40.
Figure 6.8
External Clock
t1
t3
CLK, SCLK 1.4 V
t4
AC Characteristics
t2
6-11
Table 6.15 and Figure 6.9 provide Reset Input timing data.
Table 6.15
Symbol
Reset Input
Parameter
Min
Max
Units
t1
Reset pulse width
10
–
tCLK
t2
Reset deasserted setup to CLK HIGH
0
–
ns
t3
MAD setup time to CLK HIGH (for configuring
the MAD bus only)
20
–
ns
t4
MAD hold time from CLK HIGH (for configuring
the MAD bus only)
20
–
ns
Figure 6.9
Reset Input
CLK
t1
t2
RST/
t3
Valid
Data
MAD*
*When enabled
6-12
Specifications
t4
Table 6.16 and Figure 6.10 provide Interrupt Output timing data.
Table 6.16
Symbol
Interrupt Output
Parameter
Min
Max
Units
t1
CLK HIGH to IRQ/ LOW
2
11
ns
t2
CLK HIGH to IRQ/ HIGH
2
11
ns
t3
IRQ/ deassertion time
3
–
CLK
Figure 6.10 Interrupt Output
t2
t3
t1
IRQ/
CLK
6.4 PCI and External Memory Interface Timing Diagrams
Figure 6.11 through Figure 6.34 and tables 6.17 through 6.38 represent
signal activity when the LSI53C1000 accesses the PCI bus. This section
includes timing diagrams for access to three groups of memory
configurations. The first group applies to Target Timing. The second
group applies to Initiator Timing. The third group applies to External
Memory Timing.
Note:
Multiple byte accesses to the external memory bus
increase the read or write cycle by 11 clocks for each
additional byte.
Timing diagrams included in this section are:
•
Target Timing
–
PCI Configuration Register Read
–
PCI Configuration Register Write
–
Operating Registers/SCRIPTS RAM Read, 32 Bits
–
Operating Register/SCRIPTS RAM Read, 64 Bits
PCI and External Memory Interface Timing Diagrams
6-13
•
•
–
Operating Register/SCRIPTS RAM Write, 32 Bits
–
Operating Register/SCRIPTS RAM Write, 64 Bits
Initiator Timing
–
Nonburst Opcode Fetch, 32-Bit Address and Data
–
Burst Opcode Fetch, 32-Bit Address and Data
–
Back to Back Read, 32-Bit Address and Data
–
Back to Back Write, 32-Bit Address and Data
–
Burst Read, 32-Bit Address and Data
–
Burst Read, 64-Bit Address and Data
–
Burst Write, 32-Bit Address and Data
–
Burst Write, 64-Bit Address and Data
External Memory Timing
–
External Memory Read
–
External Memory Write
–
Normal/Fast Memory (≥ 128 Kbytes) Single Byte Access Read
Cycle
–
Normal/Fast Memory (≥ 128 Kbytes) Single Byte Access Write
Cycle
–
Normal/Fast Memory (≥ 128 Kbytes) Multiple Byte Access Read
Cycle
–
Normal/Fast Memory (≥ 128 Kbytes) Multiple Byte Access Write
Cycle
–
Slow Memory (≥ 128 Kbytes) Read Cycle
–
Slow Memory (≥ 128 Kbytes) Write Cycle
–
≤ 64 Kbytes ROM Read Cycle
–
≤ 64 Kbytes ROM Write Cycle
6.4.1 Target Timing
Tables 6.17 through 6.22 and figures 6.11 through 6.16 describe Target
timing.
6-14
Specifications
Table 6.17
PCI Configuration Register Read
66 MHz PCI
Symbol
Parameter
33 MHz PCI
Min
Max
Min
Max
Unit
t1
Shared signal input setup time
3
–
7
–
ns
t2
Shared signal input hold time
0
–
0
–
ns
t3
CLK to shared signal output valid
2
6
2
11
ns
Figure 6.11 PCI Configuration Register Read
CLK
(Driven by System)
t1
FRAME/
(Driven by System)
AD[31:0]
(Driven by Master-Addr;
LSI53C1000-Data)
t2
t1
t3
Addr In
Data Out
t2
t1
C_BE[3:0]/
(Driven by Master)
CMD
t2
Byte Enable
t2
t3
t1
PAR
(Driven by Master-Addr;
LSI53C1000-Data)
Out
In
t2
IRDY/
(Driven by Master)
t2
t1
t3
TRDY/
(Driven by LSI53C1000)
STOP/
(Driven by LSI53C1000)
t3
DEVSEL/
(Driven by LSI53C1000)
t1
IDSEL
(Driven by Master)
t2
PCI and External Memory Interface Timing Diagrams
6-15
Table 6.18
PCI Configuration Register Write
66 MHz PCI
Symbol
Parameter
33 MHz PCI
Min
Max
Min
Max
Unit
t1
Shared signal input setup time
3
–
7
–
ns
t2
Shared signal input hold time
0
–
0
–
ns
t3
CLK to shared signal output valid
2
6
2
11
ns
Figure 6.12 PCI Configuration Register Write
CLK
(Driven by System)
t1
FRAME/
(Driven by Master)
t2
t1
Addr In
t1
t2
AD[31:0]
(Driven by Master)
Data In
t2
t1
C_BE[3:0]/
(Driven by Master)
t2
CMD
Byte Enable
t2
t1
PAR
(Driven by Master)
t2
t1
t2
IRDY/
(Driven by Master)
t3
TRDY/
(Driven by LSI53C1000)
STOP/
(Driven by LSI53C1000)
t3
DEVSEL/
(Driven by LSI53C1000)
t1
IDSEL
(Driven by Master)
t2
6-16
Specifications
Table 6.19
Operating Register/SCRIPTS RAM Read, 32 Bits
66 MHz PCI
Symbol
Parameter
33 MHz PCI
Min
Max
Min
Max
Unit
t1
Shared signal input setup time
3
–
7
–
ns
t2
Shared signal input hold time
0
–
0
–
ns
t3
CLK to shared signal output valid
2
6
2
11
ns
Figure 6.13 Operating Registers/SCRIPTS RAM Read, 32 Bits
CLK
(Driven by System)
t1
FRAME/
(Driven by Master)
AD[31:0]
(Driven by Master-Addr;
LSI53C1000-Data)
t2
Addr In
t1
Data
Out
t1
C_BE[3:0]/
(Driven by Master)
t2
CMD
t2
PAR
(Driven by Master-Addr;
LSI53C1000-Data)
t3
Byte Enable
t2
t1
In
t3
Out
t2
t1
t2
IRDY/
(Driven by Master)
t3
TRDY/
(Driven by LSI53C1000)
STOP/
(Driven by LSI53C1000)
t3
DEVSEL/
(Driven by LSI53C1000)
PCI and External Memory Interface Timing Diagrams
6-17
Table 6.20
Operating Register/SCRIPTS RAM Read, 64 Bits
66 MHz PCI
Symbol
6-18
Parameter
33 MHz PCI
Min
Max
Min
Max
Unit
t1
Shared signal input setup time
3
–
7
–
ns
t2
Shared signal input hold time
0
–
0
–
ns
t3
CLK to shared signal output valid
2
6
2
11
ns
Specifications
Figure 6.14 Operating Register/SCRIPTS RAM Read, 64 Bits
CLK
(Driven by System)
t1
t2
REQ64/
(Driven by Master)
ACK64/
(Driven by LSI53C1000)
t2
t1
FRAME/
(Driven by Master)
t1
Addr
Lo
AD[31:0]
(Driven by Master-Addr;
LSI53C1000-Data)
t1
Dual
Addr
C_BE[3:0]/
(Driven by Master)
t1
AD[63:32]
(Driven by Master-Addr;
LSI53C1000-Data)
Addr
Hi
t2
Data
Out
t1
Bus
CMD
t2
Byte Enable
t2
Hi Addr
t1
C_BE[7:4]/
(Driven by Master)
t2
t1
Bus CMD
t2
PAR; PAR64
(Driven by Master-Addr;
LSI53C1000-Data)
t3
Byte Enable
t2
t1
t3
In
In
Out
t2
IRDY/
(Driven by Master)
t2
t1
TRDY/
(Driven by LSI53C1000)
t3
STOP/
(Driven by LSI53C1000)
t3
DEVSEL/
(Driven by LSI53C1000)
t3
PCI and External Memory Interface Timing Diagrams
6-19
Table 6.21
Operating Register/SCRIPTS RAM Read, 32 Bits
66 MHz PCI
Symbol
6-20
Parameter
33 MHz PCI
Min
Max
Min
Max
Unit
t1
Shared signal input setup time
3
–
7
–
ns
t2
Shared signal input hold time
0
–
0
–
ns
t3
CLK to shared signal output valid
2
6
2
11
ns
Specifications
Figure 6.15 Operating Register/SCRIPTS RAM Write, 32 Bits
CLK
(Driven by System)
t1
FRAME/
(Driven by Master)
t2
Addr In
t1
Data In
t1
C_BE[3:0]/
(Driven by Master)
t2
t1
AD[31:0]
(Driven by Master)
t2
CMD
Byte Enable
t2
PAR
(Driven by Master)
t2
In
In
t2
t2
IRDY/
(Driven by Master)
t1
t1
t1
t2
t3
TRDY/
(Driven by LSI53C1000)
STOP/
(Driven by LSI53C1000)
t3
DEVSEL/
(Driven by LSI53C1000)
PCI and External Memory Interface Timing Diagrams
6-21
Table 6.22
Operating Register/SCRIPTS RAM Write, 64 Bits
66 MHz PCI
Symbol
6-22
Parameter
33 MHz PCI
Min
Max
Min
Max
Unit
t1
Shared signal input setup time
3
–
7
–
ns
t2
Shared signal input hold time
0
–
0
–
ns
t3
CLK to shared signal output valid
2
6
2
11
ns
Specifications
Figure 6.16 Operating Register/SCRIPTS RAM Write, 64 Bits
CLK
(Driven by System)
t1
REQ64/
(Driven by Master)
t2
ACK64/
(Driven by LSI53C1000)
t1
FRAME/
(Driven by Master)
t2
AD[31:0]
(Driven by Master)
t1
Addr
Lo
C_BE[3:0]/
(Driven by Master)
t1
Dual
Addr
t1
AD[63:32]
(Driven by Master)
t2
Addr
Hi
t2
t1
Bus
CMD
t2
Byte Enable
t2
Hi Addr
Data In
t1
t1
C_BE[7:4]/
(Driven by Master)
Bus CMD
t2
PAR; PAR64
(Driven by Master)
Data In
Byte Enable
t2
t1
t1
In
In
In
t2
t2
IRDY/
(Driven by Master)
t2
t1
TRDY/
t3
(Driven by LSI53C1000)
STOP/
(Driven by LSI53C1000)
DEVSEL/
(Driven by LSI53C1000)
t3
PCI and External Memory Interface Timing Diagrams
6-23
6.4.2 Initiator Timing
Tables 6.23 through 6.30 and figures 6.17 and 6.24 describe Initiator
timing.
Table 6.23
Nonburst Opcode Fetch, 32-Bit Address and Data
66 MHz PCI
Symbol
6-24
Parameter
33 MHz PCI
Min
Max
Min
Max
Unit
t1
Shared signal input setup time
3
–
7
–
ns
t2
Shared signal input hold time
0
–
0
–
ns
t3
CLK to shared signal output valid
2
6
2
11
ns
t4
Side signal input setup time
5
–
10
–
ns
t5
Side signal input hold time
0
–
0
–
ns
t6
CLK to side signal output valid
2
6
2
12
ns
Specifications
Figure 6.17 Nonburst Opcode Fetch, 32-Bit Address and Data
CLK
(Driven by System)
REQ64/
(Driven by LSI53C1000)
ACK64/
(Driven by LSI53C1000)
GPIO0_FETCH/
(Driven by LSI53C1000)
GPIO1_MASTER/
(Driven by LSI53C1000)
REQ/
(Driven by LSI53C1000)
GNT/
(Driven by Arbiter)
t6
t4
t5
FRAME/
(Driven by LSI53C1000)
t3
AD[31:0]
(Driven by LSI53C1000Addr; Target-Data)
Data
In
t1
Addr
Out
Addr
Out
t2
t3
C_BE[3:0]/
(Driven by LSI53C1000)
PAR
(Driven by LSI53C1000Addr; Target-Data)
Data
In
CMD
Byte
Enable
t3
CMD
Byte
Enable
t1
t3
t2
IRDY/
(Driven by LSI53C1000)
t3
t1
TRDY/
(Driven by Target)
t2
STOP/
(Driven by Target)
t2
DEVSEL/
(Driven by Target)
t1
PCI and External Memory Interface Timing Diagrams
6-25
Table 6.24
Burst Opcode Fetch, 32-Bit Address and Data
66 MHz PCI
Symbol
6-26
Parameter
33 MHz PCI
Min
Max
Min
Max
Unit
t1
Shared signal input setup time
3
–
7
–
ns
t2
Shared signal input hold time
0
–
0
–
ns
t3
CLK to shared signal output valid
2
6
2
11
ns
t4
Side signal input setup time
5
–
10
–
ns
t5
Side signal input hold time
0
–
0
–
ns
t6
CLK to side signal output valid
2
6
2
12
ns
Specifications
Figure 6.18 Burst Opcode Fetch, 32-Bit Address and Data
CLK
(Driven by System)
REQ64/
(Driven by LSI53C1000)
ACK64/
(Driven by LSI53C1000)
GPIO0_FETCH/
(Driven by LSI53C1000)
GPIO1_MASTER/
(Driven by LSI53C1000)
REQ/
(Driven by LSI53C1000)
GNT/
(Driven by Arbiter)
t6
t4
t5
FRAME/
(Driven by LSI53C1000)
AD[31:0]
(Driven by LSI53C1000Addr; Target-Data)
t3
Data
In
t1
t3
Addr
Out
t2
t3
C_BE[3:0]/
(Driven by LSI53C1000)
Byte
Enable
CMD
t3
PAR
(Driven by LSI53C1000Addr; Target-Data)
IRDY/
(Driven by LSI53C1000)
TRDY/
(Driven by Target)
Data
In
t1
Out
In
t3
In
t2
t3
t1
t2
STOP/
(Driven by Target)
t2
DEVSEL/
(Driven by Target)
t1
PCI and External Memory Interface Timing Diagrams
6-27
Table 6.25
Back to Back Read, 32-Bit Address and Data
66 MHz PCI
Symbol
6-28
Parameter
33 MHz PCI
Min
Max
Min
Max
Unit
t1
Shared signal input setup time
3
–
7
–
ns
t2
Shared signal input hold time
0
–
0
–
ns
t3
CLK to shared signal output valid
2
6
2
11
ns
t4
Side signal input setup time
5
–
10
–
ns
t5
Side signal input hold time
0
–
0
–
ns
t6
CLK to side signal output valid
2
6
2
12
ns
Specifications
Figure 6.19 Back to Back Read, 32-Bit Address and Data
CLK
(Driven by System)
REQ64/
(Driven by LSI53C1000)
ACK64/
(Driven by LSI53C1000)
GPIO0_FETCH/
(Driven by LSI53C1000)
GPIO1_MASTER/
(Driven by LSI53C1000)
t6
REQ/
(Driven by LSI53C1000)
GNT/
(Driven by Arbiter)
FRAME/
(Driven by LSI53C1000)
AD[31:0]
t5
t4
t3
Data
In
t1
t3
Data
In
Addr
Out
Addr
Out
(Driven by LSI53C1000-
Addr; Target-Data)
t2
t3
C_BE[3:0]/
(Driven by LSI53C1000)
PAR
(Driven by LSI53C1000-
CMD
CMD
BE
BE
t1
t3
Out
In
Out
Addr; Target-Data)
In
t2
IRDY/
t3
(Driven by LSI53C1000)
t1
TRDY/
(Driven by Target)
t2
STOP/
(Driven by Target)
t2
DEVSEL/
(Driven by Target)
t1
PCI and External Memory Interface Timing Diagrams
6-29
Table 6.26
Back to Back Write, 32-Bit Address and Data
66 MHz PCI
Symbol
6-30
Parameter
33 MHz PCI
Min
Max
Min
Max
Unit
t1
Shared signal input setup time
3
–
7
–
ns
t2
Shared signal input hold time
0
–
0
–
ns
t3
CLK to shared signal output valid
2
6
2
11
ns
t4
Side signal input setup time
5
–
10
–
ns
t5
Side signal input hold time
0
–
0
–
ns
t6
CLK to side signal output valid
2
6
2
12
ns
Specifications
Figure 6.20 Back to Back Write, 32-Bit Address and Data
CLK
(Driven by System)
REQ64/
(Driven by LSI53C1000)
ACK64/
(Driven by LSI53C1000)
GPIO0_FETCH/
(Driven by LSI53C1000)
t9
GPIO1_MASTER/
(Driven by LSI53C1000)
t10
t6
REQ/
(Driven by LSI53C1000)
GNT/
(Driven by Arbiter)
FRAME/
(Driven by LSI53C1000)
AD[31:0]
(Driven by LSI53C1000Addr; Target-Data)
t5
t4
t3
t3
Addr
Out
t2
t3
C_BE[3:0]/
(Driven by LSI53C1000)
PAR
(Driven by LSI53C1000Addr; Target-Data)
t3
Addr
Out
Data
Out
CMD
BE
Data
Out
t3
CMD
BE
t3
t3
t3
IRDY/
(Driven by LSI53C1000)
TRDY/
(Driven by Target)
STOP/
(Driven by Target)
DEVSEL/
(Driven by Target)
PCI and External Memory Interface Timing Diagrams
6-31
Table 6.27
Burst Read, 32-Bit Address and Data
66 MHz PCI
Symbol
6-32
Parameter
33 MHz PCI
Min
Max
Min
Max
Unit
t1
Shared signal input setup time
3
–
7
–
ns
t2
Shared signal input hold time
0
–
0
–
ns
t3
CLK to shared signal output valid
2
6
2
11
ns
Specifications
Figure 6.21 Burst Read, 32-Bit Address and Data
CLK
(Driven by System)
GPIO0_FETCH/
(Driven by LSI53C1000)
GPIO1_MASTER/
(Driven by LSI53C1000)
REQ/
(Driven by LSI53C1000)
GNT/
(Driven by Arbiter)
FRAME/
(Driven by LSI53C1000)
Data In
AD[31:0]
(Driven by LSI53C1000Addr; Target-Data)
Addr
Out
t3
C_BE[3:0]/
(Driven by LSI53C1000)
CMD
PAR
(Driven by LSI53C1000Addr; Target-Data)
BE
Out
In
In
IRDY/
(Driven by LSI53C1000)
t1
TRDY/
(Driven by Target)
t2
STOP/
(Driven by Target)
t2
DEVSEL/
(Driven by Target)
PCI and External Memory Interface Timing Diagrams
6-33
Table 6.28
Burst Read, 64-Bit Address and Data
66 MHz PCI
Symbol
6-34
Parameter
33 MHz PCI
Min
Max
Min
Max
Unit
t1
Shared signal input setup time
3
–
7
–
ns
t2
Shared signal input hold time
0
–
0
–
ns
t3
CLK to shared signal output valid
2
6
2
11
ns
Specifications
Figure 6.22 Burst Read, 64-Bit Address and Data
CLK
(Driven by System)
GPIO0_FETCH/
(Driven by LSI53C1000)
GPIO1_MASTER/
(Driven by LSI53C1000)
REQ/
(Driven by LSI53C1000)
GNT/
(Driven by Arbiter)
REQ64/
(Driven by LSI53C1000)
t2
ACK64/
(Driven by Target)
FRAME/
(Driven by LSI53C1000)
Data In
AD[31:0]
(Driven by LSI53C1000Addr; Target-Data)
Addr
Out Lo
t3
Dual
Addr
C_BE[3:0]/
(Driven by LSI53C1000)
Addr
Out Hi
Bus
CMD
BE
Data In
AD[63:32]
(Driven by LSI53C1000Addr; Target-Data)
Hi Address
C_BE[7:4]/
(Driven by LSI53C1000)
Bus CMD
PAR; PAR64
(Addr drvn by LSI53C1000;Data drvn by Target)
In
BE
Out
In
In
IRDY/
(Driven by LSI53C1000)
t1
TRDY/
(Driven by Target)
t2
STOP/
(Driven by Target)
t2
DEVSEL/
(Driven by Target)
PCI and External Memory Interface Timing Diagrams
6-35
Table 6.29
Burst Write, 32-Bit Address and Data
66 MHz PCI
Symbol
6-36
Parameter
33 MHz PCI
Min
Max
Min
Max
Unit
t1
Shared signal input setup time
3
–
7
–
ns
t2
Shared signal input hold time
0
–
0
–
ns
t3
CLK to shared signal output valid
2
6
2
11
ns
Specifications
Figure 6.23 Burst Write, 32-Bit Address and Data
CLK
(Driven by System)
GPIO0_FETCH/
(Driven by LSI53C1000)
GPIO1_MASTER/
(Driven by LSI53C1000)
REQ/
(Driven by LSI53C1000)
GNT/
(Driven by Arbiter)
FRAME/
(Driven by LSI53C1000)
AD[31:0]
(Driven by LSI53C1000)
Addr
Out
C_BE[3:0]/
(Driven by LSI53C1000)
CMD
Data
Out
Data
Out
BE
t3
PAR
(Driven by LSI53C1000)
IRDY/
(Driven by LSI53C1000)
t1
TRDY/
(Driven by Target)
t2
STOP/
(Driven by Target)
t1
DEVSEL/
(Driven by Target)
t2
PCI and External Memory Interface Timing Diagrams
6-37
Table 6.30
Burst Write, 64-Bit Address and Data
66 MHz PCI
Symbol
6-38
Parameter
33 MHz PCI
Min
Max
Min
Max
Unit
t1
Shared signal input setup time
3
–
7
–
ns
t2
Shared signal input hold time
0
–
0
–
ns
t3
CLK to shared signal output valid
2
6
2
11
ns
Specifications
Figure 6.24 Burst Write, 64-Bit Address and Data
CLK
(Driven by System)
GPIO0_FETCH/
(Driven by LSI53C1000)
GPIO1_MASTER/
(Driven by LSI53C1000)
REQ/
(Driven by LSI53C1000)
GNT/
(Driven by Arbiter)
REQ64/
(Driven by LSI53C1000)
t2
ACK64/
(Driven by Target)
t1
FRAME/
(Driven by LSI53C1000)
AD[31:0]
(Driven by LSI53C1000)
C_BE[3:0]/
(Driven by LSI53C1000)
Addr
Out Lo
t3
Dual
Addr
Addr
Out Hi
Data
Out
Data
Out
Bus
CMD
BE
BE
AD[63:32]
(Driven by LSI53C1000)
Hi Address
Data
Out
Data
Out
C_BE[7:4]/
(Driven by LSI53C1000)
Bus CMD
BE
BE
PAR; PAR64
(Driven by LSI53C1000)
t3
IRDY/
(Driven by LSI53C1000)
t1
TRDY/
(Driven by Target)
t2
STOP/
(Driven by Target)
t2
DEVSEL/
(Driven by Target)
t1
PCI and External Memory Interface Timing Diagrams
6-39
This page intentionally left blank.
6-40
Specifications
6.4.3 External Memory Timing
Tables 6.31 through 6.38 and figures 6.25 through 6.34 describe External
Memory timing.
Table 6.31
External Memory Read
66 MHz PCI
Symbol
Parameter
33 MHz PCI
Min
Max
Min
Max
Unit
t1
Shared signal input setup time
3
–
7
–
ns
t2
Shared signal input hold time
0
–
0
–
ns
t3
CLK to shared signal output valid
2
6
2
11
ns
t11
Address setup to MAS/ HIGH
25
–
25
–
ns
t12
Address hold from MAS/ HIGH
15
–
15
–
ns
t13
MAS/ pulse width
25
–
25
–
ns
t14
MCE/ LOW to data clocked in
150
–
150
–
ns
t15
Address valid to data clocked in
205
–
205
–
ns
t16
MOE/ LOW to data clocked in
100
–
100
–
ns
t17
Data hold from address, MOE/, MCE/ change
0
–
0
–
ns
t19
Data setup to CLK HIGH
5
–
5
–
ns
PCI and External Memory Interface Timing Diagrams
6-41
Figure 6.25 External Memory Read
1
2
3
4
5
6
7
8
9
10
CLK
(Driven by System)
t1
FRAME/
(Driven by Master)
AD[31:0]
(Driven by Master-Addr;
LSI53C1000-Data)
t2
t1
Addr
In
t2
t1
C_BE[3:0]/
(Driven by Master)
PAR
(Driven by Master-Addr;
LSI53C1000-Data)
Byte Enable
CMD
t1
t2
In
t2
t1
IRDY/
(Driven by Master)
TRDY/
(Driven by LSI53C1000)
STOP/
(Driven by LSI53C1000)
t3
DEVSEL/
(Driven by LSI53C1000)
MAD
High Order
Address
t11
t12
t13
(Addr driven by LSI53C1000;
Data Driven by Memory)
MAS1/
(Driven by LSI53C1000)
Low Order
Address
t15
MAS0/
(Driven by LSI53C1000)
MCE/
(Driven by LSI53C1000)
MOE/
(Driven by LSI53C1000)
MWE/
(Driven by LSI53C1000)
6-42
Middle Order
Address
Specifications
Figure 6.25 External Memory Read (Cont.)
11
12
13
14
15
16
17
18
19
20
21
CLK
(Driven by System)
FRAME/
(Driven by Master)
t3
AD[31:0]
(Driven by Master-Addr;
LSI53C1000-Data)
Data
Out
C_BE[3:0]/
(Driven by Master)
t3
PAR
(Driven by Master-Addr;
LSI53C1000-Data)
t2
Out
t2
IRDY/
(Driven by Master)
t3
TRDY/
(Driven by LSI53C1000)
STOP/
(Driven by LSI53C1000)
t3
DEVSEL/
(Driven by LSI53C1000)
t19
MAD
Data
In
(Addr driven by LSI53C1000;
Data Driven by Memory)
t17
MAS1/
(Driven by LSI53C1000)
t15
MAS0/
(Driven by LSI53C1000)
MCE/
(Driven by LSI53C1000)
MOE/
(Driven by LSI53C1000)
t14
t16
MWE/
(Driven by LSI53C1000)
PCI and External Memory Interface Timing Diagrams
6-43
This page intentionally left blank.
6-44
Specifications
Table 6.32
Symbol
External Memory Write
Parameter
Min
Max
Min
Max
Unit
t1
Shared signal input setup time
3
–
7
–
ns
t2
Shared signal input hold time
0
–
0
–
ns
t3
CLK to shared signal output valid
2
6
2
11
ns
t11
Address setup to MAS/ HIGH
25
–
25
–
ns
t12
Address hold from MAS/ HIGH
15
–
15
–
ns
t13
MAS/ pulse width
25
–
25
–
ns
t20
Data setup to MWE/ LOW
30
–
30
–
ns
t21
Data hold from MWE/ HIGH
20
–
20
–
ns
t22
MWE/ pulse width
100
–
100
–
ns
t23
Address setup to MWE/ LOW
60
–
60
–
ns
t24
MCE/ LOW to MWE/ HIGH
120
–
120
–
ns
t25
MCE/ LOW to MWE/ LOW
25
–
25
–
ns
t26
MWE/ HIGH to MCE/ HIGH
25
–
25
–
ns
PCI and External Memory Interface Timing Diagrams
6-45
Figure 6.26 External Memory Write
1
2
3
4
5
6
7
8
9
10
CLK
(Driven by System)
t1
FRAME/
(Driven by Master)
AD[31:0]
(Driven by Master)
t2
t1
Addr
In
t1
C_BE[3:0]/
(Driven by Master)
CMD
t1
t2
Data In
t2
Byte Enable
t1
PAR
(Driven by Master)
t2
t2
t1
In
In
t2
t2
t1
IRDY/
(Driven by Master)
t2
t3
TRDY/
(Driven by LSI53C1000)
t3
STOP/
(Driven by LSI53C1000)
t3
DEVSEL/
(Driven by LSI53C1000)
MAD
High Order
Address
t11
t12
t13
(Driven by LSI53C1000)
Middle Order
Address
MAS1/
(Driven by LSI53C1000)
MAS0/
(Driven by LSI53C1000)
MCE/
(Driven by LSI53C1000)
MOE/
(Driven by LSI53C1000)
MWE/
t23
(Driven by LSI53C1000)
6-46
Specifications
Low Order
Address
Figure 6.26 External Memory Write (Cont.)
11
12
13
14
15
16
17
18
19
20
21
CLK
(Driven by System)
FRAME/
(Driven by Master)
AD[31:0]
(Driven by Master)
C_BE[3:0]/
(Driven by Master)
PAR
(Driven by Master)
IRDY/
(Driven by Master)
TRDY/
(Driven by LSI53C1000)
STOP/
(Driven by LSI53C1000)
DEVSEL/
(Driven by LSI53C1000)
MAD
Data Out
(Driven by LSI53C1000)
MAS1/
(Driven by LSI53C1000)
MAS0/
(Driven by LSI53C1000)
t24
MCE/
(Driven by LSI53C1000)
t26
t25
MOE/
(Driven by LSI53C1000)
MWE/
(Driven by LSI53C1000)
t20
t21
t23
t22
PCI and External Memory Interface Timing Diagrams
6-47
Table 6.33
Symbol
Normal/Fast Memory (≥ 128 Kbytes) Single Byte Access Read Cycle
Parameter
Min
Max
Unit
t11
Address setup to MAS/ high
25
–
ns
t12
Address hold from MAS/ high
15
–
ns
t13
MAS/ pulse width
25
–
ns
t14
MCE/ LOW to data clocked in
150
–
ns
t15
Address valid to data clocked in
205
–
ns
t16
MOE/ LOW to data clocked in
100
–
ns
t17
Data hold from address, MOE/, MCE/ change
0
–
ns
t18
Address out from MOE/, MCE/ HIGH
50
–
ns
t19
Data setup to CLK HIGH
5
–
ns
Figure 6.27 Normal/Fast Memory (≥ 128 Kbytes) Single Byte Access Read Cycle
1
2
3
4
5
6
7
8
9
10
CLK
(Driven by System)
MAD
(Addr driven by LSI53C1000;
Data Driven by Memory)
Middle Order
Address
Low Order
Address
t12
t13
MAS1/
(Driven by LSI53C1000)
t15
MAS0/
(Driven by LSI53C1000)
t14
MCE/
(Driven by LSI53C1000)
t16
MOE/
(Driven by LSI53C1000)
MWE/
(Driven by LSI53C1000)
6-48
High Order
Address
t11
Specifications
Figure 6.27 Normal/Fast Memory (≥ 128 Kbytes) Single Byte Access Read
Cycle (Cont.)
11
12
13
14
15
16
17
18
19
20
21
CLK
(Driven by System)
Valid
Read
Data
MAD
(Addr driven by LSI53C1000;
Data Driven by Memory)
MAS1/
(Driven by LSI53C1000)
MAS0/
(Driven by LSI53C1000)
t19
t15
t14
MCE/
(Driven by LSI53C1000)
MOE/
(Driven by LSI53C1000)
t17
t18
t16
MWE/
(Driven by LSI53C1000)
PCI and External Memory Interface Timing Diagrams
6-49
Table 6.34
Symbol
Normal/Fast Memory (≥ 128 Kbytes) Single Byte Access Write Cycle
Parameter
Min
Max
Unit
t11
Address setup to MAS/ HIGH
25
–
ns
t12
Address hold from MAS/ HIGH
15
–
ns
t13
MAS/ pulse width
25
–
ns
t20
Data setup to MWE/ LOW
30
–
ns
t21
Data hold from MWE/ HIGH
20
–
ns
t22
MWE/ pulse width
100
–
ns
t23
Address setup to MWE/ LOW
60
–
ns
t24
MCE/ LOW to MWE/ HIGH
120
–
ns
t25
MCE/ LOW to MWE/ LOW
25
–
ns
t26
MWE/ HIGH to MCE/ HIGH
25
–
ns
Figure 6.28 Normal/Fast Memory (≥ 128 Kbytes) Single Byte Access Write Cycle
1
2
3
4
5
6
7
8
9
10
CLK
(Driven by System)
MAD
(Driven by LSI53C1000)
Middle Order
Address
High Order
Address
t11
Low Order
Address
Valid
Write
Data
t12
t13
MAS1/
(Driven by LSI53C1000)
MAS0/
(Driven by LSI53C1000)
t24
MCE/
(Driven by LSI53C1000)
t25
MOE/
(Driven by LSI53C1000)
t20
MWE/
(Driven by LSI53C1000)
6-50
t23
Specifications
Figure 6.28 Normal/Fast Memory (≥ 128 Kbytes) Single Byte Access Write Cycle
(Cont.)
11
12
13
14
15
16
17
18
19
20
21
CLK
(Driven by System)
MAD
(Driven by LSI53C1000)
Valid Write Data
MAS1/
(Driven by LSI53C1000)
MAS0/
(Driven by LSI53C1000)
MCE/
(Driven by LSI53C1000)
t24
t26
t25
MOE/
(Driven by LSI53C1000)
t20
MWE/
(Driven by LSI53C1000)
t23
t21
t22
PCI and External Memory Interface Timing Diagrams
6-51
Figure 6.29 Normal/Fast Memory (≥ 128 Kbytes) Multiple Byte Access Read Cycle
1
2
3
4
5
6
7
8
9
10
CLK
(Driven by System)
FRAME/
(Driven by Master)
AD[31:0]
(Driven by LSI53C1000Master-Addr; Data)
C_BE[3:0]/
(Driven by Master)
Addr
In
CMD
PAR
(Driven by LSI53C1000Master-Addr;-Data)
Byte Enable
In
IRDY/
(Driven by Master)
TRDY/
(Driven by LSI53C1000)
STOP/
(Driven by LSI53C1000)
DEVSEL/
(Driven by LSI53C1000)
MAD
(Addr Driven by LSI53C1000
Data Driven by Memory)
MAS1/
(Driven by LSI53C1000)
MAS0/
(Driven by LSI53C1000)
MCE/
(Driven by LSI53C1000)
MOE/
(Driven by LSI53C1000)
MWE/
(Driven by LSI53C1000)
6-52
Specifications
Middle
High Order
Address
Low
Order
Order
Address Address
11
12
13
14
15
Figure 6.29 Normal/Fast Memory (≥ 128 Kbytes) Multiple Byte Access Read Cycle
(Cont.)
16 17
18
19
20 21
22 23 24
25
26
27
28
29 30 31
32 33
CLK
(Driven by System)
FRAME/
(Driven by Master)
Data Out
AD[31:0]
(Driven by LSI53C1000Master-Addr; Data)
C_BE[3:0]/
(Driven by Master)
Byte Enable
PAR
(Driven by LSI53C1000Master-Addr;-Data)
Out
IRDY/
(Driven by Master)
TRDY/
(Driven by LSI53C1000)
STOP/
(Driven by LSI53C1000)
DEVSEL/
(Driven by LSI53C1000)
MAD
(Addr Driven by LSI53C1000
Data Driven by Memory)
Data In
Low Order
Data In
Address
MAS1/
(Driven by LSI53C1000)
MAS0/
(Driven by LSI53C1000)
MCE/
(Driven by LSI53C1000)
MOE/
(Driven by LSI53C1000)
MWE/
(Driven by LSI53C1000)
PCI and External Memory Interface Timing Diagrams
6-53
Figure 6.30 Normal/Fast Memory (≥ 128 Kbytes) Multiple Byte Access Write Cycle
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
(Driven by System)
FRAME/
(Driven by Master)
Addr
AD[31:0]
(Driven by Master)
C_BE[3:0]/
(Driven by Master)
PAR
(Driven by Master)
In
Data
In
CMD
Byte
Enable
In
In
IRDY/
(Driven by Master)
TRDY/
(Driven by LSI53C1000)
STOP/
(Driven by LSI53C1000)
DEVSEL/
(Driven by LSI53C1000)
Middle
MAD
High Order
Address
(Driven by LSI53C1000)
MAS1/
(Driven by LSI53C1000)
MAS0/
(Driven by LSI53C1000)
MCE/
(Driven by LSI53C1000)
MOE/
(Driven by LSI53C1000)
MWE/
(Driven by LSI53C1000)
6-54
Specifications
Low
Order
Order
Address Address
Data Out
Figure 6.30 Normal/Fast Memory (≥ 128 Kbytes) Multiple Byte Access Write Cycle
(Cont.)
16 17
18
19
20 21
22 23 24
25
26
27
28
29 30 31
32 33
CLK
(Driven by System)
FRAME/
(Driven by Master)
AD[31:0]
(Driven by Master)
C_BE[3:0]/
(Driven by Master)
Data In
Byte Enable
PAR
(Driven by Master)
IRDY/
(Driven by Master)
TRDY/
(Driven by LSI53C1000)
STOP/
(Driven by LSI53C1000)
DEVSEL/
(Driven by LSI53C1000)
Low Order
MAD
(Driven by LSI53C1000)
Address
Data Out
MAS1/
(Driven by LSI53C1000)
MAS0/
(Driven by LSI53C1000)
MCE/
(Driven by LSI53C1000)
MOE/
(Driven by LSI53C1000)
MWE/
(Driven by LSI53C1000)
PCI and External Memory Interface Timing Diagrams
6-55
Table 6.35
Symbol
Slow Memory (≥ 128 Kbytes) Read Cycle
Parameter
Min
Max
Unit
t11
Address setup to MAS/ HIGH
25
–
ns
t12
Address hold from MAS/ HIGH
15
–
ns
t13
MAS/ pulse width
25
–
ns
t14
MCE/ LOW to data clocked in
150
–
ns
t15
Address valid to data clocked in
205
–
ns
t16
MOE/ LOW to data clocked in
100
–
ns
t17
Data hold from address, MOE/, MCE/ change
0
–
ns
t18
Address out from MOE/, MCE/ HIGH
50
–
ns
t19
Data setup to CLK HIGH
5
–
ns
Figure 6.31 Slow Memory (≥ 128 Kbytes) Read Cycle
1
2
3
4
5
6
7
8
9
10
CLK
(Driven by System)
MAD
Middle Order
Address
High Order
Address
(Addr drvn by LSI53C1000
Data drvn by Mem)
t11
Low Order
Address
t12
t13
MAS1/
(Driven by LSI53C1000)
t15
MAS0/
(Driven by LSI53C1000)
t14
MCE/
(Driven by LSI53C1000)
MOE/
t16
(Driven by LSI53C1000)
MWE/
(Driven by LSI53C1000)
6-56
Specifications
Figure 6.31
Slow Memory (≥ 128 Kbytes) Read Cycle (Cont.)
11
12
13
14
15
16
17
18
19
20
21
22
CLK
(Driven by System)
Valid
Read
Data
MAD
(Addr driven by LSI53C1000;
Data Driven by Memory)
t19
t17
MAS1/
(Driven by LSI53C1000)
t15
MAS0/
(Driven by LSI53C1000)
t14
MCE/
(Driven by LSI53C1000)
MOE/
t18
t16
(Driven by LSI53C1000)
MWE/
(Driven by LSI53C1000)
PCI and External Memory Interface Timing Diagrams
6-57
Table 6.36
Symbol
Slow Memory (≥ 128 Kbytes) Write Cycle
Parameter
Min
Max
Unit
t11
Address setup to MAS/ HIGH
25
–
ns
t12
Address hold from MAS/ HIGH
15
–
ns
t13
MAS/ pulse width
25
–
ns
t20
Data setup to MWE/ LOW
30
–
ns
t21
Data hold from MWE/ HIGH
20
–
ns
t22
MWE/ pulse width
100
–
ns
t23
Address setup to MWE/ LOW
60
–
ns
t24
MCE/ LOW to MWE/ HIGH
120
–
ns
t25
MCE/ LOW to MWE/ LOW
25
–
ns
t26
MWE/ HIGH to MCE/ HIGH
25
–
ns
Figure 6.32 Slow Memory (≥ 128 Kbytes) Write Cycle
1
2
3
4
5
6
7
8
9
10
CLK
(Driven by System)
MAD
Middle Order
Address
High Order
Address
(Driven by LSI53C1000)
t11
Low Order
Address
Valid
Write
Data
t12
t13
MAS1/
(Driven by LSI53C1000)
MAS0/
(Driven by LSI53C1000)
t24
MCE/
(Driven by LSI53C1000)
t25
MOE/
t20
(Driven by LSI53C1000)
MWE/
t23
(Driven by LSI53C1000)
6-58
Specifications
Figure 6.32 Slow Memory (≥ 128 Kbytes) Write Cycle (Cont.)
11
12
13
14
15
16
17
18
19
20
21
CLK
(Driven by System)
MAD
Valid Write Data
(Driven by LSI53C1000)
MAS1/
(Driven by LSI53C1000)
MAS0/
(Driven by LSI53C1000)
MCE/
t24
t26
t25
(Driven by LSI53C1000)
MOE/
(Driven by LSI53C1000)
t20
t22
MWE/
(Driven by LSI53C1000)
t21
t23
PCI and External Memory Interface Timing Diagrams
6-59
Table 6.37
≤ 64 Kbytes ROM Read Cycle
Symbol
Parameter
Min
Max
Unit
t11
Address setup to MAS/ HIGH
25
–
ns
t12
Address hold from MAS/ HIGH
15
–
ns
t13
MAS/ pulse width
25
–
ns
t14
MCE/ LOW to data clocked in
150
–
ns
t15
Address valid to data clocked in
205
–
ns
t16
MOE/ LOW to data clocked in
100
–
ns
t17
Data hold from address, MOE/, MCE/ change
0
–
ns
t18
Address out from MOE/, MCE/ HIGH
50
–
ns
t19
Data setup to CLK HIGH
5
–
ns
Figure 6.33 ≤ 64 Kbytes ROM Read Cycle
1
2
3
4
5
6
7
8
9
10
11
12
13
CLK
(Driven by System)
Valid
MAD
(Addr drvn by LSI53C1000;
Data drvn by Mem)
High Order
Address
Read
Data
Low Order
Address
t19
t12
MAS1/
t17
t11
(Driven by LSI53C1000)
t13
t15
MAS0/
(Driven by LSI53C1000)
t14
MCE/
(Driven by LSI53C1000)
t18
t16
MOE/
(Driven by LSI53C1000)
MWE/
(Driven by LSI53C1000)
6-60
Specifications
14
15
Table 6.38
Symbol
≤ 64 Kbytes ROM Write Cycle
Parameter
Min
Max
Unit
t11
Address setup to MAS/ HIGH
25
–
ns
t12
Address hold from MAS/ HIGH
15
–
ns
t13
MAS/ pulse width
25
–
ns
t20
Data setup to MWE/ LOW
30
–
ns
t21
Data hold from MWE/ HIGH
20
–
ns
t22
MWE/ pulse width
100
–
ns
t23
Address setup to MWE/ LOW
60
–
ns
t24
MCE/ LOW to MWE/ HIGH
120
–
ns
t25
MCE/ LOW to MWE/ LOW
25
–
ns
t26
MWE/ HIGH to MCE/ HIGH
25
–
ns
Figure 6.34 ≤ 64 Kbytes ROM Write Cycle
1
2
3
4
5
6
7
8
9
10
11
12
13
CLK
(Driven by System)
MAD
(Driven by LSI53C1000)
High Order
Address
Low Order
Address
Valid Write Data
t12
MAS1/
t11
(Driven by LSI53C1000)
t13
MAS0/
(Driven by LSI53C1000)
t24
t26
MCE/
(Driven by LSI53C1000)
t25
MOE/
t21
t20
(Driven by LSI53C1000)
t22
MWE/
(Driven by LSI53C1000)
t23
PCI and External Memory Interface Timing Diagrams
6-61
6.5 SCSI Timing Diagrams
Figures 6.35 through 6.40 and tables 6.39 through 6.50 describe the
LSI53C1000 SCSI timing.
Table 6.39
Symbol
Initiator Asynchronous Send
Parameter
Min
Max
Units
t1
SACK/ asserted from SREQ/ asserted
5
–
ns
t2
SACK/ deasserted from SREQ/ deasserted
5
–
ns
t3
Data setup to SACK/ asserted
55
–
ns
t4
Data hold from SREQ/ deasserted
0
–
ns
Figure 6.35 Initiator Asynchronous Send
SREQ/
n
t1
SACK/
n+1
t2
n+1
n
t3
t4
SD[15:0]/,
SDP[1:0]/
6-62
Specifications
Valid n
Valid n + 1
Table 6.40
Symbol
Initiator Asynchronous Receive
Parameter
Min
Max
Units
t1
SACK/ asserted from SREQ/ asserted
5
–
ns
t2
SACK/ deasserted from SREQ/ deasserted
5
–
ns
t3
Data setup to SREQ/ asserted
0
–
ns
t4
Data hold from SACK/ asserted
0
–
ns
Figure 6.36 Initiator Asynchronous Receive
SREQ/
t2
n
n+1
t1
SACK/
SD[15:0]/,
SDP[1:0]/
Table 6.41
Symbol
n+1
n
t3
t4
Valid n + 1
Valid n
Target Asynchronous Send
Parameter
Min
Max
Units
t1
SREQ/ deasserted from SACK/ asserted
5
–
ns
t2
SREQ/ asserted from SACK/ deasserted
5
–
ns
t3
Data setup to SREQ/ asserted
55
–
ns
t4
Data hold from SACK/ asserted
0
–
ns
Figure 6.37 Target Asynchronous Send
SREQ/
n
t2
t1
SACK/
t3
n+1
n+1
n
t4
SD[15:0]/,
SDP[1:0]/
SCSI Timing Diagrams
Valid n
Valid n + 1
6-63
Table 6.42
Symbol
Target Asynchronous Receive
Parameter
Min
Max
Units
t1
SREQ/ deasserted from SACK/ asserted
5
–
ns
t2
SREQ/ asserted from SACK/ deasserted
5
–
ns
t3
Data setup to SACK/ asserted
0
–
ns
t4
Data hold from SREQ/ deasserted
0
–
ns
Figure 6.38 Target Asynchronous Receive
SREQ/
n
SACK/
Table 6.43
Symbol
6-64
n+1
n
t3
SD[15:0]/,
SDP[1:0]/
n+1
t2
t1
t4
Valid n
Valid n + 1
SCSI-1 Transfers (SE 5.0 Mbytes)
Parameter
Min
Max
Units
tST1
Send SREQ/ or SACK/ assertion pulse width
80
–
ns
tST2
Send SREQ/ or SACK/ deassertion pulse width
80
–
ns
tST1
Receive SREQ/ or SACK/ assertion pulse width
70
–
ns
tST2
Receive SREQ/ or SACK/ deassertion pulse width
70
–
ns
tST3
Send data setup to SREQ/ or SACK/ asserted
24
–
ns
tST4
Send data hold from SREQ/ or SACK/ asserted
54
–
ns
tST5
Receive data setup to SREQ/ or SACK/ asserted
14
–
ns
tST6
Receive data hold from SREQ/ or SACK/ asserted
24
–
ns
Specifications
Table 6.44
Symbol
SCSI-2 Fast Transfers 10.0 Mbytes (8-Bit Transfers) or
20.0 Mbytes (16-Bit Transfers) 40 MHz Clock
Parameter
Min
Max
Units
tST1
Send SREQ/ or SACK/ assertion pulse width
30
–
ns
tST2
Send SREQ/ or SACK/ deassertion pulse width
30
–
ns
tST1
Receive SREQ/ or SACK/ assertion pulse width
22
–
ns
tST2
Receive SREQ/ or SACK/ deassertion pulse width
22
–
ns
tST3
Send data setup to SREQ/ or SACK/ asserted
24
–
ns
tST4
Send data hold from SREQ/ or SACK/ asserted
34
–
ns
tST5
Receive data setup to SREQ/ or SACK/ asserted
14
–
ns
tST6
Receive data hold from SREQ/ or SACK/ asserted
24
–
ns
Min
Max
Unit
Table 6.45
Symbol
Ultra SCSI SE Transfers 20.0 Mbytes (8-Bit Transfers) or
40.0 Mbytes (16-Bit Transfers) Quadrupled 40 MHz Clock1
Parameter
tST1
Send SREQ/ or SACK/ assertion pulse width
15
–
ns
tST2
Send SREQ/ or SACK/ deassertion pulse width
15
–
ns
tST1
Receive SREQ/ or SACK/ assertion pulse width
11
–
ns
tST2
Receive SREQ/ or SACK/ deassertion pulse width
11
–
ns
tST3
Send data setup to SREQ/ or SACK/ asserted
12
–
ns
tST4
Send data hold from SREQ/ or SACK/ asserted
17
–
ns
tST5
Receive data setup to SREQ/ or SACK/ asserted
6
–
ns
tST6
Receive data hold from SREQ/ or SACK/ asserted
11
–
ns
1. Note: For fast SCSI, set the TolerANT Enable bit (bit 7 in SCSI Test Three (STEST3)).
SCSI Timing Diagrams
6-65
Table 6.46
Symbol
Ultra2 SCSI Transfers 40.0 Mbyte (8-Bit Transfers) or
80.0 Mbyte (16-Bit Transfers) Quadrupled 40 MHz Clock
Parameter
Min
Max
Unit
tST1
Send SREQ/ or SACK/ assertion pulse width
8
–
ns
tST2
Send SREQ/ or SACK/ deassertion pulse width
8
–
ns
tST1
Receive SREQ/ or SACK/ assertion pulse width
6.5
–
ns
tST2
Receive SREQ/ or SACK/ deassertion pulse width
6.5
–
ns
tST3
Send data setup to SREQ/ or SACK/ asserted
9.5
–
ns
tST4
Send data hold from SREQ/ or SACK/ asserted
9.5
–
ns
tST5
Receive data setup to SREQ/ or SACK/ asserted
4.5
–
ns
tST6
Receive data hold from SREQ/ or SACK/ asserted
4.5
–
ns
Figure 6.39 Initiator and Target ST Synchronous Transfer
tST1
SREQ/SACK
tST4
tST3
Send Data
(SD[15:0]/)
tST5
Receive Data
(SD[15:0]/)
6-66
Specifications
tST6
tST2
Table 6.47
Symbol
SCSI-2 Fast Transfers 10.0 Mbytes (8-Bit Transfers) or
20.0 Mbytes (16-Bit Transfers) 40 MHz Clock
Parameter
Min
Max
Unit
tDT1
Send SREQ/ assertion pulse width
92
–
ns
tDT2
Send SREQ/ deassertion pulse width
92
–
ns
tDT1
Receive SREQ/ assertion pulse width
80
–
ns
tDT2
Receive SREQ/ deassertion pulse width
80
–
ns
tDT3
Send data setup to SREQ/ transition
40
–
ns
tDT4
Send data hold from SREQ/ transition
40
–
ns
tDT5
Receive data setup to SREQ/ transition
10
–
ns
tDT6
Receive data hold from SREQ/ transition
10
–
ns
tDT7
Send CRC Request Setup to SREQ/ transition
50
–
ns
tDT8
Send CRC Request Hold to SREQ/ transition
40
–
ns
tDT9
Receive CRC Request Setup to SREQ/ transition
17
–
ns
tDT10
Receive CRC Request Hold to SREQ/ transition
10
–
ns
Min
Max
Unit
Table 6.48
Symbol
Ultra SCSI SE Transfers 20.0 Mbytes (8-Bit Transfers) or
40.0 Mbytes (16-Bit Transfers) Quadrupled 40 MHz Clock
Parameter
tDT1
Send SREQ/ assertion pulse width
46
–
ns
tDT2
Send SREQ/ deassertion pulse width
46
–
ns
tDT1
Receive SREQ/ assertion pulse width
40
–
ns
tDT2
Receive SREQ/ deassertion pulse width
40
–
ns
tDT3
Send data setup to SREQ/ transition
20
–
ns
tDT4
Send data hold from SREQ/ transition
20
–
ns
SCSI Timing Diagrams
6-67
Table 6.48
Symbol
Parameter
Min
Max
Unit
tDT5
Receive data setup to SREQ/ transition
5
–
ns
tDT6
Receive data hold from SREQ/ transition
5
–
ns
tDT7
Send CRC Request Setup to SREQ/ transition
30
–
ns
tDT8
Send CRC Request Hold to SREQ/ transition
20
–
ns
tDT9
Receive CRC Request Setup to SREQ/ transition
12
–
ns
tDT10
Receive CRC Request Hold to SREQ/ transition
5
–
ns
Min
Max
Unit
Table 6.49
Symbol
6-68
Ultra SCSI SE Transfers 20.0 Mbytes (8-Bit Transfers) or
40.0 Mbytes (16-Bit Transfers) Quadrupled 40 MHz Clock (Cont.)
Ultra2 SCSI Transfers 40.0 Mbyte (8-Bit Transfers) or
80.0 Mbyte (16-Bit Transfers) Quadrupled 40 MHz Clock
Parameter
tDT1
Send SREQ/ assertion pulse width
23
–
ns
tDT2
Send SREQ/ deassertion pulse width
23
–
ns
tDT1
Receive SREQ/ assertion pulse width
20
–
ns
tDT2
Receive SREQ/ deassertion pulse width
20
–
ns
tDT3
Send data setup to SREQ/ transition
10
–
ns
tDT4
Send data hold from SREQ/ transition
10
–
ns
tDT5
Receive data setup to SREQ/ transition
2.5
–
ns
tDT6
Receive data hold from SREQ/ transition
2.5
–
ns
tDT7
Send CRC Request Setup to SREQ/ transition
20
–
ns
tDT8
Send CRC Request Hold to SREQ/ transition
10
–
ns
tDT9
Receive CRC Request Setup to SREQ/ transition
9.5
–
ns
tDT10
Receive CRC Request Hold to SREQ/ transition
2.5
–
ns
Specifications
Table 6.50
Symbol
Ultra160 SCSI Transfers 160.0 Mbyte (16-Bit Transfers)
Quadrupled 40 MHz Clock
Parameter
Min
Max
Unit
tDT1
Send SREQ/ assertion pulse width
11.5
–
ns
tDT2
Send SREQ/ deassertion pulse width
11.5
–
ns
tDT1
Receive SREQ/ assertion pulse width
10
–
ns
tDT2
Receive SREQ/ deassertion pulse width
10
–
ns
tDT3
Send data setup to SREQ/ transition
5
–
ns
tDT4
Send data hold from SREQ/ transition
5
–
ns
tDT5
Receive data setup to SREQ/ transition
1.25
–
ns
tDT6
Receive data hold from SREQ/ transition
1.25
–
ns
tDT7
Send CRC Request Setup to SREQ/ transition
15
–
ns
tDT8
Send CRC Request Hold to SREQ/ transition
5
–
ns
tDT9
Receive CRC Request Setup to SREQ/ transition
8.25
–
ns
tDT10
Receive CRC Request Hold to SREQ/ transition
1.25
–
ns
Figure 6.40 Initiator and Target DT Synchronous Transfer
tDT2
tDT1
SREQ/SACK
tDT3
tDT4
tDT3
tDT4
Send Data
(SD[15:0]/)
tDT5
tDT6
tDT5
tDT6
Receive Data
(SD[15:0]/)
Send CRC
Request
(DP0/)
tDT7
tDT8
tDT9
tDT10
Receive CRC
Request
(DP0/)
SCSI Timing Diagrams
6-69
This page intentionally left blank.
6-70
Specifications
6.6 Package Drawings
Figure 6.41 illustrates the signal locations on the 329 Ball Grid Array
(BGA). Table 6.51 and Table 6.52 list all the signal names alphabetically
and by BGA position. Figure 6.42 illustrates the LSI53C1000 329 BGA.
Figure 6.43 illustrates the LSI53C1000 329 BGA mechanical drawing.
Package Drawings
6-71
Figure 6.41 LSI53C1000 329 BGA Chip - Top View
1
2
A
NC
TEST_PD SD12+
4
5
6
7
8
9
10
11
12
SD13+
SD15+
SD0+
SD2−
SD4−
SD6−
SDP0−
VDD_
BIAS
SBSY+
A
B
M66EN VDD_A
ENABLE66 SD13−
SD15−
SD0−
SD1+
SD3+
SD5+
SD7+
SATN-
SATN+
B
C
TEST_
RST/
VSS_A
VSS_IO
SD12−
SD14−
SDP1−
SD1−
SD2+
SD4+
SD6+
SDP0+
SBSY−
C
D
TCK
VSS_
CORE
VDD_
CORE
VSS_IO
SD14+
SDP1+
VDD_IO
SD3−
SD5−
VDD_IO
SD7−
VSS_IO
D
E
TDO
TDI
TMS
VDD_
CORE
E
F
ALT_
INTA/
NC
VSS_
CORE
INTA/
F
G RST/
INT_DIR
NC
VDD_IO
G
H
AD31
REQ/
CLK
GNT/
H
J
AD27
AD28
AD30
AD29
J
K
C_BE3/ AD24
AD26
VDD_IO
VSS_IO
VSS_IO
VSS_IO
K
L
AD23
AD22
IDSEL
AD25
VSS_IO
VSS_IO
VSS_IO
L
M AD21
AD19
AD20
VSS_IO
VSS_IO
VSS_IO
VSS_IO
M
N
AD17
AD18
AD16
IRDY/
VSS_IO
VSS_IO
VSS_IO
N
P
C_BE2/ FRAME/
TRDY/
VDD_IO
VSS_IO
VSS_IO
VSS_IO
P
R
DEV
SEL/
STOP/
SERR/
PERR/
R
T
PAR
C_BE1/
AD14
AD15
T
U
AD13
AD12
AD11
VDD_IO
U
V
AD10
AD9
C_BE0/
AD8
V
W AD7
AD6
AD4
AD5
W
Y
AD2
AD0
VSS_IO
AD63
AD59
VDD_IO
AD52
AD48
VDD_IO
AD44
VSS_IO
Y
REQ64/
VSS_IO
C_BE7/
PAR64
AD60
AD56
AD53
AD49
AD45
AD41
AD37
AA
AB ACK64/ VSS_
CORE
VDD_
CORE
C_BE5/
AD62
AD58
AD55
AD51
AD47
AD43
AD39
AD36
AB
AC VDD_
CORE
VSS_
CORE
C_BE6/
C_BE4/
AD61
AD57
AD54
AD50
AD46
AD42
AD40
AD38
AC
2
3
4
5
6
7
8
9
10
11
12
AD3
AA AD1
1
6-72
3
Specifications
Figure 6.41 LSI53C1000 329 BGA Chip - Top View (Cont.)
13
14
15
16
17
18
19
20
21
22
23
A
NC
SACK+
SMSG+
SC_D+
SREQ+
SD8−
SD10−
DIFFSENS
SCLK
VSS_
CORE
NC
A
B
NC
SRST−
SSEL−
NC
SI_O−
SD8+
SD10+
VSS_A
NC
VDD_
CORE
VDD_
CORE
B
C
SACK−
SMSG−
SC_D−
SREQ−
SI_O+
SD9+
SD11+
VDD_A
VSS_IO
SCAN_
MODE
TEST_
HSC
C
D
SRST+
VDD_IO
SSEL+
NC
VDD_IO
SD9−
SD11−
VSS_IO
VSS_
CORE
NC
NC
D
E
NC
NC
NC
NC
E
F
NC
NC
NC
NC
F
G
VDD_IO
NC
NC
NC
G
H
NC
NC
NC
NC
H
J
NC
NC
NC
NC
J
K
VSS_IO
VSS_IO
VDD_IO
NC
NC
NC
K
L
VSS_IO
VSS_IO
NC
NC
NC
NC
L
M
VSS_IO
VSS_IO
VSS_IO
RBIAS
VDD_
BIAS
NC
M
N
VSS_IO
VSS_IO
NC
NC
NC
NC
N
P
VSS_IO
VSS_IO
VDD_IO
NC
NC
NC
P
R
NC
NC
NC
NC
R
T
NC
NC
NC
NC
T
U
VDD_IO
NC
NC
NC
U
V
NC
NC
NC
NC
V
W
NC
NC
NC
NC
W
VDD_IO
VSS_
CORE
GPIO1_
VDD_IO
MASTER/
MOE/_
MAD7
TESTOUT
VSS_IO
NC
NC
NC
Y
AA AD33
NC
NC
GPIO2
MAS1/
MCE/
MAD6
MAD3
VSS_IO
VSS_
CORE
NC
AA
AB AD35
RESERVED
NC
GPIO0_
FETCH/
GPIO4
VDD_
CORE
VSS_
CORE
MAD4
MAD1
NC
VDD_
CORE
AB
AC AD34
AD32
NC
NC
GPIO3
MAS0/
MWE/
MAD5
VSS_
CORE
MAD2
MAD0
AC
14
15
16
17
18
19
20
21
22
23
Y
VDD_
CORE
13
Package Drawings
6-73
Table 6.51
Signal
Name
ACK64/
AD0
AD1
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD2
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD3
AD30
AD31
AD32
AD33
AD34
AD35
AD36
AD37
AD38
AD39
AD4
AD40
AD41
AD42
AD43
AD44
AD45
AD46
AD47
AD48
AD49
AD5
AD50
AD51
AD52
AD53
AD54
AD55
AD56
AD57
AD58
AD59
AD6
AD60
AD61
AD62
AD63
AD7
AD8
AD9
ALT_INTA/
C_BE0/
6-74
Alphanumeric list by Signal Names
BGA
Pos
AB1
Y3
AA1
V1
U3
U2
U1
T3
T4
N3
N1
N2
M2
Y2
M3
M1
L2
L1
K2
L4
K3
J1
J2
J4
Y1
J3
H1
AC14
AA13
AC13
AB13
AB12
AA12
AC12
AB11
W3
AC11
AA11
AC10
AB10
Y11
AA10
AC9
AB9
Y9
AA9
W4
AC8
AB8
Y8
AA8
AC7
AB7
AA7
AC6
AB6
Y6
W2
AA6
AC5
AB5
Y5
W1
V4
V2
F1
V3
Signal
Name
C_BE1/
C_BE2/
C_BE3/
C_BE4/
C_BE5/
C_BE6/
C_BE7/
CLK
DEVSEL/
DIFFSENS
ENABLE66
FRAME/
GNT/
GPIO0
_FETCH/
GPIO1
_MASTER/
GPIO2
GPIO3
GPIO4
IDSEL
INT_DIR
INTA/
IRDY/
M66EN
MAD0
MAD1
MAD2
MAD3
MAD4
MAD5
MAD6
MAD7
MAS0/
MAS1/
MCE/
MOE/
_TESTOUT
MWE/
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
BGA
Pos
T2
P1
K1
AC4
AB4
AC3
AA4
H3
R1
A20
B3
P2
H4
AB16
Y16
AA16
AC17
AB17
L3
G2
F4
N4
B1
AC23
AB21
AC22
AA20
AB20
AC20
AA19
Y19
AC18
AA17
AA18
Y18
AC19
A1
A13
A23
AA14
AA15
AA23
AB15
AB22
AC15
AC16
B13
B16
B21
D16
D22
D23
E20
E21
E22
E23
F2
F20
F21
F22
F23
G3
G21
G22
G23
Specifications
Signal
Name
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
PAR
PAR64
PERR/
RBIAS
REQ/
REQ64/
RESERVED
RST/
SACK−
SACK+
SATN−
SATN+
SBSY−
SBSY+
SC_D−
SC_D+
SCAN_MODE
SCLK
SD0−
SD0+
SD1−
SD1+
BGA
Pos
H20
H21
H22
H23
J20
J21
J22
J23
K21
K22
K23
L20
L21
L22
L23
M23
N20
N21
N22
N23
P21
P22
P23
R20
R21
R22
R23
T20
T21
T22
T23
U21
U22
U23
V20
V21
V22
V23
W20
W21
W22
W23
Y21
Y22
Y23
T1
AA5
R4
M21
H2
AA2
AB14
G1
C13
A14
B11
B12
C12
A12
C15
A16
C22
A21
B6
A6
C7
B7
Signal
Name
SD10−
SD10+
SD11−
SD11+
SD12−
SD12+
SD13−
SD13+
SD14−
SD14+
SD15−
SD15+
SD2−
SD2+
SD3−
SD3+
SD4−
SD4+
SD5−
SD5+
SD6−
SD6+
SD7−
SD7+
SD8−
SD8+
SD9−
SD9+
SDP0−
SDP0+
SDP1−
SDP1+
SERR/
SI_O−
SI_O+
SMSG−
SMSG+
SREQ−
SREQ+
SRST−
SRST+
SSEL−
SSEL+
STOP/
TCK
TDI
TDO
TEST_HSC
TEST_PD
TEST_RST/
TMS
TRDY/
VDD_A
VDD_A
VDD_BIAS
VDD_BIAS
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_IO
VDD_IO
BGA
Pos
A19
B19
D19
C19
C4
A3
B4
A4
C5
D5
B5
A5
A7
C8
D8
B8
A8
C9
D9
B9
A9
C10
D11
B10
A18
B18
D18
C18
A10
C11
C6
D6
R3
B17
C17
C14
A15
C16
A17
B14
D13
B15
D15
R2
D1
E2
E1
C23
A2
C1
E3
P3
B2
C20
A11
M22
AB18
AB23
AB3
AC1
B22
B23
D3
E4
Y13
D10
D14
Signal
Name
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VSS_A
VSS_A
VSS_CORE
VSS_CORE
VSS_CORE
VSS_CORE
VSS_CORE
VSS_CORE
VSS_CORE
VSS_CORE
VSS_CORE
VSS_CORE
VSS_IO
VSS_IO
VSS_IO
VSS_IO
VSS_IO
VSS_IO
VSS_IO
VSS_IO
VSS_IO
VSS_IO
VSS_IO
VSS_IO
VSS_IO
VSS_IO
VSS_IO
VSS_IO
VSS_IO
VSS_IO
VSS_IO
VSS_IO
VSS_IO
VSS_IO
VSS_IO
VSS_IO
VSS_IO
VSS_IO
VSS_IO
VSS_IO
VSS_IO
VSS_IO
VSS_IO
VSS_IO
VSS_IO
VSS_IO
VSS_IO
VSS_IO
VSS_IO
BGA
Pos
D17
D7
G4
G20
K20
K4
P20
P4
U20
U4
Y10
Y14
Y17
Y7
B20
C2
A22
AA22
AB19
AB2
AC2
AC21
D2
D21
F3
Y15
AA21
AA3
C21
C3
D12
D20
D4
K10
K11
K12
K13
K14
L10
L11
L12
L13
L14
M10
M11
M12
M13
M14
M20
M4
N10
N11
N12
N13
N14
P10
P11
P12
P13
P14
Y12
Y20
Y4
Table 6.52
Signal
Name
NC
TEST_PD
SD12+
SD13+
SD15+
SD0+
SD2−
SD4−
SD6−
SDP0−
VDD_BIAS
SBSY+
NC
SACK+
SMSG+
SC_D+
SREQ+
SD8−
SD10−
DIFFSENS
SCLK
VSS_CORE
NC
AD1
REQ64/
VSS_IO
C_BE7/
PAR64
AD60
AD56
AD53
AD49
AD45
AD41
AD37
AD33
NC
NC
GPIO2
MAS1/
MCE/
MAD6
MAD3
VSS_IO
VSS_CORE
NC
ACK64/
VSS_CORE
VDD_CORE
C_BE5/
AD62
AD58
AD55
AD51
AD47
AD43
AD39
AD36
AD35
RESERVED
NC
GPIO0
_FETCH/
GPIO4
VDD_CORE
VSS_CORE
MAD4
Alphanumeric List by BGA Positions
BGA
Pos
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
AA9
AA10
AA11
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AA23
AB1
AB2
AB3
AB4
AB5
AB6
AB7
AB8
AB9
AB10
AB11
AB12
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
Signal
Name
MAD1
NC
VDD_CORE
VDD_CORE
VSS_CORE
C_BE6/
C_BE4/
AD61
AD57
AD54
AD50
AD46
AD42
AD40
AD38
AD34
AD32
NC
NC
GPIO3
MAS0/
MWE/
MAD5
VSS_CORE
MAD2
MAD0
M66EN
VDD_A
ENABLE66
SD13−
SD15−
SD0−
SD1+
SD3+
SD5+
SD7+
SATN−
SATN+
NC
SRST−
SSEL−
NC
SI_O−
SD8+
SD10+
VSS_A
NC
VDD_CORE
VDD_CORE
TEST_RST/
VSS_A
VSS_IO
SD12−
SD14−
SDP1−
SD1−
SD2+
SD4+
SD6+
SDP0+
SBSY−
SACK−
SMSG−
SC_D−
SREQ−
SI_O+
SD9+
BGA
Pos
AB21
AB22
AB23
AC1
AC2
AC3
AC4
AC5
AC6
AC7
AC8
AC9
AC10
AC11
AC12
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AC21
AC22
AC23
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
Signal
Name
SD11+
VDD_A
VSS_IO
SCAN_MODE
TEST_HSC
TCK
VSS_CORE
VDD_CORE
VSS_IO
SD14+
SDP1+
VDD_IO
SD3−
SD5−
VDD_IO
SD7−
VSS_IO
SRST+
VDD_IO
SSEL+
NC
VDD_IO
SD9−
SD11−
VSS_IO
VSS_CORE
NC
NC
TDO
TDI
TMS
VDD_CORE
NC
NC
NC
NC
ALT_INTA/
NC
VSS_CORE
INTA/
NC
NC
NC
NC
RST/
INT_DIR
NC
VDD_IO
VDD_IO
NC
NC
NC
AD31
REQ/
CLK
GNT/
NC
NC
NC
NC
AD27
AD28
AD30
AD29
NC
NC
NC
Package Drawings
BGA
Pos
C19
C20
C21
C22
C23
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
E1
E2
E3
E4
E20
E21
E22
E23
F1
F2
F3
F4
F20
F21
F22
F23
G1
G2
G3
G4
G20
G21
G22
G23
H1
H2
H3
H4
H20
H21
H22
H23
J1
J2
J3
J4
J20
J21
J22
Signal
Name
NC
C_BE3/
AD24
AD26
VDD_IO
VSS_IO
VSS_IO
VSS_IO
VSS_IO
VSS_IO
VDD_IO
NC
NC
NC
AD23
AD22
IDSEL
AD25
VSS_IO
VSS_IO
VSS_IO
VSS_IO
VSS_IO
NC
NC
NC
NC
AD21
AD19
AD20
VSS_IO
VSS_IO
VSS_IO
VSS_IO
VSS_IO
VSS_IO
VSS_IO
RBIAS
VDD_BIAS
NC
AD17
AD18
AD16
IRDY/
VSS_IO
VSS_IO
VSS_IO
VSS_IO
VSS_IO
NC
NC
NC
NC
C_BE2/
FRAME/
TRDY/
VDD_IO
VSS_IO
VSS_IO
VSS_IO
VSS_IO
VSS_IO
VDD_IO
NC
NC
NC
DEVSEL/
BGA
Pos
J23
K1
K2
K3
K4
K10
K11
K12
K13
K14
K20
K21
K22
K23
L1
L2
L3
L4
L10
L11
L12
L13
L14
L20
L21
L22
L23
M1
M2
M3
M4
M10
M11
M12
M13
M14
M20
M21
M22
M23
N1
N2
N3
N4
N10
N11
N12
N13
N14
N20
N21
N22
N23
P1
P2
P3
P4
P10
P11
P12
P13
P14
P20
P21
P22
P23
R1
Signal
Name
STOP/
SERR/
PERR/
NC
NC
NC
NC
PAR
C_BE1/
AD14
AD15
NC
NC
NC
NC
AD13
AD12
AD11
VDD_IO
VDD_IO
NC
NC
NC
AD10
AD9
C_BE0/
AD8
NC
NC
NC
NC
AD7
AD6
AD4
AD5
NC
NC
NC
NC
AD3
AD2
AD0
VSS_IO
AD63
AD59
VDD_IO
AD52
AD48
VDD_IO
AD44
VSS_IO
VDD_CORE
VDD_IO
VSS_CORE
GPIO1
_MASTER/
VDD_IO
MOE/
_TESTOUT
MAD7
VSS_IO
NC
NC
NC
BGA
Pos
R2
R3
R4
R20
R21
R22
R23
T1
T2
T3
T4
T20
T21
T22
T23
U1
U2
U3
U4
U20
U21
U22
U23
V1
V2
V3
V4
V20
V21
V22
V23
W1
W2
W3
W4
W20
W21
W22
W23
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
Y23
6-75
Figure 6.42 LSI53C1000 329 Ball Grid Array (Bottom view)
6-76
Specifications
Figure 6.43 LSI53C1000 329 BGA Mechanical Drawing
Important:
This drawing may not be the latest version. For board layout and manufacturing, obtain the
most recent engineering drawings from your LSI Logic marketing representative by
requesting the outline drawing for package code VW.
Package Drawings
6-77
6-78
Specifications
Appendix A
Register Summary
Table A.1 lists the LSI53C1000 PCI registers by register name.
Table A.1
LSI53C1000 PCI Register Map
Register Name
Address
Read/Write
Page
Base Address Register Four (BAR4) (SCRIPTS RAM)
0x20–0x23
Read/Write
4-11
Base Address Register One (BAR1) (MEMORY)
0x14–0x17
Read/Write
4-10
Base Address Register Three (BAR3) (SCRIPTS RAM)
0x1C–0x1F
Read/Write
4-11
Base Address Register Two (BAR2) (MEMORY)
0x18–0x1B
Read/Write
4-10
Base Address Register Zero (BAR0) (I/O)
0x10–0x13
Read/Write
4-9
Bridge Support Extensions (PMCSR_BSE)
0x46
Read Only
4-20
Cache Line Size (CLS)
0x0C
Read/Write
4-7
Capabilities Pointer (CP)
0x34
Read Only
4-15
Capability ID (CID)
0x40
Read Only
4-18
Class Code (CC)
0x09–0x0B
Read Only
4-7
Command
0x04–0x05
Read/Write
4-3
Data
0x47
Read Only
4-21
Device ID
0x02–0x03
Read Only
4-3
Expansion ROM Base Address (ERBA)
0x30–0x33
Read/Write
4-14
Header Type (HT)
0x0E
Read Only
4-8
Interrupt Line (IL)
0x3C
Read/Write
4-16
Interrupt Pin (IP)
0x3D
Read Only
4-16
PCI Registers
LSI53C1000 PCI to Ultra160 SCSI Controller
A-1
Table A.1
LSI53C1000 PCI Register Map (Cont.)
Register Name
Address
Read/Write
Page
Latency Timer (LT)
0x0D
Read/Write
4-8
Max_Lat (ML)
0x3F
Read Only
4-17
Min_Gnt (MG)
0x3E
Read Only
4-17
Next Item Pointer (NIP)
0x41
Read Only
4-18
Power Management Capabilities (PMC)
0x42–0x43
Read Only
4-18
Power Management Control/Status (PMCSR)
0x44–0x45
Read/Write
4-19
Reserved
0x0F
–
4-9
Reserved
0x24–0x27
–
4-12
Reserved
0x28–0x2B
–
4-12
Reserved
0x35–0x37
–
4-15
Reserved
0x38–0x3B
–
4-15
Revision ID (RID)
0x08
Read Only
4-6
Status
0x06–0x07
Read/Write
4-5
Subsystem ID (SID)
0x2E–0x2F
Read Only
4-13
Subsystem Vendor ID (SVID)
0x2C–0x2D
Read Only
4-12
Vendor ID
0x00–0x01
Read Only
4-2
A-2
Register Summary
Table A.2 lists the LSI53C1000 SCSI registers, Phase Mismatch Jump
registers, and Shadow registers by register name.
Table A.2
LSI53C1000 SCSI Register Map
Register Name
Address
Read/Write
Page
Adder Sum Output (ADDER)
0x3C–0x3F
Read Only
4-68
AIP Control One (AIPCNTL1)
0xBF
Read/Write
4-109
AIP Control Zero (AIPCNTL0)
0xBE
Read Only
4-108
Chip Control One (CCNTL1)
0x57
Read/Write
4-91
Chip Control Three (CCNTL3)
0x5B
Read/Write
4-93
Chip Control Two (CCNTL2)
0x5A
Read/Write
4-93
Chip Control Zero (CCNTL0)
0x56
Read/Write
4-89
Chip Test Five (CTEST5)
0x22
Read/Write
4-56
Chip Test Four (CTEST4)
0x21
Read/Write
4-55
Chip Test One (CTEST1)
0x19
Read Only
4-51
Chip Test Six (CTEST6)
0x23
Read/Write
4-57
Chip Test Three (CTEST3)
0x1B
Read/Write
4-53
Chip Test Two (CTEST2)
0x1A
Read Only
(bit 3 write)
4-52
Chip Test Zero (CTEST0)
0x18
Read/Write
4-51
Current Inbound SCSI Offset (CSO)
0x53
Read Only
4-88
Data Structure Address (DSA)
0x10–0x13
Read/Write
4-45
DMA Byte Counter (DBC)
0x24–0x26
Read/Write
4-58
DMA Command (DCMD)
0x27
Read/Write
4-59
DMA Control (DCNTL)
0x3B
Read/Write
4-65
DMA Interrupt Enable (DIEN)
0x39
Read/Write
4-64
DMA Mode (DMODE)
0x38
Read/Write
4-61
DMA Next Address (DNAD)
0x28–0x2B
Read/Write
4-59
SCSI Registers
Register Summary
A-3
Table A.2
LSI53C1000 SCSI Register Map (Cont.)
Register Name
Address
Read/Write
Page
DMA Next Address 64 (DNAD64)
0xB8–0xBB
Read/Write
4-98
DMA SCRIPTS Pointer (DSP)
0x2C–0x2F
Read/Write
4-60
DMA SCRIPTS Pointer Save (DSPS)
0x30–0x33
Read/Write
4-60
DMA Status (DSTAT)
0x0C
Read Only
4-39
DSA Relative Selector (DRS)
0xAC–0xAF
Read/Write
4-97
Dynamic Block Move Selector (DBMS)
0xB4–0xB7
Read/Write
4-98
General Purpose (GPREG)
0x07
Read/Write
4-35
General Purpose Pin Control (GPCNTL)
0x47
Read/Write
4-77
Interrupt Status One (ISTAT1)
0x15
Read/Write
4-49
Interrupt Status Zero (ISTAT0)
0x14
Read/Write
4-46
Mailbox One (MBOX1)
0x17
Read/Write
4-50
Mailbox Zero (MBOX0)
0x16
Read/Write
4-50
Memory Move Read Selector (MMRS)
0xA0–0xA3
Read/Write
4-95
Memory Move Write Selector (MMWS)
0xA4–0xA7
Read/Write
4-96
Reserved
0x20
–
4-55
Reserved
0x44
–
4-76
Reserved
0x46
–
4-76
Reserved
0xBD
–
4-108
Response ID One (RESPID1)
0x4B
Read/Write
4-81
Response ID Zero (RESPID0)
0x4A
Read/Write
4-80
Scratch Byte Register (SBR)
0x3A
Read/Write
4-65
Scratch Register A (SCRATCHA)
0x34–0x37
Read/Write
4-61
Scratch Register B (SCRATCHB)
0x5C–0x5F
Read/Write
4-94
Scratch Registers C–R (SCRATCHC–SCRATCHR)
0x60–0x9F
Read/Write
4-95
SCRIPT Fetch Selector (SFS)
0xA8–0xAB
Read/Write
4-96
A-4
Register Summary
Table A.2
LSI53C1000 SCSI Register Map (Cont.)
Register Name
Address
Read/Write
Page
SCSI Bus Control Lines (SBCL)
0x0B
Read Only
4-38
SCSI Bus Data Lines (SBDL)
0x58–0x59
Read Only
4-92
SCSI Chip ID (SCID)
0x04
Read/Write
4-32
SCSI Control Four (SCNTL4)
0xBC
Read/Write
4-99
SCSI Control One (SCNTL1)
0x01
Read/Write
4-27
SCSI Control Three (SCNTL3)
0x03
Read/Write
4-31
SCSI Control Two (SCNTL2)
0x02
Read/Write
4-29
SCSI Control Zero (SCNTL0)
0x00
Read/Write
4-23
SCSI Destination ID (SDID)
0x06
Read/Write
4-34
SCSI First Byte Received (SFBR)
0x08
Read/Write
4-36
SCSI Input Data Latch (SIDL)
0x50–0x51
Read Only
4-87
SCSI Interrupt Enable One (SIEN1)
0x41
Read/Write
4-70
SCSI Interrupt Enable Zero (SIEN0)
0x40
Read/Write
4-68
SCSI Interrupt Status One (SIST1)
0x43
Read Only
4-75
SCSI Interrupt Status Zero (SIST0)
0x42
Read Only
4-72
SCSI Output Control Latch (SOCL)
0x09
Read/Write
4-37
SCSI Output Data Latch (SODL)
0x54–0x55
Read/Write
4-88
SCSI Selector ID (SSID)
0x0A
Read Only
4-38
SCSI Status One (SSTAT1)
0x0E
Read Only
4-43
SCSI Status Two (SSTAT2)
0x0F
Read Only
4-44
SCSI Status Zero (SSTAT0)
0x0D
Read Only
4-42
SCSI Test Four (STEST4)
0x52
Read Only
4-87
SCSI Test One (STEST1)
0x4D
Read/Write
4-83
SCSI Test Three (STEST3)
0x4F
Read/Write
4-85
SCSI Test Two (STEST2)
0x4E
Read/Write
4-84
Register Summary
A-5
Table A.2
LSI53C1000 SCSI Register Map (Cont.)
Register Name
Address
Read/Write
Page
SCSI Test Zero (STEST0)
0x4C
Read Only
4-81
SCSI Timer One (STIME1)
0x49
Read/Write
4-79
SCSI Timer Zero (STIME0)
0x48
Read/Write
4-78
SCSI Transfer (SXFER)
0x05
Read/Write
4-33
SCSI Wide Residue (SWIDE)
0x45
Read/Write
4-76
Static Block Move Selector (SBMS)
0xB0–0xB3
Read/Write
4-97
Temporary (TEMP)
0x1C–0x1F
Read/Write
4-54
CRC Control One (CRCCNTL1)
0xE3
Read/Write
4-116
CRC Control Zero (CRCCNTL0)
0xE2
Read/Write
4-115
CRC Data (CRCD)
0xE4–0xE7
Read/Write
4-117
CRC Pad Byte Value (CRCPAD)
0xE0–0xE1
Read/Write
4-115
Cumulative SCSI Byte Count (CSBC)
0xDC–0xDF Read/Write
4-114
DMA FIFO Byte Count (DFBC)
0xF0–0xF1
Read Only
4-118
Entry Storage Address (ESA)
0xD0–0xD3
Read/Write
4-112
Instruction Address (IA)
0xD4–0xD7
Read/Write
4-113
Phase Mismatch Jump Address One (PMJAD1)
0xC0–0xC3
Read/Write
4-110
Phase Mismatch Jump Address Two (PMJAD2)
0xC4–0xC7
Read/Write
4-110
Remaining Byte Count (RBC)
0xC8–0xCB
Read/Write
4-111
Reserved
0xDB
–
4-114
Reserved
0xE8–0xEF
–
4-118
Reserved
0xF2–0xF3
–
4-118
Reserved
0xF4–0xFF
–
4-119
SCSI Byte Count (SBC)
0xD8–0xDA
Read Only
4-113
Updated Address (UA)
0xCC–0xCF Read/Write
4-111
Phase Mismatch Jump Registers
A-6
Register Summary
Table A.2
LSI53C1000 SCSI Register Map (Cont.)
Register Name
Address
Read/Write
Page
Shadowed Memory Move Read Selector (MMRS)
0xA0–0xA3
Read/Write
4-122
Shadowed Memory Move Write Selector (MMWS)
0xA4–0xA7
Read/Write
4-122
Shadowed Scratch Register A (SCRATCHA)
0x34–0x37
Read/Write
4-119
Shadowed Scratch Register B (SCRATCHB)
0x5C–0x5F
Read/Write
4-121
Shadowed SCRIPT Fetch Selector (SFS)
0xA8–0xAB
Read/Write
4-123
Shadowed SCSI Interrupt Status One (SIST1)
0x43
Read Only
4-120
Shadowed SCSI SGE Status 0
0x42
Read/Write
4-120
Shadow Registers
Register Summary
A-7
A-8
Register Summary
Appendix B
External Memory
Interface Diagram
Examples
Appendix B has example external memory interface diagrams.
Figure B.1
16 Kbyte Interface with 200 ns Memory
MOE/
OE
MCE/
CE
D[7:0]
MAD[7:0]
Bus
A[7:0]
VDD
MAD0
A[13:8]
4.7 K
27C128
8 D[7:0]
LSI53C1000
MAS0/
MAS1/
Q[7:0]
HCT374
CK
QE
8
Q[5:0]
6 D[5:0]
HCT374
CK
QE
6
Note: MAD[3:1] pulled LOW internally. MAD bus sense logic enabled for 16 Kbyte of slow memory (200 ns
devices @ 66 MHz).
LSI53C1000 PCI to Ultra160 SCSI Controller
B-1
Figure B.2
64 Kbyte Interface with 150 ns Memory
Optional - for Flash Memory only, not
required for EEPROMS.
VPP
+ 12 V
VPP
Control
GPIO4
MWE/
WE
MOE/
OE
MCE/
CE
MAD[7:0]
Bus
A[7:0]
VDD
MAD2
D[7:0]
A[15:8]
4.7 K
27C512-15/
28F512-15/
Socket
LSI53C1000
8 D[7:0]
MAS0/
MAS1/
Q[7:0]
HCT374
CK
QE
8
Q[7:0]
8 D[7:0]
HCT374
CK
QE
8
Note: MAD 3, 1, 0 pulled LOW internally. MAD bus sense logic enabled for 64 Kbyte of fast memory (150 ns
devices @ 66 MHz).
B-2
External Memory Interface Diagram Examples
Figure B.3
128, 256, 512 Kbyte or 1 Mbyte Interface with 150 ns Memory
Optional - for Flash Memory only, not
required for EEPROMS.
VPP
+ 12 V
VPP
Control
GPIO4
MWE/
WE
MOE/
OE
MCE/
CE
MAD[7:0]
Bus
A[7:0]
VDD
MAD3
D[7:0]
A[15:8]
4.7 K
27C020-15/
28F020-15/
Socket
A[19:16]
LSI53C1000
8 D[7:0]
MAS0/
MAS1/
Q[7:0]
HCT374
CK
QE
8
Q[7:0]
8 D[7:0]
HCT374
CK
QE
8
MAD[3:0]
Q[3:0]
Bus
4 D[3:0]
HCT377
CK
QE
E
4
Note: MAD[2:0] pulled LOW internally. MAD bus sense logic enabled for 128, 256, 512 Kbytes, or 1 Mbyte of fast
memory (150 ns devices @ 66 MHz). The HCT374s may be replaced with HCT377s.
External Memory Interface Diagram Examples
B-3
Figure B.4
512 Kbyte Interface with 150 ns Memory
Optional - for Flash Memory only, not
required for EEPROMS.
27C010-15/28F010-15 Sockets
VPP
+ 12 V
VPP
Control
GPIO4
MWE/
WE
WE
WE
WE
OE
OE
OE
OE
D[7:0]
D[7:0]
D[7:0]
D[7:0]
A0
A0
A0
A0
A16
A16
A16
A16
MOE/
MAD[7:0]
Bus
LSI53C1000
MAD3
4.7 K
MAD1
4.7 K
MAD3
4.7 K
8 D[7:0]
MAS0/
MAS1/
MCE/
A[7:0]
VDD
D[7:0]
A[15:8]
Q[7:0]
HCT374
CK
QE
8
Q[7:0]
8
CE
8 D[7:0]
HCT374
CK
QE
MAD[2:0]
Q0
Bus
3 D[2:0]
HCT377
CK
Q2
E
.
.
.
A
B
.
.
.
CE
.
.
.
CE
.
.
.
CE
Y0
Y1
Y2
GB
Y3
HCT139
Note: MAD2 pulled LOW internally. MAD bus sense logic enabled for 512 Kbytes of slow memory (150 ns
devices, additional time required for HCT139 @ 66 MHz). The HCT374s may be replaced with HCT377s.
B-4
External Memory Interface Diagram Examples
Index
Symbols
(64TIMOD) 4-91
(A) 5-21
(A[6:0]) 5-24
(A[7:0]) 5-39
(A7) 5-24
(AAP) 4-26
(ABRT) 4-40, 4-46
(ACK) 4-37, 4-39
(ADB) 4-27
(ADDER) 4-68
(AESP) 4-28
(AIP) 4-42
(AIPCKEN) 4-99
(ARB[1:0]) 4-23
(ART) 4-82
(ATN) 4-37, 4-39, 5-21
(AUXC) 4-19
(BAR0[31:0]) 4-9
(BAR1[31:0]) 4-10
(BAR2[31:0]) 4-10
(BAR3[31:0]) 4-11
(BAR4[31:0]) 4-11
(BC) 5-39
(BF) 4-40, 4-64
(BL[1:0]) 4-61
(BL2) 4-57
(BOF) 4-63
(BSE[7:0]) 4-20
(BSY) 4-37, 4-39
(C_D) 4-37, 4-39, 4-44
(CA) 5-21
(CC[23:0]) 4-7
(CCNTL0) 4-88, 4-89
(CCNTL1) 4-91
(CCNTL2) 4-93
(CD) 5-32
(CHM) 4-30
(CID[7:0]) 4-18
(CIO) 4-52
(CLF) 2-51, 4-54
(CLS[7:0]) 4-7
(CLSE) 2-7, 4-65
(CM) 4-52
(CMP) 4-68, 4-72
(CON) 4-28, 4-47
(CP) 5-32
(CP[7:0]) 4-15
(CSBC) 4-114
(CSF) 2-51, 4-86
(CT) 5-31
(CTEST0) 4-51
(CTEST1) 4-51
(CTEST2) 4-52
(CTEST3) 4-53
(CTEST4) 4-55
(CTEST5) 4-56
(CTEST6) 4-57
(D1S) 4-19
(D2S) 4-19
(D8) 5-23
(DATA[7:0]) 4-21
(DBC) 4-58
(DBMS) 4-98
(DC) 5-33
(DCMD) 4-59
(DCNTL) 4-65
(DCRCC) 4-115
(DCRCPC) 4-115
(DDAC) 4-91
(DF[7:0]) 4-57
(DFE) 4-39
(DHP) 4-27
(DID[15:0]) 4-3
(DIEN) 4-64
(DIOM) 4-62
(DIP) 2-50, 2-52, 4-49
(DISFC) 4-90
(DMODE) 4-61
(DNAD) 4-59
(DNAD64) 4-98
(DPE) 4-5
(DPR) 4-6
(DRS) 4-97
(DSA) 4-45, 5-39
(DSCL) 4-20
(DSI) 4-19, 4-86
(DSLT) 4-20
(DSP) 4-60
(DSPS) 4-60
(DSTAT) 4-39
(DT[1:0]) 4-5
(EBM) 4-4
(EIS) 4-4
(EMS) 4-4
(EN64DBMV) 4-92
(EN64TIBMV) 4-92
(ENC[3:0]) 4-32, 4-34
(ENDID[3:0]) 5-20
(ENID[3:0]) 4-38
(ENNDJ) 4-90
(ENPMJ) 4-89
(EPC) 4-25
LSI53C1000 PCI to Ultra160 SCSI Controller
IX-1
(EPER) 4-3
(ERBA[31:11]) 4-14
(ERL) 4-63
(ERMP) 4-63
(ESA) 4-112
(EWS) 4-32
(FBL[2:0]) 4-55
(FBL3) 4-55
(FE) 4-77
(FFL[7:0]) 4-51
(FLF) 4-53
(FLSH) 4-49
(FMT[7:0]) 4-51
(GEN) 4-71, 4-75
(GEN[3:0]) 4-80
(GENSF) 4-79
(GPCNTL) 4-77
(GPIO[0]) 2-61
(GPIO[1:0]) 4-78
(GPIO[1]) 2-61
(GPIO[4:0]) 4-35
(GPIO[4:2]) 4-77
(GPREG) 4-35
(HT[7:0]) 4-8
(HTH) 4-71, 4-75
(HTH[3:0]) 4-78
(HTHBA) 4-79
(HTHSF) 4-80
(I/O) 4-9, 4-37, 4-39, 4-44
(IA) 4-113, 5-5
(IARB) 4-28
(IF) 5-31
(IID) 4-40, 4-64
(IL[7:0]) 4-16
(ILF) 4-42
(ILF1) 4-44
(IMMD) 5-24
(INTF) 4-48
(IP[7:0]) 4-16
(IRM[1:0]) 4-83
(IRQM) 4-66
(ISTAT0) 4-46
(ISTAT1) 4-49
(IT[1:0]) 5-5, 5-14, 5-23, 5-27
(IT[2:0]) 5-35, 5-38
(J) 5-31
(LDSC) 4-45
(LEDC) 4-77
(LOA) 4-42
(LOW) 4-85
(LS) 5-39
(LT[7:0]) 4-8
(M/A) 4-68, 4-72
(MAD[7]) 2-61
(MAN) 4-63
(MBOX0) 4-50
(MBOX0[7:0]) 4-50
(MBOX1) 4-50
(MC) 5-32
(MDPE) 4-40, 4-64
(ME) 4-77
(MEMORY) 4-10, 4-11
(MG[7:0]) 4-17
(ML[7:0]) 4-17
(MMRS) 4-95, 4-122
(MMWS) 4-96, 4-122
IX-2
Index
(MO[5:0]) 4-33
(MPEE) 4-55
(MSG) 4-37, 4-39, 4-43
(NC) 4-6
(NF) 5-35, 5-39
(NIP[7:0]) 4-18
(O[2:0]) 5-23
(OLF) 4-42
(OLF1) 4-44
(OPC) 5-9
(OPC[2:0]) 5-14, 5-23, 5-27
(PAR) 4-70, 4-74
(PCICIE) 4-52
(PEN) 4-20
(PFEN) 4-65
(PFF) 4-65
(PMC) 4-18
(PMCSR) 4-19
(PMCSR_BSE) 4-20
(PMEC) 4-19
(PMES[15:11]) 4-18
(PMJAD1) 4-110
(PMJAD2) 4-110
(PMJCTL) 4-89
(PST) 4-19
(PWS[1:0]) 4-20
(QEN) 4-83
(QSEL) 4-83
(RA) 5-18, 5-30
(RBC) 4-111
(REQ) 4-37, 4-39
(RESPID0) 4-80
(RESPID1) 4-81
(RID[7:0]) 4-6
(RMA) 4-5
(ROF) 4-84
(RRE) 4-32
(RSL) 4-69, 4-73
(RST) 4-28, 4-43, 4-70, 4-74
(RTA) 4-5
(SA) 5-22
(SBC) 4-113
(SBCL) 4-38
(SBDL) 4-92
(SBMC) 4-71, 4-75
(SBMS) 4-97
(SBR) 4-65
(SCE) 4-84
(SCF[2:0]) 2-42, 4-31
(SCID) 4-32
(SCNTL0) 4-23
(SCNTL1) 4-27
(SCNTL2) 4-29
(SCNTL3) 4-31
(SCRATCHA) 4-61, 4-119
(SCRATCHB) 4-94, 4-121
(SCRATCHC–SCRATCHR) 4-95
(SCSIP[2:0]) 5-12, 5-29
(SDID) 4-34
(SDP0) 4-43
(SDP0L) 4-43
(SDP1) 4-45
(SDU) 4-29
(SE) 4-3
(SEL) 4-37, 4-39, 4-69, 4-73
(Sel) 5-20
Numerics
(SEM) 4-47
(SFBR) 4-36
(SFS) 4-96, 4-123
(SGE) 4-69, 4-73
(SI) 4-49
(SID[15:0]) 4-13
(SIEN0) 4-68
(SIEN1) 4-70
(SIGP) 4-47, 4-52
(SIP) 4-48
(SIR) 4-40, 4-64
(SIST0) 4-72
(SIST1) 4-75, 4-120
(SLT) 4-82
(SMODE[1:0]) 4-87
(SOCL) 4-37
(SODL) 4-88
(SOM) 4-82
(SOZ) 4-82
(SPL1) 4-45
(SRE) 4-32
(SRST) 4-46
(SRUN) 4-49
(SSAID[3:0]) 4-81
(SSE) 4-5
(SSI) 4-40, 4-64
(SSID) 4-38
(SSM) 4-66
(SSTAT0) 4-42
(SSTAT1) 4-43
(SSTAT2) 4-44
(START) 4-24
(STD) 4-67
(STEST0) 4-81
(STEST1) 4-83
(STEST2) 4-84
(STEST3) 4-85
(STEST4) 4-87
(STIME0) 4-78
(STIME1) 4-79
(STO) 4-71, 4-75
(SWIDE) 4-76
(SXFER) 4-33
(SZM) 4-85
(TC[23:0]) 5-12, 5-35
(TE) 4-85
(TEMP) 4-54
(TF) 5-31
(TI) 5-18
(TIA) 5-6
(TM) 5-21
(TRG) 4-26
(TTM) 4-86
(UA) 4-111
(UDC) 4-70, 4-74
(VAL) 4-38
(VER[2:0]) 4-19
(VP) 5-32
(VUE0) 4-30
(VUE1) 4-30
(WATN) 4-25
(WIE) 4-4
(WOA) 4-43
(WRIE) 4-54
(WSR) 4-31
(WSS) 4-30
160 2-22
MAD 3-18
32/64-bit jump 5-31
32-bit addressing 5-6
3-state 3-2
64 bit
addressing 5-8
addressing in SCRIPTS 2-20
64 Kbytes ROM read cycle 6-60, 6-61
64-bit
table indirect indexing mode (64TIMOD) 4-91
A
A and B DIFFSENS SCSI signals 6-4
A[6:0] 5-24
A_DIFFSENS 3-11
A_GPIO0_ FETCH/ 3-13
A_GPIO1_ MASTER/ 3-13
A_GPIO2 3-13
A_GPIO3 3-13
A_GPIO4 3-13
A_SACK+- 3-12
A_SATN+- 3-12
A_SBSY+- 3-12
A_SC_D+- 3-12
A_SDP[1:0]+- 3-10
A_SI_O+- 3-12
A_SMSG+- 3-12
A_SREQ+- 3-12
A_SRST+- 3-12
A_SSEL+- 3-12
abort operation (ABRT) 4-46
aborted (ABRT) 4-40, 4-64
absolute maximum stress ratings 6-2
AC characteristics 6-11
ACK64/ 3-7
acknowledge 64 3-7
active termination 2-39
AD[63:0] 3-6
adder sum output (ADDER) 4-68
address and data signals 3-6
address/data bus 2-3
AIP 1-5, 2-25
control and generation 2-34
enable 4-99
options 2-33
alt interrupt A 3-9
arbitration
in progress (AIP) 4-42
mode bits 1 and 0 (ARB[1
0]) 4-23
priority encoder test (ART) 4-82
signals 3-8
assert
even SCSI parity (force bad parity) (AESP) 4-28
SATN/ on parity/CRC error (AAP) 4-26
SCSI
ACK/ signal (ACK) 4-37, 4-39
ATN/ signal (ATN) 4-37, 4-39
BSY/ signal (BSY) 4-37, 4-39
C_D/ signal (C_D) 4-37, 4-39
data bus (ADB) 4-27
I_O/ signal (I/O) 4-37, 4-39
Index
IX-3
assert
SCSI (Cont.)
MSG/ signal (MSG) 4-37, 4-39
REQ/ signal (REQ) 4-37, 4-39
RST/ signal (RST) 4-28
SEL/ signal (SEL) 4-37, 4-39
asynchronous information protection 2-25
enable 4-99
asynchronous SCSI
receive 2-38
send 2-37
aux_current 4-19
B
base address register
four (BAR4) 4-11
one (BAR1) 2-4, 4-10
three (BAR3) 4-11
two (BAR2) 4-10
zero (BAR0) 2-4, 4-9
BCH 2-25
bidirectional 3-2
signals 6-5, 6-6
BIOS 2-3
bits used for parity control and generation 2-34
block move 2-10
instructions 5-4
bridge support extensions (BSE[7:0]) 4-20
burst
length (BL[1:0]) 4-61
length bit 2 (BL2) 4-57
opcode fetch enable (BOF) 4-63
size selection 2-7
bus
command and byte enables 3-6
fault (BF) 4-40, 4-64
byte
count 5-39
empty in DMA FIFO (FMT[7:0]) 4-51
full in DMA FIFO (FFL[7:0]) 4-51
C
C_BE[3:0]/ 2-3
C_BE[7:0]/ 3-6
cache line size
(CLS) 2-8, 4-7
enable (CLSE) 2-8, 4-65
register 2-7, 2-10
cache mode, See PCI cache mode 2-10
call instruction 5-28
Cap_ID (CID[7:0]) 4-18
capabilities pointer (CP[7:0]) 4-15
capability ID register 4-18
carry test 5-31
chained block moves 2-55, 2-57
chained mode (CHM) 4-30
change bus phases 2-18
chip
control 0 (CCNTL0) 4-89
control 1 (CCNTL1) 4-91
test five (CTEST5) 2-7, 4-56
test four (CTEST4) 2-34, 4-55
test one (CTEST1) 4-51
test six (CTEST6) 4-57
IX-4
Index
test three (CTEST3) 2-9, 2-12, 4-53
test two (CTEST2) 4-52
test zero (CTEST0) 4-51
CHMOV 2-55
class code register 4-7
clear DMA FIFO (CLF) 2-51, 4-54
clear instruction 5-16
clear SCSI FIFO (CSF) 2-51, 4-86
CLK 3-5
clock 3-5
quadrupler 2-30
command register 2-12, 4-3
compare
data 5-32
phase 5-32
configuration
read command 2-6
space 2-3
write command 2-6
configured
as I/O (CIO) 4-52
as memory (CM) 4-52
connected (CON) 4-28, 4-47
CRC 1-4, 2-23
control and generation 2-34
disable checking 4-115
disable protocol checking 4-115
options 2-33
CRC-32 1-4
cumulative SCSI byte count (CSBC) 4-114
current
function of input voltage 6-9
function of output voltage 6-10
cycle frame 3-7
cyclic redundancy check 1-4
D
D0 2-63
D1 2-63
D1_Support (D1S) 4-19
D2 2-64
D2_Support (D2S) 4-19
D3 2-64
D3cold 2-64
D3hot 2-64
DACs 2-21
data
(DATA[7:0]) 4-21
compare mask 5-32
compare value 5-33
parity error reported (DPR) 4-6
paths 2-37
structure address (DSA) 4-45
data_scale (DSCL) 4-20
data_select (DSLT) 4-20
DC characteristics 6-1
default download mode 2-61
destination
address 5-24
I/O-memory enable (DIOM) 4-62
detected parity error (from slave) (DPE) 4-5
device
ID (DID[15:0]) 4-3
select 3-7
specific initialization (DSI) 4-19
DEVSEL/ 3-7
timing (DT[1:0]) 4-5
DIEN 2-48
differential mode 2-39
DIP 2-51
direct 5-19
disable
auto FIFO clear (DISFC) 4-90
CRC checking 4-115
CRC protocol checking 4-115
dual address cycle (DDAC) 4-91
halt on parity/CRC error or ATN (target only) (DHP) 4-27
single initiator response (DSI) 4-86
disable internal SCRIPT RAM cycles 4-90
disconnect 2-18
instruction 5-15
DMA
byte counter (DBC) 4-58
command (DCMD) 4-59
control (DCNTL) 2-7, 2-8, 2-9, 2-48, 4-65
FIFO 2-9, 2-36, 2-47
(DF[7:0]) 4-57
empty (DFE) 4-39
sections 2-36
interrupt 2-51
enable (DIEN) 2-35, 2-48, 4-64
interrupt pending (DIP) 4-49
mode (DMODE) 2-7, 2-8, 2-9, 2-12, 2-32, 4-61
next address (DNAD) 4-59
next address 64 (DNAD64) 4-98
SCRIPTS
pointer (DSP) 4-60
pointer save (DSPS) 4-60
status (DSTAT) 2-34, 2-48, 2-50, 2-51, 2-52, 4-39
domain validation 1-5, 2-22
double transition
clocking 2-23
download mode 2-62
DSA
relative 5-39
relative selector (DRS) 4-97
DSPS register 5-36
DSTAT 2-48
DT data-in 2-23
DT data-out 2-23
DT transfers
configuration 2-44
dual address cycles 2-21
command 2-7
dynamic block move selector (DBMS) 4-98
E
EEPROM 2-61
default download mode 2-61
enable
64-bit
direct BMOV (EN64DBMV) 4-92
table indirect BMOV (EN64TIBMV) 4-92
AIP 4-99
asynchronous information protection 4-99
bus mastering (EBM) 4-4
I/O space (EIS) 4-4
jump on nondata phase mismatches (ENNDJ) 4-90
memory space (EMS) 4-4
parity
Index
checking 2-33
checking (EPC) 4-25
error response (EPER) 4-3
phase mismatch jump (ENPMJ) 4-89
read
line (ERL) 4-63
multiple (ERMP) 4-63
response to
reselection (RRE) 4-32
selection (SRE) 4-32
wide SCSI (EWS) 4-32
ENABLE66 3-5
Enable66 3-5
enabling cache mode 2-12
encoded
chip SCSI ID (ENC[3:0]) 4-32
destination SCSI ID
(ENC[3:0]) 4-34
(ENID[3:0]) 4-38
SCSI destination ID 5-20
entry storage address (ESA) 4-112
error reporting signals 3-8
even parity 2-33
expansion ROM base address 4-14
external
clock 6-11
memory
configuration 2-60
diagram examples B-1
multiple byte accesses 6-13
read 6-41
timing 6-41
write 6-45
F
fast back to back capable 4-6
fatal interrupt 2-48
fetch enable (FE) 4-77
FIFO
byte control (FBL[2:0]) 4-55
byte control (FBL3) 4-55
first dword 5-5, 5-14, 5-23, 5-27, 5-38
flush DMA FIFO (FLF) 4-53
flushing (FLSH) 4-49
FRAME/ 3-7
full arbitration, selection/reselection 4-24
function complete (CMP) 4-68, 4-72
G
general description 1-1
general purpose
(GPREG) 4-35
I/O (GPIO[4:0]) 4-35
I/O pin 0 3-13
I/O pin 1 3-13
I/O pin 2 3-13
I/O pin 3 3-13
I/O pin 4 3-13
pin control (GPCNTL) 4-77
timer expired (GEN) 4-71, 4-75
timer period (GEN[3:0]) 4-80
timer scale factor (GENSF) 4-79
GNT/ 3-8
GPIO enable (GPIO[1:0]) 4-78
IX-5
GPIO enable (GPIO[4:2]) 4-77
grant 3-8
H
halting 2-51
handshake-to-handshake
timer bus activity enable (HTHBA) 4-79
timer expired (HTH) 4-71, 4-75
timer period (HTH[3:0]) 4-78
timer scale factor (HTHSF) 4-80
hardware control of SCSI activity LED 2-21
hardware interrupts 2-45
header type (HT[7:0]) 4-8
high impedance mode (SZM) 4-85
high voltage differential mode
description 2-39
HVD 2-39
I
I/O 3-2
instructions 5-14
read command 2-5
space 2-3, 2-4
write command 2-5
IDSEL 2-3, 3-7
illegal instruction detected (IID) 4-40, 4-64
immediate
arbitration (IARB) 4-28
data 5-24
index mode 0 5-8
index mode 1 5-8
indirect addressing 5-5
initialization device select 3-7
initiator
asynchronous receive 6-63
asynchronous send 6-62
mode 5-11, 5-16
phase mismatch 4-72
ready 3-7
synchronous transfer 6-66, 6-69
timing 6-24
input 3-2
capacitance 6-4
current as a function of input voltage 6-9
signals 6-6
instruction
address (IA) 4-113
type 5-38
block move 5-5
I/O instruction 5-14
memory move 5-35
read/write instruction 5-23
transfer control instruction 5-27
INTA/ 2-46, 2-52
INTC/ 2-53
interface
128, 256, 512 Kbyte or 1 Mbyte
150 ns memory B-3
16 Kbyte
200 ns memory B-1
512 Kbyte
150 ns memory B-4
64 Kbyte
150 ns memory B-2
IX-6
Index
control signals 3-7
parallel ROM 2-59
internal
RAM 2-19
SCRIPTS RAM 2-19
interrupt
A 3-9
acknowledge command 2-5
direction 3-9
fatal 2-48
halting 2-51
handling 2-45
hardware 2-45
instruction 5-29
INTC/ 2-53
line 4-16
masking 2-49
nonfatal 2-48
on the fly 5-31
on the fly (INTF) 4-48
output 6-13
pin (IP[7:0]) 4-16
polling 2-45
registers 2-46
DIEN 2-48
DSTAT 2-48
ISTAT 2-46
SIEN0 2-48
SIEN1 2-48
SIST0 2-47
SIST1 2-47
request 2-46
routing mode (IRM[1:0]) 4-83
sample interrupt service routine 2-52
stacked 2-50
status 0 (ISTAT0) 2-46, 4-46
status 1 (ISTAT1) 2-46, 4-49
interrupt-on-the-fly instruction 5-29
interrupts 2-48, 2-53
nonfatal 2-48
IRDY/ 3-7
IRQ mode (IRQM) 4-66
issuing cache commands 2-12
ISTAT 2-46
J
JTAG boundary scan testing 2-33
jump
address 5-33
call a relative address 5-30
call an absolute address 5-30
control (PMJCTL) 4-89
if true/false 5-31
instruction 5-27
JUMP64 address 5-33
L
last disconnect (LDSC) 4-45
latched SCSI parity
(SDP0L) 4-43
for SD[15:8] (SPL1) 4-45
latency 2-10
timer (LT[7:0]) 4-8
LED 2-21
LED_CNTL (LEDC) 4-77
little endian 2-18
load and store
instructions 2-32, 5-37
prefetch unit and store instructions 2-32
load/store 5-39
lost arbitration (LOA) 4-42
low voltage differential, See LVDlink 2-39
LSI53C1000
329 ball grid array 6-76
329 BGA mechanical drawing 6-77
new features 1-3
register map A-1, A-3
LVD 2-39
driver SCSI signals 6-3
receiver SCSI signals 6-3
LVDlink 1-2, 1-6, 2-39
benefits 1-6
operation 2-39
M
M66EN 3-5
MAD bus programming 3-17
MAD[0] 3-18
MAD[3:1] 3-18
MAD[4] 3-18
MAD[5] 3-18
MAD[6] 3-18
MAD[7:0] 3-14, 3-17
MAD[7] 3-17
mailbox0 (MBOX0) 2-46, 4-50
mailbox0 [7:0] (MBOX0[7:0]) 4-50
mailbox1 (MBOX1) 2-46, 4-50
mailbox1 [7:0] (MBOX1[7:0]) 4-50
manual start mode (MAN) 4-63
MAS0/ 3-14
MAS1/ 3-14
masking 2-49
master
data parity error (MDPE) 4-40, 4-64
enable (ME) 4-77
parity error enable (MPEE) 4-55
max SCSI synchronous offset (MO[5:0]) 4-33
Max_Lat (ML[7:0]) 4-17
maximum stress ratings 6-2
MCE/ 3-14
memory
address strobe 0 3-14
address strobe 1 3-14
address/data bus 3-14
chip enable 3-14
I/O address/DSA offset 5-40
move 2-10
move instructions 2-31, 5-34
no flush option 2-31
move read selector (MMRS) 4-95, 4-122
move write selector (MMWS) 4-96, 4-122
output enable 3-14, 3-15
read 2-12, 2-13
read caching 2-13
read command 2-6
read line 2-12, 2-13
read line command 2-8
read multiple 2-12, 2-13
read multiple command 2-7
Index
space 2-3, 2-4
to memory 2-18
to memory moves 2-18
write 2-12, 2-13
write and invalidate 2-12
write and invalidate command 2-9
write caching 2-13
write command 2-6
write enable 3-14
Min_Gnt (MG[7:0]) 4-17
MOE/_TESTOUT 3-14, 3-15
move to/from SFBR cycles 5-25
multiple cache line transfers 2-9
MWE/ 3-14
N
new capabilities (NC) 4-6
new features in the LSI53C1000 1-3
next item pointer register 4-18
Next_Item_Ptr (NIP[7:0]) 4-18
no flush 5-35
store instruction only 5-39
nonburst opcode fetch
32-bits address and data 6-24, 6-26, 6-28, 6-30
none 2-62
nonfatal interrupts 2-48
normal/fast memory (128 Kbytes)
multiple byte access read cycle 6-52
multiple byte access write cycle 6-54
single byte access read cycle 6-48
single byte access write cycle 6-50
O
objectives of DMA architecture 2-59
opcode 5-9, 5-14, 5-23, 5-27
fetch burst capability 2-32
operating conditions 6-2
operating register/SCRIPTS RAM read
32-bits 6-17
64-bits 6-18, 6-20, 6-22, 6-32, 6-34, 6-36, 6-38
operator 5-23
output current as a function of output voltage 6-10
output signals 6-5
P
PAR 3-6
PAR64 3-6
parallel
protocol request 2-24
ROM 2-59
ROM support 2-60
parity 3-6
control and generation 2-34
error 3-8
(PAR) 4-74
errors and interrupts 2-35
options 2-33
parity64 3-6
PCI
addressing 2-3
bus commands and encoding types 2-4
bus commands and functions supported 2-4
IX-7
PCI (Cont.)
cache line size register 2-9
cache mode 2-10
command register 2-9
commands 2-4
configuration info enable (PCICIE) 4-52
configuration register read 6-15, 6-16
configuration registers 4-1
configuration space 2-3
external memory interface timing diagrams 6-13
functional description 2-3
I/O space 2-4
interface signals 3-4
master transaction 2-12
master transfer 2-12
memory space 2-4
performance 1-9
target disconnect 2-10
target retry 2-10
PERR/ 3-8
phase mismatch
handling in SCRIPTS 2-19
jump address 1 (PMJAD1) 4-110
jump address 2 (PMJAD2) 4-110
physical dword address and data 3-6
pin decoding 3-18
PME
clock (PMEC) 4-19
enable (PEN) 4-20
status (PST) 4-19
support (PMES[15:11]) 4-18
polling 2-45
power
and ground signals 3-16
management 2-62
capabilities 4-18
control/status 4-19
state
D0 2-63
D1 2-63
D2 2-64
D3 2-64
state (PWS[1:0]) 4-20
prefetch
enable (PFEN) 4-65
flush 2-32
flush (PFF) 4-65
SCRIPTS instructions 2-31
protocol options 2-25
pull-ups, internal, conditions 3-4
R
RAM, See also SCRIPTS RAM 2-19
RBIAS 3-16
read
line 2-11, 2-12, 2-13
line function 2-8
modify-write cycles 5-24
multiple 2-8, 2-11, 2-12, 2-13
multiple with read line enabled 2-8
write instructions 5-23
write system memory from a SCRIPT 5-35
read/write
instructions 5-23, 5-25
system memory from a SCRIPT 5-35
IX-8
Index
receive rate calculation 2-43
received
master abort (from master) (RMA) 4-5
target abort (from master) (RTA) 4-5
register
address 5-39
address - A[6:0] 5-24
interrupt 2-46
map
PCI A-1
SCSI A-3
relative 5-20
relative addressing mode 5-18, 5-30
remaining byte count (RBC) 4-111
REQ/ 3-8
req/ack offset 2-24
REQ64/ 3-7
request 3-8
request 64 3-7
reselect 2-18
during reselection 2-40
instruction 5-15
reselected (RSL) 4-69, 4-73
reserved command 2-6
reset 3-5
input 6-12
SCSI offset (ROF) 4-84
response ID one (RESPID1) 4-81
response ID zero (RESPID0) 4-80
return instruction 5-28
revision ID register 4-6
(RID[7:0]) 4-6
rise and fall time test condition 6-8
ROM 2-59
flash and memory interface signals 3-14
routing interrupts 2-53
routing, RAID ready 2-53
RST/ 3-5
S
SACK 2-51
SACs 2-21
scan mode 3-15
SCAN_MODE 3-15
SCF divisor values 2-42
SCLK 3-9
quadrupler enable (QEN) 4-83
quadrupler select (QSEL) 4-83
scratch
byte register (SBR) 4-65
register A (SCRATCHA) 4-61, 4-119
register B (SCRATCHB) 4-94, 4-121
registers C–R (SCRATCHC–SCRATCHR) 4-95
script fetch selector (SFS) 4-96, 4-123
SCRIPTS 2-57
64-bit addressing 2-20
block move
index mode 0 5-8
index mode 1 5-8
indirect addressing 5-5
instruction type 5-5
opcode 5-9
SCSI phase 5-12
start address 5-13, 5-14
table indirect addressing 5-6
transfer counter 5-12
SCRIPTS (Cont.)
block move instructions 5-4
call instruction 5-28
chained block moves 2-55
clear instruction 5-16
disconnect instruction 5-15
I/O
encoded SCSI destination ID 5-20
instruction type 5-14
opcode 5-14
relative addressing mode 5-18
select with ATN/ 5-20
set/clear carry 5-21
set/clear SACK/ 5-21
set/clear SATN/ 5-21
set/clear target mode 5-21
start address 5-22
table indirect mode 5-18
I/O instructions 5-14
instruction prefetch 2-31
internal RAM 2-19
interrupt instruction 5-29
interrupt instruction received (SIR) 4-40, 4-64
interrupt-on-the-fly instruction 5-29
jump instruction 5-27
load and store
byte count 5-39
DSA relative 5-39
instruction type 5-38
instructions 2-32
load/store 5-39
memory I/O address and DSA offset 5-40
no flush 5-39
register address 5-39
memory move
DSPS register 5-36
instruction type 5-35
no flush 5-35
TEMP register 5-37
transfer count 5-35
operation 5-1
overview 5-4
phase mismatch handling 2-19
processor 2-19
internal RAM for instruction storage 2-19
performance 2-19
RAM 2-4, 2-19
read/write
A[6:0] 5-24
destination address 5-24
immediate data 5-24
instruction type 5-23
opcode 5-23
operator 5-23
upper register address line [A7] 5-24
use data8/SFBR 5-23
reselect instruction 5-15
return instruction 5-28
running (SRUN) 4-49
select instruction 5-17
set instruction 5-16, 5-18
transfer control
32/64-bit jump 5-31
carry test 5-31
compare data 5-32
compare phase 5-32
Index
data compare mask 5-32
data compare value 5-33
instruction type 5-27
interrupt-on-the-fly 5-31
jump address 5-33
jump if true/false 5-31
jump64 address 5-33
opcode 5-27
relative addressing 5-30
SCSI phase 5-29
wait for valid phase 5-32
wait disconnect instruction 5-17
wait select instruction 5-15
SCSI
activity LED 2-21
asynchronous receive 2-38
asynchronous send 2-37
ATN condition - target mode (M/A) 4-68
bit mode change (SBMC) 4-75
bus control lines (SBCL) 4-38
bus data lines (SBDL) 4-92
bus interface 2-39, 2-41
bus mode change (SBMC) 4-71
byte count (SBC) 4-113
C_D/ signal (C_D) 4-44
chip ID (SCID) 4-32
clock 3-9
clock quadrupler 2-30
control enable (SCE) 4-84
control one (SCNTL1) 2-34, 4-27
control three (SCNTL3) 2-42, 4-31
control two (SCNTL2) 4-29
control zero (SCNTL0) 2-34, 4-23
cumulative byte count 4-114
destination ID (SDID) 4-34
disconnect unexpected (SDU) 4-29
encoded destination ID 5-20
first byte received (SFBR) 4-36
function A control 3-12
function A GPIO signals 3-13
functional description 2-18
gross error (SGE) 4-69, 4-73
hysteresis of receivers 6-9
I/O instructions 5-14
I_O/ signal (I/O) 4-44
input data latch (SIDL) 4-87
input filtering 6-8
instructions
block move 5-4
I/O 5-14
read/write 5-23
interface signals 3-9
interrupt 2-51
enable one (SIEN1) 2-48
enable zero (SIEN0) 2-34, 2-48
status one (SIST1) 2-47, 2-48, 2-50, 2-52
status zero (SIST0) 2-34, 2-47, 2-48, 2-50, 2-52
interrupt enable one (SIEN1) 4-70
interrupt enable zero (SIEN0) 4-68
interrupt pending (SIP) 4-48
interrupt status one (SIST1) 4-75, 4-120
interrupt status zero (SIST0) 4-72
low level mode (LOW) 4-85
LVD 2-39
LVDlink 2-39
mode (SMODE[1:0]) 4-87
IX-9
SCSI (Cont.)
MSG/ signal (MSG) 4-43
new phases on the SCSI bus 2-23
output control latch (SOCL) 4-37
output data latch (SODL) 4-88
parity errors and interrupts 2-35
parity/CRC error (PAR) 4-70
performance 1-7
phase 5-12, 5-29
phase mismatch - initiator mode 4-68
receive rate 2-43
registers 4-21
reset condition (RST) 4-70
RST/ received (RST) 4-74
RST/ signal (RST) 4-43
SCRIPTS operation 5-1
sample instruction 5-3
SDP0/ parity signal (SDP0) 4-43
SDP1/ parity signal (SDP1) 4-45
selected as ID (SSAID[3:0]) 4-81
selector ID (SSID) 4-38
send rate 2-43
single-ended 2-39
SODL register 2-57
status one (SSTAT1) 2-34, 4-43
status two (SSTAT2) 2-34, 4-44
status zero (SSTAT0) 2-34, 4-42
synchronous offset maximum (SOM) 4-82
synchronous offset zero (SOZ) 4-82
synchronous operation 2-41
synchronous receive 2-39
synchronous send 2-38
termination 2-39
test four (STEST4) 4-87
test one (STEST1) 4-83
test three (STEST3) 4-85
test two (STEST2) 4-84
test zero (STEST0) 4-81
timer one (STIME1) 4-79
timer zero (STIME0) 4-78
timing diagrams 6-62
TolerANT technology 1-6
transfer (SXFER) 4-33
Ultra 160 features 2-22
Ultra160 SCSI 2-22
valid (VAL) 4-38
wide residue (SWIDE) 4-76
wide SCSI receive bit 2-56
wide SCSI send bit 2-56
SCSI-1
transfers (single-ended 5.0 Mbytes) 6-64
SCSI-2
fast transfers 6-65, 6-67
second dword 5-13, 5-22, 5-24, 5-33, 5-36, 5-39
select 2-18
during selection 2-40
instruction 5-17
with ATN/ 5-20
with SATN/ on a start sequence (WATN) 4-25
selected (SEL) 4-69, 4-73
selection or reselection time-out (STO) 4-71, 4-75
selection response logic test (SLT) 4-82
semaphore (SEM) 4-47
send rate calculation 2-43
serial EEPROM
data format 2-61
IX-10
Index
interface 2-61
SERR/ 3-8
SERR/enable (SE) 4-3
set instruction 5-16
SCRIPTS 5-18
set/clear
carry 5-21
SACK/ 5-21
SATN/ 5-21
target mode 5-21
SIDL
least significant byte full (ILF) 4-42
most significant byte full (ILF1) 4-44
SIEN0 2-48
SIEN1 2-48
signal process (SIGP) 4-47, 4-52
signaled system error (SSE) 4-5
simple arbitration 4-23
single
address cycles 2-21
ended SCSI signals 6-7
step interrupt (SSI) 4-40, 4-64
step mode (SSM) 4-66
transition
data-in 2-23
data-out 2-23
SIP 2-50, 2-51
SIST0 2-47
SIST1 2-47
slow memory
read cycle 6-56
write cycle 6-58
slow ROM pin 3-18
SODL
least significant byte full (OLF) 4-42
most significant byte full (OLF1) 4-44
SODL register 2-57
software reset (SRST) 4-46
source
I/O-memory enable (SIOM) 4-62
special cycle command 2-5
SREQ 2-51
stacked interrupts 2-50
start
address 5-13, 5-14, 5-22
DMA operation (STD) 4-67
sequence (START) 4-24
static block move selector (SBMS) 4-97
status register 4-5
STOP command 2-10
stop signal 3-7
STOP/ 3-7
store instruction 2-32
stress ratings 6-2
subsystem ID 2-62
(SID[15:0]) 4-13
subsystem vendor ID 2-61
(SVID[15:0]) 4-12
SureLINK 1-5
SWIDE register 2-57
SYNC_IRQD (SI) 4-49
synchronous
clock conversion factor (SCF[2:0]) 4-31
data transfer rates 2-41
operation 2-41
period, See transfer period
synchronous (Cont.)
SCSI receive 2-39
SCSI send 2-38
transfer rate 2-45
system
application 1-3
system error 3-8
system signals 3-5
T
table indirect 5-6, 5-19
index mode mapping 5-9
mode 5-18
table relative 5-20
target
asynchronous receive 6-64
asynchronous send 6-63
mode 5-10, 5-15
SATN/ active (M/A) 4-72
mode (TRG) 4-26
ready 3-7
synchronous transfer 6-66, 6-69
timing 6-14
TCK 3-15
TDI 3-15
TDO 3-15
TEMP register 5-37
temporary (TEMP) 4-54
termination 2-39
test clock 3-15
test data in 3-15
test data out 3-15
test halt SCSI clock 3-15
test interface signals 3-15
test mode select 3-15
test power down 3-15
test reset 3-15
TEST_HSC 3-15
TEST_PD 3-15
TEST_RSTN 3-15
third dword 5-14, 5-33, 5-36
timer test mode (TTM) 4-86
timing diagrams 6-13
TMS 3-15
TolerANT 1-6
enable (TE) 4-85
technology 1-6
benefits 1-7
electrical characteristics 6-6
totem pole output 3-2
transfer
control 2-32
control instructions 5-27
and SCRIPTS instruction prefetching 2-32
count 5-35
counter 5-12
information 2-18
period factor 2-24
rate synchronous 2-41
width exponent 2-24
TRDY/ 2-10, 3-7
Ultra SCSI
single-ended transfers 6-65, 6-67
Ultra160 2-22
Ultra160 SCSI 1-4
benefits 1-4
designing an Ultra160 SCSI system 2-22
enabling 2-26
LVDlink 2-39
Ultra2 SCSI
transfers 6-66, 6-68, 6-69
unexpected disconnect (UDC) 4-70, 4-74
updated address (UA) 4-111
upper register address line (A7) 5-24
use data8/SFBR 5-23
V
VDD 3-16
-A 3-16
-Bias 3-16
-Core 3-16
vendor
ID (VID[15:0]) 4-2
unique enhancement, bit 1 (VUE1) 4-30
unique enhancements, bit 0 (VUE0) 4-30
version (VER[2:0]) 4-19
VSS 3-16
-A 3-16
-Core 3-16
W
wait
disconnect instruction 5-17
for disconnect 2-18
for valid phase 5-32
reselect instruction 5-17
select instruction 5-15
wide SCSI
chained block moves 2-55
receive (WSR) 4-31
receive bit 2-56
send (WSS) 4-30
send bit 2-56
won arbitration (WOA) 4-43
write
read instructions 5-23
read system memory from a SCRIPT 5-35
write and invalidate 2-9, 2-10, 2-11, 2-12
enable (WIE) 4-4
enable (WRIE) 4-54
X
XCLKH_DT 2-42
XCLKH_ST 2-43
XCLKS_DT 2-43
XCLKS_ST 2-43
U
Ultra 160/m features 2-22
Index
IX-11
IX-12
Index
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Name
Telephone
Title
Department
Company Name
Street
City, State, Zip
Customer Feedback
Date
Fax
Mail Stop
U.S. Distributors
by State
A. E.
Avnet Electronics
http://www.hh.avnet.com
B. M.
Bell Microproducts,
Inc. (for HAB’s)
http://www.bellmicro.com
I. E.
Insight Electronics
http://www.insight-electronics.com
W. E.
Wyle Electronics
http://www.wyle.com
Alabama
Daphne
I. E.
Tel: 334.626.6190
Huntsville
A. E.
Tel: 256.837.8700
B. M.
Tel: 256.705.3559
I. E.
Tel: 256.830.1222
W. E. Tel: 800.964.9953
Alaska
A. E.
Tel: 800.332.8638
Arizona
Phoenix
A. E.
Tel: 480.736.7000
B. M.
Tel: 602.267.9551
W. E. Tel: 800.528.4040
Tempe
I. E.
Tel: 480.829.1800
Tucson
A. E.
Tel: 520.742.0515
Arkansas
W. E. Tel: 972.235.9953
California
Agoura Hills
B. M.
Tel: 818.865.0266
Granite Bay
B. M.
Tel: 916.523.7047
Irvine
A. E.
Tel: 949.789.4100
B. M.
Tel: 949.470.2900
I. E.
Tel: 949.727.3291
W. E. Tel: 800.626.9953
Los Angeles
A. E.
Tel: 818.594.0404
W. E. Tel: 800.288.9953
Sacramento
A. E.
Tel: 916.632.4500
W. E. Tel: 800.627.9953
San Diego
A. E.
Tel: 858.385.7500
B. M.
Tel: 858.597.3010
I. E.
Tel: 800.677.6011
W. E. Tel: 800.829.9953
San Jose
A. E.
Tel: 408.435.3500
B. M.
Tel: 408.436.0881
I. E.
Tel: 408.952.7000
Santa Clara
W. E. Tel: 800.866.9953
Woodland Hills
A. E.
Tel: 818.594.0404
Westlake Village
I. E.
Tel: 818.707.2101
Colorado
Denver
A. E.
Tel: 303.790.1662
B. M.
Tel: 303.846.3065
W. E. Tel: 800.933.9953
Englewood
I. E.
Tel: 303.649.1800
Idaho Springs
B. M.
Tel: 303.567.0703
Illinois
North/South
A. E.
Tel: 847.797.7300
Tel: 314.291.5350
Chicago
B. M.
Tel: 847.413.8530
W. E. Tel: 800.853.9953
Schaumburg
I. E.
Tel: 847.885.9700
Connecticut
Cheshire
A. E.
Tel: 203.271.5700
I. E.
Tel: 203.272.5843
Wallingford
W. E. Tel: 800.605.9953
Indiana
Fort Wayne
I. E.
Tel: 219.436.4250
W. E. Tel: 888.358.9953
Indianapolis
A. E.
Tel: 317.575.3500
Delaware
North/South
A. E.
Tel: 800.526.4812
Tel: 800.638.5988
B. M.
Tel: 302.328.8968
W. E. Tel: 856.439.9110
Iowa
W. E. Tel: 612.853.2280
Cedar Rapids
A. E.
Tel: 319.393.0033
Florida
Altamonte Springs
B. M.
Tel: 407.682.1199
I. E.
Tel: 407.834.6310
Boca Raton
I. E.
Tel: 561.997.2540
Bonita Springs
B. M.
Tel: 941.498.6011
Clearwater
I. E.
Tel: 727.524.8850
Fort Lauderdale
A. E.
Tel: 954.484.5482
W. E. Tel: 800.568.9953
Miami
B. M.
Tel: 305.477.6406
Orlando
A. E.
Tel: 407.657.3300
W. E. Tel: 407.740.7450
Tampa
W. E. Tel: 800.395.9953
St. Petersburg
A. E.
Tel: 727.507.5000
Georgia
Atlanta
A. E.
Tel: 770.623.4400
B. M.
Tel: 770.980.4922
W. E. Tel: 800.876.9953
Duluth
I. E.
Tel: 678.584.0812
Hawaii
A. E.
Tel: 800.851.2282
Idaho
A. E.
W. E.
Tel: 801.365.3800
Tel: 801.974.9953
Kansas
W. E. Tel: 303.457.9953
Kansas City
A. E.
Tel: 913.663.7900
Lenexa
I. E.
Tel: 913.492.0408
Kentucky
W. E. Tel: 937.436.9953
Central/Northern/ Western
A. E.
Tel: 800.984.9503
Tel: 800.767.0329
Tel: 800.829.0146
Louisiana
W. E. Tel: 713.854.9953
North/South
A. E.
Tel: 800.231.0253
Tel: 800.231.5775
Maine
A. E.
W. E.
Tel: 800.272.9255
Tel: 781.271.9953
Maryland
Baltimore
A. E.
Tel: 410.720.3400
W. E. Tel: 800.863.9953
Columbia
B. M.
Tel: 800.673.7461
I. E.
Tel: 410.381.3131
Massachusetts
Boston
A. E.
Tel: 978.532.9808
W. E. Tel: 800.444.9953
Burlington
I. E.
Tel: 781.270.9400
Marlborough
B. M.
Tel: 800.673.7459
Woburn
B. M.
Tel: 800.552.4305
Michigan
Brighton
I. E.
Tel: 810.229.7710
Detroit
A. E.
Tel: 734.416.5800
W. E. Tel: 888.318.9953
Clarkston
B. M.
Tel: 877.922.9363
Minnesota
Champlin
B. M.
Tel: 800.557.2566
Eden Prairie
B. M.
Tel: 800.255.1469
Minneapolis
A. E.
Tel: 612.346.3000
W. E. Tel: 800.860.9953
St. Louis Park
I. E.
Tel: 612.525.9999
Mississippi
A. E.
Tel: 800.633.2918
W. E. Tel: 256.830.1119
Missouri
W. E. Tel: 630.620.0969
St. Louis
A. E.
Tel: 314.291.5350
I. E.
Tel: 314.872.2182
Montana
A. E.
Tel: 800.526.1741
W. E. Tel: 801.974.9953
Nebraska
A. E.
Tel: 800.332.4375
W. E. Tel: 303.457.9953
Nevada
Las Vegas
A. E.
Tel: 800.528.8471
W. E. Tel: 702.765.7117
New Hampshire
A. E.
Tel: 800.272.9255
W. E. Tel: 781.271.9953
New Jersey
North/South
A. E.
Tel: 201.515.1641
Tel: 609.222.6400
Mt. Laurel
I. E.
Tel: 856.222.9566
Pine Brook
B. M.
Tel: 973.244.9668
W. E. Tel: 800.862.9953
Parsippany
I. E.
Tel: 973.299.4425
Wayne
W. E. Tel: 973.237.9010
New Mexico
W. E. Tel: 480.804.7000
Albuquerque
A. E.
Tel: 505.293.5119
U.S. Distributors
by State
(Continued)
New York
Hauppauge
I. E.
Tel: 516.761.0960
Long Island
A. E.
Tel: 516.434.7400
W. E. Tel: 800.861.9953
Rochester
A. E.
Tel: 716.475.9130
I. E.
Tel: 716.242.7790
W. E. Tel: 800.319.9953
Smithtown
B. M.
Tel: 800.543.2008
Syracuse
A. E.
Tel: 315.449.4927
North Carolina
Raleigh
A. E.
Tel: 919.859.9159
I. E.
Tel: 919.873.9922
W. E. Tel: 800.560.9953
North Dakota
A. E.
Tel: 800.829.0116
W. E. Tel: 612.853.2280
Ohio
Cleveland
A. E.
Tel: 216.498.1100
W. E. Tel: 800.763.9953
Dayton
A. E.
Tel: 614.888.3313
I. E.
Tel: 937.253.7501
W. E. Tel: 800.575.9953
Strongsville
B. M.
Tel: 440.238.0404
Valley View
I. E.
Tel: 216.520.4333
Oklahoma
W. E. Tel: 972.235.9953
Tulsa
A. E.
Tel: 918.459.6000
I. E.
Tel: 918.665.4664
Oregon
Beaverton
B. M.
Tel: 503.524.1075
I. E.
Tel: 503.644.3300
Portland
A. E.
Tel: 503.526.6200
W. E. Tel: 800.879.9953
Pennsylvania
Mercer
I. E.
Tel: 412.662.2707
Philadelphia
A. E.
Tel: 800.526.4812
B. M.
Tel: 877.351.2355
W. E. Tel: 800.871.9953
Pittsburgh
A. E.
Tel: 412.281.4150
W. E. Tel: 440.248.9996
Rhode Island
A. E.
800.272.9255
W. E. Tel: 781.271.9953
South Carolina
A. E.
Tel: 919.872.0712
W. E. Tel: 919.469.1502
South Dakota
A. E.
Tel: 800.829.0116
W. E. Tel: 612.853.2280
Tennessee
W. E. Tel: 256.830.1119
East/West
A. E.
Tel: 800.241.8182
Tel: 800.633.2918
Texas
Arlington
B. M.
Tel: 817.417.5993
Austin
A. E.
Tel: 512.219.3700
B. M.
Tel: 512.258.0725
I. E.
Tel: 512.719.3090
W. E. Tel: 800.365.9953
Dallas
A. E.
Tel: 214.553.4300
B. M.
Tel: 972.783.4191
W. E. Tel: 800.955.9953
El Paso
A. E.
Tel: 800.526.9238
Houston
A. E.
Tel: 713.781.6100
B. M.
Tel: 713.917.0663
W. E. Tel: 800.888.9953
Richardson
I. E.
Tel: 972.783.0800
Rio Grande Valley
A. E.
Tel: 210.412.2047
Stafford
I. E.
Tel: 281.277.8200
Utah
Centerville
B. M.
Tel: 801.295.3900
Murray
I. E.
Tel: 801.288.9001
Salt Lake City
A. E.
Tel: 801.365.3800
W. E. Tel: 800.477.9953
Vermont
A. E.
Tel: 800.272.9255
W. E. Tel: 716.334.5970
Virginia
A. E.
Tel: 800.638.5988
W. E. Tel: 301.604.8488
Haymarket
B. M.
Tel: 703.754.3399
Springfield
B. M.
Tel: 703.644.9045
Washington
Kirkland
I. E.
Tel: 425.820.8100
Maple Valley
B. M.
Tel: 206.223.0080
Seattle
A. E.
Tel: 425.882.7000
W. E. Tel: 800.248.9953
West Virginia
A. E.
Tel: 800.638.5988
Wisconsin
Milwaukee
A. E.
Tel: 414.513.1500
W. E. Tel: 800.867.9953
Wauwatosa
I. E.
Tel: 414.258.5338
Wyoming
A. E.
Tel: 800.332.9326
W. E. Tel: 801.974.9953
Direct Sales
Representatives by State
(Components and Boards)
E. A.
E. L.
GRP
I. S.
ION
R. A.
SGY
Earle Associates
Electrodyne - UT
Group 2000
Infinity Sales, Inc.
ION Associates, Inc.
Rathsburg Associates, Inc.
Synergy Associates,
Inc.
Arizona
Tempe
E. A.
Tel: 480.921.3305
California
Calabasas
I. S.
Tel: 818.880.6480
Irvine
I. S.
Tel: 714.833.0300
San Diego
E. A.
Tel: 619.278.5441
Illinois
Elmhurst
R. A.
Tel: 630.516.8400
Indiana
Cicero
R. A.
Tel: 317.984.8608
Ligonier
R. A.
Tel: 219.894.3184
Plainfield
R. A.
Tel: 317.838.0360
Massachusetts
Burlington
SGY
Tel: 781.238.0870
Michigan
Byron Center
R. A.
Tel: 616.554.1460
Good Rich
R. A.
Tel: 810.636.6060
Novi
R. A.
Tel: 810.615.4000
North Carolina
Cary
GRP
Tel: 919.481.1530
Ohio
Columbus
R. A.
Tel: 614.457.2242
Dayton
R. A.
Tel: 513.291.4001
Independence
R. A.
Tel: 216.447.8825
Pennsylvania
Somerset
R. A.
Tel: 814.445.6976
Texas
Austin
ION
Tel: 512.794.9006
Arlington
ION
Tel: 817.695.8000
Houston
ION
Tel: 281.376.2000
Utah
Salt Lake City
E. L.
Tel: 801.264.8050
Wisconsin
Muskego
R. A.
Tel: 414.679.8250
Saukville
R. A.
Tel: 414.268.1152
Sales Offices and Design
Resource Centers
LSI Logic Corporation
Corporate Headquarters
1551 McCarthy Blvd
Milpitas CA 95035
Tel: 408.433.8000
Fax: 408.433.8989
Fort Collins
2001 Danfield Court
Fort Collins, CO 80525
Tel: 970.223.5100
Fax: 970.206.5549
New Jersey
Red Bank
125 Half Mile Road
Suite 200
Red Bank, NJ 07701
Tel: 732.933.2656
Fax: 732.933.2643
NORTH AMERICA
Florida
Boca Raton
Cherry Hill - Mint Technology
California
Irvine
2255 Glades Road
Suite 324A
Boca Raton, FL 33431
Tel: 561.989.3236
Fax: 561.989.3237
Tel: 856.489.5530
Fax: 856.489.5531
Georgia
Alpharetta
New York
Fairport
2475 North Winds Parkway
Suite 200
Alpharetta, GA 30004
550 Willowbrook Office Park
Fairport, NY 14450
18301 Von Karman Ave
Suite 900
Irvine, CA 92612
♦ Tel: 949.809.4600
Fax: 949.809.4444
Pleasanton Design Center
5050 Hopyard Road, 3rd Floor
Suite 300
Pleasanton, CA 94588
Tel: 925.730.8800
Fax: 925.730.8700
Tel: 770.753.6146
Fax: 770.753.6147
Illinois
Oakbrook Terrace
215 Longstone Drive
Cherry Hill, NJ 08003
Tel: 716.218.0020
Fax: 716.218.9010
North Carolina
Raleigh
Phase II
4601 Six Forks Road
Suite 528
Raleigh, NC 27609
Tel: 630.954.2234
Fax: 630.954.2235
Tel: 919.785.4520
Fax: 919.783.8909
Kentucky
Bowling Green
Oregon
Beaverton
1551 McCarthy Blvd
Sales Office
M/S C-500
Milpitas, CA 95035
1262 Chestnut Street
Bowling Green, KY 42101
15455 NW Greenbrier Parkway
Suite 235
Beaverton, OR 97006
Fax: 408.954.3353
Maryland
Bethesda
7585 Ronson Road
Suite 100
San Diego, CA 92111
Tel: 858.467.6981
Fax: 858.496.0548
Silicon Valley
♦ Tel: 408.433.8000
Design Center
M/S C-410
Tel: 408.433.8000
Fax: 408.433.7695
Wireless Design Center
11452 El Camino Real
Suite 210
San Diego, CA 92130
Tel: 858.350.5560
Fax: 858.350.0171
Colorado
Boulder
4940 Pearl East Circle
Suite 201
Boulder, CO 80301
♦ Tel: 303.447.3800
Fax: 303.541.0641
Colorado Springs
Tel: 270.793.0010
Fax: 270.793.0040
6903 Rockledge Drive
Suite 230
Bethesda, MD 20817
Tel: 301.897.5800
Fax: 301.897.8389
Massachusetts
Waltham
200 West Street
Waltham, MA 02451
♦ Tel: 781.890.0180
Fax: 781.890.6158
Tel: 503.645.0589
Fax: 503.645.6612
Texas
Austin
9020 Capital of TX Highway North
Building 1
Suite 150
Austin, TX 78759
Tel: 512.388.7294
Fax: 512.388.4171
Plano
500 North Central Expressway
Suite 440
Plano, TX 75074
♦ Tel: 972.244.5000
Burlington - Mint Technology
Fax: 972.244.5001
77 South Bedford Street
Burlington, MA 01803
Houston
Tel: 781.685.3800
Fax: 781.685.3801
20405 State Highway 249
Suite 450
Houston, TX 77070
4420 Arrowswest Drive
Colorado Springs, CO 80907
Minnesota
Minneapolis
Tel: 719.533.7000
Fax: 719.533.7020
8300 Norman Center Drive
Suite 730
Minneapolis, MN 55437
♦ Tel: 612.921.8300
Fax: 612.921.8399
260 Hearst Way
Suite 400
Kanata, ON K2L 3H1
♦ Tel: 613.592.1263
Fax: 613.592.3253
Two Mid American Plaza
Suite 800
Oakbrook Terrace, IL 60181
San Diego
Canada
Ontario
Ottawa
Tel: 281.379.7800
Fax: 281.379.7818
INTERNATIONAL
France
Paris
LSI Logic S.A.
Immeuble Europa
53 bis Avenue de l'Europe
B.P. 139
78148 Velizy-Villacoublay
Cedex, Paris
♦ Tel: 33.1.34.63.13.13
Fax: 33.1.34.63.13.19
Germany
Munich
LSI Logic GmbH
Orleansstrasse 4
81669 Munich
♦ Tel: 49.89.4.58.33.0
Fax: 49.89.4.58.33.108
Stuttgart
Mittlerer Pfad 4
D-70499 Stuttgart
♦ Tel: 49.711.13.96.90
Fax: 49.711.86.61.428
Italy
Milan
LSI Logic S.P.A.
Centro Direzionale Colleoni
Palazzo Orione Ingresso 1
20041 Agrate Brianza, Milano
♦ Tel: 39.039.687371
Fax: 39.039.6057867
Japan
Tokyo
LSI Logic K.K.
Rivage-Shinagawa Bldg. 14F
4-1-8 Kounan
Minato-ku, Tokyo 108-0075
♦ Tel: 81.3.5463.7821
Fax: 81.3.5463.7820
Osaka
Crystal Tower 14F
1-2-27 Shiromi
Chuo-ku, Osaka 540-6014
♦ Tel: 81.6.947.5281
Fax: 81.6.947.5287
Sales Offices and Design
Resource Centers
(Continued)
Korea
Seoul
LSI Logic Corporation of
Korea Ltd
10th Fl., Haesung 1 Bldg.
942, Daechi-dong,
Kangnam-ku, Seoul, 135-283
Tel: 82.2.528.3400
Fax: 82.2.528.2250
The Netherlands
Eindhoven
LSI Logic Europe Ltd
World Trade Center Eindhoven
Building ‘Rijder’
Bogert 26
5612 LZ Eindhoven
Tel: 31.40.265.3580
Fax: 31.40.296.2109
Singapore
Singapore
LSI Logic Pte Ltd
7 Temasek Boulevard
#28-02 Suntec Tower One
Singapore 038987
Tel: 65.334.9061
Fax: 65.334.4749
Sweden
Stockholm
LSI Logic AB
Finlandsgatan 14
164 74 Kista
♦ Tel: 46.8.444.15.00
Fax: 46.8.750.66.47
Taiwan
Taipei
LSI Logic Asia, Inc.
Taiwan Branch
10/F 156 Min Sheng E. Road
Section 3
Taipei, Taiwan R.O.C.
Tel: 886.2.2718.7828
Fax: 886.2.2718.8869
United Kingdom
Bracknell
LSI Logic Europe Ltd
Greenwood House
London Road
Bracknell, Berkshire RG12 2UB
♦ Tel: 44.1344.426544
Fax: 44.1344.481039
♦ Sales Offices with
Design Resource Centers
International Distributors
Australia
New South Wales
Reptechnic Pty Ltd
Hong Kong
Hong Kong
AVT Industrial Ltd
3/36 Bydown Street
Neutral Bay, NSW 2089
Unit 608 Tower 1
Cheung Sha Wan Plaza
833 Cheung Sha Wan Road
Kowloon, Hong Kong
♦ Tel: 612.9953.9844
Fax: 612.9953.9683
Belgium
Acal nv/sa
Lozenberg 4
1932 Zaventem
Tel: 32.2.7205983
Fax: 32.2.7251014
China
Beijing
LSI Logic International
Services Inc.
Beijing Representative
Office
Room 708
Canway Building
66 Nan Li Shi Lu
Xicheng District
Beijing 100045, China
Tel: 86.10.6804.2534 to 38
Fax: 86.10.6804.2521
France
Rungis Cedex
Azzurri Technology France
22 Rue Saarinen
Sillic 274
94578 Rungis Cedex
Tel: 33.1.41806310
Fax: 33.1.41730340
Germany
Haar
EBV Elektronik
Tel: 852.2428.0008
Fax: 852.2401.2105
Serial System (HK) Ltd
2301 Nanyang Plaza
57 Hung To Road, Kwun Tong
Kowloon, Hong Kong
Tel: 852.2995.7538
Fax: 852.2950.0386
India
Bangalore
Spike Technologies India
Private Ltd
951, Vijayalakshmi Complex,
2nd Floor, 24th Main,
J P Nagar II Phase,
Bangalore, India 560078
♦ Tel: 91.80.664.5530
Fax: 91.80.664.9748
Macnica Corporation
Tel: 44.1628.826826
Fax: 44.1628.829730
Hakusan High-Tech Park
1-22-2 Hadusan, Midori-Ku,
Yokohama-City, 226-8505
Milton Keynes
Ingram Micro (UK) Ltd
Tel: 81.45.939.6140
Fax: 81.45.939.6141
The Netherlands
Eindhoven
Acal Nederland b.v.
Japan
Tokyo
Daito Electron
Tel: 49.89.4600980
Fax: 49.89.46009840
Munich
Avnet Emg GmbH
Global Electronics
Corporation
Stahlgruberring 12
81829 Munich
Nichibei Time24 Bldg. 35 Tansu-cho
Shinjuku-ku, Tokyo 162-0833
Tel: 49.89.45110102
Fax: 49.89.42.27.75
Tel: 81.3.3260.1411
Fax: 81.3.3260.7100
Technical Center
Tel: 81.471.43.8200
Tel: 81.3.5778.8662
Fax: 81.3.5778.8669
Shinki Electronics
Myuru Daikanyama 3F
3-7-3 Ebisu Minami
Shibuya-ku, Tokyo 150-0022
Tel: 81.3.3760.3110
Fax: 81.3.3760.3101
Tel: 44.1908.260422
Swindon
EBV Elektronik
Tel: 31.40.2.502602
Fax: 31.40.2.510255
12 Interface Business Park
Bincknoll Lane
Wootton Bassett,
Swindon, Wiltshire SN4 8SY
Switzerland
Brugg
LSI Logic Sulzer AG
Mattenstrasse 6a
CH 2555 Brugg
14F, No. 145,
Sec. 2, Chien Kuo N. Road
Taipei, Taiwan, R.O.C.
Tel: 886.2.2516.7303
Fax: 886.2.2505.7391
Lumax International
Corporation, Ltd
7th Fl., 52, Sec. 3
Nan-Kang Road
Taipei, Taiwan, R.O.C.
Tel: 886.2.2788.3656
Fax: 886.2.2788.3568
Prospect Technology
Corporation, Ltd
4Fl., No. 34, Chu Luen Street
Taipei, Taiwan, R.O.C.
Tel: 886.2.2721.9533
Fax: 886.2.2773.3756
Marubeni Solutions
1-26-20 Higashi
Shibuya-ku, Tokyo 150-0001
Garamonde Drive
Wymbush
Milton Keynes
Buckinghamshire MK8 8DF
Beatrix de Rijkweg 8
5657 EG Eindhoven
Taiwan
Taipei
Avnet-Mercuries
Corporation, Ltd
Tel: 81.3.3264.0326
Fax: 81.3.3261.3984
Tel: 49.2957.79.1692
Fax: 49.2957.79.9341
16 Grove Park Business Estate
Waltham Road
White Waltham
Maidenhead, Berkshire SL6 3LW
11 Rozanis Street
P.O. Box 39300
Tel Aviv 61392
Tel: 972.3.6458777
Fax: 972.3.6458666
United Kingdom
Maidenhead
Azzurri Technology Ltd
Tel: 81.45.474.9037
Fax: 81.45.474.9065
Tel: 41.32.3743232
Fax: 41.32.3743233
Sogo Kojimachi No.3 Bldg
1-6 Kojimachi
Chiyoda-ku, Tokyo 102-8730
Graf-Zepplin-Str 14
D-33181 Wuennenberg-Haaren
2-15-10 Shin Yokohama
Kohoku-ku
Yokohama-City, 222-8580
Israel
Tel Aviv
Eastronics Ltd
Hans-Pinsel Str. 4
D-85540 Haar
Wuennenberg-Haaren
Peacock AG
Yokohama-City
Innotech
Wintech Microeletronics
Co., Ltd
7F., No. 34, Sec. 3, Pateh Road
Taipei, Taiwan, R.O.C.
Tel: 886.2.2579.5858
Fax: 886.2.2570.3123
Tel: 44.1793.849933
Fax: 44.1793.859555
♦ Sales Offices with
Design Resource Centers