TECHNICAL MANUAL LSI53C1510 I2O-Ready PCI RAID Ultra2 SCSI Controller Version 2.2 April 2001 ® S14024.B This document contains proprietary information of LSI Logic Corporation. The information contained herein is not to be used by or disclosed to third parties without the express written permission of an officer of LSI Logic Corporation. LSI Logic products are not intended for use in life-support appliances, devices, or systems. Use of any LSI Logic product in such applications without written consent of the appropriate LSI Logic officer is prohibited. Document DB14-000101-02, Fourth Edition (April 2001) This document describes the LSI Logic LSI53C1510 I2O-Ready PCI RAID Ultra2 SCSI Controller and will remain the official reference source for all revisions/releases of this product until rescinded by an update. To receive product literature, visit us at http://www.lsilogic.com. LSI Logic Corporation reserves the right to make changes to any products herein at any time without notice. LSI Logic does not assume any responsibility or liability arising out of the application or use of any product described herein, except as expressly agreed to in writing by LSI Logic; nor does the purchase or use of a product from LSI Logic convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of LSI Logic or third parties. Ultra SCSI is the term used by the SCSI Trade Association (STA) to describe Fast-20 SCSI, as documented in the SCSI-3 Fast-20 Parallel Interface standard, X3.277-199X. Ultra2 SCSI is the term used by the SCSI Trade Association (STA) to describe Fast-40 SCSI, as documented in the SCSI Parallel Interface–2 standard, (SPI–2) X3T10/1142D. Copyright © 1998–2001 by LSI Logic Corporation. All rights reserved. TRADEMARK ACKNOWLEDGMENT The LSI Logic logo design, TolerANT, SDMS, SCRIPTS, SYMplicity, and LVDlink are registered trademarks or trademarks of LSI Logic Corporation. ARM is a registered trademark of Advanced RISC Machines Limited, used under license. All other brand and product names may be trademarks of their respective companies. SR ii Preface This book is the primary reference and technical manual for the LSI Logic Corporation LSI53C1510 I2O-Ready PCI RAID Ultra2 SCSI Controller. It contains a complete functional description for the product and includes complete physical and electrical specifications. This technical manual assumes the user is familiar with the current and proposed standards for SCSI and PCI. For additional background information on these topics, please refer to the list of reference materials provided in the Related Publications list. Audience This document was prepared for system designers and programmers who are using this device to design an Ultra2 SCSI port for PCI-based personal computers, workstations, servers or embedded applications. Organization This document has the following chapters and appendix: • Chapter 1, Introduction, provides a general overview about the LSI53C1510. • Chapter 2, Functional Description, describes the main functional areas of the chip in more detail, including the interfaces to the SCSI bus and external memory. • Chapter 3, Software Description, describes the software features, firmware features, and hardware requirements. • Chapter 4, Signal Descriptions, contains the pin configuration signal definitions. Preface iii • Chapter 5, Registers (Nonintelligent Mode), describes the PCI and host interface registers that are visible to the host in nonintelligent mode. • Chapter 6, Registers (Intelligent Mode), describes the PCI and host interface registers that are visible to the host in intelligent mode. • Chapter 7, Specifications, contains the electrical characteristics and AC timing diagrams. • Appendix A, Register Summary, is a register summary. Related Publications For background please contact: ANSI 11 West 42nd Street New York, NY 10036 (212) 642-4900 Ask for document number X3.131-199X (SCSI-2) Global Engineering Documents 15 Inverness Way East Englewood, CO 80112 (800) 854-7179 or (303) 397-7956 (outside U.S.) FAX (303) 397-2740 Ask for document number X3.131-1994 (SCSI-2) or X3.253 (SCSI-3 Parallel Interface) ENDL Publications 14426 Black Walnut Court Saratoga, CA 95070 (408) 867-6642 Document names: SCSI Bench Reference, SCSI Encyclopedia, SCSI Tutor Prentice Hall 113 Sylvan Avenue Englewood Cliffs, NJ 07632 (800) 947-7700 Ask for document number ISBN 0-13-796855-8, SCSI: Understanding the Small Computer System Interface iv Preface LSI Logic World Wide Web Home Page www.lsil.com PCI Special Interest Group 2575 N. E. Katherine Hillsboro, OR 97214 (800) 433-5177; (503) 693-6232 (International); FAX (503) 693-8344 I2O (Intelligent Input/Output) SIG Web Site http:\\www.i2osig.org LSI53C1510 I2O-Ready PCI RAID Ultra2 SCSI Controller Programming Guide SCSI SCRIPTS Processors Programming Guide, Order Number S14044.A LSI53C896 PCI to Dual Channel Ultra2 SCSI Multifunction Controller Technical Manual, Order Number S14015.B Conventions Used in This Manual The word assert means to drive a signal true or active. The word deassert means to drive a signal false or inactive. Hexadecimal numbers are indicated by the prefix “0x” —for example, 0x32CF. Binary numbers are indicated by the prefix “0b” —for example, 0b0011.0010.1100.1111. Preface v Revision Record Revision Date Remarks 0.1 3/98 First Draft. 0.2 4/98 Second Draft. 1.0 5/98 Preliminary. 1.1 5/98 Preliminary. Change bars mark all changes. In Chapter 7, all GPIO0_FETCH/ and GPIO1_MASTER/ items were deleted. 2.0 1/00 Final Version. 2.1 11/00 Updated Table 7.2 Operating Conditions. All product names changed from SYM to LSI. 2.2 4/01 Updated DC electrical specifications and test conditions. vi Preface Contents Chapter 1 Introduction 1.1 General Description 1.1.1 Block Diagram 1.2 Module Overviews 1.2.1 PCI Interface 1.2.2 Memory Controller 1.2.3 I2O Message Unit 1.2.4 ARM7TDMI RISC Processor 1.2.5 RAID Parity Assist Engine (PAE) 1.2.6 SCSI Cores 1.3 LSI53C1510 Features 1.3.1 Features List 1.4 LSI53C1510 Benefits 1.4.1 Ultra2 SCSI Benefits 1.4.2 LVDlink™ Benefits 1.4.3 TolerANT® Technology Benefits 1.4.4 I2O Benefits 1.4.5 PAE Benefits 1.4.6 ARM7TDMI RISC Processor Benefits 1.5 LSI53C1510 Benefits Summary 1.5.1 PCI Performance 1.5.2 SCSI Performance 1.5.3 RAID Performance 1.5.4 Testability 1.5.5 Integration 1.5.6 Reliability 1.6 Applications 1.6.1 Embedded Motherboard Application 1.6.2 Host Adapter Board Application Contents 1-1 1-2 1-3 1-3 1-3 1-3 1-4 1-4 1-4 1-4 1-5 1-5 1-5 1-6 1-6 1-7 1-7 1-8 1-8 1-8 1-8 1-9 1-9 1-10 1-10 1-11 1-11 1-12 vii Chapter 2 Chapter 3 viii Functional Description 2.1 Modes of Operation 2.1.1 LSI53C1510 Overview 2.1.2 Configuration and Initialization 2.1.3 I2O Overview 2.1.4 I2O Conceptual Overview 2.1.5 I2O Benefits 2.1.6 The I2O Communications Model 2.1.7 Operational Overview 2.1.8 System Interface 2.2 The Host Interface 2.2.1 Messages 2.2.2 Message Transport 2.2.3 Request Message 2.2.4 Reply Message 2.3 LSI53C1510 Protocol Engine 2.3.1 Random Block Storage Class 2.4 Support Components 2.4.1 DRAM Memory 2.4.2 Flash ROM 2.4.3 Serial EEPROM Software Description 3.1 PCI RAID Software Solutions 3.1.1 PCI RAID 3.1.2 SYMplicity Storage Manager 3.1.3 Wind River Systems’ IxWorks RTOS 3.2 Management Software Features 3.3 RAID Firmware Features 3.3.1 RAID Levels 0, 1, 3, 5, and 10 3.3.2 Caching 3.3.3 Runs in Optimal and Degraded Mode 3.3.4 Hardware Assisted Parity Calculation 3.3.5 Tagged Command Queuing 3.3.6 Global Hot Spare Drives 3.3.7 Hot Swap Drive with Automatic, Transparent Reconstruction Contents 2-2 2-3 2-4 2-6 2-6 2-7 2-8 2-8 2-8 2-11 2-11 2-11 2-12 2-14 2-16 2-16 2-18 2-19 2-19 2-19 3-1 3-1 3-2 3-3 3-3 3-3 3-4 3-5 3-5 3-6 3-6 3-6 3-7 3.4 3.5 Chapter 4 3.3.8 Variable Stripe Size 3.3.9 Online Dynamic Capacity Expansion 3.3.10 Online RAID Level Migration/Reconfiguration 3.3.11 Battery Backup Support and Cache Recovery 3.3.12 Supports SAF-TE SDMS Software Memory Requirements Signal Descriptions 4.1 Signal Groupings 4.2 PCI Interface Signals 4.2.1 System Signals 4.2.2 Address and Data Signals 4.2.3 Interface Control Signals 4.2.4 Arbitration Signals 4.2.5 Interrupt Signals 4.2.6 ARM Signal 4.2.7 Error Recording Signals 4.2.8 Power Management Signal 4.2.9 GPIO Interface Signals 4.3 SCSI Interface Signals 4.3.1 SCSI Clock Signal 4.3.2 SCSI A-Channel Interface Signals 4.3.3 SCSI B-Channel Interface Signals 4.4 Memory Interface Signals 4.4.1 ROM/SRAM Interface Signals 4.4.2 SCAN Signals 4.4.3 DRAM Interface Signals 4.5 Miscellaneous Interface Signals 4.5.1 UART Interface Signals 4.5.2 JTAG Interface Signals 4.5.3 ARM Debug Interface Signals 4.5.4 RAID Interface Signal 4.5.5 Power and Ground Signals Contents 3-7 3-7 3-7 3-8 3-8 3-8 3-8 4-2 4-4 4-4 4-5 4-6 4-7 4-7 4-8 4-8 4-8 4-9 4-10 4-10 4-10 4-13 4-15 4-15 4-16 4-17 4-18 4-18 4-18 4-19 4-19 4-20 ix Chapter 5 Chapter 6 Chapter 7 Appendix A Registers (Nonintelligent Mode) 5.1 PCI Functional Description (Nonintelligent Mode) 5.1.1 PCI Addressing 5.1.2 PCI Bus Commands and Functions Supported 5.1.3 Internal Arbiter 5.1.4 PCI Cache Mode 5.2 PCI Configuration Registers (Nonintelligent Mode) 5.3 Differences from the LSI53C895 and the LSI53C896 5-3 5-3 5-5 5-9 5-9 5-10 5-26 Registers (Intelligent Mode) 6.1 Programming Models 6.1.1 System Programming Model 6.1.2 Local Programming Model 6.2 PCI Configuration Registers (Intelligent Mode) 6.3 Host Interface Registers (Intelligent Mode) 6.4 Shared Memory 6-3 6-3 6-3 6-4 6-19 6-27 Specifications 7.1 DC Characteristics 7.2 TolerANT Technology Electrical Characteristics 7.3 AC Characteristics 7.4 PCI and External Memory Interface Timing Diagrams 7.4.1 Target Timing 7.4.2 Initiator Timing 7.4.3 External Memory Timing 7.5 SCSI Timing Diagrams 7.6 Pinouts and Packaging 7-1 7-7 7-11 7-14 7-14 7-20 7-31 7-36 7-43 Register Summary Index Customer Feedback x Contents Figures 1.1 1.2 1.3 2.1 2.2 2.3 2.4 2.5 2.6 4.1 5.1 6.1 6.2 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 7.16 7.17 7.18 7.19 7.20 7.21 7.22 7.23 LSI53C1510 Block Diagram Typical LSI53C1510 Mainboard Applications Typical LSI53C1510 Host Adapter Board Application LSI53C1510 Block Diagram Example of LSI53C1510 Physical Configurations Hardware Messaging Unit LSI53C1510 Request Message Transport LSI53C1510 Reply Message Transport Typical Implementations LSI53C1510 Functional Signal Groupings LSI53C1510 Block Diagram in Nonintelligent Mode LSI53C1510 Block Diagram in Intelligent Mode Shared Memory Address Translation LVD Driver LVD Receiver Rise and Fall Time Test Condition SCSI Input Filtering Hysteresis of SCSI Receivers Input Current as a Function of Input Voltage Output Current as a Function of Output Voltage External Clock Reset Input Interrupt Output PCI Configuration Register Read PCI Configuration Register Write Operating Registers/SCRIPTS RAM Read, 32-Bit Operating Registers/SCRIPTS RAM Write, 32-Bit Nonburst Opcode Fetch, 32-Bit Address and Data Burst Opcode Fetch, 32-Bit Address and Data Back-to-Back Read, 32-Bit Address and Data Back-to-Back Write, 32-Bit Address and Data Burst Read, 32-Bit Address and Data Burst Write, 32-Bit Address and Data EDO DRAM Burst Read FLASH ROM Normal Read Only Mode FLASH ROM Program/Verify Mode Contents 1-2 1-11 1-12 2-3 2-7 2-10 2-14 2-15 2-18 4-3 5-2 6-2 6-27 7-3 7-4 7-8 7-8 7-9 7-9 7-10 7-11 7-12 7-13 7-15 7-16 7-17 7-18 7-21 7-23 7-25 7-27 7-29 7-31 7-33 7-34 7-35 xi 7.24 7.25 7.26 7.27 7.28 7.29 7.30 7.31 Initiator Asynchronous Send Initiator Asynchronous Receive Target Asynchronous Send Target Asynchronous Receive Initiator and Target Synchronous Transfer Left Half of the LSI53C1510 388 BGA Chip - Top View LSI53C1510 388 Ball Grid Array 388 PBGA (II) Mechanical Drawing 7-36 7-37 7-38 7-38 7-42 7-44 7-48 7-49 2.1 2.2 2.3 2.4 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12 4.13 4.14 4.15 4.16 4.17 4.18 4.19 4.20 4.21 5.1 5.2 LSI53C1510 Modes ROM Size Configurations Configuration Options Supported Random Block Storage Messages Pin Type Description System Signals Address and Data Signals Interface Control Signals Arbitration Signals Interrupt Signals ARM Signal Error Recording Signals Power Management Signal GPIO Interface Signals SCSI Clock Signal SCSI A-Channel Interface Signals SCSI B-Channel Interface Signals ROM/SRAM Interface Signals SCAN Signals DRAM Interface Signals UART Interface Signals JTAG Interface Signals ARM Debug Interface Signals RAID Interface Signal Power and Ground Signals PCI Bus Commands Encoding PCI Configuration Register Map 2-2 2-5 2-5 2-17 4-1 4-4 4-5 4-6 4-7 4-7 4-8 4-8 4-8 4-9 4-10 4-10 4-13 4-15 4-16 4-17 4-18 4-18 4-19 4-19 4-20 5-5 5-10 Tables xii Contents 6.1 6.2 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 7.16 7.17 7.18 7.19 7.20 7.21 7.22 7.23 7.24 7.25 7.26 7.27 PCI Configuration Register Map LSI53C1510 Host Interface Register Map Absolute Maximum Stress Ratings Operating Conditions LVD Driver SCSI Signals—SD[15:0]+, SDP[1:0]/, SREQ/, SACK/, SMSG/, SIO/, SCD/, SATN/, SBSY/, SSEL/, SRST/ LVD Receiver SCSI Signals—SD[15:0]/, SDP[1:0]/, SREQ/, SACK/, SMSG/, SIO/, SCD/, SATN/, SBSY/, SSEL/, SRST/ DIFFSENS SCSI Signal RBIAS SCSI Signal Input Capacitance Bidirectional Signals—GPIO0, GPIO1, GPIO2, GPIO3, GPIO4 Output Signals—MCE/, MOE/_TESTOUT, MWE/, TDO Bidirectional Signals—AD[31:0], C_BE[7:0]/, FRAME/, IRDY/, TRDY/, DEVSEL/, STOP/, PERR/, PAR Input Signals—CLK, GNT/, IDSEL, RST/, SCLK, TCK, TDI, TEST_HSC, TEST_RSTN, TMS Output Signals—INTA, INTB Output Signal—SERR/ TolerANT Technology Electrical Characteristics for SE SCSI Signals External Clock Reset Input Interrupt Output PCI Configuration Register Read PCI Configuration Register Write Operating Registers/SCRIPTS RAM Read, 32-Bit Operating Registers/SCRIPTS RAM Write, 32-Bit Nonburst Opcode Fetch, 32-Bit Address and Data Burst Opcode Fetch, 32-Bit Address and Data Back-to-Back Read, 32-Bit Address and Data Back-to-Back Write, 32-Bit Address and Data Burst Read, 32-Bit Address and Data Burst Write, 32-Bit Address and Data Contents 6-4 6-19 7-2 7-2 7-3 7-3 7-4 7-4 7-4 7-5 7-5 7-5 7-6 7-6 7-6 7-7 7-11 7-12 7-13 7-15 7-16 7-17 7-18 7-20 7-22 7-24 7-26 7-28 7-30 xiii 7.28 7.29 7.30 7.31 7.32 7.33 7.34 7.35 7.36 7.37 7.38 7.39 7.40 7.41 A.1 A.2 A.3 xiv DRAM Timing Parameters (Using 50 ns Extended Data Out Mode) Initiator Asynchronous Send Initiator Asynchronous Receive Target Asynchronous Send Target Asynchronous Receive SCSI-1 Transfers (SE 5.0 Mbytes) SCSI-1 Transfers (Differential 4.17 Mbytes) SCSI-2 Fast Transfers 10.0 Mbytes (8-Bit transfers) or 20.0 Mbytes (16-Bit transfers) 40 MHz Clock SCSI-2 Fast Transfers 10.0 Mbytes (8-Bit Transfers) or 20.0 Mbytes (16-Bit Transfers) 50 MHz Clock Ultra SCSI SE Transfers 20.0 Mbytes (8-Bit Transfers) or 40.0 Mbytes (16-Bit Transfers) Quadrupled 40 MHz Clock Ultra SCSI HVD Transfers 20.0 Mbytes (8-Bit Transfers) or 40.0 Mbytes (16-Bit Transfers) 80 MHz Clock Ultra2 SCSI Transfers 40.0 Mbytes (8-Bit Transfers) or 80.0 Mbytes (16-Bit Transfers) Quadrupled 40 MHz Clock Signal Names and BGA Position Signal Names By BGA Position LSI53C1510 PCI Registers (Nonintelligent Mode) Register Map LSI53C1510 PCI Registers (Intelligent Mode) Register Map LSI53C1510 Host Interface Registers (Intelligent Mode) Contents 7-32 7-36 7-37 7-38 7-38 7-39 7-39 7-40 7-40 7-41 7-41 7-42 7-46 7-47 A-1 A-2 A-4 Chapter 1 Introduction This chapter provides a general overview of the LSI53C1510 I2O-Ready PCI RAID Ultra2 SCSI Controller. The chapter contains the following sections: • Section 1.1, “General Description,” page 1-1 • Section 1.2, “Module Overviews,” page 1-3 • Section 1.3, “LSI53C1510 Features,” page 1-4 • Section 1.4, “LSI53C1510 Benefits,” page 1-5 • Section 1.5, “LSI53C1510 Benefits Summary,” page 1-8 • Section 1.6, “Applications,” page 1-11 1.1 General Description The LSI53C1510 is a single chip I2O-Ready PCI RAID Ultra2 SCSI Controller. The LSI53C1510 contains a 32-bit RISC ARM7TDMI Processor and a RAID Parity Assist Engine (PAE). The RISC processor frees the host CPU from the burden of processing I/O requests and reduces the number of I/O interrupts, thus improving system performance. The RISC processor and associated firmware contain the ability to manage an I/O from start to finish without host intervention. The RISC processor manages the Intelligent Input/Output (I2O) message passing interface. LSI53C1510 I2O-Ready PCI RAID Ultra2 SCSI Controller 1-1 The LSI53C1510 has two modes of operation: intelligent or nonintelligent mode. In intelligent mode, the LSI53C1510 functions as an embedded RAID controller on a motherboard or as an add-in RAID host adapter board. In nonintelligent mode the LSI53C1510 functions as a PCI to SCSI dual channel wide Ultra2 controller. The LSI53C1510 is sold as a package with LSI Logic I2O RAID software to provide a RAID solution. Therefore, this manual describes the hardware and software only in enough detail for system intergrators to design the LSI53C1510 onto a motherboard or a host adapter board. The I2O RAID software consists of the LSI Logic I2O RAID Device Driver Module (DDM), SYMplicity™ Storage Manager, and Wind River Systems’ IxWorks RTOS. The LSI53C1510 is a combination of many tried and proven modules. These modules have been proven in single and multimodule configurations. The following block diagram illustrates the major modules of the LSI53C1510. 1.1.1 Block Diagram The LSI53C1510 is a multifunction device composed of many modules. Figure 1.1 is a block diagram of the LSI53C1510. Figure 1.1 LSI53C1510 Block Diagram 32-Bit, 33 MHz PCI Bus 132 Mbytes 160 Mbytes, Memory Interface DRAM PCI Interface SCSI Core 32-Bit Memory Controller Introduction RAID Parity Assist Engine 80 Mbytes Wide Ultra2 SCSI Bus 32-Bit RISC ARM7TDMI Processor DRAM 1-2 I2O Message Unit SCSI Core 80 Mbytes 1.2 Module Overviews This section provides an overview of the six major LSI53C1510 modules, which consist of the PCI Interface, Memory Controller, I2O Messaging Unit, ARM7TDMI RISC Processor, RAID PAE and SCSI Cores. Chapter 2, “Functional Description,” provides a detailed description of the functions of each module. 1.2.1 PCI Interface The PCI interface is a 32-bit, 33 MHz host PCI bus. The PCI interface supports Dual Address Cycle (DAC), PCI Power Management, and Subsystem Vendor ID. The PCI interface also contains a PCI Master and Slave control block, PCI configuration registers, and DMA channel arbitration. This chip supports 64-bit addressing as a PCI master and supports 32-bit addressing as a PCI slave. 1.2.2 Memory Controller The memory controller provides access to Flash ROM, SRAM, and 32-bit EDO DRAM with parity (50 ns access time). It supports two 64 Mbytes (maximum configuration of 128 Mbytes) banks of DRAM. To support the ROM and SRAM, there is a general purpose 8-bit expansion memory bus that supports up to 4 Mbytes Flash ROM. It also supports up to 2 Mbytes of SRAM and is designed to interface efficiently to an external 8 K x 8 battery backed up SRAM. 1.2.3 I2O Message Unit The messaging interface efficiently passes messages between the LSI53C1510 and other I/O agents in an I2O enabled system. The I2O Message Unit consists of the following four hardware FIFOs for the message queuing lists: Request Free, Request Post, Reply Free, and Reply Post. The LSI53C1510 provides control logic for the I2O Message Unit and external local memory provides storage for the messages. Module Overviews 1-3 1.2.4 ARM7TDMI RISC Processor The LSI53C1510 uses an optimized 32-bit ARM7 RISC Processor core to control all RAID functionality. This frees the host CPU for other processing activity and improves I/O performance. The RISC processor and associated firmware contain the ability to manage an I/O from start to finish without host intervention. The RISC processor also manages the I2O message passing I/O interface. 1.2.5 RAID Parity Assist Engine (PAE) The Hardware PAE offloads the parity generation and checking from the host. It allows multiple parity operations to be queued for maximum efficiency. 1.2.6 SCSI Cores The integrated SCSI cores are high-performance dual wide Ultra2 SCSI channels supporting either Single-Ended (SE) or Low Voltage Differential (LVD) SCSI. The cores are based on the popular LSI53C8XX controllers and are capable of up to Ultra2 transfer rates for each channel. 1.3 LSI53C1510 Features The LSI53C1510 integrates a PCI bus master DMA core, two high-performance SCSI cores, and two LSI Logic SCSI SCRIPTS™ processors to meet the broad requirements of Wide Ultra2 SCSI standards. It is designed to implement multithreaded I/O algorithms with a minimum of processor intervention, solving the protocol overhead problems of previous intelligent and nonintelligent controller designs. In nonintelligent mode, the LSI53C1510 is fully supported by the Storage Device Management System (SDMS™), a software package that supports the Advanced SCSI Protocol Interface (ASPI). SDMS software provides BIOS and driver support for hard disk, tape, removable media products, and CD-ROM under the major PC operating systems. 1-4 Introduction In intelligent mode, the LSI53C1510 is a complete, single chip RAID solution for the motherboard—just add memory. The RAID product solution consists of a RAID SYMplicity Storage Manager, SYMplicity I2O RAID firmware with Wind River System IxWorks, and hardware. 1.3.1 Features List • Highly integrated single chip RAID Controller • I2O Messaging Unit • RAID PAE • 32-bit/33 MHz host PCI Bus • – DAC – PCI Power Management – PCI cache commands (MRL, MRM, MWI) Two wide Ultra2 SCSI Channels – SE or LVD SCSI – Based upon the popular LSI53C8XX controller • 32-bit RISC ARM7TDMI Processor • 32-bit Memory Controller – • Up to two banks of 64 Mbytes EDO (50 ns access time) DRAM General purpose 8-bit expansion bus – Supports up to 4 Mbytes ROM – Chip enable to support an external 8 K x 8 battery backed SRAM 1.4 LSI53C1510 Benefits This section provides a description of the major LSI53C1510 benefits. 1.4.1 Ultra2 SCSI Benefits Ultra2 SCSI is an extension of the SPI-2 draft standard that allows faster synchronous SCSI transfer rates and defines a new physical layer, LVD SCSI, that provides an incremental evolution from SCSI-2 and Ultra SCSI. When enabled, Ultra2 SCSI (8-bit) performs transfers of LSI53C1510 Benefits 1-5 40 Mbytes/s, which results in approximately double the synchronous transfer rate of Ultra SCSI. The LSI53C1510 can perform 16-bit (wide), Ultra2 SCSI synchronous transfers as fast as 80 Mbytes/s. This advantage is most noticeable in heavily loaded systems, or large block size applications such as video on-demand and image processing. An advantage of Ultra2 SCSI is that it significantly improves SCSI bandwidth while preserving existing hardware and software investments. 1.4.2 LVDlink™ Benefits The LSI53C1510 supports LVD SCSI, a signaling technology that increases the reliability of SCSI data transfers over longer distances than supported by SE SCSI. The low current output of LVD allows the I/O transceivers to be integrated directly onto the chip. LVD provides the reliability of High Voltage Differential (HVD) SCSI without the added cost of external differential transceivers. Ultra2 SCSI with LVD allows a longer SCSI cable and more devices on the bus, with the same cables defined in the SCSI-3 parallel interface standard for Fast-20 (Ultra SCSI). LVD provides a long-term migration path to even faster SCSI transfer rates without compromising signal integrity, cable length, or connectivity. For backward compatibility to existing SE devices, the LSI53C1510 features universal LVDlink transceivers that can switch between LVD SCSI and SE modes. The LVDlink technology also supports high power differential signaling in legacy systems, when external transceivers are connected to the LSI53C1510. This allows the LSI53C1510 to be used in both legacy and Ultra2 SCSI applications. 1.4.3 TolerANT® Technology Benefits The LSI53C1510 features TolerANT technology, which includes active negation on the SCSI drivers and input signal filtering on the SCSI receivers. Through active negation, the SCSI Request, Acknowledge, Data, and Parity signals are actively driven high rather than passively pulled up by terminators. Active negation is enabled by setting bit 7 in the STEST3 register. TolerANT receiver technology improves data integrity in unreliable cabling environments, where other devices are subject to data corruption. TolerANT receivers filter the SCSI bus signals to eliminate unwanted transitions, without the long signal delay associated with RC-type input 1-6 Introduction filters. This improved driver and receiver technology helps eliminate double clocking of data, the single biggest reliability issue with SCSI operations. TolerANT input signal filtering is a built-in feature of the LSI53C1510 and all LSI Logic fast SCSI, Ultra SCSI, and Ultra2 SCSI devices. The benefits of TolerANT technology include increased immunity to noise on the deasserting signal edge, better performance due to balanced duty cycles, and improved Ultra2 SCSI transfer rates. In addition, TolerANT SCSI devices do not cause glitches on the SCSI bus at power-up or power-down, so other devices on the bus are also protected from data corruption. TolerANT technology is compatible with both the Alternative One and Alternative Two termination schemes proposed by the American National Standards Institute. 1.4.4 I2O Benefits The I2O-ready design of the LSI53C1510 improves system performance by reducing interrupts to the host CPU and minimizing PCI bandwidth through the packetized mailbox interface. These features are particularly important in high-performance symmetric multiprocessing servers and clustered computing systems. The benefits of the I2O architecture fully compliment those of SCSI and include reduced host CPU I/O overhead for better system performance, improved scalability, reduced time to market for new I/O technology, reduced cost of integration and support for I/O. 1.4.5 PAE Benefits When the LSI53C1510 is in intelligent mode, the embedded PAE works with RAID applications to perform parity generation or checking as requested. The PAE writes any generated parity data block back into local memory. The hardware PAE offloads the parity generation and checking from the host and it generates parity faster than software applications. The PAE allows multiple parity operations to be queued for maximum efficiency. This frees the host CPU for other processing activity and improves I/O performance. LSI53C1510 Benefits 1-7 1.4.6 ARM7TDMI RISC Processor Benefits The ARM processor manages the I2O message passing I/O interface. The embedded RISC processor (ARM7TDMI) improves system performance by reducing interrupts to the host CPU and minimizing PCI bandwidth. The ARM processor and associated software contain the ability to manage an I/O from start to finish without host intervention. This frees the host CPU for other processing activity and improves I/O performance. 1.5 LSI53C1510 Benefits Summary This section provides a summary of the PCI, SCSI, and RAID performance benefits. It also provides a summary of the Testability, Integration, and Reliability benefits. 1.5.1 PCI Performance • Fully PCI 2.1 Specification compliant • True multifunction device as defined in PCI 2.1 Specification in nonintelligent mode and it presents only one load to the PCI bus • Supports 32-bit word data bursts with variable burst lengths of 2, 4, 8, 16, 32, 64 or 128 Dwords across the PCI bus • Prefetches up to 8 Dwords of SCSI SCRIPTS • Performs zero wait-state bus master data bursts at 132 Mbytes/s (@ 33 MHz) • Supports PCI Cache Line Size register • Supports PCI Memory Write and Invalidate, Memory Read Line, and Memory Read Multiple commands 1.5.2 SCSI Performance 1-8 • Includes 4 Kbytes internal RAM on each SCSI channel for SCRIPTS instruction storage, thus reducing PCI bus utilization • Wide Ultra SCSI SE Interface • Performs Wide Ultra2 SCSI synchronous transfers as fast as 80 Mbytes/s with LVD Introduction • 816-byte DMA FIFO for more effective PCI and SCSI bus utilization • SCSI synchronous offset of 31 levels for maximum performance in long cable situations • Supports variable block size and scatter/gather data transfers • Minimizes SCSI I/O start latency • Performs complex bus sequences without interrupts, including restore data pointers • Reduces ISR overhead through a unique interrupt status reporting method • Load/Store SCRIPTS instruction increases performance of data transfers to and from chip registers • Supports target disconnect and later reconnect with no interrupt to the system processor • Supports multithreaded I/O algorithms in SCSI SCRIPTS with fast I/O context switching • Expanded register Move instruction support • Software (drivers and SCRIPTS) compatible with LSI53C8XX • Integrated clock quadrupler enables Ultra2 SCSI with 40 MHz SCSI clock input 1.5.3 RAID Performance • Maximum transfer rate: 80 Mbytes/s with Wide Ultra2 SCSI • Number of drives: 30 maximum (10 to 15 drives in typical application) • Supports RAID levels 0, 1, 3, 5, 10 and JBOD 1.5.4 Testability • Access to all SCSI signals through programmed I/O • SCSI loopback diagnostics • SCSI bus signal continuity checking • Single-step mode operation LSI53C1510 Benefits Summary 1-9 1.5.5 Integration • Dual Channel SCSI Multifunction Controller • 3.3 V/5 V PCI interface • Full 32-bit PCI DMA bus master • High-performance SCSI cores • Integrated SCSI SCRIPTS processors • ARM7TDMI 32-bit RISC processor • RAID PAE • I2O Message Unit 1.5.6 Reliability 1-10 • 2 kV ESD protection on SCSI signals • Typical 300 mV SCSI bus hysteresis • Protection against bus reflections due to impedance mismatches • Controlled bus assertion times (reduces RFI, improves reliability, and eases FCC certification) • Latch-up protection greater than 150 mA • Voltage feed-through protection (minimum leakage current through SCSI pads) • Power and ground isolation of I/O pads and internal chip logic • TolerANT technology provides: – Active negation of SCSI Data, Parity, Request, and Acknowledge signals for improved fast SCSI transfer rates – Input signal filtering on SCSI receivers improves data integrity, even in noisy cabling environments Introduction 1.6 Applications There are many different applications and configurations for the LSI53C1510 I2O-Ready PCI RAID Ultra2 SCSI Controller. Figure 1.2 illustrates a typical LSI53C1510 embedded motherboard application. Figure 1.3 illustrates a typical LSI53C1510 host adapter board application. Figure 1.2 Host PCI Bridge Typical LSI53C1510 Mainboard Applications 32-bit, 33 MHz Primary PCI Bus LSI53C1510 PCI to SCSI I2O-Ready RAID Controller EDO DRAM w/parity (8–128 Mbyte) Flash (Up to 4 Mbyte) 8 Kbyte Battery Backed SRAM w/RTC SCSI A SCSI B Ultra2 SCSI Bus 1.6.1 Embedded Motherboard Application The LSI53C1510 is ideally suited for embedded motherboard RAID applications. The amount of motherboard space required to implement such an application is critical. The limited space available on the motherboard dictates a highly integrated solution like the LSI53C1510. All of the major functional blocks of RAID controller including processor, memory controller, XOR engine, and SCSI controllers are integrated into the LSI53C1510. This greatly reduces the amount of board space Applications 1-11 required to implement a RAID controller. Not only does this make RAID on the motherboard a viable solution, it also greatly reduces the cost of implementing it. Because the LSI53C1510 supports both RAID and non-RAID operational modes, it gives the motherboard designer the option of building a base motherboard that uses the LSI53C1510 as a dual channel Ultra2 SCSI controller. The additional memory and real time clock required for RAID operation can then be provided on an optional RAID upgrade card that plugs into a connector mounted on the motherboard. Figure 1.3 Typical LSI53C1510 Host Adapter Board Application 68-pin High Density 68-pin High Density Ultra2 SCSI Bus VHDCI Auto Term Flash (2 to 4 Mbyte) Ultra2 SCSI Bus VHDCI Battery Backed SRAM (8 K x 8) w/RTC Auto Term LSI53C1510 PCI to SCSI I2O-Ready RAID Controller Clock NVRAM EDO DRAM w/parity (8 to 128 Mbyte) Memory Back-up 32-bit, 33 MHz PCI Bus 1.6.2 Host Adapter Board Application The LSI53C1510 single chip RAID solution can be designed on an add-in host adapter card. This provides a highly scalable solution where additional storage and/or performance can be obtained by adding additional host adapter cards. 1-12 Introduction Chapter 2 Functional Description The chapter contains the following sections: • Section 2.1, “Modes of Operation,” page 2-2 • Section 2.2, “The Host Interface,” page 2-11 • Section 2.3, “LSI53C1510 Protocol Engine,” page 2-16 • Section 2.4, “Support Components,” page 2-18 The LSI53C1510 contains an ARM7 32-bit RISC Processor, a RAID PAE, and a DMA engine. The RISC processor frees the host CPU for other processing activity and improves performance. The RISC processor and associated software contain the ability to manage an I/O from start to finish without host intervention. The RISC processor also manages the I2O message passing I/O interface. The DMA engine moves blocks of data between system memory and the LSI53C1510 local memory. The LSI53C1510 uses a 32-bit PCI interface for communication with the host CPUs and system memory. The host interface to the LSI53C1510 is designed to minimize the amount of PCI bandwidth required to support I/O requests. A packetized message passing I/O interface is used to reduce the number of single cycle PCI bus cycles. All data traffic across the PCI bus occurs with zero wait-state bursts. The intelligent LSI53C1510 architecture allows the host to specify I/Os at a very high level. Complete SCSI functionality is provided in the LSI53C1510, relieving the host CPU(s) from managing I/Os. LSI53C1510 I2O-Ready PCI RAID Ultra2 SCSI Controller 2-1 2.1 Modes of Operation The LSI53C1510 has two modes of operation: intelligent or nonintelligent mode. In intelligent mode, the LSI53C1510 functions as an embedded RAID controller on a motherboard or as an add-in RAID host adapter board. In nonintelligent mode the LSI53C1510 functions as a PCI to SCSI dual channel wide Ultra2 controller. These modes are entered during the initialization of the LSI53C1510 on power-up. The presence or absence of external memory determines which mode is entered. In intelligent mode, the LSI53C1510 uses its built-in ARM processor. In nonintelligent mode, the ARM processor is disabled. Table 2.1 shows the LSI53C1510 modes of operation. Table 2.1 LSI53C1510 Modes Modes 2-2 External Memory Configurations Intelligent I2O RAID Controller Yes RAID Nonintelligent Dual Channel Controller No Dual Channel Wide Ultra2 SCSI Controller Functional Description 2.1.1 LSI53C1510 Overview Figure 2.1 LSI53C1510 Block Diagram Host PCI Bus (32-bit, 33 MHz) PCI Master and Slave Control Block, PCI Configuration Registers (1/2 sets), and DMA Channel Arbitration Ultra2 SCSI Controller 8 Dword SCRIPTS Prefetch Buffer 816 Byte DMA FIFO Buffer I2O Msg Unit DMA Slave Buffer 4 Kbyte SCRIPTS RAM SCSI SCRIPTS Processor Ultra2 SCSI Controller 4 Kbyte SCRIPTS RAM 8 Kbyte ARM Instruction/ Data Buffer Operating Registers Serial EEPROM and AutoConfiguration SCSI FIFO and SCSI Control Block ARM RISC Processor Internal Module Bus Parity Assist Engine LVDlink Drivers and Receivers Flash ROM Memory Control 816 Byte DMA FIFO 8 Dword SCRIPTS Prefetch Buffer SCSI SCRIPTS Processor Operating Registers SCSI FIFO and SCSI Control Block DRAM Engine LVDlink Drivers and Receivers JTAG Wide Ultra2 SCSI Bus (A Channel) JTAG ARM Debug 2-Wire Serial EEPROM Bus External Interrupt Pin Wide Ultra2 SCSI Bus (B Channel) Flash ROM/DRAM Memory Bus Figure 2.1 illustrates the major components of the LSI53C1510 controller. A dual channel PCI interface function block provides slave access steering between the two SCSI cores when operating in nonintelligent mode. The Slave Access and Messaging Unit utilizes a FIFO for fast host system service and for speed matching between the 33 MHz domain of the PCI bus and the 40 MHz clock domain of the memory controller. The DMA unit contains a single data FIFO for both read and write operations. The SCSI cores each contain control registers and 4 Kbytes SCRIPTS RAM. When operating in nonintelligent mode, these are mapped Modes of Operation 2-3 according to the Memory 0 and Memory 1 Base Address registers. When in intelligent mode, the control registers are mapped into Memory 0 Base Address registers. The PAE accesses data and parity in the LSI53C1510 local memory and performs XOR operations to generate parity and data blocks. Multiple sources can be specified for each operation and multiple operations can be queued within the unit. The memory controller includes a 32-bit with parity EDO DRAM interface, plus an 8-bit utility interface supporting SRAM, Flash ROM, plus user-defined external components. 2.1.2 Configuration and Initialization The LSI53C1510 initializes as a nonintelligent dual channel SCSI controller, or as an intelligent I/O Processor (IOP). External pins are sensed at power-on and either nonintelligent mode or intelligent mode is selected. The power-on mode also determines which set of PCI configuration register values will be used. When in nonintelligent mode, the LSI53C1510 is a dual function PCI device with two sets of configuration registers. When in intelligent mode, the LSI53C1510 is a single function device with a single set of PCI configuration registers. The MEM_ADDR bus is used to determine power-on configuration. During power-on, internal 25 µA pull-downs are activated. If desired, these pull-downs can be overridden using 10 kΩ external pull-up resistors. This will change the default power-up conditions of the part. Table 2.2 shows the ROM size configurations the eight MEM_ADDR lines generate. The eight MEM_ADDR lines control the following configuration options. Options shown in Table 2.3 are enabled using pull-up resistors. 2-4 Functional Description Table 2.2 ROM Size Configurations MEM_ADDR [3:0] Options 0000 16 Kbytes ROM Size (No external pull-ups) 0001 32 Kbytes ROM Size 0010 64 Kbytes ROM Size 0011 128 Kbytes ROM Size 0100 256 Kbytes ROM Size 0101 512 Kbytes ROM Size 0110 1024 Kbytes ROM Size 0111 2048 Kbytes ROM Size 1000 4096 Kbytes ROM Size 1001–1110 1111 Table 2.3 Reserved No ROM present Configuration Options MEM_ADDR [4:9] Options Bit 4 Disable boot Bit 5 RAID_MODE, based on SIMM/memory population Bit 6 Disables SCSI SCRIPTS RAM Bit 7 Disables EEPROM downloads Bit 8 Reserved Bit 9 Channel B uses INTA instead of INTB Modes of Operation 2-5 2.1.3 I2O Overview When the LSI53C1510 is in intelligent mode, the RISC processor manages the I2O message passing I/O interface. I2O defines a standard architecture for intelligent I/O, where low level interrupts are offloaded from the host CPU to the ARM IOP designed specifically to handle I/O. With support for message passing between multiple independent processors, the I2O architecture relieves the host of interrupt intensive I/O tasks, greatly improving I/O performance in high bandwidth applications such as RAID. I2O imposes no restrictions on where layered modules execute, providing support for single processor, multiprocessor and clustered systems. The I2O specification also defines a “split driver” model for creating drivers that are portable across multiple OSs and host platforms. Through the split driver model, I2O significantly decreases the number of drivers required. OS vendors write a single I2O-ready driver for each class of device, such as SCSI Peripheral Class or Random Block Storage Class. Device manufacturers, like LSI Logic, write a single I2O software program for each device, such as the LSI53C1510, which works for any OS that supports I2O. 2.1.4 I2O Conceptual Overview The split I2O drivers are composed of two parts: the Operating System Services Module (OSM), that resides on and interfaces to the host OS; and the Hardware Device Module (HDM), that resides on and interfaces with the LSI53C1510 adapter to be managed by the driver. The HDM and the Intermediate Service Module (ISM) are often referred to collectively as DDMs. The ISM is a driver an independent software vendor can supply to add value or a specialized function to the LSI53C1510. These modules interface with each other through a communication system comprised of two layers: a Message Layer that sets up a communication session, and a Transport Layer that defines how information will be shared. Much like a standard communications protocol, the Message Layer resides on top of the Transport Layer. 2-6 Functional Description 2.1.5 I2O Benefits The I2O operating environment of the LSI53C1510 provides two main advantages. First, it enables the system vendor, LSI Logic, to create an I/O platform that can support a number of intelligent configurations. The second advantage is the capability of stacked drivers, that enable a third party software vendor to provide value added expansion capability, independent of both the OS and the hardware. Figure 2.2 illustrates various ways the LSI53C1510 can be configured. Figure 2.2 Example of LSI53C1510 Physical Configurations Host System System Bus System Memory LSI53C1510 Disk Drive Disk Drive RISC Processor Disk Drive Disk Drive Other Modules Disk Drive IOP Memory (Shared Memory) Disk Drive Modes of Operation SCSI Channel B SCSI Bus B Disk Drive SCSI Bus A SCSI Channel A Disk Drive Disk Drive 2-7 2.1.6 The I2O Communications Model The communications model for the I2O architecture is a message passing system. The communication model defines how two entities exchange messages by using the Message Layer to set up a connection and exchange data and control. When the OSM is presented with a request from the host OS, it translates the request into an I2O message and dispatches it to the LSI53C1510 for processing. Upon completion of the request, the LSI53C1510 dispatches the result back to the OSM by sending a message through the I2O Message Layer. To the host OS, the OSM appears just like any other device driver. See Section 2.2.1, “Messages,” later in this chapter for more detail. 2.1.7 Operational Overview After power-on, the LSI53C1510 is configured as either a nonintelligent or intelligent controller. In intelligent mode, the LSI53C1510 initializes from local ROM and then issues and responds to I2O messages exchanged with the host system. Messages are decoded into local actions, usually involving the transfer of data. Data may be moved between the host system and the LSI53C1510 local memory through the LSI53C1510’s DMA controller, or by the host system. The two SCSI cores transfer data between disk and local memory or between disk and host system memory. 2.1.8 System Interface The LSI53C1510 architecture features a generic, message passing I/O interface. The LSI53C1510 Protocol Engine provides a set of four hardware FIFOs for Message Queuing between the LSI53C1510 and the primary host (or other hosts and peers). The four FIFOs are: • Request Free List • Request Post List • Reply Free List • Reply Post List These FIFOs are used to manage how/where messages are sent and received. 2-8 Functional Description Control logic for the four hardware FIFOs is provided within the Protocol Engine. Storage for the FIFO entries is provided in external local memory. Each element within each of these FIFOs contains a Message Frame Address (MFA). The MFA is the offset from the first memory base address register (Memory 0 Base Address) where a Message Frame is located (Push model). The number of FIFO elements is configurable. Supported FIFO depths are powers of two between 256 and 4096. In addition to the hardware FIFOs, a region of shared memory is provided (the LSI53C1510 local memory mapped to System Addresses) for the host to write Request Message Frames into. This is the default method (Push model) for Request Message Frame transport, where the host itself copies the Request Message Frame into the LSI53C1510 local memory. To support shared memory access (read/write), the LSI53C1510 Protocol Engine includes a slave burst FIFO (depth of 128 bytes), slave burst logic including address capture and increment, and address translation between System and Local memory addresses. Reply Message Frames are always pushed from the LSI53C1510 Protocol Engine to System memory; the Protocol Engine includes a DMA channel for transferring Reply Message Frames. This DMA channel may also be used for other purposes such as downloading software or uploading trace information. Also present within the Protocol Engine is a System Read/Write interface which provides the ARM processor the ability to read/write a single arbitrary Dword from system memory. See Figure 2.3 for an illustration of the FIFOs and memory in the Protocol Engine and External Memory. 2.1.8.1 LSI53C1510 Protocol Engine Overview The LSI53C1510 Protocol Engine contains an ARM processor core, a local bus and controller, an 8 Kbytes Instruction Cache, an 8 Kbyte Instruction/Data Buffer, an External Memory Controller, an Instruction Prefetch Unit, a write Buffer, an interface to the host system, and a Timer/Control block. The LSI53C1510 Protocol Engine functions as an intelligent IOP. It receives Request Messages from the host CPU, processes them, and sends Reply Messages back to the host. Processing of Request Messages typically involves an I/O transaction; the Protocol Engine and associated software together contain the ability to manage an I/O from start to finish without host intervention. Modes of Operation 2-9 Figure 2.3 Hardware Messaging Unit Protocol Engine PCI Interface External Memory 2-10 Request Free List FIFO Control Request Free List FIFO Data Request Post List FIFO Control Request Post List FIFO Data Reply Free List FIFO Control Reply Free List FIFO Data Reply Post List FIFO Control Reply Post List FIFO Data Slave Burst FIFO Shared Memory (Request Message Frames) Master Burst FIFO Private Memory (Code + Data) Functional Description 2.2 The Host Interface The LSI53C1510 host interface is compliant with the I2O Specification, Revision 1.5. This host interface is a high-performance, packetized, mailbox architecture which leverages intelligence in the LSI53C1510 to minimize traffic on PCI. See http:\\www.i2osig.org on the I2O Special Interest Group (SIG) web site for more information. SYMplicity is the LSI Logic implementation of I2O architecture. There are two basic constructs in I2O. The first construct, the Message, is used to communicate between the host and the LSI53C1510. Messages are moved between the host(s) and the LSI53C1510 using the second construct, a Transport mechanism. 2.2.1 Messages The LSI53C1510 uses Request and Reply Messages to communicate with the host. Request messages are created by the host to “request” an action by the LSI53C1510. Reply messages are used by the LSI53C1510 to send status information back to the host. Request message data structures are 128 bytes in length. The message includes a message header and a payload. The header includes information to uniquely identify the message. The message header information is sophisticated enough to support multiple hosts and targets. The payload may be any one of three different mechanisms to communicate scatter/gather information to the LSI53C1510. 2.2.2 Message Transport Request and Reply Messages reside in preallocated message frames. Message frames may reside in PCI shared memory local to the LSI53C1510 or in host memory. The host selects where the Request and Reply messages are located during the LSI53C1510 initialization. The default, power-up configuration, places Request messages in PCI shared memory local to the LSI53C1510. As an option, the Request messages can reside in host memory. The Reply messages, however, always reside in host memory. The Host Interface 2-11 Pointers that point to the Request and Reply Messages are called MFAs. The LSI53C1510 is responsible for the initialization and management of the MFAs in the default model. The LSI53C1510 includes a set of four FIFOs which are used to track the Request and Reply MFAs. The four FIFOs are: • Request Free List • Request Post List • Reply Free List • Reply Post List Each element within the FIFOs contains the 32-bit MFAs. The Free List FIFO contains MFAs to memory locations which are “free” to be used for new messages. The LSI53C1510 first enters these MFAs into the Request Free List FIFO at initialization. The Host initializes the Reply Free List by writing the MFAs for the Reply messages into the Reply Register. The act of writing to this register pushes the MFA into the FIFO. The Post List FIFOs contain pointers to memory locations which contain new messages. The presence of a MFA in the Post FIFO indicates to the host or to the LSI53C1510 that a message is pending. The depth of the FIFOs determines the number of outstanding Request Messages which may be pending. The total number of outstanding or open I/Os is limited by the number of Request Messages. Therefore, the maximum number of open I/Os is determined by the size or depth of the FIFOs. The depth of the FIFOs in the LSI53C1510 is software configurable, from 256 to 4096, in powers of two. The storage elements for the FIFO are in the local DRAM external to the chip. Therefore, the size of the FIFOs will have an impact on the total amount of DRAM required. See Section 2.4.1, “DRAM Memory,” later in the chapter for more information regarding local DRAM requirements. 2.2.3 Request Message The LSI53C1510 maintains a list of pointers to memory structures. The pool of pointers (MFAs) are stored in the LSI53C1510 Free FIFO. The top FIFO entry is provided to the host driver by reading the LSI53C1510 Request Register. In the default operation, the LSI53C1510 provides MFAs to the LSI53C1510 local memory, mapped as shared memory. The 2-12 Functional Description process of the host writing to shared memory local to the LSI53C1510 is analogous to “pushing” messages down the PCI hierarchy to the LSI53C1510. This process may be referred to as the Push model. Alternatively, the LSI53C1510 may be configured to provide MFAs to memory located on the host. Once configured as such, the LSI53C1510 will “pull” the messages to memory local to the LSI53C1510 using PCI bus master cycles. This process may be referred to as the Pull model. The LSI Logic I2O RAID software uses the Push model. 2.2.3.1 To Send a Request Message Figure 2.4 illustrates the LSI53C1510 Request Message Transport. 1. The host driver reads the LSI53C1510 Request Register to retrieve a pointer to the next available message structure. If the Message structure resides in PCI shared memory local to the LSI53C1510 (the default), the host reads the offset of the Message structure with shared memory. Device drivers may be written to request several pointers through a series of fast back-to-back PCI slave read cycles. If there are no available message structures, Request Register reads return the value of FFFF–0xFFFF. 2. The host driver then builds the Request Message(s) and writes the contents to the available message structure(s). 3. When the Request Message is built, the host driver writes the MFA(s) back to the LSI53C1510 Request Register. This action creates a queued entry in the LSI53C1510 Post FIFO. Host drivers may post several MFAs during fast back-to-back PCI write cycles. 4. The LSI53C1510 Protocol Engine is interrupted on the first post creating a “Request Post FIFO Not Empty” condition. 5. The LSI53C1510 removes all of the MFAs from the Post FIFO. 6. If the LSI53C1510 is operating under the Pull model, then the LSI53C1510 arbitrates for the PCI bus with the intent to copy the Request Message(s) in host memory using burst read cycles to memory local to the LSI53C1510. The LSI53C1510 will immediately start operating on request message(s) already written to local PCI shared memory, if it is operating in the Push model. The Host Interface 2-13 7. Finally, the LSI53C1510 frees the memory associated with the message request by placing the MFA back in the Request Free FIFO. If the operation requested by the Request Message requires a Reply Message from the LSI53C1510 to the host, then a similar message transfer process is initiated (see Section 2.2.4, “Reply Message”). The host driver may choose to poll the Reply Messages or have the LSI53C1510 interrupt on exception conditions. Figure 2.4 LSI53C1510 Request Message Transport MF_1 2 Host Driver MF_2 MF_3 1 MFA_1 1 3 Request Register 3 MFA_2 MFA_1 MFA_2 4 MFA_N MF_N Free FIFO MFA_N 6 REQUEST Message Frames 5 7 Post FIFO LSI53C1510 2.2.4 Reply Message The Reply Queue provided by the LSI53C1510 is managed similarly, except the LSI53C1510 generates the Reply Messages. The host has the responsibility to allocate the Reply Message Pool, and post the MFA of each message frame to the Reply Register. 2.2.4.1 To Send a Reply Message Figure 2.5 illustrates the LSI53C1510 Reply Message Transport. 1. The LSI53C1510 retrieves a MFA to the next free message frame from the Reply Message Free FIFO. 2. The LSI53C1510 then writes the message to the Reply Message frame queue. 2-14 Functional Description 3. When the Reply Message is written into the queue, the LSI53C1510 writes the pointer into the LSI53C1510 Post FIFO. 4. The LSI53C1510 Protocol Engine causes an interrupt to the host when the Reply Message is posted. 5. The host driver reads the Reply Register to retrieve the Reply Message pointer from the Post FIFO. If there are no posted messages when the host reads the Reply Register, the host receives the value FFFF–0xFFFF. 6. The host driver then retrieves the Reply Message. 7. Finally, the host driver writes the MFA (now a free message frame) to the Reply Register. Figure 2.5 LSI53C1510 Reply Message Transport 6 Host Driver MF_1 MF_2 7 MFA_1 MF_3 5 7 5 MFA_2 MFA_1 MFA_2 Reply Register MFA_N MFA_N 4 Free FIFO Post FIFO 3 1 2 MF_N LSI53C1510 REPLY Message Frames 2.2.4.2 The “Push” Model The “Push” model for the data transfer defines the host’s “push” of request messages down to the PCI shared memory local to the LSI53C1510. The location to which the host writes is provided by the Request Free List. The Host Interface 2-15 2.3 LSI53C1510 Protocol Engine The LSI53C1510 provides a Protocol Engine to manage the execution of various I2O protocols. The Protocol Engine offloads the host processor from management of the I2O protocol by providing a higher level of abstraction for the SCSI protocols. This abstraction allows multiple SCSI protocols to operate simultaneously, with no coordination required between the host-based drivers. Each of the abstracted classes of service has well defined Request and Reply Message protocols. The SYMplicity I2O RAID software supports the Random Block Storage Class. This class provides a high level abstraction for random access block-oriented storage devices. 2.3.1 Random Block Storage Class The Random Block Storage Class provides a high level abstraction for random access block-oriented storage media. The class definition abstracts normal I/O operation using a message that consists of the starting logical block address, the number of bytes, the data buffer, the operation code, and the device handle on which to operate. The LSI53C1510 optimizes the request processing by attempting to sort and concatenate different requests, thereby reducing seek and latency time on the drives, and overall command overhead per request. Each request is managed as a single exchange and appropriate error recovery and reporting is provided. Table 2.4 lists the base messages that comprise the Random Block Storage Class message protocol. 2-16 Functional Description Table 2.4 Supported Random Block Storage Messages Function Description BsaBlockRead Read from device to memory BsaBlockReassign Reassign block addresses BsaBlockWrite Write to device from memory BsaBlockWriteVerify Write to device from memory then verify BsaCacheFlush Write dirty cache to media BsaDeviceReset Reset the device BsaMediaFormat Not defined at this time BsaMediaVerify Verify accessibility of data BsaPowerMgt Power Management BsaStatusCheck Check device status In addition to the base messages for each class, the class definitions also provide utility messages to allow for management and configuration of devices. A generic user interface scripting language is used to allow for building generic configuration and management applications. LSI53C1510 Protocol Engine 2-17 2.4 Support Components The memory controller block within the LSI53C1510 provides access to external local memory resources. External memory devices supported include Flash ROM, DRAM, and SRAM. The sections below provide guidance in choosing the support components necessary for a fully functional implementation using the LSI53C1510. A LSI53C1510 typical implementation diagram is shown below in Figure 2.6 for reference. Figure 2.6 Typical Implementations 68-pin High Density 68-pin High Density Ultra2 SCSI Bus VHDCI Auto Term Flash (2 to 4 Mbyte) Ultra2 SCSI Bus VHDCI Auto Term Clock LSI53C1510 PCI to SCSI I2O-Ready RAID Controller NVRAM 32-bit, 33 MHz PCI Bus 2-18 Battery Backed SRAM (8 K x 8) w/RTC Functional Description EDO DRAM w/parity (8 to 128 Mbyte) Memory Backup 2.4.1 DRAM Memory The DRAM memory stores a run time image of the LSI53C1510 software. This memory also provides a data cache for RAID operations. The LSI53C1510 uses a 32-bit demultiplexed memory bus to access the DRAM. This memory bus has the capability to address up to 128 Mbytes of EDO DRAM. The memory controller managing this bus has the flexibility to support variable DRAM access speeds. The speed of the DRAMs will have a dramatic impact on the performance of the LSI53C1510 and 50 ns EDO DRAM is required. The LSI53C1510 memory controller also supports optional byte-wide parity error detection. 2.4.2 Flash ROM The memory controller in the LSI53C1510 manages an optional Flash ROM. If present, the Flash ROM is used to store the software for the LSI53C1510 Protocol Engine and INT 0x13 boot software. If the Flash ROM is not used, then the host platform is responsible for downloading the Protocol Engine software to the LSI53C1510 through the PCI interface. The LSI53C1510 supports a diagnostic interface that is enabled through a sequence of commands issued to the WRSEQ register in the host interface register set. Software may be directly written to the LSI53C1510 internal memory and external DRAM through the diagnostic interface. Details of this implementation are not currently defined; therefore, LSI Logic recommends using Flash ROM for software storage. The Flash ROM is accessed using the lower 8 bits of the DRAM Memory Interface. 2.4.3 Serial EEPROM The serial EEPROM is primarily used during nonintelligent mode operations. It can be programmed using the host interface of the LSI53C1510. Support Components 2-19 2-20 Functional Description Chapter 3 Software Description This chapter describes the software features, firmware features, and memory requirements for the LSI53C1510 in the following sections: • Section 3.1, “PCI RAID Software Solutions,” page 3-1 • Section 3.2, “Management Software Features,” page 3-3 • Section 3.3, “RAID Firmware Features,” page 3-3 • Section 3.4, “SDMS Software,” page 3-8 • Section 3.5, “Memory Requirements,” page 3-8 3.1 PCI RAID Software Solutions The LSI53C1510 is the first in high-integration RAID processor. LSI Logic offers a full PCI RAID software solution consisting of the LSI Logic RAID DDM, SYMplicity Storage Manager utility, and Wind River Systems’ IxWorks RTOS. These applications run in the LSI53C1510 intelligent mode. 3.1.1 PCI RAID Operating in intelligent mode, the LSI53C1510 can use the LSI Logic PCI RAID software package. Leveraging third generation software from the LSI Logic established and successful bridge controllers and subsystems, the LSI Logic RAID software for the LSI53C1510 provides an extremely stable, feature rich, high availability platform. LSI53C1510 I2O-Ready PCI RAID Ultra2 SCSI Controller 3-1 3.1.2 SYMplicity Storage Manager SYMplicity Storage Manager provides host-based, transparent management of disk array controllers and the following features. • • • • • 3-2 Common Features – Obtaining a RAID Module Profile – Naming a RAID Module (user-defined) – Locating a RAID Module Configuration – LUN creation, deletion using GUI or command line – Easy default configurations or detailed parameter options available – Manages multiple RAID modules – Hot Spare Creation/Deletion – Dynamic Reconfiguration features Status – Event logging in system log or Storage Manager (specific log) – Scriptable error notification_SNMP, email, etc. – LUN Reconstruction progress and in-progress tuning – Performance Monitor ◊ GUI displays key statistics for a card and its logical units ◊ Command line interface captures full set of detailed data Recovery – Health Check for immediate report of component failures – Lead-through Recovery Steps from Single or Multiple Failures Maintenance/Tuning – Cache Management – Parity Check and Repair – Set LUN Reconstruction Rates Software Description 3.1.3 Wind River Systems’ IxWorks RTOS Wind River Systems has ported IxWorks to the LSI53C1510. This version of IxWorks has been tuned for optimal performance. 3.2 Management Software Features Management software has the following features: • Supported by SYMplicity Storage Manager • Client/Server Model (Windows NT/Win95 Client with Windows NT, Netware, or UNIXWare Server) • Compatible with Microsoft Cluster Server (Wolfpack) • Online maintenance and event notification • BBU Support with Utility level software • Remote Diagnostic Capability • Configurable Drive Rebuild rate • Recovery Guru 3.3 RAID Firmware Features RAID firmware has the following features: • RAID Levels 0, 1, 3, 5, and 10 • Caching – Caching (Read-ahead, write through, or write back) – Cache memory options of 8 Mbyte to 128 Mbyte • Runs in optimal and degraded mode • Hardware Assisted Parity Calculation • Variable Stripe Size • Tagged Command Queuing • Global hot spare drives • Drive hot swap with automatic, transparent reconstruction Management Software Features 3-3 • Online Dynamic Capacity Expansion • Online RAID Level Migration/Reconfiguration • Battery Backup Support and Cache Recovery • Supports SCSI Accessed Fault-Tolerant Enclosure (SAF-TE) 3.3.1 RAID Levels 0, 1, 3, 5, and 10 This section describes RAID and the different RAID levels. 3.3.1.1 RAID (Redundant Array of Independent Disks) A disk array in which part of the storage capacity is used to store redundant information about user data stored on the remainder of the storage capacity. The redundant information enables regeneration of user data if one of the disk drives in the drive group fails. 3.3.1.2 RAID Level Indicates the way the controller reads and writes data and array parity on the drives. The LSI53C1510 controller can create RAID Level 0, 1, 3, and 5 logical units. These levels DO NOT indicate any certain hierarchy or preference. 3.3.1.3 RAID Level 0 RAID Level 0 is a nonredundant RAID Level where data, without parity, is striped across a drive group/LUN. All drives are available for storing user data. Any single drive failure causes data loss and a logical unit status of Dead. 3.3.1.4 RAID Level 1 RAID Level 1 or disk mirroring, protects data against disk failure by replicating all data stored on the virtual disk at least once. For some I/O intensive applications, a RAID Level 1 can improve performance significantly over a single disk. As implemented by LSI Logic, RAID 1 combines both striping and mirroring. The striping and mirroring combination is also referred to as RAID 0+1 or RAID 10. 3-4 Software Description 3.3.1.5 RAID Level 3 RAID Level 3 adds parity to a striped array, permitting user data to be regenerated in the event of a failure. RAID Level 3 arrays use normal disk mechanisms for failure detection and the parity for data regeneration in the event of a failure. RAID Level 3 relies on close coordination of member disk activities. 3.3.1.6 RAID Level 5 RAID Level 5 is another independent access RAID Level. It is functionally equivalent to RAID Level 4, using a single parity strip to protect data stored on several data strips in the same stripe. It differs from RAID Level 4 in that its parity strips are distributed across multiple array members rather than being concentrated on a dedicated parity disk. This provides some relief from the write bottleneck that characterizes RAID Level 4, and is the reason that RAID 5 is most often implemented in independent access RAID array products rather than RAID Level 4. 3.3.2 Caching Cache memory is an area on the controller used for intermediate storage of read and write data. By using cache, you can increase system performance because the data for a read or write operation from the host may already be in the cache from a previous operation (thus the need to access the drive itself is eliminated), or the write operation is considered complete once it is written to the cache. The following caching options are supported. • Caching (Read-ahead, write through, or write back) • Cache memory options of 8 Mbyte to 128 Mbyte 3.3.3 Runs in Optimal and Degraded Mode The software permits your RAID system to produce optimal performance. If a failure occurs, the system can run in a degraded mode until replacement of the failed unit occurs. RAID Firmware Features 3-5 3.3.4 Hardware Assisted Parity Calculation RAID firmware uses the Hardware PAE in the LSI53C1510 to offload parity generation and checking from the host. The PAE calculates the parity for write operations much faster than what can be done in software/firmware. It also allows multiple parity operations to be queued for maximum efficiency. 3.3.5 Tagged Command Queuing Tagged command queuing provides the capability for the host to issue multiple commands to a logical unit. This capability is essential for an array logical unit that is made up of multiple devices. Without tagged queuing, the controller can only execute one operation on the logical unit at a time, even though there are multiple drives available for overlapped operations. The maximum number of commands which can be queued in the controller (the sum of all logical units) is 256. This is the number of available structures the controller has for operations received from the host. If the host attempts to issue more commands to the controller than it has structures available for, a Queue Full status will be returned. The controller maintains a queue for each logical unit and a queue for each drive in the logical unit. How a command moves from queue to queue is dependent on the type of queue tag received with the command. 3.3.6 Global Hot Spare Drives This drive contains no valid data but if a failure occurs, the controller can automatically reconstruct and use the global hot spare drive to replace a failed drive. Hot spare drive allows full performance and data redundancy to be restored without user intervention. The user simply replaces the failed drive at a later time. This is an important feature because it can significantly reduce mean time to data loss. A global hot spare drive can replace a failed drive of the same or smaller capacity anywhere on the disk array. 3-6 Software Description 3.3.7 Hot Swap Drive with Automatic, Transparent Reconstruction This disk drive replaces a failed drive. Hot Swap technology makes it possible to remove and replace an array component while power is applied and data activity to and from the system continues. The controller automatically reconstructs data on the new drive, or initiates copying back the data from the global hot spare drive that is standing in for the failed drive. This data reconstruction is transparent to the user and allows full performance and data redundancy to be restored. 3.3.8 Variable Stripe Size The Dynamic Segment Sizing (DSS) feature provides the ability to change the segment size for a LUN. Changing the segment size causes the LUN to be reconfigured such that the data is mapped according to the new segment size. This feature is provided while allowing full user data availability and accessibility. The RAID firmware allows variable stripe size. A striped array is also known as a RAID Level 0 array. 3.3.9 Online Dynamic Capacity Expansion The Dynamic Capacity Expansion feature provides the ability to add drives to a drive group. Adding drives to a drive group causes the LUNs on that drive group to be reconfigured such that the data is spread onto the additional drives. After reconfiguration, the additional capacity may be used to create additional LUNs on the drive group. This feature is provided while allowing full user data availability and accessibility. 3.3.10 Online RAID Level Migration/Reconfiguration The Dynamic RAID Migration (DRM) feature provides the ability to change the RAID Level for a drive group. Changing the RAID Level causes the LUNs in the drive group to be reconfigured such that the data is mapped according to the definition of the new RAID Level. This feature is provided while allowing full user data availability and accessibility. Valid RAID Level Migrations are: 0>1, 0>3, 0>5, 1>0, 1>3, 1>5, 3>0, 3>1, 3>5, 5>0, 5>1, and 5>3. RAID Firmware Features 3-7 3.3.11 Battery Backup Support and Cache Recovery The Battery Backup feature allows data in cache memory to be saved and then recovered following a power failure. 3.3.12 Supports SAF-TE SAF-TE support has been added to the destination (drive) side of the controller. This allows attachment of drive enclosures that support SAF-TE. 3.4 SDMS Software Operating in nonintelligent mode, the LSI53C1510 can use the SDMS software package. SDMS software is a complete software package that solves the increasingly complex problem of managing system I/O. It seamlessly addresses hardware and software interfaces by supporting the LSI Logic family of SCSI processors and controllers, and a wide range of SCSI peripheral devices, while offering interoperability across application programs, operating systems, and host platforms. SDMS software consists of a resident SCSI BIOS that manages all SCSI controller or processor specific functions, and a series of SCSI device drivers that provide operating system and peripheral specific support. SDMS software provides a standard method to interface SCSI I/O subsystems with devices, operating systems, and application software. It also enhances system capabilities already provided by SCSI controllers and processors by facilitating multithreaded I/O support, system wide SCSI device access, and the creation of new applications. 3.5 Memory Requirements To run the LSI53C1510 in intelligent mode, with the PCI RAID software solutions (LSI Logic RAID DDM, SYMplicity Storage Manager utility, and Wind River Systems’ IxWorks RTOS), your memory should meet the following requirements. 3-8 Software Description • EDO DRAM (with parity) - 8 Mbytes to 128 Mbytes • Flash ROM - minimum of 2 Mbytes • NVRAM (with real time clock) - 8 Kbytes (equivalent to SGS-Thomson MK48T18) To run the LSI53C1510 in nonintelligent mode, with LSI Logic the SDMS software package, your memory should meet the following requirements. • Two Serial EEPROM - 2 Kbytes • Flash ROM - 128 Kbytes Memory Requirements 3-9 3-10 Software Description Chapter 4 Signal Descriptions This chapter presents the LSI53C1510 pin configuration and signal definitions using tables and illustrations. Figure 4.1 is the functional signal grouping. The signal descriptions are organized into functional groups: • Section 4.1, “Signal Groupings,” page 4-2 • Section 4.2, “PCI Interface Signals,” page 4-4 • Section 4.3, “SCSI Interface Signals,” page 4-10 • Section 4.4, “Memory Interface Signals,” page 4-15 • Section 4.5, “Miscellaneous Interface Signals,” page 4-18 A slash (/) at the end of a signal name indicates that the active state occurs when the signal is at a LOW voltage. When the slash is absent, the signal is active at a HIGH voltage. All signals/pins described in this chapter are identified by a pin type described in Table 4.1. Table 4.1 Type Pin Type Description Description I Input, a standard input only signal O Totem Pole Output, a standard output driver I/O Input and Output (bidirectional) T/S 3-state, a bidirectional, 3-state input/output signal S/T/S Sustained 3-state, an active LOW 3-state signal owned and driven by one and only one agent at a time LSI53C1510 I2O-Ready PCI RAID Ultra2 SCSI Controller 4-1 4.1 Signal Groupings The LSI53C1510 signals fall into the following groups. These groups are illustrated in Figure 4.1. • • • • • 4-2 PCI Interface Signals – System Signals – Address and Data Signals – Interface Control Signals – Arbitration Signals – Interrupt Signals – Error Reporting Signals – Power Management Event Signals SCSI Interface Signals – A-Channel – B-Channel Memory Interface Signals – ROM/SRAM Signals – EDO DRAM Signals Miscellaneous Interface Signals – SCSI GPIO Function Signals – UART Signals – JTAG Signals – ARM Debug Signals – ARM – RAID Mode Power and Ground Signals Signal Descriptions Figure 4.1 LSI53C1510 Functional Signal Groupings System Address and Data PCI Bus Interface 32-bit 33 MHz Interface Control CLK RST/ PCI_AD[31:0] C_BE[3:0]/ PAR A_SCTRL/ FRAME/ TRDY/ IRDY/ STOP/ DEVSEL/ IDSEL/ Arbitration REQ/ GNT/ Interrupt INTA/ INTB/ Error Reporting Power Management Event ROM SRAM Signals LSI53C1510 EDO DRAM Signals B_SCTRL/ MCE2_RD/ MCE2_WR/ MEM_CE[2:0] MEM_WE/ MOE/_TESTOUT MEM_ADDR[12:0] MEM_DATA[7:0] DRAM_CASFB_A DRAM_CASFB_B DRAM_WE/ DRAM_OE/ DRAM_ADDR[12:0] DRAM_DATA[31:0] DRAM_PAR[3:0] DRAM_RAS/[3:0] DRAM_CAS/[7:0] Signal Groupings SCSI Interface SCLK SCANMODE SCAN_EN SCAN_RAM_EN SCAN_RST_EN SCAN_TEST_CLK_EN TEST_HSC TEST_DRAMCLK TESTIN Memory Interface SCSI LVD Channel A A_DIFFSENS A_RBIAS SERR/ PERR/ PME/ A_SD[15:0] / A_SDP[1:0] / A_SC_D / A_SI_O / A_SMSG / A_SREQ / A_SACK / A_SBSY / A_SATN / A_SRST / A_SSEL / B_SD[15:0] / B_SDP[1:0] / B_SC_D / B_SI_O / B_SMSG / B_SREQ / B_SACK / B_SBSY / B_SATN / B_SRST / B_SSEL / SCSI LVD Channel B B_DIFFSENS B_RBIAS SCSI GPIO Functions A_GPIO[4:0] B_GPIO[4:0] RXT TXT UART TCK TMS TDI TDO TRST/ JTAG ARM_TMS ARM_TDO ARM_TRST/ XINT POWER_FAIL/ Misc. Interface ARM Debug ARM RAID Mode 4-3 4.2 PCI Interface Signals The PCI Bus Interface Signals section contains tables describing the signals for the following signal groups: System Signals, Address and Data Signals, Interface Control Signals, Arbitration Signals, Interrupt Signals, the ARM Signal, Error Recording Signals, the Power Management Signal, and GPIO Interface Signals. 4.2.1 System Signals Table 4.2 describes the System signals. Table 4.2 System Signals Name Bump CLK RST/ 4-4 Type Strength Description F25 I N/A Clock provides timing for all transactions on the PCI bus and is an input to every PCI device. All other PCI signals are sampled on the rising edge of CLK, and other timing parameters are defined with respect to this edge. Clock can optionally serve as the SCSI core clock, but this may effect fast SCSI transfer rates. N24 I N/A Reset forces the PCI sequencer of each device to a known state. All T/S and S/T/S signals are forced to a high impedance state, and all internal logic is reset. The RST/ input is synchronized internally to the rising edge of CLK. The CLK input must be active while RST/ is active to properly reset the device. Signal Descriptions 4.2.2 Address and Data Signals Table 4.3 describes the Address and Data signals. Table 4.3 Name Address and Data Signals Bump Type Strength PCI_AD[31:0] M25, M24, M26, L25, L24, L26, K23, K25, J25, H25, J24, H26, H23, G25, G26, H24, C25, D24, A25, C23, B24, A24, D22, B23, B22, A22, D20, B21, A21, C21, B20, A20 T/S 16 mA PCI Physical dword PCI Address and Data are multiplexed on the same PCI pins. During the first clock of a transaction, AD[31:0] contain a physical byte address. During subsequent clocks, AD[31:0] contain data. A bus transaction consists of an address phase followed by one or more data phases. PCI supports both read and write bursts. AD[7:0] define the least significant byte, and AD[31:24] define the most significant byte. C_BE[3:0]/ K26, G23, E24, A23 T/S 16 mA PCI Bus Command and Byte Enables are multiplexed on the same PCI pins. During the address phase of a transaction, C_BE[3:0]/ define the bus command. During the data phase, C_BE[3:0]/ are used as byte enables. The byte enables determine which byte lanes carry meaningful data. C_BE[0]/ applies to byte 0, and C_BE[3]/ to byte 3. PAR C26 T/S 16 mA PCI Parity is even parity across the AD[31:0] and C_BE[3:0]/ lines. During the address phase, both the address and command bits are covered. During data phase, both data and byte enables are covered. PCI Interface Signals Description 4-5 4.2.3 Interface Control Signals Table 4.4 describes the Interface Control signals. Table 4.4 Interface Control Signals Name Bump Type Strength FRAME/ G24 S/T/S 16 mA PCI Cycle Frame is driven by the current master to indicate the beginning and duration of an access. FRAME/ is asserted to indicate that a bus transaction is beginning. While FRAME/ is deasserted, either the transaction is in the final data phase or the bus is idle. IRDY/ E26 S/T/S 16 mA PCI Initiator Ready indicates the initiating agent’s (bus master’s) ability to complete the current data phase of the transaction. IRDY/ is used with TRDY/. A data phase is completed on any clock when both IRDY/ and TRDY/ are sampled asserted. During a write, IRDY/ indicates that valid data is present on AD[31:0]. During a read, it indicates that the master is prepared to accept data. Wait cycles can be inserted until both IRDY/ and TRDY/ are asserted together. TRDY/ E25 S/T/S 16 mA PCI Target Ready indicates the target agent’s (selected device’s) ability to complete the current data phase of the transaction. TRDY/ is used with IRDY/. A data phase is completed on any clock when both TRDY/ and IRDY/ are sampled asserted. During a read, TRDY/ indicates that valid data is present on AD[31:0]. During a write, it indicates that the target is prepared to accept data. Wait cycles can be inserted until both IRDY/ and TRDY/ are asserted together. STOP/ D26 S/T/S 16 mA PCI Stop indicates that the selected target is requesting the master to stop the current transaction. DEVSEL/ F24 S/T/S 16 mA PCI Device Select indicates that the driving device has decoded its address as the target of the current access. As an input, it indicates to a master whether any device on the bus has been selected. IDSEL K24 I N/A 4-6 Signal Descriptions Description Initialization Device Select is used as a chip select in place of the upper 24 address lines during configuration read and write transactions. 4.2.4 Arbitration Signals Table 4.5 describes the Arbitration signals. Table 4.5 Arbitration Signals Name Bump Type Strength REQ/ GNT/ Description N26 O 16 mA PCI Request indicates to the arbiter that this agent desires use of the PCI bus. Both SCSI functions share the REQ/ signal. M23 I N/A Grant indicates to the agent that access to the PCI bus has been granted. Both SCSI functions share the GNT/ signal in nonintelligent mode. In intelligent mode, the GNT/ signal is shared by the Internal Module Bus (IMB) bus agents. 4.2.5 Interrupt Signals Table 4.6 describes the Interrupt signals. Table 4.6 Interrupt Signals Name Bump Type Strength INTA/ INTB/ Description P24 O 16 mA PCI Interrupt Function A. This signal, when asserted LOW, indicates an interrupting condition in SCSI Function A and that service is required from the host CPU. The output drive of this pin is open drain. If the SCSI Function B interrupt is rerouted at power-up using the INTA/ enable sense resistor (pull-down on MEM_ADDR9), this signal indicates that an interrupting condition has occurred in either the SCSI Function A or SCSI Function B. N23 O 16 mA PCI Interrupt Function B. This signal, when asserted LOW, indicates an interrupting condition in SCSI Function B and that service is required from the host CPU. The output drive of this pin is open drain. This interrupt can be rerouted to INTA/ at power-up using the INTA/ enable sense resistor (pull-down on MEM_ADDR9). This causes the LSI53C1510 to program the SCSI Function B PCI register Interrupt Pin (3D) to 0x01. In intelligent mode, this signal is not used. PCI Interface Signals 4-7 4.2.6 ARM Signal Table 4.7 describes the ARM signal. Table 4.7 ARM Signal Name Bump XINT N25 Type Strength I – Description External Interrupt. This pin, when asserted, indicates that an interrupting condition is pending. 4.2.7 Error Recording Signals Table 4.8 describes the Error Recording signals. Table 4.8 Error Recording Signals Name Bump Type Strength Description PERR/ D25 S/T/S 16 mA PCI Parity Error. This may be pulsed active by an agent that detects a data parity error. PERR/ can be used by any agent to signal data corruption. However, on detection of a PERR/ pulse, the central resource may generate a nonmaskable interrupt to the host CPU, which often implies the system is unable to continue operation once error processing is complete. SERR/ E23 O 16 mA PCI System Error. This output is used to report address and data parity errors. 4.2.8 Power Management Signal Table 4.9 describes the Power Management signal. Table 4.9 Power Management Signal Name Bump PME/ TI 4-8 Type Strength O 16 mA PCI Signal Descriptions Description Power Management Event. This signal, when asserted LOW, indicates a power management event has occurred. 4.2.9 GPIO Interface Signals Table 4.10 describes the GPIO Interface signals. Table 4.10 Name GPIO Interface Signals Bump Type Strength A_GPIO [4:0] W24, V26, V25, V24, U26 I/O 24 mA A General Purpose I/O. Signals GPIO0–GPIO3 default to input mode on reset. Signal GPIO4 defaults to output mode on reset. These signals are controlled or observed by firmware and may be configured as inputs or outputs. B_GPIO [4:0] W2, V1, U3, U1, U2 I/O 24 mA B General Purpose I/O. Signals GPIO0–GPIO3 default to input mode on reset. Signal GPIO4 defaults to output mode on reset. These signals are controlled or observed by firmware and may be configured as inputs or outputs. PCI Interface Signals Description 4-9 4.3 SCSI Interface Signals The SCSI Bus Interface Signals section contains tables describing the signals for the following signal groups: the SCSI Clock Signal, SCSI A-Channel Interface Signals, and SCSI B-Channel Interface Signals. 4.3.1 SCSI Clock Signal Table 4.11 describes the SCSI Clock signal. Table 4.11 SCSI Clock Signal Name Bump Type Strength SCLK AD13 I N/A Description SCSI Clock is used to derive all SCSI related timings. The speed of this clock is determined by the application’s requirements. The clock supplied to SCLK must be at 40 MHz. This frequency is doubled to create the 80 MHz clock required by both SCSI functions. For Ultra2, this frequency is quadrupled to create 160 MHz. 4.3.2 SCSI A-Channel Interface Signals Table 4.12 describes the SCSI A-Channel Interface signals. Table 4.12 SCSI A-Channel Interface Signals1 Name Bump A_SD[15:0]−/ AA26, Y25, Y24, W26, AF14, AD15, AE16, AF16, AE23, AF24, AE24, AE26, AD25, AB23, AC26, AB25 4-10 Type Strength I/O 48 mA SCSI Signal Descriptions Description SCSI Function A Data. LVD Mode: A_SD[15:0]−/ signals are the negative half of the LVDlink 16-bit pair of SCSI data lines. SE Mode: The SE interface uses only the plus signals, therefore, these signals are not used. Table 4.12 SCSI A-Channel Interface Signals1 (Cont.) Name Bump A_SD[15:0]+/ A_SDP[1:0]−/ Type Strength AA24, Y26, W25, W23, AE15, AF15, AD16, AC17, AC22, AD22, AD23, AC24, AD26, AC25, AB24, AB26 I/O 48 mA SCSI Y23, AD21 I/O Description SCSI Function A Data. LVD Mode: A_SD[15:0]+/ signals are the positive half of the LVDlink 16-bit pair of SCSI data lines. SE Mode: The SE interface uses only the plus signals as the 16-bit SCSI data and parity bus. 48 mA SCSI SCSI Function A Data Parity. LVD Mode: A_SDP[1:0]−/ are the negative half of the LVDlink pair for SCSI data parity lines. SE Mode: The SE interface uses only the plus signals, therefore, these signals are not used. A_SDP[1:0]+/ AA25, AF23 I/O 48 mA SCSI SCSI Function A Data Parity. LVD Mode: A_SDP[1:0]+/ are the positive half of the LVDlink pair for SCSI data parity lines. SE Mode: The SE interface uses only the plus signals as the 16-bit SCSI data and parity bus. A_DIFFFSENS AD14 I N/A SCSI Function A Differential Sense. This pin detects the presence of a SE device on a differential system. When external differential transceivers are used, and a zero is detected on this pin, all SCSI Function A chip outputs are 3-stated to avoid damage to the transceivers. Tie this pin HIGH during SE operation. A_SC_D / AE19, AF18 I/O 48 mA SCSI Control/Data. The target asserts this signal with the MSG/ and C_D signals to determine the information transfer phase. A_SI_O / AF17, AE17 I/O 48 mA SCSI Input/Output. The target asserts this signal with the MSG/ and C_D signals to determine the information transfer phase. A_SMSG / AE20, AC19 I/O 48 mA SCSI Message. The target asserts this signal with the I_O and C_D signals to determine the information transfer phase. SCSI Interface Signals 4-11 Table 4.12 SCSI A-Channel Interface Signals1 (Cont.) Name Bump Type Strength A_SREQ / Description AE18, AE17 I/O 48 mA SCSI Request. This signal is a data handshake line from a target device. The target asserts this signal when requesting a data transfer. A_SACK / AF21, AC20 I/O 48 mA SCSI Acknowledge. This signal is a data handshake signal from initiator device. The initiator asserts this signal in response to the REQ/ signal to acknowledge a data transfer. A_SBSY / AD20, AE21 I/O 48 mA SCSI Busy. This signal is asserted when the SCSI bus is busy. When a device wants to arbitrate to use the SCSI bus, BSY/ is driven active. Once the arbitration and selection phases are complete, the target drives this signal active. A_SATN / AE22, AF22 I/O 48 mA SCSI Attention. The initiator asserts this signal when requesting a message out phase. A_SRST / AD19, AF20 I/O 48 mA SCSI Reset. This signal performs a SCSI bus reset when asserted. A_SSEL / AF, AD18 I/O 48 mA SCSI Select. This signal selects or reselects another SCSI device when asserted. 1. The SE interface uses only the − signals. LVD interface uses both the + and − signals. 4-12 Signal Descriptions 4.3.3 SCSI B-Channel Interface Signals Table 4.13 describes the SCSI B-Channel Interface signals. Table 4.13 SCSI B-Channel Interface Signals1 Name Bump B_SD[15:0]−/ B_SD[15:0]+/ B_SDP[1:0]−/ Type Strength AE11, AD11, AF13, AD12, W1, Y2, W3, AA1, AE6, AD6, AF7, AE8, AC8, AF9, AD9, AE10 I/O 48 mA SCSI AC10, AF12, AE12, AE13, V3, W4, Y1, Y4, AC7, AF6, AE7, AD7, AF8, AD8, AE9, AF10 I/O AF11, AF5 I/O Description SCSI Function B Data. LVD Mode: B_SD[15:0]−/ signals are the negative half of the LVDlink 16-bit pair of SCSI data lines. SE Mode: The SE interface uses only the plus signals, therefore, these signals are not used. 48 mA SCSI SCSI Function B Data. LVD Mode: B_SD[15:0]+/ signals are the positive half of the LVDlink 16-bit pair of SCSI data lines. SE Mode: The SE interface uses only the plus signals as the 16-bit SCSI data and parity bus. 48 mA SCSI SCSI Function B Data Parity. LVD Mode: B_SDP[1:0]−/ are the negative half of the LVDlink pair for SCSI data parity lines. SE Mode: The SE interface uses only the plus signals, therefore, these signals are not used. B_SDP[1:0]+/ AD10, AE5 I/O 48 mA SCSI SCSI Function B Data Parity. LVD Mode: B_SDP[1:0]+/ are the positive half of the LVDlink pair for SCSI data parity lines. SE Mode: The SE interface uses only the plus signals as the 16-bit SCSI data and parity bus. B_DIFFFSENS AC12 I N/A SCSI Function B Differential Sense. This pin detects the presence of a SE device on a differential system. When external differential transceivers are used, and a zero is detected on this pin, all SCSI Function B chip outputs are 3-stated to avoid damage to the transceivers. Tie this pin HIGH during SE operation. SCSI Interface Signals 4-13 Table 4.13 SCSI B-Channel Interface Signals1 (Cont.) Name Bump Type Strength B_SC_D / Description AA3, AC1 I/O 48 mA SCSI Control/Data. The target asserts this signal with the MSG/ and C_D signals to determine the information transfer phase. B_SI_O / AA2, Y3 I/O 48 mA SCSI Input/Output. The target asserts this signal with the MSG/ and C_D signals to determine the information transfer phase. B_SMSG / AD1, AB3 I/O 48 mA SCSI Message. The target asserts this signal with the I_O and C_D signals to determine the information transfer phase. B_SREQ / AB1, AB2 I/O 48 mA SCSI Request. This signal is a data handshake line from a target device. The target asserts this signal when requesting a data transfer. B_SACK / AF2, AD4 I/O 48 mA SCSI Acknowledge. This signal is a data handshake signal from initiator device. The initiator asserts this signal in response to the REQ/ signal to acknowledge a data transfer. B_SBSY / AE3, AF3 I/O 48 mA SCSI Busy. This signal is asserted when the SCSI bus is busy. When a device wants to arbitrate to use the SCSI bus, BSY/ is driven active. Once the arbitration and selection phases are complete, the target drives this signal active. B_SATN / AC5, AE4 I/O 48 mA SCSI Attention. The initiator asserts this signal when requesting a message out phase. B_SRST / AD2, AC3 I/O 48 mA SCSI Reset. This signal performs a SCSI bus reset when asserted. B_SSEL / AC2, AB4 I/O 48 mA SCSI Select. This signal selects or reselects another SCSI device when asserted. 1. The SE interface uses only the − signals. LVD interface uses both the + and − signals. 4-14 Signal Descriptions 4.4 Memory Interface Signals The Memory Interface Signals section contains tables describing the signals for the following groups: ROM/SRAM Interface Signals, SCAN Signals, and DRAM Interface Signals. 4.4.1 ROM/SRAM Interface Signals Table 4.14 describes the ROM/SRAM Interface signals. Table 4.14 ROM/SRAM Interface Signals Name Bump MCE2_RD/ K4 O 8 mA Memory Signal for MEM_CE(2). MCE2_WR/ L2 O 8 mA Memory Signal for MEM_CE(2). MEM_CE/[2:0] K3, K2, K1 O 8 mA Memory Chip Enable. These pins are used as chip enable signals to external memory devices. MEM_WE/ M1 O 8 mA Memory Write Enable. This pin is used as a write enable signal to external memories selected by MEM_CE[2:0]. MOE/_TESTOUT J3 O 8 mA Memory. This pin is used as an output enable signal to external memories during read operations. MEM_ADDR [12:0] J2, J1, H3, H1, H2, G3, G1, G2, F3, F1, F2, G4, E1 O 24 mA Memory Address. The memory address bus provides a total of 8 K addressing of general purpose memory addressing. The memory address bus is also used for power-on configuration with pull-up/pull-down resistors. The resistors determine the ROM size. Is concatenated with DRAM_ADDR for MEM_CE cycles. Mirrors DRAM_ADDR signals for DRAM cycles. MEM_DATA [7:0] I/O 8 mA Memory Data lines. N3, M4, P2, M3, N2, N1, M2, L3 Type Strength Description Memory Interface Signals 4-15 4.4.2 SCAN Signals Table 4.15 describes the SCAN signals. Table 4.15 SCAN Signals Name Bump SCANMODE R1 I N/A Scan Mode Enable. Used for manufacturing test. SCAN_EN R3 I N/A Scan Enable. Used for manufacturing test. SCAN_RAM_EN P3 I N/A Scan RAM Enable. Used for manufacturing test. SCAN_RST_EN R2 I N/A Scan Reset Enable. Used for manufacturing test. SCAN_TEST_CLK_EN R4 I N/A Scan Test Clock Enable. Used for manufacturing test. SCAN_TRI_EN I N/A Scan 3-State Enable. Used for manufacturing test. 4-16 P1 Type Strength Description Signal Descriptions 4.4.3 DRAM Interface Signals Table 4.16 describes the DRAM Interface signals. Table 4.16 DRAM Interface Signals Name Bump Type Strength DRAM_CASFB_A A5 I N/A DRAM Column Address Strobe Feedback. DRAM_CASFB_B C7 I N/A DRAM Column Address Strobe Feedback. DRAM_WE/ B4 O 24 mA DRAM Write Enable. Indicates the direction data is to be transferred to/from DRAM. DRAM_OE/ A4 O 16 mA DRAM Output Enable. DRAM_ADDR [12:0] E3, D1, D2, E4, C1, C2, D3, B1, C4, B3, C5, A3, D5 O 24 mA DRAM Memory Address lines. DRAM_DATA [31:0] B19, C18, B16, C15, D12, C11, B18, D17, B14, C13, B11, D19, A18, B17, A16, C16, A14, D15, D13, B12, A12, A19, C19, A17, C17, A15, B15, B13, C14, A13, C12, ALL I/O 8 mA DRAM Data lines. DRAM_PAR[3:0] D10, A10, B10, C10 I/O 8 mA DRAM Data Parity. These bits provide one parity bit for each byte of data. DRAM_RAS[3:0]/ C6, B5, A9, B8 O 24 mA DRAM Row Address Strobe. Indicates the presence of a valid row address. DRAM_CAS[7:0]/ C9, D8, A7, D7, A8, B7, C8, B6 O 26 mA DRAM Column Address Strobe. Indicates the presence of a valid column address. Memory Interface Signals Description 4-17 4.5 Miscellaneous Interface Signals The Miscellaneous Interface Signals section contains tables describing the signals for the following signal groups: UART Interface Signals, JTAG Interface Signals, ARM Debug Interface Signals, the RAID Interface Signal and Power and Ground Signals. 4.5.1 UART Interface Signals Table 4.17 describes the UART Interface signals. Table 4.17 UART Interface Signals Name Bump Type Strength RXT TXT Description P25 I N/A Receive Data. R24 O 4 mA Transmit Data. 4.5.2 JTAG Interface Signals Table 4.18 describes the JTAG Interface signals. Table 4.18 JTAG Interface Signals Name Bump TCK T25 I N/A TMS T24 I 4 mA Test Mode Select. This signal is decoded to select the JTAG test operation. TDI R26 I N/A Test Data Input. This signal is the serial input signal for JTAG. It receives the JTAG test logic instructions. TDO P26 O 4 mA Test Data Output. This signal is the serial output signal for test instructions and data from the JTAG test logic. TRST/ R25 I N/A Test Reset. This signal resets the JTAG logic. TESTIN P4 I N/A Test In. For test purposes only. This signal, when driven HIGH, is used for manufacturing test. It should be pulled LOW or left unconnected for normal operation. 4-18 Type Strength Description Signal Descriptions Test Clock. This signal provides the clock for the JTAG test logic. Table 4.18 JTAG Interface Signals (Cont.) Name Bump TEST_HSC AC14 Type Strength Description TEST_DRAMCLK E2 I N/A Test HSC. For test purposes only. I N/A Test DRAM Clock. For test purposes only. 4.5.3 ARM Debug Interface Signals Table 4.19 describes the ARM Debug Interface signals. Table 4.19 ARM Debug Interface Signals Name Bump Type Strength ARM_TMS Description U23 I N/A ARM Test Mode Select. This signal is decoded to select the test operation. ARM_TDO U24 O N/A ARM Test Data Output. This signal is the serial output for test instructions and data from the ARM test logic. ARM_TRST/ T26 I N/A ARM Test Reset. This signal resets the ARM test logic. 4.5.4 RAID Interface Signal Table 4.20 describes the signal for the RAID Interface signal. Table 4.20 RAID Interface Signal Name Bump POWER_FAIL/ T3 Type Strength Description I N/A Power Fail. Miscellaneous Interface Signals 4-19 4.5.5 Power and Ground Signals Table 4.21 describes the signals for the Power and Ground signals. Table 4.21 Power and Ground Signals Name Bump Type Strength Vdd D6, D11, D16, D21, F4, F23, L4, L23, T4, T23, AA4, AA23, AC6, AC11, AC16, AC21 P N/A Power for PCI bus drivers/receivers, SCSI bus drivers/receivers, local memory interface drivers/receivers, and other I/O pins. Vdd-A AC15 P N/A Power for analog cells (clock quadrupler and DIFFSENS logic). VddCORE [5:0] V2, H4, A6, C20, J26, U25 P N/A Power for core logic. VSS A1, A2, A26, B2, B25, B26, C3, C24, D4, D9, D14, D18, D23, J4, J23, L11, L12, L13, L14, L15, L16, M11, M12, M13, M14, M15, M16, N4, N11, N12, N13, N14, N15, N16, P11, P12, P13, P14, P15, P16, P23, R11, R12, R13, R14, R15, R16, T11, T12, T13, T14, T15, T16, V4, V23, AC4, AC9, AC13, AC18, AC23, AD3, AD24, AE1, AE2, AE25, AF1, AF25, AF26 G N/A Ground for PCI bus drivers/receivers, SCSI bus drivers/receivers, local memory interface drivers, and other I/O pins. VSS-A AE14 G N/A Ground for analog cells (clock quadrupler and DIFFSENS logic). G N/A Ground for core logic. VSSCORE [5:0] U4, L1, B9, C22, F26, R23 4-20 Signal Descriptions Description Chapter 5 Registers (Nonintelligent Mode) This chapter contains the following sections: • Section 5.1, “PCI Functional Description (Nonintelligent Mode),” page 5-3 • Section 5.2, “PCI Configuration Registers (Nonintelligent Mode),” page 5-10 • Section 5.3, “Differences from the LSI53C895 and the LSI53C896,” page 5-26 After power-on, the LSI53C1510 is configured as either a nonintelligent or intelligent controller. This chapter describes the PCI and host interface registers that are visible to the host in nonintelligent mode. In nonintelligent mode the LSI53C1510 operates similar to the LSI53C896 product. Therefore, for detailed information, see the LSI53C896 PCI to Dual Channel Ultra2 SCSI Multifunction Controller Technical Manual. In nonintelligent mode, two Base Address regions (one for control and one for SCRIPTS RAM registers) are defined for each SCSI core. Figure 5.1 illustrates which modules are used in the nonintelligent mode. LSI53C1510 I2O-Ready PCI RAID Ultra2 SCSI Controller 5-1 Figure 5.1 LSI53C1510 Block Diagram in Nonintelligent Mode Host PCI Bus (32-bit, 33 MHz) PCI Master and Slave Control Block, PCI Configuration Registers (2 sets), and DMA Channel Arbitration Ultra2 SCSI Controller 8 Dword SCRIPTS Prefetch Buffer Buffer I2O Msg Unit 4 Kbyte SCRIPTS RAM DMA es ul ed d s Mo t8UKbyte ARM o N Instruction/ Slave Buffer Ultra2 SCSI Controller 4 Kbyte SCRIPTS RAM 8 Dword SCRIPTS Prefetch Buffer Data Buffer 816 Byte DMA FIFO SCSI SCRIPTS Processor Operating Registers Serial EEPROM and AutoConfiguration SCSI FIFO and SCSI Control Block ARM RISC Processor Internal Module Bus Parity Assist Engine LVDlink Drivers and Receivers Flash ROM Memory Control 816 Byte DMA FIFO SCSI SCRIPTS Processor Operating Registers SCSI FIFO and SCSI Control Block DRAM Engine LVDlink Drivers and Receivers JTAG Wide Ultra2 SCSI Bus (A Channel) JTAG 2-Wire Serial EEPROM Bus Wide Ultra2 SCSI Bus (B Channel) Flash ROM/DRAM Memory Bus This section contains descriptions of the LSI53C1510 PCI and host interface commands and registers. In the descriptions the term “set” is used to refer to bits that are programmed to a binary one. Similarly, the terms “clear” and “reset” are used to refer to bits that are programmed to a binary zero. Do not set reserved bits. Reserved bit functions may change at any time. Unless otherwise indicated, all bits in registers are active high, that is, the feature is enabled by setting the bit. The bottom row of every register diagram shows the default register values, which are enabled after the chip is powered on or reset. 5-2 Registers (Nonintelligent Mode) 5.1 PCI Functional Description (Nonintelligent Mode) In nonintelligent mode, the LSI53C1510 implements two PCI to Wide Ultra2 SCSI controllers in a single package. This configuration presents only one load to the PCI bus and uses one REQ/ - GNT/ pair to arbitrate for PCI bus mastership. However, separate interrupt signals are generated for SCSI Function A and SCSI Function B. 5.1.1 PCI Addressing There are three physical PCI defined address spaces: • Configuration Space • I/O Space • Memory Space 5.1.1.1 Configuration Space The host processor uses this configuration space to initialize the LSI53C1510. Two independent sets of PCI configuration space registers are defined, one set for each SCSI function. The PCI configuration space registers are accessible only by system BIOS during PCI configuration cycles. Each configuration space is a contiguous 256 x 8-bit set of addresses. Decoding C_BE/[3:0] determines if a PCI cycle is intended to access the configuration register space. The IDSEL bus signal is a “chip select” that allows access to the configuration register space only. A configuration read/write cycle without IDSEL is ignored. The eight lower order addresses AD[7:0] are used to select a specific 8-bit register. Since the LSI53C1510 is a PCI multifunction device, AD[10:8] decodes either SCSI Function A configuration register (AD[10:8] = 000 binary) or SCSI Function B configuration register (AD[10:8] = 001 binary). PCI Functional Description (Nonintelligent Mode) 5-3 At initialization time, each PCI device is assigned a base address for memory accesses and I/O accesses. This is accomplished using registers in the configuration space. On every nonconfiguration space access, the LSI53C1510 compares its assigned base addresses with the value on the Address/Data bus during the PCI address phase. If there is a match of the upper 24 bits, the access is for the LSI53C1510 and the low order eight bits to define the register to be accessed. A decode of C_BE/[3:0] determines which registers and what type of access is to be performed. 5.1.1.2 I/O Space The PCI specification defines I/O space as a contiguous 32-bit I/O address that is shared by all system resources, including the LSI53C1510. Base Address Register Zero (I/O) register determines which 256 byte I/O area this device occupies. 5.1.1.3 Memory Space The PCI specification defines memory space as a contiguous 32-bit memory address that is shared by all system resources, including the LSI53C1510. Base Address Register One (MEMORY) register determines which 1 Kbyte memory area this device occupies. Each SCSI function uses a 4 K SCRIPTS RAM memory space. Base Address Register Two (SCRIPTS RAM) register determines the 4 Kbyte memory area that the SCRIPTS RAM occupies. 5-4 Registers (Nonintelligent Mode) 5.1.2 PCI Bus Commands and Functions Supported Bus commands indicate to the target the type of transaction the master is requesting. Bus commands are encoded on the C_BE/[3:0] lines during the address phase. PCI bus command encoding and types appear in Table 5.1. Reserved commands are shaded. Table 5.1 PCI Bus Commands Encoding C_BE[3:0]/ Command Type Supported as Master Supported as Slave 0000 Interrupt Acknowledge No No 0001 Special Cycle No No 0010 I/O Read Yes Yes 0011 I/O Write Yes Yes 0100 Reserved N/A N/A 0101 Reserved N/A N/A 0110 Memory Read Yes Yes 0111 Memory Write Yes Yes 1000 Reserved N/A N/A 1001 Reserved N/A N/A 1010 Configuration Read No Yes 1011 Configuration Write No Yes 1100 Memory Read Multiple Yes Yes (defaults to 0110) 1101 DAC Yes Yes 1110 Memory Read Line Yes Yes (defaults to 0110) 1111 Memory Write and Invalidate Yes Yes (defaults to 0111) 5.1.2.1 Interrupt Acknowledge Command The LSI53C1510 does not respond to this command as a slave and it never generates this command as a master. PCI Functional Description (Nonintelligent Mode) 5-5 5.1.2.2 Special Cycle Command The LSI53C1510 does not respond to this command as a slave and it never generates this command as a master. 5.1.2.3 I/O Read Command The LSI53C1510 uses the I/O Read command to read data from an agent mapped in I/O address space. 5.1.2.4 I/O Write Command The LSI53C1510 uses the I/O Write command to write data to an agent mapped in I/O address space. 5.1.2.5 Reserved Command The LSI53C1510 does not respond to this command as a slave and it never generates this command as a master. 5.1.2.6 Memory Read Command The LSI53C1510 uses the Memory Read command to read data from an agent mapped in the Memory Address Space. The target is free to do an anticipatory read for this command only if it can guarantee that such a read has no side effects. 5.1.2.7 Memory Write Command The LSI53C1510 uses the Memory Write command to write data to an agent mapped in the Memory Address Space. When the target returns “ready”, it assumes responsibility for the coherency (which includes ordering) of the subject data. 5.1.2.8 Configuration Read Command The LSI53C1510 uses the Configuration Read command to read the configuration space of each agent. An agent is selected during a configuration access when its IDSEL signal is asserted and AD[1:0] are 00. During the address phase of a configuration cycle AD[7:2] addresses one of the 64 Dword registers (where byte enables address the bytes 5-6 Registers (Nonintelligent Mode) within each Dword) in the configuration space of each device. AD[31:11] are logical don’t cares to the selected agent. AD[10:8] indicate which device of a multifunction agent is being addressed. 5.1.2.9 Configuration Write Command The LSI53C1510 uses the Configuration Write command to transfer data to the configuration space of each agent. An agent is selected when its IDSEL signal is asserted and AD[1:0] are 00. During the address phase of a configuration cycle, the AD[7:2] lines address the 64 Dword registers (where byte enables address the bytes within each Dword) in the configuration space of each device. AD[31:11] are logical don’t cares to the selected agent. AD[10:8] indicate which device of a multifunction agent is addressed. 5.1.2.10 Memory Read Multiple Command This command is identical to the Memory Read command except it indicates that the master may intend to fetch more than one cache line before disconnecting. The LSI53C1510 supports PCI Memory Read Multiple functionality and issues Memory Read Multiple commands on the PCI bus when the Memory Read Multiple Mode is enabled. 5.1.2.11 DAC Command The LSI53C1510 performs DACs when 64-bit addressing is required. See PCI 2.1 Specification. 5.1.2.12 Memory Read Line Command This command is identical to the Memory Read command, except that it additionally indicates that the master intends to fetch a complete cache line. This command is intended for use with bulk sequential data transfers where the memory system and the requesting master might gain some performance advantage by reading to a cache line boundary rather than a single memory cycle. Read Multiple with Read Line Enabled – When both the Read Multiple and Read Line modes are enabled, a Memory Read Multiple command is issued, even though conditions for Memory Read Line are met. PCI Functional Description (Nonintelligent Mode) 5-7 If the Read Multiple mode is enabled and the Read Line mode is disabled, Memory Read Multiple commands are issued if the Memory Read Multiple conditions are met. 5.1.2.13 Memory Write and Invalidate Command The Memory Write and Invalidate command is identical to the Memory Write command, except that it additionally guarantees a minimum transfer of one complete cache line; that is to say, the master intends to write all bytes within the addressed cache line in a single PCI transaction unless interrupted by the target. This command requires implementation of the PCI Cache Line Size register at address 0x0C in PCI configuration space. Multiple Cache Line Transfers – The Memory Write and Invalidate command can write multiple cache lines of data in a single bus ownership. The chip issues a burst transfer as soon as it reaches a cache line boundary. The size of the transfer is not automatically the cache line size, but rather a multiple of the cache line size specified in PCI 2.1 Specification. After each data transfer, the chip re-evaluates the burst size based on the amount of remaining data to transfer and again selects the highest possible multiple of the cache line size, and no larger than the burst size. The most likely scenario of this scheme is that the chip selects the burst size after alignment, and issues bursts of this size. The burst size is, in effect, throttled down toward the end of a long Memory Move or Block Move transfer until only the cache line size burst size is left. The chip finishes the transfer with this burst size. Latency – In accordance with the PCI specification, the latency timer is ignored when issuing a Memory Write and Invalidate command such that when a latency time-out occurs, the LSI53C1510 continues to transfer up to a cache line boundary. At that point, the chip relinquishes the bus, and finishes the transfer at a later time using another bus ownership. If the chip is transferring multiple cache lines it continues to transfer until the next cache boundary is reached. PCI Target Retry – During a Memory Write and Invalidate transfer, if the target device issues a retry (STOP with no TRDY, indicating that no data was transferred), the chip relinquishes the bus and immediately tries to 5-8 Registers (Nonintelligent Mode) finish the transfer on another bus ownership. The chip issues the appropriate command on the next ownership, in accordance with the PCI specification. PCI Target Disconnect – During a Memory Write and Invalidate transfer, if the target device issues a disconnect the LSI53C1510 relinquishes the bus and immediately tries to finish the transfer on another bus ownership. The chip issues the appropriate command on the next ownership, in accordance with the PCI specification. 5.1.3 Internal Arbiter The PCI SCSI controller uses a single REQ/ - GNT/ signal pair to arbitrate for access to the PCI bus. An internal arbiter circuit allows the different bus mastering functions resident in the chip to arbitrate among themselves for the privilege of arbitrating for PCI bus access. There are two independent bus mastering functions inside the LSI53C1510, one for each of the SCSI functions. The internal arbiter uses a round robin arbitration scheme to decide which internal bus mastering function may arbitrate for access to the PCI bus. This ensures that no function is starved for access to the PCI bus. 5.1.4 PCI Cache Mode The LSI53C1510 supports the PCI specification for an 8-bit Cache Line Size register located in the PCI configuration space. The Cache Line Size register provides the ability to sense and react to nonaligned addresses corresponding to cache line boundaries. In conjunction with the Cache Line Size register, the PCI commands Memory Read Line, Memory Read Multiple, Memory Write and Invalidate are each software enabled or disabled to allow the user full flexibility in using these commands. 5.1.4.1 Memory to Memory Moves Memory to Memory Moves also support PCI cache commands, as described above, with one limitation. Memory Write and Invalidate on Memory to Memory Move writes are only supported if the source and destination address are quad word aligned. If the source and destination are not quad word aligned (i.e. Source address[2:0] == Destination Address[2:0]), no write aligning will be performed nor will Memory Write and Invalidates be issued. The LSI53C1510 is little endian only. PCI Functional Description (Nonintelligent Mode) 5-9 5.2 PCI Configuration Registers (Nonintelligent Mode) The PCI Configuration Registers, as shown in Table 5.2, are accessed by performing a configuration read/write to the device with its IDSEL pin asserted and the appropriate value in AD[10:8] during the address phase of the transaction. SCSI Function A is identified by a binary value of 000b, and SCSI Function B by a value of 001b. Each SCSI function contains the same register set with identical default values, except the Interrupt Pin register. All PCI compliant devices, such as the LSI53C1510, must support the Vendor ID, Device ID, Command, and Status registers. Support of other PCI compliant registers is optional. In the LSI53C1510, registers that are not supported are not writable and return all zeros when read. Only those registers and bits that are currently supported by the LSI53C1510 are described in this chapter. Reserved bits should not be accessed. Reserved registers and bits are shaded. Table 5.2 PCI Configuration Register Map 31 16 15 Device ID Status Vendor ID Command Revision ID (Rev ID) Class Code BIST Header Type Latency Timer Cache Line Size Base Address Register Zero (I/O) Base Address Register One (MEMORY) Base Address Register Two (SCRIPTS RAM) Reserved Reserved Reserved Reserved Subsystem ID Subsystem Vendor ID Expansion ROM Base Address Reserved Capabilities Pointer Reserved Max_Lat Min_Gnt Interrupt Pin Interrupt Line Power Management Capabilities Next Item Pointer Capability ID Bridge Support Data Power Management Control/Status Extensions 5-10 Registers (Nonintelligent Mode) 0 Address Page 0x00 5-11 0x04 5-11 0x08 5-15 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C 0x40 5-15 5-17 5-18 5-18 5-18 5-18 5-18 5-18 5-19 5-20 5-21 5-21 5-22 5-23 0x44 5-25 Registers: 0x00–0x01 Vendor ID Read Only 15 0 VID 0 0 0 1 VID 0 0 0 0 0 0 0 0 0 0 0 0 Vendor ID [15:0] This 16-bit register identifies the manufacturer of the device. The Vendor ID is 0x1000. Registers: 0x02–0x03 Device ID Read Only 15 0 DID 0 0 0 0 DID 0 0 0 0 0 0 0 0 1 0 1 0 Device ID [15:0] This 16-bit register identifies the particular device. The Device ID in nonintelligent mode is 0x000A. Registers: 0x04–0x05 Command Read/Write 15 9 R 0 0 0 0 0 0 0 8 7 6 5 4 3 2 1 0 SE R EPER R WIE R EBM EMS EIS 0 0 0 0 0 0 0 0 0 The SCSI Command register provides coarse control over a device’s ability to generate and respond to PCI cycles. When a zero is written to this register, the LSI53C1510 is logically disconnected from the PCI bus for all accesses except configuration accesses. R Reserved PCI Configuration Registers (Nonintelligent Mode) [15:9] 5-11 5-12 SE SERR/ Enable 8 This bit enables the SERR/ driver. SERR/ is disabled when this bit is clear. The default value of this bit is zero. This bit and bit 6 must be set to report address parity errors. R Reserved EPER Enable Parity Error Response 6 This bit allows the LSI53C1510 to detect parity errors on the PCI bus and report these errors to the system. Only data parity checking is enabled and disabled with this bit. The LSI53C1510 always generates parity for the PCI bus. R Reserved 5 WIE Write and Invalidate Enable This bit allows the LSI53C1510 to generate memory Write and Invalidate commands on the PCI bus. 4 R Reserved 3 EBM Enable Bus Mastering 2 This bit controls the ability of the LSI53C1510 to act as a master on the PCI bus. A value of zero disables this device from generating PCI bus master accesses. A value of one allows the LSI53C1510 to behave as a bus master. The device must be a bus master in order to fetch SCRIPTS instructions and transfer data. EMS Enable Memory Space 1 This bit controls the ability of the LSI53C1510 to respond to Memory space accesses. A value of zero disables the device response. A value of one allows the LSI53C1510 to respond to Memory Space accesses at the address range specified by the Base Address Register One (MEMORY) and Base Address Register Two (SCRIPTS RAM) registers in the PCI configuration space. EIS Enable I/O Space 0 This bit controls the LSI53C1510 response to I/O space accesses. A value of zero disables the device response. A value of one allows the LSI53C1510 to respond to I/O Space accesses at the address range specified by the Base Address Register Zero (I/O) register in the PCI configuration space. Registers (Nonintelligent Mode) 7 Registers: 0x06–0x07 Status Read/Write 15 14 13 12 DPE SSE RMA RTA 0 0 0 0 11 10 R 0 9 DT 0 8 7 DPR 0 0 5 R 0 0 4 3 0 NC 0 1 R 0 0 0 0 Reads to this register behave normally. Writes are slightly different in that bits can be cleared, but not set. A bit is reset whenever the register is written, and the data in the corresponding bit location is a one. For instance, to clear bit 15 and not affect any other bits, write the value 0x8000 to the register. DPE Detected Parity Error (from Slave) 15 This bit is set by the LSI53C1510 whenever it detects a data parity error, even if the data parity error handling is disabled. SSE Signaled System Error 14 This bit is set whenever the device asserts the SERR/ signal. RMA Received Master Abort (from Master) 13 A master device should set this bit whenever its transaction (except for Special Cycle) is terminated with Master Abort. RTA Received Target Abort (from Master) A master device should set this bit whenever its transaction is terminated by target abort. 12 R Reserved 11 DT DEVSEL/ Timing [10:9] These bits encode the timing of DEVSEL/. These are encoded as: 00b fast 01b medium 10b slow 11b reserved PCI Configuration Registers (Nonintelligent Mode) 5-13 These bits are read only and should indicate the slowest time that a device asserts DEVSEL/ for any bus command except Configuration Read and Configuration Write. The LSI53C1510 supports a value of 01b. DPR Data Parity Error Reported This bit is set when the following conditions are met: 8 • The bus agent asserted PERR/ itself or observed PERR/ asserted and; • The agent setting this bit acted as the bus master for the operation in which the error occurred and; • The Parity Error Response bit in the Command register is set. 5-14 R Reserved NC New Capabilities 4 A value of one implements a list of extended capabilities. R Reserved Registers (Nonintelligent Mode) [7:5] [3:0] Register: 0x08 Revision ID (Rev ID) Read Only 7 0 RID 0 0 RID 0 0 0 0 0 0 Revision ID [7:0] This register specifies a device specific revision identifier. This silicon version of the LSI53C1510 is set to 0x00 for Rev A silicon. Registers: 0x09–0x0B Class Code Read Only 23 0 CC 0 0 0 0 0 0 0 1 0 CC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Class Code [23:0] This 24-bit register is used to identify the generic function of the device. The upper byte of this register is a base class code, the middle byte is a subclass code, and the lower byte identifies a specific register level programming interface. The value of this register is 0x010000, which identifies a SCSI controller. Register: 0x0C Cache Line Size Read/Write 7 0 CLS 0 CLS 0 0 0 0 0 0 0 Cache Line Size [7:0] This register specifies the system cache line size in units of 32-bit words. The value in this register is used by the device to determine whether to use Memory Write and Invalidate or Write commands for performing write cycles, PCI Configuration Registers (Nonintelligent Mode) 5-15 and whether to use Memory Read, Memory Read Line, or Memory Read Multiple commands for performing read cycles as a bus master. Devices participating in the caching protocol use this field to know when to retry burst accesses at cache line boundaries. If this register is programmed to a number which is not a power of 2, the device will not use PCI performance commands to perform data transfers. Register: 0x0D Latency Timer Read/Write 7 0 LT 0 LT 0 0 0 0 0 0 0 Latency Timer [7:0] The Latency Timer register specifies, in units of PCI bus clocks, the value of the Latency Timer for this PCI bus master. The SCSI functions of the LSI53C1510 support this timer. All eight bits are writable, allowing latency values of 0–255 PCI clocks. Use the following equation to calculate an optimum latency value for the SCSI functions of the LSI53C1510. Latency = 2 + (Burst Size * (typical wait states + 1)) Values greater than optimum are also acceptable. 5-16 Registers (Nonintelligent Mode) Register: 0x0E Header Type Read Only 7 0 HT[7:0] 1 0 HT 0 0 0 0 0 0 Header Type [7:0] This 8-bit register identifies the layout of bytes 0x10 through 0x3F in configuration space and also whether or not the device contains multiple functions. Since the LSI53C1510 is a multifunction controller the value of this register is 0x80. Register: 0x0F Not Supported Registers: 0x10–0x13 Base Address Register Zero (I/O) Read/Write 31 0 BARZ 0 0 0 0 0 0 0 0 0 BARZ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Base Address Register Zero - I/O [31:0] This base address register is used to map the operating register set into I/O space. The LSI53C1510 requires 256 bytes of I/O space for this base address register. It has bit zero hardwired to one. Bit 1 is reserved and returns a zero on all reads, and the other bits are used to map the device into I/O space. For detailed information on the operation of this register, refer to the PCI 2.1 Specification. PCI Configuration Registers (Nonintelligent Mode) 5-17 Registers: 0x14–0x17 Base Address Register One (MEMORY) Read/Write 31 0 BARO 0 0 0 0 0 0 0 0 0 0 0 0 BARO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Base Address Register One [31:0] This base address register maps SCSI operating registers into memory space. This device requires 1024 bytes of address space for this base register. The default value of this register is 0x00000000. For detailed information on the operation of this register, refer to the PCI 2.1 Specification. Registers: 0x18–0x1B Base Address Register Two (SCRIPTS RAM) Read/Write 31 0 BART 0 0 0 0 0 0 0 0 0 0 0 BART 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Base Address Register Two [31:0] This base register is used to map the SCRIPTS RAM into memory space. The LSI53C1510 requires 4 K of address space for this base register. This register has bits [11:0] hardwired to 000000000000. For detailed information on the operation of this register, refer to the PCI 2.1 Specification. Registers: 0x1C–0x2B Reserved 5-18 Registers (Nonintelligent Mode) Registers: 0x2C–0x2D Subsystem Vendor ID Read Only 15 0 SVID 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Default: If MEM_ADDR7 is HIGH 0 0 0 0 0 0 Default: If MEM_ADDR7 is LOW SVID Subsystem Vendor ID [15:0] This 16-bit register is used to uniquely identify the vendor manufacturing the add-in board or subsystem where this PCI device resides. It provides a mechanism for an add-in card vendor to distinguish its cards from another vendor’s cards, even if the cards have the same PCI controller installed on them (and therefore the same Vendor ID and Device ID). If the external serial EEPROM interface is disabled (MEM_ADDR7 pulled HIGH), this register returns a value of 0x1000 (LSI Logic Vendor ID). The 16-bit value that should be stored in the external serial EEPROM for this register is the vendor’s PCI Vendor ID and must be obtained from the PCI SIG. Please see Section 2.4.3, “Serial EEPROM,” for more information on downloading a value for this register. If the external serial EEPROM interface is enabled (MEM_ADDR7 pulled LOW), this register is automatically loaded at power-up from the external serial EEPROM and will contain the value downloaded from the serial EEPROM or a value of 0x0 if the download fails. PCI Configuration Registers (Nonintelligent Mode) 5-19 Registers: 0x2E–0x2F Subsystem ID Read Only 15 0 SID 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x x x Default: If MEM_ADDR7 is HIGH x x x x x x Default: If MEM_ADDR7 is LOW SID Subsystem ID [15:0] This 16-bit register is used to uniquely identify the add-in board or subsystem where this PCI device resides. It provides a mechanism for an add-in card vendor to distinguish its cards from one another even if the cards have the same PCI controller installed on them (and therefore the same Vendor ID and Device ID). If the external serial EEPROM is disabled (MEM_ADDR7 pulled HIGH), the register returns a value of 0x1000. The 16-bit value that should be stored in the external serial EEPROM is vendor specific. If the external serial EEPROM interface is enabled (MEM_ADDR7 pulled LOW), this register is automatically loaded at power-up from the external serial EEPROM. Registers: 0x30–0x33 Expansion ROM Base Address Read/Write 31 0 ERBA 0 0 0 0 0 0 0 0 0 ERBA 5-20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Expansion ROM Base Address [31:0] This four byte register handles the base address and size information for the expansion ROM. It functions exactly like the Base Address Register One (MEMORY) and Base Address Register Two (SCRIPTS RAM) registers, Registers (Nonintelligent Mode) except that the encoding of the bits is different. The upper 21 bits correspond to the upper 21 bits of the expansion ROM base address. The expansion ROM Enable bit, bit 0, is the only bit defined in this register. This bit is used to control whether or not the device accepts accesses to its expansion ROM. When the bit is set, address decoding is enabled, and a device is used with or without an expansion ROM depending on the system configuration. To access the external memory interface, also set the Memory Space bit in the Command register. The host system detects the size of the external memory by first writing the Expansion ROM Base Address register with all ones and then reading back the register. The SCSI functions of the LSI53C1510 respond with zeros in all don’t care locations. The ones in the remaining bits represent the binary version of the external memory size. For example, to indicate an external memory size of 32 Kbytes, this register, when written with ones and read back, returns ones in the upper 17 bits. The size of the external memory is set through MEM_ADDR[3:0]. Please see Section 2.1.2, “Configuration and Initialization,” for the possible size encodings available. Register: 0x34 Capabilities Pointer Read Only 7 0 CP 0 CP 0 0 0 0 1 0 0 Capabilities Pointer [7:0] This register indicates that the first extended capability register is located at offset 0x40 in the PCI Configuration. Registers: 0x35–0x3B Reserved PCI Configuration Registers (Nonintelligent Mode) 5-21 Register: 0x3C Interrupt Line Read/Write 7 0 IL 0 0 IL 0 0 0 0 0 0 Interrupt Line [7:0] This register is used to communicate interrupt line routing information. POST software writes the routing information into this register as it configures the system. The value in this register tells which input of the system interrupt controller(s) the device’s interrupt pin is connected to. Values in this register are specified by system architecture. Register: 0x3D Interrupt Pin Read Only 7 0 IP 0 0 0 0 0 0 0 1 0 0 1 0 Default: SCSI Function A, INTA/ signal 0 0 0 0 Default: SCSI Function B, INTB/ signal IP 5-22 Interrupt Pin [7:0] This register is unique to each SCSI function. It tells which interrupt pin the device uses. Its value is set to 0x01 for the Function A (INTA/) signal, and 0x02 for the Function B (INTB/) signal at power-up. Registers (Nonintelligent Mode) Register: 0x3E Min_Gnt Read Only 7 0 MG 0 0 MG 0 1 1 1 1 0 Min_Gnt [7:0] This register is used to specify the desired settings for latency timer values. Min_Gnt is used to specify how long a burst period the device needs. The value specified in these registers is in units of 0.25 microseconds. The LSI53C1510 sets this register to 0x1E. Register: 0x3F Max_Lat Read Only 7 0 ML 0 0 ML 0 0 1 0 0 0 Max_Lat [7:0] This register is used to specify the desired settings for latency timer values. Max_Lat is used to specify how often the device needs to gain access to the PCI bus. The value specified in these registers is in units of 0.25 microseconds. The LSI53C1510 SCSI function sets this register to 0x08. Register: 0x40 Capability ID Read Only 7 0 CID 0 CID 0 0 0 0 0 0 Cap_ID Bits [7:0] identify this register as a PCI power management register (0x01). PCI Configuration Registers (Nonintelligent Mode) 1 [7:0] 5-23 Register: 0x41 Next Item Pointer Read Only 7 0 NIP 0 0 0 NIP 0 0 0 0 0 Next_Item_Ptr [7:0] Bits [7:0] contain the offset location of the next item in the function’s capabilities list. The LSI53C1510 has these bits set to zero indicating no further extended capabilities registers exist. Registers: 0x42–0x43 Power Management Capabilities Read Only 15 11 PMES[4:0] 0 5-24 0 0 10 9 8 D2S D1S 0 0 1 1 6 R 0 0 5 4 3 2 DSI APS PMEC 0 0 0 0 0 VER[2:0] 0 0 1 PMES[4:0] PME_Support [15:11] Bits [15:11] define the power management states in which the LSI53C1510 will assert the PME pin. These bits are all set to zero. D2S D2_Support D2 power management state is not supported. 10 D1S D1_Support D1 power management state is not supported. 9 R Reserved DSI Device Specific Initialization 5 This bit is a device specific initialization bit and is set to zero to indicate that no special initialization is required. APS Auxiliary Power Source This bit is set to zero and indicates that an auxiliary power source is not needed for the LSI53C1510. Registers (Nonintelligent Mode) [8:6] 4 PMEC PME Clock Bit 3 is set to zero and indicates that no PCI clock is required to assert the PME pin. 3 VER[2:0] Version [2:0] These three bits indicate that the LSI53C1510 complies with Version 1.0 of the PCI Power Management Specification. Registers: 0x44–0x45 Power Management Control/Status Read/Write 15 14 13 12 PST DSCL[1:0] 0 0 0 9 DSLT 0 0 0 8 7 2 PEN 0 0 R 0 0 0 0 PWS[1:0] 0 0 0 0 0 PST PME_Status This bit defines if the LSI53C1510 has generated a Power Management Event. 15 DSCL[1:0] Data_Scale These bits are not used in the LSI53C1510. [14:13] DSLT Data_Select These bits are not used in the LSI53C1510. [12:9] PEN PME_Enable This bit is not used in the LSI53C1510. R Reserved PWS[1:0] Power State [1:0] These bits are used to determine the current power state of the LSI53C1510. They are used to place the LSI53C1510 in a new power state. Power states are defined as: 8 [7:2] 00b D0 11b D3 hot PCI Configuration Registers (Nonintelligent Mode) 5-25 Register: 0x46 Bridge Support Extensions Read Only 7 0 BSE 0 0 BSE 0 0 0 0 0 0 Bridge Support Extensions [7:0] Bits [7:0] are not used and will return to 0x00 if read. Register: 0x47 Data Read Only 7 0 DATA 0 DATA 0 0 0 0 0 0 0 Data [7:0] Bits [7:0] are not used and will return to 0x00 if read. 5.3 Differences from the LSI53C895 and the LSI53C896 The LSI53C1510 SCSI cores are similar to the LSI53C895 and LSI53C896, but there are differences. The differences are listed below. • FIFO Depth The LSI53C1510 SCSI DMA FIFOs are 816 bytes deep (the same as the LSI53C895). The LSI53C896 FIFOs are 944 bytes deep. • SCRIPTS RAM The LSI53C1510 SCRIPTS RAMs are 4 Kbytes while the LSI53C896 are 8 Kbytes. • Register Differences Differences do exist between the LSI53C1510 and the LSI53C896 register bits. Chapter 12, “SCSI Interface,” in the LSI53C1510 I2OReady PCI RAID Ultra2 SCSI Controller Programming Guide describes the differences. 5-26 Registers (Nonintelligent Mode) Chapter 6 Registers (Intelligent Mode) This chapter contains the following sections: • Section 6.1, “Programming Models,” page 6-3 • Section 6.2, “PCI Configuration Registers (Intelligent Mode),” page 6-4 • Section 6.3, “Host Interface Registers (Intelligent Mode),” page 6-19 • Section 6.4, “Shared Memory,” page 6-27 After power-on, the LSI53C1510 is configured as either a nonintelligent or intelligent controller. This chapter describes the PCI and host interface registers that are visible to the host in intelligent mode. In intelligent mode, the LSI53C1510 is configured as an Intelligent IOP supporting either dual channel SCSI or RAID. In intelligent mode, a single Base Address region is defined that contains the I2O messaging interface and control. Figure 6.1 illustrates how, in intelligent mode of operation, the I2O messages are routed to the ARM RISC processor and the processor controls the other modules including the two SCSI modules. LSI53C1510 I2O-Ready PCI RAID Ultra2 SCSI Controller 6-1 Figure 6.1 LSI53C1510 Block Diagram in Intelligent Mode Host PCI Bus (32-bit, 33 MHz) PCI Master and Slave Control Block, PCI Configuration Registers, and DMA Channel Arbitration Ultra2 SCSI Controller 8 Dword SCRIPTS Prefetch Buffer 816 Byte DMA FIFO Buffer I2O Msg Unit DMA Slave Buffer 4 Kbyte SCRIPTS RAM SCSI SCRIPTS Processor Ultra2 SCSI Controller 4 Kbyte SCRIPTS RAM 8 Kbyte ARM Instruction/ Data Buffer Operating Registers Serial EEPROM and AutoConfiguration SCSI FIFO and SCSI Control Block ARM RISC Processor Internal Module Bus Parity Assist Engine LVDlink Drivers and Receivers Flash ROM Memory Control 816 Byte DMA FIFO 8 Dword SCRIPTS Prefetch Buffer SCSI SCRIPTS Processor Operating Registers SCSI FIFO and SCSI Control Block DRAM Engine LVDlink Drivers and Receivers JTAG Wide Ultra2 SCSI Bus (A Channel) JTAG ARM Debug 2-Wire Serial EEPROM Flash ROM/DRAM Memory Bus Wide Ultra2 SCSI Bus (B Channel) This section contains descriptions of the LSI53C1510 PCI and host interface commands and registers. In the descriptions the term “set” is used to refer to bits that are programmed to a binary one. Similarly, the terms “clear” and “reset” are used to refer to bits that are programmed to a binary zero. Do not set reserved bits. Reserved bit functions may change at any time. Unless otherwise indicated, all bits in registers are active high, that is, the feature is enabled by setting the bit. The bottom row of every register diagram shows the default register values, which are enabled after the chip is powered on or reset. Reserved registers and bits are shaded. 6-2 Registers (Intelligent Mode) 6.1 Programming Models The LSI53C1510 in intelligent mode contains two programming models: a System (host) Programming Model and a Local Programming Model. The system model includes all necessary hardware registers, shared memory and associated memory addresses from the host viewpoint using system addresses. The Local Programming Model includes all hardware and memory which are private from the system. 6.1.1 System Programming Model The System Programming Model consists of PCI Configuration Registers, Host Interface Registers, and a Shared Memory Region. 6.1.2 Local Programming Model The Local Programming Model consists of ARM Registers, Protocol Engine Registers, and Local Memory Regions. Programming Models 6-3 6.2 PCI Configuration Registers (Intelligent Mode) The PCI Configuration registers, as shown in Table 6.1, are accessed by performing a configuration read/write to the device with its IDSEL pin asserted and the appropriate value in AD[10:8] during the address phase of the transaction. All PCI compliant devices, such as the LSI53C1510, must support the Vendor ID, Device ID, Command, and Status registers. Support of other PCI compliant registers is optional. In the LSI53C1510, registers that are not supported are not writable and return all zeros when read. Only those registers and bits that are currently supported by the LSI53C1510 are described in this chapter. Reserved bits should not be accessed. Reserved registers and bits are shaded. Table 6.1 PCI Configuration Register Map 31 16 15 Device ID Status Vendor ID Command Class Code BIST (Built-In Self Test) Header Type Latency Timer Revision ID (Rev ID) 0x08 6-8 Cache Line Size 0x0C 6-9 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C 0x40 6-11 6-12 6-12 6-12 6-12 6-12 6-12 6-12 6-13 6-14 6-14 6-14 6-16 0x44 6-17 Base Address Register Zero (I/O) Base Address Register One (Shared MEMORY) Reserved Reserved Reserved Reserved Reserved Subsystem ID Subsystem Vendor ID Expansion ROM Base Address Reserved Capabilities Pointer Reserved Max_Lat Min_Gnt Interrupt Pin Interrupt Line Power Management Capabilities (PMC) Next Item Pointer Capability ID Bridge Support ExtenData Power Management Control/Status (PMCSR) sions (PMCSR_BSE) 6-4 Registers (Intelligent Mode) 0 Address Page 0x00 6-5 0x04 6-5 Registers: 0x00–0x01 Vendor ID Read Only 15 0 VID 0 0 0 VID 1 0 0 0 0 0 0 0 0 0 0 0 0 Vendor ID [15:0] This 16-bit register identifies the manufacturer of the device. The Vendor ID is 0x1000. Registers: 0x02–0x03 Device ID Read Only 15 0 DID 0 0 0 DID 0 0 0 0 0 0 0 0 1 0 0 0 0 Device ID [15:0] This 16-bit register identifies the particular device. The Device ID is 0x10. Registers: 0x04–0x05 Command Read/Write 15 9 R 0 0 0 0 0 0 0 8 7 6 5 4 3 SE R EPER R WIE R 0 0 0 0 0 0 2 1 0 EBM EMS EIS 0 0 0 The Command register provides coarse control over a device’s ability to generate and respond to PCI cycles. When a zero is written to this register, the LSI53C1510 is logically disconnected from the PCI bus for all accesses except configuration accesses. PCI Configuration Registers (Intelligent Mode) 6-5 6-6 R Reserved SE SERR/ Enable 8 This bit enables the SERR/ driver. SERR/ is disabled when this bit is zero and enabled when the bit is one. The default value of this bit is zero. This bit and bit 6 must be set to report address parity errors. R Reserved EPER Enable Parity Error Response 6 This bit allows the LSI53C1510 to detect parity errors on the PCI bus and report these errors to the system. Only data parity checking is enabled and disabled with this bit. The LSI53C1510 always generates parity for the PCI bus. R Reserved WIE Write and Invalidate Enable 4 This bit allows the LSI53C1510 to generate write and invalidate commands on the PCI bus. R Reserved EBM Enable Bus Mastering 2 This bit controls the ability of the LSI53C1510 to act as a master on the PCI bus. A value of zero disables this device from generating PCI bus master accesses. A value of one allows the LSI53C1510 to behave as a bus master. The device must be a bus master in order to fetch SCRIPTS instructions and transfer data. EMS Enable Memory Space 1 This bit controls the ability of the LSI53C1510 to respond to Memory space accesses. A value of zero disables the device response. A value of one allows the LSI53C1510 to respond to Memory Space accesses. EIS Enable I/O Space 0 This bit controls the LSI53C1510 response to I/O space accesses. A value of zero disables the device response. A value of one allows the LSI53C1510 to respond to I/O space accesses. Registers (Intelligent Mode) [15:9] 7 5 3 Registers: 0x06–0x07 Status Read/Write 15 14 13 12 DPE SSE RMA RTA 0 0 0 0 11 10 R 0 9 DT 0 8 7 DPR 0 0 5 R 0 0 4 3 0 NC 0 1 R 0 0 0 0 The Status register is used to record status information for PCI bus related events. Reads to this register behave normally. Writes are slightly different in that bits can be cleared, but not set. A bit is cleared whenever the register is written, and the data in the corresponding bit location is a one. For instance, to clear bit 15 and not affect any other bits, write the value 0x8000 to the register. DPE Detected Parity Error (from Slave) 15 This bit is set by the LSI53C1510 whenever it detects a data parity error, even if data parity error handling is disabled. SSE Signaled System Error 14 The LSI53C1510 sets this bit whenever it asserts the SERR/ signal. RMA Received Master Abort (from Master) 13 A master device should set this bit whenever its transaction (except for Special Cycle) is terminated with Master Abort. RTA Received Target Abort (from Master) A master device should set this bit whenever its transaction is terminated by target abort. PCI Configuration Registers (Intelligent Mode) 12 6-7 R Reserved DT DEVSEL/Timing [10:9] These bits encode the timing of DEVSEL/. These bits are read only and should indicate the slowest time that a device asserts DEVSEL/ for any bus command except Configuration Read and Configuration Write. The LSI53C1510 supports a value of 01b. DPR 11 0, 0 fast 0, 1 medium 1, 0 slow 1, 1 reserved Data Parity Error Reported This bit is set when the following conditions are met: 8 • The bus agent asserted PERR/ itself or observed PERR/ asserted and; • The agent setting this bit acted as the bus master for the operation in which the error occurred and; • The Parity Error Response bit in the Command register is set. R Reserved [7:5] NC New Capabilities 4 A value of one implements a list of extended capabilities. R Reserved [3:0] Register: 0x08 Revision ID (Rev ID) Read Only 7 0 RID 0 RID 6-8 0 0 0 0 0 0 0 Revision ID [7:0] This register specifies a device specific revision identifier. This silicon version of the LSI53C1510 is set to 0x00 for Rev A silicon. Registers (Intelligent Mode) Registers: 0x09–0x0B Class Code Read Only 23 0 CC 0 0 0 0 1 1 1 0 0 0 CC 0 0 1 1 1 0 0 0 0 0 1 1 1 0 Class Code [23:0] This 24-bit register is used to identify the generic function of the device. The upper byte of this register is a base class code, the middle byte is a subclass code, and the lower byte identifies a specific register level programming interface. The value of this register is 0x0E0000, which identifies an I2O IOP (LSI53C1510 in intelligent mode). Register: 0x0C Cache Line Size Read/Write 7 0 CLS 0 CLS 0 0 0 0 0 0 0 Cache Line Size [7:0] This register specifies the system cache line size in units of 32-bit words. The value in this register is used by the device to determine whether to use Write and Invalidate or Write commands for performing write cycles, and whether to use Memory Read, Memory Read Line, or Memory Read Multiple commands for performing read cycles as a bus master. Devices participating in the caching protocol use this field to know when to retry burst accesses at cache line boundaries. These devices can ignore the PCI cache support lines (SDONE and SB0/) when this register is set to 0. If this register is programmed to a number which is not a power of 2, the device will not use PCI performance commands to perform data transfers. PCI Configuration Registers (Intelligent Mode) 6-9 Register: 0x0D Latency Timer Read/Write 7 0 LT 0 0 LT 0 0 0 0 0 0 Latency Timer [7:0] The Latency Timer register specifies, in units of PCI bus clocks, the value of the Latency Timer for this PCI bus master. The SCSI functions of the LSI53C1510 support this timer. All eight bits are writable, allowing latency values of 0–255 PCI clocks. Use the following equation to calculate an optimum latency value for the SCSI functions of the LSI53C1510. Latency = 2 + (Burst Size * (typical wait states + 1)) Values greater than optimum are also acceptable. Register: 0x0E Header Type Read Only 7 0 HT 0 HT 6-10 0 0 0 0 0 0 0 Header Type [7:0] This 8-bit register identifies the layout of bytes 0x10 through 0x3F in configuration space and also whether or not the device contains multiple functions. In intelligent mode, the LSI53C1510 is a single function controller, therefore, the value of this register is 0x00. Registers (Intelligent Mode) Register: 0x0F BIST (Built-In Self Test) Read/Write 7 6 BC SB 0 0 5 4 3 0 R CC 0 0 0 0 0 0 BC BIST Capable 7 Should return a one if the device implements a BIST, a zero if it does not. SB Start BIST 6 Writing a one into this bit starts the device’s BIST. The device resets this bit automatically upon completion. Software should fail the device if the BIST does not complete within two seconds. R Reserved CC Completion Code [3:0] A value of zero indicates successful completion, while a nonzero result indicates a device specific error. [5:4] Registers: 0x10–0x13 Base Address Register Zero (I/O) Read/Write 31 0 BARZ 0 0 0 0 0 0 0 0 0 BARZ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Base Address Register Zero - I/O [31:0] This base address register is used to map the operating register set into I/O space. The LSI53C1510 requires 256 bytes of I/O space for this base address register. This register has bit zero hardwired to one. Bit 1 is reserved and returns a zero on all reads, and the other bits are used to map the device into I/O space. For detailed information on the operation of this register, refer to the PCI 2.1 Specification. PCI Configuration Registers (Intelligent Mode) 6-11 Registers: 0x14–0x17 Base Address Register One (Shared MEMORY) Read/Write 31 0 BARO[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 BARO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 MEMORY Base Address Register One [31:0] This base address register map indicates width (32-bit) and location of memory required by the device and its size is programmable from 1 K (210) through 128 M (227) bytes in steps of powers of 2. This memory is specified as nonprefetchable due to the messaging FIFOs. The default size is 128 K. Registers: 0x18–0x2B Reserved Registers: 0x2C–0x2D Subsystem Vendor ID Read Only 15 0 SVID 0 SVID 6-12 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 Subsystem Vendor ID [15:0] This 16-bit register is used to uniquely identify the vendor manufacturing the add-in board or subsystem where this PCI device resides. It provides a mechanism for an add-in card vendor to distinguish its cards from another vendor’s cards, even if the cards have the same PCI controller installed on them (and therefore the same Vendor ID and Device ID). The ARM programs this 16-bit value at startup or reset time. Registers (Intelligent Mode) Registers: 0x2E–0x2F Subsystem ID Read Only 15 0 SID 0 0 0 1 SID 0 0 0 0 0 0 0 0 0 0 0 0 Subsystem ID [15:0] This 16-bit register is used to uniquely identify the add-in board or subsystem where this PCI device resides. It provides a mechanism for an add-in card vendor to distinguish its cards from one another even if the cards have the same PCI controller installed on them (and therefore the same Vendor ID and Device ID). The ARM programs this 16-bit value at startup or reset time. Registers: 0x30–0x33 Expansion ROM Base Address Read/Write 31 0 ERBA 0 0 0 0 0 0 0 0 0 ERBA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Expansion ROM Base Address [31:0] This register indicates the location of expansion ROM device and is programmable from 16 K (214) through 4 (222) Mbytes in steps of powers of 2 (using external pin pull-up options on the external memory address (MEM_ADDR) bits [3:0]). PCI Configuration Registers (Intelligent Mode) 6-13 Register: 0x34 Capabilities Pointer Read Only 7 0 CP 0 0 CP 0 0 0 1 0 0 Capabilities Pointer [7:0] This register indicates that the first extended capability register is located at offset 0x40 in the PCI Configuration. Registers: 0x35–0x3B Reserved Register: 0x3C Interrupt Line Read/Write 7 0 IL 0 IL 6-14 0 0 0 0 0 0 0 Interrupt Line [7:0] This register is used to communicate interrupt line routing information. POST software writes the routing information into this register as it configures the system. The value in this register tells which input of the system interrupt controller(s) the device’s interrupt pin is connected to. Values in this register are specified by system architecture. Registers (Intelligent Mode) Register: 0x3D Interrupt Pin Read Only 7 0 IP 0 0 IP 0 0 0 0 0 1 Interrupt Pin [7:0] This register tells which interrupt pin the device uses. Its value is set to 0x01. Register: 0x3E Min_Gnt Read Only 7 0 MG 0 0 MG 0 1 1 1 1 0 Min_Gnt [7:0] This register is used to specify the desired settings for latency timer values. Min_Gnt is used to specify how long a burst period the device needs. The value specified in these registers is in units of 0.25 microseconds. The LSI53C1510 sets this register to 0x1E. Register: 0x3F Max_Lat Read Only 7 0 ML 0 ML 0 0 0 1 0 0 0 Max_Lat [7:0] This register is used to specify the desired settings for latency timer values. Max_Lat is used to specify how often the device needs to gain access to the PCI bus. PCI Configuration Registers (Intelligent Mode) 6-15 The value specified in these registers is in units of 0.25 microseconds. The LSI53C1510 SCSI function sets this register to 0x08. Register: 0x40 Capability ID Read Only 7 0 CID 0 0 0 CID 0 0 0 0 1 Cap_ID Bits [7:0] identify this register as a PCI power management register (0x01). [7:0] Register: 0x41 Next Item Pointer Read Only 7 0 NIP 0 0 0 NIP 0 0 0 0 0 Next_Item_Ptr [7:0] The LSI53C1510 has these bits set to zero indicating PCI does not have any further PCI extended capabilities registers. Registers: 0x42–0x43 Power Management Capabilities (PMC) Read Only 15 11 PMES[4:0] 0 0 0 PMES[4:0] 6-16 10 9 8 D2S D1S 0 0 1 0 6 R 0 0 5 4 3 2 DSI APS PMEC 0 0 0 0 0 VER[2:0] 0 0 1 PME_Support [15:11] Bits [15:11] define the power management states in which the LSI53C1510 will assert the PME pin. These bits are all set to zero. Registers (Intelligent Mode) D2S D2_Support D2 power management state is not supported. 10 D1S D1_Support D1 power management state is not supported. 9 R Reserved DSI Device Specific Initialization 5 This bit is a device specific initialization bit and is set to zero to indicate that no special initialization is required. APS Auxiliary Power Source This bit is set to zero and indicates that an auxiliary power source is not needed for the LSI53C1510. 4 PMEC PME Clock Bit 3 is set to zero and indicates that no PCI clock is required to assert the PME pin. 3 VER[2:0] Version [2:0] These bits indicate the version of the PCI Power Management Specification the LSI53C1510 complies to version 1.0. [8:6] Registers: 0x44–0x45 Power Management Control/Status (PMCSR) Read/Write 15 14 13 12 PST DSCL[1:0] 0 0 0 9 DSLT 0 0 0 8 7 2 PEN 0 0 R 0 0 0 0 PWS[1:0] 0 0 0 0 0 PST PME_Status 15 Bit 15 defines if the LSI53C1510 has generated a Power Management Event. DSCL[1:0] Data_Scale [14:13] Bits [14:13] are not supported in the LSI53C1510. DSLT Data_Select [12:9] Bits [12:9] are not supported in the LSI53C1510. PEN PME_Enable Bit 8 is not supported in the LSI53C1510. PCI Configuration Registers (Intelligent Mode) 8 6-17 R Reserved [7:2] PWS[1:0] Power State [1:0] Bits [1:0] are used to determine the current power state of the LSI53C1510. They are also used to set the LSI53C1510 to a new power state. Power states are defined as: 00b00 D0 0b11 D3 hot Register: 0x46 Bridge Support Extensions (PMCSR_BSE) Read Only 7 0 BSE 0 0 BSE 0 0 0 0 0 0 Bridge Support Extensions [7:0] Bits [7:0] are not supported and will return 0x00 when read. Register: 0x47 Data Read Only 7 0 DATA 0 DATA 6-18 0 0 0 0 0 0 0 Data [7:0] Bits [7:0] are not supported and will return 0x00 when read. Registers (Intelligent Mode) 6.3 Host Interface Registers (Intelligent Mode) The host interface contains the following registers as shown in Table 6.2. Reserved registers and bits are shaded. Table 6.2 31 LSI53C1510 Host Interface Register Map 16 15 DiagINT1 WRSEQ1 DIAG1 Test Base Address1 Reserved Reserved Reserved Reserved Host Doorbell Reserved Reserved Reserved Reply Interrupt Status Reply Interrupt Mask Reserved Reserved Request Free List FIFO (read only), Request Post List FIFO (write only)2 Reply Post List FIFO (read only), Reply Free List FIFO (write only)2 0 Address 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C 0x40 0x44 Page 6-20 6-21 6-22 6-23 6-23 6-23 6-23 6-23 6-24 6-24 6-24 6-24 6-25 6-25 6-26 6-26 6-26 6-26 1. These registers are for diagnostic or test use only. 2. Write access to the Request Post List and Reply Free List FIFOs that are less than 32 bits are ignored. Host Interface Registers (Intelligent Mode) 6-19 Register: 0x00 DiagINT Read/Write 31 2 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note: 1 0 IEN DiagINT/CLRINT 0 0 This register is intended for diagnostic/test use only. The DiagINT register contains interrupt status and control as described below. The LSI53C1510 Protocol Engine can be configured to generate interrupts using direct F/W control. This register is used to report and enable/mask interrupts to PCI. The normal PCI interrupt reporting mechanism occurs in the Reply Interrupt Status register. This register is provided for diagnostic purposes only. R Reserved [31:2] IEN Interrupt Enable 1 The IEN control bit provides an enable function for the PCI interrupt pin when F/W generated interrupts are selected. In order for the external PCI INT/ interrupt pin to be asserted when F/W generated interrupts are selected, the IEN bit must be set to one. DiagINT/CLRINT Diagnostic Interrupt (read)/ Clear Interrupt (write) 0 The DiagINT status bit indicates that the Protocol Engine is alerting the host of an interrupt condition. When the F/W generated interrupt source is selected, writing a one to bit 0 of this register will clear the F/W generated interrupt. This interrupt status bit is not normally used except for diagnostic purposes. 6-20 Registers (Intelligent Mode) Register: 0x04 WRSEQ Write Only 31 4 R 0 0 0 0 0 0 0 0 0 0 0 Note: 0 0 0 3 0 KEY_VALUE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 This register is intended for diagnostic/test use only. The WRSEQ register is used to enable write accesses to the DIAG register. In order to prevent inadvertent access, the DIAG register cannot be written to unless a specific sequence of data is written to the WRSEQ register. The WRSEQ register is write only. R Reserved [31:4] KEY_VALUE KEY_VALUE [3:0] A sequence of five data writes must be written into the KEY_VALUE field of the WRSEQ register in order to enable writes to the DIAG register. Any data value written out that does not match the expected sequence value will cause the WRSEQ register to restart by looking for the first sequence value. The required data sequence is: 0x4, 0xB, 0x2, 0x7, 0xD After the last value (0xD) is written, the DIAG register may be written to until another write to the WRSEQ register occurs of any value. A bit is provided within the DIAG register which may be read at any time to determine if write access is enabled for the DIAG register (e.g. to verify that the WRSEQ data sequence was correct or to verify that writes to the DIAG register are disabled). Host Interface Registers (Intelligent Mode) 6-21 Register: 0x08 DIAG Read/Write 31 8 7 6 4 R DWE R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note: 3 2 1 0 TTL_INT RSTA DISARM DMMAP 0 0 0 0 This register is intended for diagnostic/test use only. The register contains low level diagnostic control and status. 6-22 R Reserved DWE DIAG Register Write Enabled (read only) 7 This read only bit when set indicates that write access to the DIAG register may occur. The DWE bit is set when the correct key sequence has been written to the WRSEQ register. R Reserved TTL_INT Select TTL Output for PCI-INTA/ 3 This bit determines whether the LSI53C1510 PCI-INTA/ interrupt pin is configured as a TTL or open drain output. This bit defaults to zero (open drain) on reset. This bit should only be set to one (TTL) during chip testing. RSTA Reset Adapter (write only) 2 This write only bit will cause the Protocol Engine reset controller to generate a soft reset to all LSI53C1510 logic. This bit will be automatically cleared when the soft reset condition is generated. The ARM core will start executing from its Reset Vector when the soft reset condition subsides. DISARM Disable ARM Core 1 The DISARM control bit causes the ARM core, the Instruction Prefetch Unit, the Read Path Control Unit, and the Write Buffer to be held reset. This bit will remain set until cleared by the host. This bit is included to allow low level testing and programming of FLASH memory using a host resident utility. Registers (Intelligent Mode) [31:8] [6:4] DMMAP Diagnostic Memory Map 0 This bit when set causes all PCI accesses to Memory Base 0 address space (except for offsets 0x00–0x7F) to be mapped to internal local bus accesses. This allows Host utilities the capability to read or write any arbitrary internal local address. This is useful for low level testing and for programming FLASH memory using host resident utilities. To form an internal local address, the lower 13 bits of the PCI address are combined with the contents of the Test Base Address register. This gives an 8 Kbyte window of addressability into local address space at any one time. Register: 0x0C Test Base Address Read/Write 31 13 12 0 TBA 0 0 0 0 0 0 0 0 0 0 R 0 Note: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 This register is intended for diagnostic/test use only. TBA Test Base Address [31:13] The TBA Register is used to provide address bits [31:13] of the local address during diagnostic host<->local accesses (the lower 13 address bits come directly from the host address). R Reserved [12:0] Registers: 0x10–0x1F Reserved Host Interface Registers (Intelligent Mode) 6-23 Register: 0x20 Host Doorbell Read/Write 31 0 HD 0 0 0 0 0 0 0 0 0 0 0 HD 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Host Doorbell [31:0] This is a 32-bit inbound doorbell register accessible by the host. All 32 bits of the register are read/write by a PCI master, although the PCI master can only set a bit to one. The PCI master cannot clear a bit to zero. The ARM can read and write all 32 doorbell bits using a locally mapped ARM Doorbell register, although the ARM can only clear a bit to zero. The ARM cannot set a bit to one. Should a PCI master setting operation occur simultaneously with an ARM clearing operation, the clearing operation takes precedence. The default reset state of the doorbell register is all zeros. A read only interrupt status bit is available to the ARM to indicate that any of the 32 doorbell bits are set. A read/write interrupt enable bit is available to the ARM to allow the interrupt status bit to generate an interrupt to the ARM when both the interrupt status bit and the interrupt enable bit are set to one. Registers: 0x24–0x2F Reserved 6-24 0 Registers (Intelligent Mode) Register: 0x30 Reply Interrupt Status Read Only 31 4 R 0 0 0 0 0 0 0 0 3 2 ReplyINT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R 0 0 0 The Reply Interrupt Status register reports interrupt status to PCI. R Reserved [31:4] ReplyINT Reply Message Interrupt 3 This read only bit is set whenever a Posted Reply Message is available for the host to process (ReplyPostFIFO not empty and prefetch of ReplyPostMFA complete). This bit will cause a PCI interrupt to be generated when ReplyIntMask = 0. This is the default interrupt reporting mechanism for the LSI53C1510 Protocol Engine. R Reserved [2:0] Register: 0x34 Reply Interrupt Mask Read/Write 31 4 3 2 0 R ReplyIntMask R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 The Reply Interrupt Mask register masks interrupt reporting to PCI. R Reserved [31:4] ReplyIntMask Reply Message Interrupt Mask 3 This bit masks the PCI interrupt generated by the ReplyPostFIFO not empty condition. When this bit is set to one, the PCI interrupt will not be generated. When this bit is reset to zero, the PCI interrupt will be generated. This bit defaults to one on hard or soft reset. R Reserved Host Interface Registers (Intelligent Mode) [2:0] 6-25 Registers: 0x38–0x3F Reserved Register: 0x40 Request Free List FIFO (Read Only) Request Post List FIFO (Write Only) 31 0 FIFO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Request messages are created by the host to “request” an action by the LSI53C1510. For a complete explanation of how the Request Free/Post List FIFOs are used in the message passing I/O interface, see Section 2.2, “The Host Interface.” Register: 0x44 Reply Post List FIFO (Read Only) Reply Free List FIFO (Write Only) 31 0 FIFO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reply messages are used by the LSI53C1510 to send status information back to the host. For a complete explanation of how the Reply Post/Free List FIFOs are used in the message passing I/O interface, see Section 2.2, “The Host Interface.” 6-26 Registers (Intelligent Mode) 6.4 Shared Memory A region of Shared Memory (LSI53C1510 local memory mapped to System Addresses) is provided to allow the host to write Request Message Frames into. This is the default method (Push model) for Request Message Frame transport, where the host itself copies the Request Message Frame into the LSI53C1510 local memory. The total size of Shared Memory is configured by the Protocol Engine on reset. Supported values are: 32 Kbytes, 64 Kbytes, 128 Kbytes (default), 256 Kbytes, 512 Kbytes, 1 Mbyte, 2 Mbytes, 4 Mbytes, 8 Mbytes, 16 Mbytes, 32 Mbytes, 64 Mbytes, and 128 Mbytes. Address translation between System and Local addresses is performed as illustrated in Figure 6.2. Figure 6.2 Shared Memory Address Translation PCI Memory 0 Address Space 0x00 LSI53C1510 Address Space 0x01000000 Host Interface Registers Offset from PCI Memory 0 Base Address 0x7F 0x80 0x01000080 LSI53C1510 DRAM Address Size of (Shared Memory) -1 Shared Memory LSI53C1510 DRAM Memory 0x01000000 + Size of (Shared Memory) -1 6-27 6-28 Registers (Intelligent Mode) 3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc 4.333 pc Chapter 7 Specifications 12 pc 12.938 pc 13.851 pc This chapter specifies the LSI53C1510 electrical and mechanical characteristics. It is divided into the following sections: • Section 7.1, “DC Characteristics,” page 7-1 • Section 7.2, “TolerANT Technology Electrical Characteristics,” page 7-7 • Section 7.3, “AC Characteristics,” page 7-11 • Section 7.4, “PCI and External Memory Interface Timing Diagrams,” page 7-14 • Section 7.5, “SCSI Timing Diagrams,” page 7-36 • Section 7.6, “Pinouts and Packaging,” page 7-43 7.1 DC Characteristics 34.732 pc This section of the manual describes the LSI53C1510 DC characteristics. Table 7.1 through Table 7.13 give current and voltage specifications. Figure 7.1 and Figure 7.2 are driver schematics. 48.583 pc LSI53C1510 I2O-Ready PCI RAID Ultra2 SCSI Controller 7-1 52.5 pc 3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc 4.333 pc Table 7.1 Absolute Maximum Stress Ratings Symbol Parameter Min Max1 Unit Test Conditions TSTG Storage temperature −55 150 °C – VDD Supply voltage −0.5 5.0 V – VIN Input voltage VSS −0.3 VDD +0.3 V – Input voltage (5 V tolerant pins) VSS −0.3 5.25 V – Latch-up current 150 – mA – Electrostatic discharge – 2K V MIL-STD 883C, Method 3015.7 VIN5V ILP2 ESD3 1. Stresses beyond those listed above may cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any other conditions beyond those indicated in the Operating Conditions section of the manual is not implied. 2. −2 V < VPIN < 8 V. 3. SCSI pins only. Table 7.2 Operating Conditions 44.25 pc Parameter Min Max1 Unit Test Conditions VDD Supply voltage 3.13 3.47 V – IDD Supply current (dynamic) Supply current (static) – 800 1 mA mA – LVD pad current supply – 1.2 A RBIAS = 9.76 kΩ VDD = 3.3 V Operating free air 0 70 °C – Thermal resistance (junction to ambient air) – 14.8 °C/W – Tj Temperature of the die – 110 °C – Tc Temperature of the case – 100 °C – Symbol IDD-SCSI TA θJA 1. Conditions that exceed the operating limits may cause the device to function incorrectly. 48.583 pc 7-2 Specifications 52.5 pc 3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc 4.333 pc Table 7.3 LVD Driver SCSI Signals—SD[15:0]+, SDP[1:0]/, SREQ/, SACK/, SMSG/, SIO/, SCD/, SATN/, SBSY/, SSEL/, SRST/ Symbol Parameter Min Max Units Test Conditions IO+ Source (+) current 7 11 mA Asserted state IO− Sink (−) current −7 −11 mA Asserted state IO+ Source (+) current −3.5 −5.5 mA Negated state IO− Sink (−) current 3.5 5.5 mA Negated state IOZ 3-state leakage −20 20 µA VPIN = 0 V, 3.47 V IOZ (SRST - only) 3-state leakage −500 −50 µA – Notes: VCM = 0.7–1.8 V. RL = 0–110 Ω. Rbias = 9.76 kΩ. Figure 7.1 LVD Driver RL 44.25 pc IO+ 2 + + VCM − IO− RL 2 Table 7.4 Symbol LVD Receiver SCSI Signals—SD[15:0]/, SDP[1:0]/, SREQ/, SACK/, SMSG/, SIO/, SCD/, SATN/, SBSY/, SSEL/, SRST/ Parameter Min Max Units VI LVD receiver voltage asserting 60 – mV VI LVD receiver voltage negating – −60 mV Note:VCM = 0.7–1.8 V 48.583 pc DC Characteristics 7-3 52.5 pc 3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc Figure 7.2 4.333 pc LVD Receiver + VI + 2 VCM + − + − − VI 2 Table 7.5 DIFFSENS SCSI Signal Parameter Min Max Unit Test Conditions1 VIH HVD sense voltage 2.4 5.0 V Note 1 VS LVD sense voltage 0.7 1.9 V Note 1 VIL SE sense voltage VSS −0.3 0.5 V Note 1 IIN Input leakage −10 10 µA VPIN = 0 V, 5.25 V Symbol 44.25 pc − 1. Functional test specified for each mode (VIH, VS, VIL). Table 7.6 Symbol VIN Table 7.7 Symbol CI CIO RBIAS SCSI Signal Parameter Input Voltage Min Max Unit Test Conditions VDD −0.2 – V −125 µA Input Capacitance Parameter Min Max Unit Test Conditions Input capacitance of input pads – 7 pF – Input capacitance of I/O pads – 15 pF – 48.583 pc 7-4 Specifications 52.5 pc 3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc Table 7.8 Symbol 4.333 pc Bidirectional Signals—GPIO0, GPIO1, GPIO2, GPIO3, GPIO4 Parameter Min Max Unit Test Conditions VIH Input high voltage 2.0 5.0 V – VIL Input low voltage VSS −0.3 0.8 V – VOH Output high voltage 2.4 VDD V −8 mA dynamic VOL Output low voltage VSS 0.4 V 8 mA dynamic IOZ 3-state leakage −10 10 µA VPIN = 0 V, 5.25 V Pull-down current 7.5 75 µA – IPULL Table 7.9 Symbol Output Signals—MCE/, MOE/_TESTOUT, MWE/, TDO Parameter Min Max Unit Test Conditions VOH Output high voltage 2.4 VDD V −4 mA dynamic VOL Output low voltage VSS 0.4 V 4 mA dynamic IOZ 3-state leakage −10 10 µA VPIN = 0 V, 5.25 V 44.25 pc Table 7.10 Symbol Bidirectional Signals—AD[31:0], C_BE[7:0]/, FRAME/, IRDY/, TRDY/, DEVSEL/, STOP/, PERR/, PAR Parameters Min Max Unit Test Conditions VIH Input high voltage 0.5 VDD 5.0 V – VIL Input low voltage VSS −0.3 0.3 VDD V – VOH Output high voltage 0.9 VDD – V −500 µA VOL Output low voltage – 0.1 VDD V 1500 µA VOH 5 V tolerant output high voltage 2.4 – V −16 mA VOL 5 V tolerant output low voltage – 0.55 V 16 mA IOZ 3-state leakage −10 10 µA VPIN = 0 V, 5.25 V Pull-down current 7.5 75 µA – IPULL 48.583 pc DC Characteristics 7-5 52.5 pc 3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc Table 7.11 Symbol Input Signals—CLK, GNT/, IDSEL, RST/, SCLK, TCK, TDI, TEST_HSC1, TEST_RSTN, TMS Parameters Min Max Unit Test Conditions VIH Input high voltage 0.5 VDD 5.0 V – VIL Input low voltage VSS −0.3 0.3 VDD V – IIN Input leakage2 −10 10 µA VPIN = 0 V, 5.25 V Pull-down current −75 −7.5 µA – IPULL3 4.333 pc 1. TEST_HSC has a pull-down 2. The Input leakage test does not apply to the TEST_RST/ pin with VPIN = 0 V. 3. Pull-up spec does not apply to: SCLK, CLK, GNT/, IDSEL, and RST/. Table 7.12 Symbol 44.25 pc Output Signals—INTA, INTB Parameters Min Max Unit Test Conditions VOH Output high voltage 0.9 VDD – V −500 µA VOL Output low voltage – 0.1 VDD V 1500 µA VOH 5 V tolerant output high voltage 2.4 – V −16 mA VOL 5 V tolerant output low voltage – 0.55 V 16 mA IOZ 3-state leakage −10 10 µA VPIN = 0 V, 5.25 V Pull-down current −75 −7.5 µA – IPULL Table 7.13 Symbol Output Signal—SERR/ Parameters VOL Output low voltage IOZ 3-state leakage Min Max Unit Test Conditions – 0.1 VDD V 1.5 mA −10 10 µA – 48.583 pc 7-6 Specifications 52.5 pc 3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc 4.333 pc 7.2 TolerANT Technology Electrical Characteristics The LSI53C1510 features TolerANT technology, which includes active negation on the SCSI drivers and input signal filtering on the SCSI receivers. Active negation actively drives the SCSI Request, Acknowledge, Data, and Parity signals HIGH rather than allowing them to be passively pulled up by terminators. Table 7.14 provides electrical characteristics for SE SCSI signals. Figure 7.3 through Figure 7.7 provide reference information for testing SCSI signals. Table 7.14 Symbol 44.25 pc TolerANT Technology Electrical Characteristics for SE SCSI Signals1 Parameter Min Max Units Test Conditions VOH2 Output high voltage 2.0 VDD V IOH = −7 mA VOL Output low voltage VSS 0.5 V IOL = 48 mA VIH Input high voltage 2.0 VDD +0.3 V – VIL Input low voltage VSS −0.3 0.8 V Referenced to VSS VIK Input clamp voltage −0.66 −0.77 V VDD = 4.75; II = −20 mA VTH Threshold, HIGH to LOW 1.0 1.2 V – VTL Threshold, LOW to HIGH 1.4 1.6 V – 300 500 mV – VTH–VTL Hysteresis IOH2 Output high current 2.5 24 mA VOH = 2.5 V IOL Output low current 100 200 mA VOL = 0.5 V IOSH2 Short-circuit output high current – 625 mA Output driving low, pin shorted to VDD supply3 IOSL Short-circuit output low current – 95 mA Output driving high, pin shorted to VSS supply ILH Input high leakage – 20 µA VDD 5%, VPIN = 2.7 V ILL Input low leakage −20 – µA VDD 5%, VPIN = 0 V IPD Power down leakage – 20 µA VDD = 0 V, VPIN = 1.2 V RI Input resistance 20 – MΩ SCSI pins4 CP Capacitance per pin – 15 pF 388 BGA 48.583 pc TolerANT Technology Electrical Characteristics 7-7 52.5 pc 3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc Table 7.14 Symbol TolerANT Technology Electrical Characteristics for SE SCSI Signals1 Parameter Min Max Units Test Conditions tR2 Rise time, 10% to 90% 4.0 18.5 ns Figure 7.3 tF Fall time, 90% to 10% 4.0 18.5 ns Figure 7.3 dVH/dt Slew rate LOW to HIGH 0.15 0.50 V/ns Figure 7.3 dVL/dt Slew rate, HIGH to LOW 0.15 0.50 V/ns Figure 7.3 2 – kV MIL-STD-883C; 3015-7 Latch-up 100 – mA – Filter delay 20 30 ns Figure 7.4 Ultra filter delay 10 15 ns Figure 7.4 Ultra2 filter delay 5 8 ns Figure 7.4 Extended filter delay 40 60 ns Figure 7.4 ESD Electrostatic discharge 4.333 pc 1. These values are guaranteed by periodic characterization; they are not 100% tested on every device. 2. Active negation outputs only: Data, Parity, SREQ/, SACK/. 44.25 pc 3. Single pin only; irreversible damage may occur if sustained for one second. 4. SCSI RESET pin has 10 kΩ pull-up resistor. Figure 7.3 Rise and Fall Time Test Condition 47 Ω 20 pF + − Figure 7.4 2.5 V SCSI Input Filtering t1 VTH REQ/ or ACK/ Input Note: t1 is the input filtering period. 48.583 pc 7-8 Specifications 52.5 pc 3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc 4.333 pc Figure 7.5 Hysteresis of SCSI Receivers 1.1 1.3 Receiving Logic Level 1 0 1.5 1.7 Input Voltage (Volts) Figure 7.6 Input Current as a Function of Input Voltage +40 Input Current (milliAmperes) 44.25 pc +20 14.4 V 8.2 V 0 − 0.7 V HIGH-Z OUTPUT −20 ACTIVE −40 −4 0 4 8 12 16 Input Voltage (Volts) 48.583 pc TolerANT Technology Electrical Characteristics 7-9 52.5 pc 3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc 0 −200 −400 −600 −800 0 4.333 pc Output Current as a Function of Output Voltage 1 2 3 4 Output Voltage (Volts) 5 Output Source Current (milliamperes) Output Sink Current (milliamperes) Figure 7.7 100 80 60 40 20 0 0 1 2 3 4 5 Output Voltage (Volts) 44.25 pc 48.583 pc 7-10 Specifications 52.5 pc 3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc 4.333 pc 7.3 AC Characteristics The AC characteristics described in this section apply over the entire range of operating conditions (refer to the Section 7.1, “DC Characteristics”). Chip timing is based on simulation at worst case voltage, temperature, and processing. Timing was developed with a load capacitance of 50 pF Table 7.15 and Figure 7.8 provide External Clock data. Table 7.15 Symbol t1 t2 44.25 pc t3 t4 External Clock1 Parameter Min Max Units PCI bus clock cycle time 30 DC ns SCSI clock cycle time (SCLK)2 25 60 ns CLK LOW time3 12 – ns SCLK LOW time3 10 36 ns 12 – ns SCLK HIGH time3 10 36 ns CLK slew rate 1 – V/ns SCLK slew rate 1 – V/ns CLK HIGH time3 1. Timing is for an external 40 MHz clock. A quadrupled 40 MHz clock is required for Ultra2 SCSI operation. 2. This parameter must be met to ensure SCSI timing is within specification. 3. Duty cycle not to exceed 60/40. Figure 7.8 External Clock t3 t1 CLK, SCLK t2 t4 48.583 pc AC Characteristics 7-11 52.5 pc 3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc 4.333 pc Table 7.16 and Figure 7.9 provide Reset Input data. Table 7.16 Symbol Reset Input Parameter Min Max Units t1 Reset pulse width 10 – tCLK t2 Reset deasserted setup to CLK HIGH 0 – ns t3 MEM_ADDR setup time to CLK HIGH (for configuring the MEM_ADDR bus only) 20 – ns t4 MEM_ADDR hold time from CLK HIGH (for configuring the MEM_ADDR bus only) 20 – ns Figure 7.9 Reset Input CLK t1 t2 RST/ t3 t4 44.25 pc Valid Data MAD* *When enabled 48.583 pc 7-12 Specifications 52.5 pc 3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc 4.333 pc Table 7.17 and Figure 7.10 provide Interrupt Output data. Table 7.17 Symbol Interrupt Output Parameter Min Max Units t1 CLK HIGH to IRQ/ LOW 2 11 ns t2 CLK HIGH to IRQ/ HIGH 2 11 ns t3 IRQ/ deassertion time 3 – CLK Figure 7.10 Interrupt Output t2 t3 t1 IRQ/ CLK 44.25 pc 48.583 pc AC Characteristics 7-13 52.5 pc 3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc 4.333 pc 7.4 PCI and External Memory Interface Timing Diagrams Figure 7.11 through Figure 7.14 represent signal activity when the LSI53C1510 accesses the PCI bus. This section includes timing diagrams for access to four groups of memory configurations. The first group applies to Target Timing. The second group applies to Initiator Timing. The third group applies to External Memory Timing. Note: Multiple byte accesses to the external memory bus increase the read or write cycle by 11 clocks for each additional byte. Timing diagrams included in this section are: • 44.25 pc • • Target Timing – PCI Configuration Register Read – PCI Configuration Register Write – Operating Registers/SCRIPTS RAM Read, 32-Bit – Operating Registers/SCRIPTS RAM Write, 32-Bit Initiator Timing – Nonburst Opcode Fetch, 32-Bit Address and Data – Burst Opcode Fetch, 32-Bit Address and Data – Back-to-Back Read, 32-Bit Address and Data – Back-to-Back Write, 32-Bit Address and Data – Burst Read, 32-Bit Address and Data – Burst Write, 32-Bit Address and Data External Memory Timing – EDO DRAM Burst Read – FLASH ROM Normal Read Only Mode – FLASH ROM Program/Verify Mode 7.4.1 Target Timing Table 7.18 through Table 7.21 and Figure 7.11 through Figure 7.14 describe Target timing. 48.583 pc 7-14 Specifications 52.5 pc 3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc 4.333 pc Table 7.18 Symbol PCI Configuration Register Read Parameter Min Max Unit t1 Shared signal input setup time 7 – ns t2 Shared signal input hold time 0 – ns t3 CLK to shared signal output valid 2 11 ns Figure 7.11 PCI Configuration Register Read CLK (Driven by System) t1 FRAME/ (Driven by System) t2 t1 AD (Driven by Master-Addr; LSI53C1510-Data) Data Out t2 t1 44.25 pc t3 Addr In C_BE/ (Driven by Master) t2 Byte Enable CMD t2 t3 t1 PAR (Driven by Master-Addr; LSI53C1510-Data) Out In t2 IRDY/ (Driven by Master) t2 t1 t3 TRDY/ (Driven by LSI53C1510) STOP/ (Driven by LSI53C1510) t3 DEVSEL/ (Driven by LSI53C1510) t1 IDSEL (Driven by Master) t2 48.583 pc PCI and External Memory Interface Timing Diagrams 7-15 52.5 pc 3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc Table 7.19 Symbol 4.333 pc PCI Configuration Register Write Parameter Min Max Unit t1 Shared signal input setup time 7 – ns t2 Shared signal input hold time 0 – ns t3 CLK to shared signal output valid 2 11 ns Figure 7.12 PCI Configuration Register Write CLK (Driven by System) t1 FRAME/ (Driven by Master) t2 t1 Addr In t1 t2 AD (Driven by Master) Data In t2 t1 C_BE/ (Driven by Master) t2 Byte Enable CMD 44.25 pc t2 t1 PAR (Driven by Master) t2 t1 t2 IRDY/ (Driven by Master) t3 TRDY/ (Driven by LSI53C1510) STOP/ (Driven by LSI53C1510) t3 DEVSEL/ (Driven by LSI53C1510) t1 IDSEL (Driven by Master) t2 48.583 pc 7-16 Specifications 52.5 pc 3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc Table 7.20 Symbol 4.333 pc Operating Registers/SCRIPTS RAM Read, 32-Bit Parameter Min Max Unit t1 Shared signal input setup time 7 – ns t2 Shared signal input hold time 0 – ns t3 CLK to shared signal output valid 2 11 ns Figure 7.13 Operating Registers/SCRIPTS RAM Read, 32-Bit CLK (Driven by System) t1 FRAME/ (Driven by Master) t2 Addr In t1 AD (Driven by Master-Addr; LSI53C1510-Data) Data Out t1 C_BE/ (Driven by Master) 44.25 pc t2 Byte Enable CMD t2 PAR (Driven by Master-Addr; LSI53C1510-Data) t3 t2 t1 In t3 Out t2 t1 t2 IRDY/ (Driven by Master) t3 TRDY/ (Driven by LSI53C1510) STOP/ (Driven by LSI53C1510) t3 DEVSEL/ (Driven by LSI53C1510) 48.583 pc PCI and External Memory Interface Timing Diagrams 7-17 52.5 pc 3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc Table 7.21 Symbol 4.333 pc Operating Registers/SCRIPTS RAM Write, 32-Bit Parameter Min Max Unit t1 Shared signal input setup time 7 – ns t2 Shared signal input hold time 0 – ns t3 CLK to shared signal output valid 2 11 ns Figure 7.14 Operating Registers/SCRIPTS RAM Write, 32-Bit CLK (Driven by System) t1 FRAME/ (Driven by Master) t2 Addr In t1 AD (Driven by Master) Data In t1 C_BE/ (Driven by Master) 44.25 pc t2 t1 t2 Byte Enable CMD t2 t2 t1 PAR (Driven by Master) t1 In In t2 t2 IRDY/ (Driven by Master) t1 t2 t3 TRDY/ (Driven by LSI53C1510) STOP/ (Driven by LSI53C1510) t3 DEVSEL/ (Driven by LSI53C1510) 48.583 pc 7-18 Specifications 52.5 pc 3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc 4.333 pc This page intentionally left blank. 44.25 pc 48.583 pc PCI and External Memory Interface Timing Diagrams 7-19 52.5 pc 3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc 4.333 pc 7.4.2 Initiator Timing Table 7.22 through Table 7.27 and Figure 7.15 through Figure 7.20 describe Initiator timing. Table 7.22 Symbol Nonburst Opcode Fetch, 32-Bit Address and Data Parameter Min Max Unit t1 Shared signal input setup time 7 – ns t2 Shared signal input hold time 0 – ns t3 CLK to shared signal output valid 2 11 ns t4 Side signal input setup time 10 – ns t5 Side signal input hold time 0 – ns t6 CLK to side signal output valid – 12 ns 44.25 pc 48.583 pc 7-20 Specifications 52.5 pc 3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc 4.333 pc Figure 7.15 Nonburst Opcode Fetch, 32-Bit Address and Data CLK (Driven by System) REQ/ (Driven by LSI53C1510) GNT/ (Driven by Arbiter) t6 t4 t5 FRAME/ (Driven by LSI53C1510) t3 AD (Driven by LSI53C1510-Addr; Target-Data) Data In t1 Addr Out Addr Out t2 t3 C_BE/ (Driven by LSI53C1510) CMD Byte Enable t3 CMD Byte Enable t1 PAR (Driven by LSI53C1510)Addr; Target-Data) 44.25 pc IRDY/ (Driven by LSI53C1510) Data In t3 t2 t3 t1 TRDY/ (Driven by Target) t2 STOP/ (Driven by Target) t2 DEVSEL/ (Driven by Target) t1 48.583 pc PCI and External Memory Interface Timing Diagrams 7-21 52.5 pc 3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc Table 7.23 Symbol 4.333 pc Burst Opcode Fetch, 32-Bit Address and Data Parameter Min Max Unit t1 Shared signal input setup time 7 – ns t2 Shared signal input hold time 0 – ns t3 CLK to shared signal output valid 2 11 ns t4 Side signal input setup time 10 – ns t5 Side signal input hold time 0 – ns t6 CLK to side signal output valid – 12 ns 44.25 pc 48.583 pc 7-22 Specifications 52.5 pc 3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc 4.333 pc Figure 7.16 Burst Opcode Fetch, 32-Bit Address and Data CLK (Driven by System) REQ/ (Driven by LSI53C1510) GNT/ (Driven by Arbiter) t6 t4 t5 FRAME/ (Driven by LSI53C1510) AD (Driven by LSI53C1510Addr; Target-Data) C_BE/ (Driven by LSI53C1510) PAR (Driven by LSI53C1510Addr; Target-Data) 44.25 pc IRDY/ (Driven by LSI53C1510) TRDY/ (Driven by Target) t3 t1 t3 Data In Data In Addr Out t2 t3 Byte Enable CMD t3 t1 Out In t3 In t2 t3 t1 t2 STOP/ (Driven by Target) t2 DEVSEL/ (Driven by Target) t1 48.583 pc PCI and External Memory Interface Timing Diagrams 7-23 52.5 pc 3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc Table 7.24 Symbol 4.333 pc Back-to-Back Read, 32-Bit Address and Data Parameter Min Max Unit t1 Shared signal input setup time 7 – ns t2 Shared signal input hold time 0 – ns t3 CLK to shared signal output valid 2 11 ns t4 Side signal input setup time 10 – ns t5 Side signal input hold time 0 – ns t6 CLK to side signal output valid – 12 ns 44.25 pc 48.583 pc 7-24 Specifications 52.5 pc 3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc 4.333 pc Figure 7.17 Back-to-Back Read, 32-Bit Address and Data CLK (Driven by System) t6 REQ/ (Driven by LSI53C1510) GNT/ (Driven by Arbiter) FRAME/ (Driven by LSI53C1510) AD (Driven by LSI53C1510Addr; Target-Data) C_BE/ (Driven by LSI53C1510) PAR (Driven by LSI53C1510Addr; Target-Data) 44.25 pc IRDY/ (Driven by LSI53C1510) t5 t4 t3 Data In t1 t3 Data In Addr Out Addr Out t2 t3 CMD CMD BE t3 BE t1 Out In Out In t2 t3 t1 TRDY/ (Driven by Target) t2 STOP/ (Driven by Target) t2 DEVSEL/ (Driven by Target) t1 48.583 pc PCI and External Memory Interface Timing Diagrams 7-25 52.5 pc 3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc Table 7.25 Symbol 4.333 pc Back-to-Back Write, 32-Bit Address and Data Parameter Min Max Unit t1 Shared signal input setup time 7 – ns t2 Shared signal input hold time 0 – ns t3 CLK to shared signal output valid 2 11 ns t4 Side signal input setup time 10 – ns t5 Side signal input hold time 0 – ns t6 CLK to side signal output valid – 12 ns 44.25 pc 48.583 pc 7-26 Specifications 52.5 pc 3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc 4.333 pc Figure 7.18 Back-to-Back Write, 32-Bit Address and Data CLK (Driven by System) t6 REQ/ (Driven by LSI53C1510) GNT/ (Driven by Arbiter) FRAME/ (Driven by LSI53C1510) AD (Driven by LSI53C1510Addr; Target-Data) C_BE/ (Driven by LSI53C1510) PAR (Driven by LSI53C1510) t5 t4 t3 t1 t3 t3 Addr Data Out Out Addr Data Out Out t2 t3 CMD t3 CMD BE BE t3 t3 t3 44.25 pc IRDY/ (Driven by LSI53C1510) t1 TRDY/ (Driven by Target) t2 STOP/ (Driven by Target) t1 t2 DEVSEL/ (Driven by Target) 48.583 pc PCI and External Memory Interface Timing Diagrams 7-27 52.5 pc 3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc Table 7.26 Symbol 4.333 pc Burst Read, 32-Bit Address and Data Parameter Min Max Unit t1 Shared signal input setup time 7 – ns t2 Shared signal input hold time 0 – ns t3 CLK to shared signal output valid 2 11 ns 44.25 pc 48.583 pc 7-28 Specifications 52.5 pc 3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc 4.333 pc Figure 7.19 Burst Read, 32-Bit Address and Data CLK (Driven by System) GPIO0_FETCH/ (Driven by LSI53C1510) GPIO1_MASTER/ (Driven by LSI53C1510) REQ/ (Driven by LSI53C1510) GNT/ (Driven by Arbiter) FRAME/ (Driven by LSI53C1510) Data In AD (Driven by LSI53C151044.25 pc Addr; Target-Data) C_BE/ (Driven by LSI53C1510) Addr Out t3 CMD PAR (Driven by LSI53C1510Addr; Target-Data) BE Out In In IRDY/ (Driven by LSI53C1510) t1 TRDY/ (Driven by Target) t2 STOP/ (Driven by Target) t2 DEVSEL/ (Driven by Target) 48.583 pc PCI and External Memory Interface Timing Diagrams 7-29 52.5 pc 3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc Table 7.27 Symbol 4.333 pc Burst Write, 32-Bit Address and Data Parameter Min Max Unit t1 Shared signal input setup time 7 – ns t2 Shared signal input hold time 0 – ns t3 CLK to shared signal output valid 2 11 ns 44.25 pc 48.583 pc 7-30 Specifications 52.5 pc 3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc 4.333 pc Figure 7.20 Burst Write, 32-Bit Address and Data CLK (Driven by System) REQ/ (Driven by LSI53C1510) GNT/ (Driven by Arbiter) FRAME/ (Driven by LSI53C1510) AD (Driven by LSI53C1510) Addr Out C_BE/ (Driven by LSI53C1510) CMD Data Out Data Out BE t3 44.25 pc PAR (Driven by LSI53C1510) IRDY/ (Driven by LSI53C1510) t1 TRDY/ (Driven by Target) t2 STOP/ (Driven by Target) t1 DEVSEL/ (Driven by Target) t2 7.4.3 External Memory Timing Table 7.28 and Figure 7.21 through Figure 7.23 describe DRAM timing parameters. 48.583 pc PCI and External Memory Interface Timing Diagrams 7-31 52.5 pc 3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc 4.333 pc Table 7.28 Symbol 44.25 pc DRAM Timing Parameters (Using 50 ns Extended Data Out Mode) Parameter Min Max Unit Taa Access from column address 25 – ns Tasc Common address setup 0 – ns Tasr Row address setup 0 – ns Tcac Access time from CAS/ – 15 ns Tcah Column address hold 8 – ns Tcas CAS/ LOW 10 10,000 ns Tcp CAS/ precharge 8 – ns Tcpa Access time from CAS/ HIGH 30 – ns Tcrp CAS/ to RAS/ precharge 5 – ns Tcsh RAS/ LOW to CAS/ HIGH 40 – ns Tdh DRAM data in hold 8 – ns Tds DRAM data in setup 0 – ns Tpc EDO page cycle time 25 – ns Trac Access time for RAS/ – 50 ns Trad RAS/ to column address 9 25 ns Trah Row address hold 9 – ns Tral Column address lead time to rising RAS/ 25 – ns RAS/ LOW, EDO fast page mode 50 100,000 ns Trc Random access cycle time 90 – ns Trcd RAS/ to CAS/ delay 11 35 ns Trp RAS/ precharge 30 – ns Trsh RAS/ hold time (CAS/ LOW to RAS/ HIGH) 13 – ns Trasp 48.583 pc 7-32 Specifications 52.5 pc 3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc 4.333 pc Figure 7.21 EDO DRAM Burst Read 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 M_CLK B_CLK D_SEL B_ A MEM_RA A0+1 A0 ROW 0 COL 0 COL 0+1 A0+2 A0+3 A0+4 COL 0+2 COL 0+3 COL 0+4 D0+1 D0+2 D0+3 nRAS nCAS nOE 44.25 pc MEM_DO B_D D0 D0 D0+1 D0+2 D0+3 WAIT 48.583 pc PCI and External Memory Interface Timing Diagrams 7-33 52.5 pc 7-34 Specifications 7 8 9 10 ADR-1 B_D[31:0] nWAIT DRAM_DATA [31:0] MEM_WE/ MEM_OEN_TESTOUT MEM_CEO/ flash_oe_dly=0(nom) flash_cs_dly=0(nom) 6 11 12 byte_rd_cycle ADR-1 5 MEM_ADDR [12:0] 4 ADR-1 3 DRAM_ADDR [12:0] B_ A[31:0] 2 13 14 15 D-1 D-1 16 17 18 19 20 22 ADR-2 ADR-2 ADR-2 21 23 24 25 10.25 pc D_SEL 1 44.25 pc B_CLK M_CLK 3.75 pc 11.25 pc 38.25 pc 34.5 pc Figure 7.22 FLASH ROM Normal Read Only Mode 4.333 pc 48.583 pc 52.5 pc 6 8 flash_cs_dly 7 9 ADR-1 10 11 PCI and External Memory Interface Timing Diagrams B_D[31:0] nWAIT DRAM_DATA [31:0] MEM_WE/ MEM_OEN_TESTOUT MEM_CEO/ flash_ce_dly 12 13 byte_rd_cycle ADR-1 5 MEM_ADDR [12:0] 4 ADR-1 3 DRAM_ADDR [12:0] B_ A[31:0] 2 14 15 D-1 D-1 16 17 18 20 22 ADR-2 ADR-2 ADR-2 21 byte_oe_addr_x 19 23 24 25 10.25 pc D_SEL B_CLK 1 44.25 pc M_CLK 3.75 pc 11.25 pc 38.25 pc 34.5 pc Figure 7.23 FLASH ROM Program/Verify Mode 4.333 pc 48.583 pc 7-35 52.5 pc 3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc 4.333 pc 7.5 SCSI Timing Diagrams Table 7.29 through Table 7.39 and Figure 7.24 through Figure 7.28 describe SCSI timing data. Table 7.29 Symbol Initiator Asynchronous Send Parameter Min Max Units t1 SACK/ asserted from SREQ/ asserted 5 – ns t2 SACK/ deasserted from SREQ/ deasserted 5 – ns t3 Data setup to SACK/ asserted 55 – ns t4 Data hold from SREQ/ deasserted 20 – ns Figure 7.24 Initiator Asynchronous Send SREQ/ n+1 t1 44.25 pc t2 SACK/ t3 SD[15:0]/ SDP[1:0]/ n+1 n t4 Valid n Valid n + 1 48.583 pc 7-36 Specifications 52.5 pc 3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc 4.333 pc Table 7.30 Symbol Initiator Asynchronous Receive Parameter Min Max Units t1 SACK/ asserted from SREQ/ asserted 5 – ns t2 SACK/ deasserted from SREQ/ deasserted 5 – ns t3 Data setup to SREQ/ asserted 0 – ns t4 Data hold from SACK/ asserted 0 – ns Figure 7.25 Initiator Asynchronous Receive SREQ/ n n+1 t1 SACK/ n t3 SD[15:0]/, SDP[1:0]/ t2 n+1 t4 Valid n Valid n + 1 44.25 pc 48.583 pc SCSI Timing Diagrams 7-37 52.5 pc 3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc Table 7.31 Symbol 4.333 pc Target Asynchronous Send Parameter Min Max Units t1 SREQ/ deasserted from SACK/ asserted 5 – ns t2 SREQ/ asserted from SACK/ deasserted 5 – ns t3 Data setup to SREQ/ asserted 55 – ns t4 Data hold from SACK/ asserted 20 – ns Figure 7.26 Target Asynchronous Send SREQ/ n n+1 t1 SACK/ t2 n t3 SD[15:0]/, SDP[1:0]/ n+1 t4 Valid n Valid n + 1 44.25 pc Table 7.32 Symbol Target Asynchronous Receive Parameter Min Max Units t1 SREQ/ deasserted from SACK/ asserted 5 – ns t2 SREQ/ asserted from SACK/ deasserted 5 – ns t3 Data setup to SACK/ asserted 0 – ns t4 Data hold from SREQ/ deasserted 0 – ns Figure 7.27 Target Asynchronous Receive SREQ/ n n+1 t1 SACK/ t2 t3 SD[15:0]/, SDP[1:0]/ n+1 n t4 Valid n Valid n + 1 48.583 pc 7-38 Specifications 52.5 pc 3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc Table 7.33 Symbol 4.333 pc SCSI-1 Transfers (SE 5.0 Mbytes) Parameter Min Max Units t1 Send SREQ/ or SACK/ assertion pulse width 90 – ns t2 Send SREQ/ or SACK/ deassertion pulse width 90 – ns t1 Receive SREQ/ or SACK/ assertion pulse width 90 – ns t2 Receive SREQ/ or SACK/ deassertion pulse width 90 – ns t3 Send data setup to SREQ/ or SACK/ asserted 55 – ns t4 Send data hold from SREQ/ or SACK/ asserted 100 – ns t5 Receive data setup to SREQ/ or SACK/ asserted 0 – ns t6 Receive data hold from SREQ/ or SACK/ asserted 45 – ns Table 7.34 Symbol SCSI-1 Transfers (Differential 4.17 Mbytes) Parameter Min Max Units 44.25 pc t1 Send SREQ/ or SACK/ assertion pulse width 96 – ns t2 Send SREQ/ or SACK/ deassertion pulse width 96 – ns t1 Receive SREQ/ or SACK/ assertion pulse width 84 – ns t2 Receive SREQ/ or SACK/deassertion pulse width 84 – ns t3 Send data setup to SREQ/ or SACK/ asserted 65 – ns t4 Send data hold from SREQ/ or SACK/ asserted 110 – ns t5 Receive data setup to SREQ/ or SACK/ asserted 0 – ns t6 Receive data hold from SREQ/ or SACK/ asserted 45 – ns 48.583 pc SCSI Timing Diagrams 7-39 52.5 pc 3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc Table 7.35 Symbol 4.333 pc SCSI-2 Fast Transfers 10.0 Mbytes (8-Bit transfers) or 20.0 Mbytes (16-Bit transfers) 40 MHz Clock Parameter Min Max Units t1 Send SREQ/ or SACK/ assertion pulse width 35 – ns t2 Send SREQ/ or SACK/ deassertion pulse width 35 – ns t1 Receive SREQ/ or SACK/ assertion pulse width 20 – ns t2 Receive SREQ/ or SACK/ deassertion pulse width 20 – ns t3 Send data setup to SREQ/ or SACK/ asserted 33 – ns t4 Send data hold from SREQ/ or SACK/ asserted 45 – ns t5 Receive data setup to SREQ/ or SACK/ asserted 0 – ns t6 Receive data hold from SREQ/ or SACK/ asserted 10 – ns Min Max Unit Table 7.36 44.25 pc Symbol SCSI-2 Fast Transfers 10.0 Mbytes (8-Bit Transfers) or 20.0 Mbytes (16-Bit Transfers) 50 MHz Clock1 Parameter2 t1 Send SREQ/ or SACK/ assertion pulse width 35 – ns t2 Send SREQ/ or SACK/ deassertion pulse width 35 – ns t1 Receive SREQ/ or SACK/ assertion pulse width 20 – ns t2 Receive SREQ/ or SACK/ deassertion pulse width 20 – ns t3 Send data setup to SREQ/ or SACK/ asserted 33 – ns t4 Send data hold from SREQ/ or SACK/ asserted 403 – ns t5 Receive data setup to SREQ/ or SACK/ asserted 0 – ns t6 Receive data hold from SREQ/ or SACK/ asserted 10 – ns 1. Transfer period bits (bits [6:4] in the SXFER register) are set to zero and the Extra Clock Cycle of Data Setup bit (bit 7 in SCNTL1) is set. 2. Note: for fast SCSI, set the TolerANT Enable bit (bit 7 in STEST3). 3. Analysis of system configuration is recommended due to reduced driver skew margin in differential systems. 48.583 pc 7-40 Specifications 52.5 pc 3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc Table 7.37 Symbol 4.333 pc Ultra SCSI SE Transfers 20.0 Mbytes (8-Bit Transfers) or 40.0 Mbytes (16-Bit Transfers) Quadrupled 40 MHz Clock1 Parameter2 Min Max Unit t1 Send SREQ/ or SACK/ assertion pulse width 16 – ns t2 Send SREQ/ or SACK/ deassertion pulse width 16 – ns t1 Receive SREQ/ or SACK/ assertion pulse width 10 – ns t2 Receive SREQ/ or SACK/ deassertion pulse width 10 – ns t3 Send data setup to SREQ/ or SACK/ asserted 12 – ns t4 Send data hold from SREQ/ or SACK/ asserted 17 – ns t5 Receive data setup to SREQ/ or SACK/ asserted 0 – ns t6 Receive data hold from SREQ/ or SACK/ asserted 6 – ns 1. Transfer period bits (bits [6:4] in the SXFER register) are set to zero and the Extra Clock Cycle of Data Setup bit (bit 7 in SCNTL1) is set. 2. Note: for fast SCSI, set the TolerANT Enable bit (bit 7 in STEST3). During Ultra SCSI transfers, the value of the Extend REQ/ACK Filtering bit (STEST2, bit 1) has no effect. 44.25 pc Table 7.38 Symbol Ultra SCSI HVD Transfers 20.0 Mbytes (8-Bit Transfers) or 40.0 Mbytes (16-Bit Transfers) 80 MHz Clock1 Parameter2 Min Max Unit t1 Send SREQ/ or SACK/ assertion pulse width 16 – ns t2 Send SREQ/ or SACK/ deassertion pulse width 16 – ns t1 Receive SREQ/ or SACK/ assertion pulse width 10 – ns t2 Receive SREQ/ or SACK/ deassertion pulse width 10 – ns t3 Send data setup to SREQ/ or SACK/ asserted 16 – ns t4 Send data hold from SREQ/ or SACK/ asserted 21 – ns t5 Receive data setup to SREQ/ or SACK/ asserted 0 – ns t6 Receive data hold from SREQ/ or SACK/ asserted 6 – ns 1. Transfer period bits (bits [6:4] in the SXFER register) are set to zero and the Extra Clock Cycle of Data Setup bit (bit 7 in SCNTL1) is set. 2. During Ultra SCSI transfers, the value of the Extend REQ/ACK Filtering bit (STEST2, bit 1) has no effect. 48.583 pc SCSI Timing Diagrams 7-41 52.5 pc 3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc Table 7.39 Symbol 4.333 pc Ultra2 SCSI Transfers 40.0 Mbytes (8-Bit Transfers) or 80.0 Mbytes (16-Bit Transfers) Quadrupled 40 MHz Clock1 Parameter2 Min Max Unit t1 Send SREQ/ or SACK/ assertion pulse width 8 – ns t2 Send SREQ/ or SACK/ deassertion pulse width 8 – ns t1 Receive SREQ/ or SACK/ assertion pulse width 6.5 – ns t2 Receive SREQ/ or SACK/ deassertion pulse width 6.5 – ns t3 Send data setup to SREQ/ or SACK/ asserted 9.5 – ns t4 Send data hold from SREQ/ or SACK/ asserted 9.5 – ns t5 Receive data setup to SREQ/ or SACK/ asserted 3.5 – ns t6 Receive data hold from SREQ/ or SACK/ asserted 3.5 – ns 1. Transfer period bits (bits [7:5] in the SXFER register) are set to zero and the Extra Clock Cycle of Data Setup bit (bit 7 in SCNTL1) is set. 2. During Ultra2 SCSI transfers, the value of the Extend REQ/ACK Filtering bit (STEST2, bit 1) has no effect. 44.25 pc Figure 7.28 Initiator and Target Synchronous Transfer t1 SREQ/ or SACK/ n t3 Send Data SD[15:0]/, SDP[1:0]/ Receive Data SD[15:0]/, SDP[1:0]/ n+1 t4 Valid n t5 t2 Valid n + 1 t6 Valid n Valid n + 1 48.583 pc 7-42 Specifications 52.5 pc 3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc 4.333 pc 7.6 Pinouts and Packaging Figure 7.29 is pinout information for the LSI53C1510 388 BGA chip package. Table 7.40 provides the 388 BGA pin list by location and Table 7.41 provides the same pin list alphabetically. Figure 7.30 illustrates the signal locations on the LSI53C1510 388 BGA. Figure 7.31 is the package drawing for the LSI53C1510. 44.25 pc 48.583 pc Pinouts and Packaging 7-43 52.5 pc 3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc 4.333 pc Figure 7.29 Left Half of the LSI53C1510 388 BGA Chip - Top View 44.25 pc 1 2 3 4 5 6 7 8 9 10 11 12 13 A VSS VSS DRAM_ ADD1 DRAM_OE/ DRAM_ CASFB_A VDDCORE3 DRAM_ CAS5/ DRAM_ CAS3/ DRAM_ RAS1/ DRAM_ PAR2 DRAM_ DATA0 DRAM_ DATA17 DRAM_ DATA3 A B DRAM_ ADD5 VSS DRAM_ ADD3 DRAM_WE/ DRAM_ RAS2/ DRAM_ CAS0/ DRAM_ CAS2/ DRAM_ RAS0/ VSSCORE3 DRAM_ PAR1 DRAM_ DATA1 DRAM_ DATA18 DRAM_ DATA6 B C DRAM_ ADD8 DRAM_ ADD7 VSS DRAM_ ADD4 DRAM_ ADD2 DRAM_ RAS3/ DRAM_ CASFB_B DRAM_ CAS1/ DRAM_ CAS7/ DRAM_ PAR0 DRAM_ DATA16 DRAM_ DATA2 DRAM_ DATA4 C D DRAM_ ADD11 DRAM_ ADD10 DRAM_ ADD6 VSS DRAM_ ADD0 VDD DRAM_ CAS4/ DRAM_ CAS6/ VSS DRAM_ PAR3 VDD DRAM_ DATA19 DRAM_ DATA20 D E MEM_ ADD0 TEST_ DRAMCLK DRAM_ ADD12 DRAM_ ADD9 E F MEM_ ADD3 MEM_ ADD2 MEM_ ADD4 VDD F G MEM_ ADD6 MEM_ ADD5 MEM_ ADD7 MEM_ ADD1 G H MEM_ ADD9 MEM_ ADD8 MEM_ ADD10 VDDCORE4 H J MEM_ ADD11 MEM_ ADD12 MO3/_ TESTOUT VSS J K MEM_CE0/ MEM_CE1/ MEM_CE2/ MCE2_RD/ K L VSSCORE4 MCE2_WR/ MEM_ DATA0 VDD VSS VSS VSS L M MEM_WE/ MEM_ DATA1 MEM_ DATA4 MEM_ DATA6 VSS VSS VSS M N MEM_ DATA2 MEM_ DATA3 MEM_ DATA7 VSS VSS VSS VSS N P SCAN_ TRI_E/ MEM_ DATA5 SCAN_ RAM_E/ TESTIN VSS VSS VSS P SCAN_ RST_E/ SCAN_E/ SCAN_TEST _CLK_E/ VSS VSS VSS R VSS VSS VSS T R SCANMODE T PME NC POWER_ FAIL VDD U B_GPIO1 B_GPIO0 B_GPIO2 VSSCORE5 U V B_GPIO3 VDDCORE5 B_SD11+/ VSS V W B_SD11−/ B_GPIO4 B_SD9−/ B_SD10+/ W Y B_SD9+/ B_SD10−/ B_SI_O−/ B_SD8+/ Y AA B_SD8−/ B_SI_O+/ B_SC_D+/ VDD AA AB B_SREQ+/ B_SREQ−/ B_SMSG−/ B_SSEL−/ AB AC B_SC_D−/ B_SSEL+/ B_SRST−/ VSS B_SATN+/ VDD B_SD7+/ B_SD3−/ VSS B_SD15+/ VDD B_DIFFSENS VSS AC AD B_SMSG+/ B_SRST+/ VSS B_SACK−/ B_RBIAS- B_SD6−/ B_SD4+/ B_SD2+/ B_SD1−/ B_SDP1+/ B_SD14−/ B_SD12−/ SCLK AD AE VSS VSS B_SBSY+/ B_SATN−/ B_SDP0+/ B_SD7−/ B_SD5+/ B_SD4−/ B_SD1+/ B_SD0−/ B_SD15−/ B_SD13+/ B_SD12+/ AE AF VSS B_SACK+/ B_SBSY−/ B_RBIAS+ B_SDP0-/ B_SD6+/ B_SD5−/ B_SD3+/ B_SD2−/ B_SD0+/ B_SDP1−/ B_SD14+/ B_SD13−/ AF 1 2 3 4 5 6 7 8 9 10 11 12 13 48.583 pc 7-44 Specifications 52.5 pc 3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc 4.333 pc Figure 7.29 Right Half of the LSI53C1510 388 BGA Chip - Top View (Cont.) 44.25 pc 14 15 16 17 18 19 20 21 22 23 24 25 26 A DRAM_ DATA23 DRAM_ DATA9 DRAM_ DATA26 DRAM_ DATA12 DRAM_ DATA29 DRAM_ DATA15 PCI_AD0 PCI_AD3 PCI_AD6 C_BE0 PCI_AD10 PCI_AD13 VSS A B DRAM_ DATA7 DRAM_ DATA8 DRAM_ DATA25 DRAM_ DATA27 DRAM_ DATA13 DRAM_ DATA31 PCI_AD1 PCI_AD4 PCI_AD7 PCI_AD8 PCI_AD11 VSS VSS B C DRAM_ DATA5 DRAM_ DATA22 DRAM_ DATA24 DRAM_ DATA11 DRAM_ DATA28 DRAM_ DATA14 VDDCORE2 PCI_AD2 VSSCORE2 PCI_AD12 VSS PCI_AD15 PAR C D VSS DRAM_ DATA21 VDD DRAM_ DATA10 VSS DRAM_ DATA30 PCI_AD5 VDD PCI_AD9 VSS PCI_AD14 PEER/ STOP/ D E SERR/ C_BE1 TRDY/ IRDY/ E F VDD DEVSEL/ CLK G C_BE2 FRAME/ PCI_AD18 PCI_AD17 G H PCI_AD19 PCI_AD16 PCI_AD22 PCI_AD20 H J VSS PCI_AD21 PCI_AD23 VDDCORE1 J K PCI_AD25 IDSEL PCI_AD24 C_BE3 K VSSCORE1 F L VSS VSS VSS VDD PCI_AD27 PCI_AD28 PCI_AD26 L M VSS VSS VSS GNT/ PCI_AD30 PCI_AD31 PCI_AD29 M N VSS VSS VSS INTB RST/ XINT REQ/ N P VSS VSS VSS VSS INTA RXT TDO P R VSS VSS VSS VSSCORE0 TXT TRST TDI R T VSS VSS VSS VDD TMS TCK ARM_ TRST T U ARM_TMS ARM_TDO VDDCORE0 A_GPIO0 U V VSS A_GPIO1 A_GPIO2 A_GPIO3 V W A_SD12+/ A_GPIO4 A_SD13+/ A_SD12−/ W Y A_SDP1−/ A_SD13−/ A_SD14−/ A_SD14+/ Y AA VDD A_SD15+/ A_SDP1+/ A_SD15−/ AA AB A_SD2−/ A_SD1+/ A_SD0−/ A_SD0+/ AB AC TEST_HSC VDD_A VDD A_SD8+/ VSS A_SMSG−/ A_SACK−/ VDD A_SD7+/ VSS A_SD4+/ A_SD2+/ A_SD1−/ AC AD A_DIFFSENS A_SD10−/ A_SD9+/ A_SREQ−/ A_SSEL−/ A_SRST+/ A_SBSY+/ A_SDP0−/ A_SD6+/ A_SD5+/ VSS A_SD3−/ A_SD3+/ AD AE VSS_A A_SD11+/ A_SD9−/ A_SI_O−/ A_SREQ+/ A_SC_D+/ A_SMSG+/ A_SBSY−/ A_SATN+/ A_SD7−/ A_SD5−/ VSS A_SD4−/ AE AF A_SD11−/ A_SD10+/ A_SD8−/ A_SI_O+/ A_SC_D-/ A_SSEL+/ A_SRST−/ A_SACK+/ A_SATN−/ A_SDP0+/ A_SD6−/ VSS VSS AF 14 15 16 17 18 19 20 21 22 23 24 25 26 48.583 pc Pinouts and Packaging 7-45 52.5 pc 3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc Table 7.40 Signal Name 44.25 pc VSS VSS DRAM_ADDR1 DRAM_OE/ DRAM_CASFB_A VDDCORE3 DRAM_CAS5/ DRAM_CAS3/ DRAM_RAS1/ DRAM_PAR2 DRAM_DATA0 DRAM_DATA17 DRAM_DATA3 DRAM_DATA23 DRAM_DATA9 DRAM_DATA26 DRAM_DATA12 DRAM_DATA29 DRAM_DATA15 PCI_AD0 PCI_AD3 PCI_AD6 C_BE0 PCI_AD10 PCI_AD13 VSS DRAM_ADDR5 VSS DRAM_ADDR3 DRAM_WE/ DRAM_RAS2/ DRAM_CAS0/ DRAM_CAS2/ DRAM_RAS0/ VSSCORE3 DRAM_PAR1 DRAM_DATA1 DRAM_DATA18 DRAM_DATA6 DRAM_DATA7 DRAM_DATA8 DRAM_DATA25 DRAM_DATA27 DRAM_DATA13 DRAM_DATA31 PCI_AD1 PCI_AD4 PCI_AD7 PCI_AD8 PCI_AD11 VSS VSS DRAM_ADDR8 DRAM_ADDR7 VSS DRAM_ADDR4 DRAM_ADDR2 DRAM_RAS3/ DRAM_CASFB_B DRAM_CAS1/ DRAM_CAS7/ DRAM_PAR0 DRAM_DATA16 DRAM_DATA2 DRAM_DATA4 DRAM_DATA5 DRAM_DATA22 DRAM_DATA24 DRAM_DATA11 DRAM_DATA28 DRAM_DATA14 VDDCORE2 PCI_AD2 VSSCORE2 PCI_AD12 VSS PCI_AD15 PAR 4.333 pc Signal Names and BGA Position BGA Signal Pos Name A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 DRAM_ADDR11 DRAM_ADDR10 DRAM_ADDR6 VSS DRAM_ADDR0 VDD DRAM_CAS4/ DRAM_CAS6/ VSS DRAM_PAR3 VDD DRAM_DATA19 DRAM_DATA20 VSS DRAM_DATA21 VDD DRAM_DATA10 VSS DRAM_DATA30 PCI_AD5 VDD PCI_AD9 VSS PCI_AD14 PERR/ STOP/ MEM_ADDR0 TEST_DRAMCLK DRAM_ADDR12 DRAM_ADDR9 SERR/ C_BE1 TRDY/ IRDY/ MEM_ADDR3 MEM_ADDR2 MEM_ADDR4 VDD VDD DEVSEL/ CLK VSSCORE1 MEM_ADDR6 MEM_ADDR5 MEM_ADDR7 MEM_ADDR1 C_BE2 FRAME/ PCI_AD18 PCI_AD17 MEM_ADDR9 MEM_ADDR8 MEM_ADDR10 VDDCORE4 PCI_AD19 PCI_AD16 PCI_AD22 PCI_AD20 MEM_ADDR11 MEM_ADDR12 MOE/_TESTOUT VSS VSS PCI_AD21 PCI_AD23 VDDCORE1 MEM_CE0/ MEM_CE1/ MEM_CE2/ MCE2_RD/ PCI_AD25 IDSEL PCI_AD24 C_BE3 VSSCORE4 MCE2_WR/ MEM_DATA0 VDD BGA Signal Pos Name D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 E1 E2 E3 E4 E23 E24 E25 E26 F1 F2 F3 F4 F23 F24 F25 F26 G1 G2 G3 G4 G23 G24 G25 G26 H1 H2 H3 H4 H23 H24 H25 H26 J1 J2 J3 J4 J23 J24 J25 J26 K1 K2 K3 K4 K23 K24 K25 K26 L1 L2 L3 L4 BGA Signal Pos Name VSS VSS VSS VSS VSS VSS VDD PCI_AD27 PCI_AD28 PCI_AD26 MEM_WE/ MEM_DATA1 MEM_DATA4 MEM_DATA6 VSS VSS VSS VSS VSS VSS GNT/ PCI_AD30 PCI_AD31 PCI_AD29 MEM_DATA2 MEM_DATA3 MEM_DATA7 VSS VSS VSS VSS VSS VSS VSS INTB RST/ XINT REQ/ SCAN_TRI_EN MEM_DATA5 SCAN_RAM_EN TESTIN VSS VSS VSS VSS VSS VSS VSS INTA RXT TDO SCANMODE SCAN_RST_EN SCAN_EN SCAN_TST_CLK_EN VSS VSS VSS VSS VSS VSS VSSCORE0 TXT TRST/ TDI PME NC POWER_FAIL/ VDD VSS VSS VSS VSS VSS VSS VDD TMS L11 L12 L13 L14 L15 L16 L23 L24 L25 L26 M1 M2 M3 M4 M11 M12 M13 M14 M15 M16 M23 M24 M25 M26 N1 N2 N3 N4 N11 N12 N13 N14 N15 N16 N23 N24 N25 N26 P1 P2 P3 P4 P11 P12 P13 P14 P15 P16 P23 P24 P25 P26 R1 R2 R3 R4 R11 R12 R13 R14 R15 R16 R23 R24 R25 R26 T1 T2 T3 T4 T11 T12 T13 T14 T15 T16 T23 T24 TCK ARM_TRST/ B_GPIO1 B_GPIO0 B_GPIO2 VSSCORE5 ARM_TMS ARM_TDO VDDCORE0 A_GPIO0 B_GPIO3 VDDCORE5 B_SD11+/ VSS VSS A_GPIO1 A_GPIO2 A_GPIO3 B_SD11−/ B_GPIO4 S_SD9−/ B_SD10+/ A_SD12+/ A_GPIO4 A_SD13+/ A_SD12−/ B_SD9+/ B_SD10−/ B_SI_O−/ B_SD8+/ A_SDP−/ A_SD13−/ A_SD14−/ A_SD14+/ B_SD8−/ B_SI_O+/ B_SC_D+/ VDD VDD A_SD15+/ A_SDP1+/ A_SD15−/ B_SREQ+/ B_SREQ−/ B_SMSG−/ B_SSEL−/ A_SD2−/ A_SD1+/ A_SD0−/ A_SD0+/ B_SC_D−/ B_SSEL+/ B_SRST−/ VSS B_SATN+/ VDD B_SD7+/ B_SD3−/ VSS B_SD15+/ VDD B_DIFFSENS VSS TEST_HSC VDD-A VDD A_SD8+/ VSS A_SMSG−/ A_SACK−/ VDD A_SD7+/ VSS A_SD4+/ A_SD2+/ A_SD1−/ B_SMSG+/ B_SRST+/ BGA Signal Pos Name T25 T26 U1 U2 U3 U4 U23 U24 U25 U26 V1 V2 V3 V4 V23 V24 V25 V26 W1 W2 W3 W4 W23 W24 W25 W26 Y1 Y2 Y3 Y4 Y23 Y24 Y25 Y26 AA1 AA2 AA3 AA4 AA23 AA24 AA25 AA26 AB1 AB2 AB3 AB4 AB23 AB24 AB25 AB26 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 AD1 AD2 VSS B_SACK−/ B_RBIAS− B_SD6−/ B_SD4+/ B_SD2+/ B_SD1−/ B_SDP1+/ B_SD14−/ B_SD12−/ SCLK A_DIFFSENS A_SD10−/ A_SD9+/ A_SREQ−/ A_SSEL−/ A_SRST+/ A_SBSY+/ A_SDP0−/ A_SD6+/ A_SD5+/ VSS A_SD3−/ A_SD3+/ VSS VSS B_SBSY+/ B_SATN−/ B_SDP0+/ B_SD7−/ B_SD5+/ B_SD4−/ B_SD1+/ B_SD0−/ B_SD15−/ B_SD13+/ B_SD12+/ VSS-A A_SD11+/ A_SD9−/ A_SI_O−/ A_SREQ+/ A_SC_D+/ A_SMSG+/ A_SBSY−/ A_SATN+/ A_SD7−/ A_SD5−/ VSS A_SD4−/ VSS B_SACK+/ B_SBSY−/ B_RBIAS+ B_SDP0−/ B_SD6+/ B_SD5−/ B_SD3+/ B_SD2−/ B_SD0+/ B_SDP1−/ B_SD14+/ B_SD13−/ A_SD11−/ A_SD10+/ A_SD8−/ A_SI_O+/ A_SC_D−/ A_SSEL+/ A_SRST−/ A_SACK+/ A_SATN−/ A_SDP0+/ A_SD6−/ VSS VSS BGA Pos AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AE1 AE2 AE3 AE4 AE5 AE6 AE7 AE8 AE9 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 48.583 pc 7-46 Specifications 52.5 pc 3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc Table 7.41 Signal Name 44.25 pc A_SACK−/ A_SACK+/ A_SATN−/ A_SATN+/ A_SBSY−/ A_SBSY+/ A_SC_D−/ A_SC_D+/ A_DIFFSENS A_GPIO0 A_GPIO1 A_GPIO2 A_GPIO3 A_GPIO4 A_SI_O−/ A_SI_O+/ A_SMSG−/ A_SMSG+/ A_SREQ−/ A_SREQ+/ A_SRST−/ A_SRST+/ A_SD0−/ A_SD1−/ A_SD2−/ A_SD3−/ A_SD4−/ A_SD5−/ A_SD6−/ A_SD7−/ A_SD8−/ A_SD9−/ A_SD10−/ A_SD11−/ A_SD12−/ A_SD13−/ A_SD14−/ A_SD15−/ A_SD0+/ A_SD1+/ A_SD2+/ A_SD3+/ A_SD4+/ A_SD5+/ A_SD6+/ A_SD7+/ A_SD8+/ A_SD9+/ A_SD10+/ A_SD11+/ A_SD12+/ A_SD13+/ A_SD14+/ A_SD15+/ A_SDP0−/ A_SDP1−/ A_SDP0+/ A_SDP1+/ A_SSEL−/ A_SSEL+/ ARM_TDO ARM_TMS ARM_TRST/ B_SACK−/ B_SACK+/ B_SATN−/ B_SATN+/ B_SBSY−/ B_SBSY+/ B_SC_D−/ B_SC_D+/ B_DIFFSENS B_GPIO0 B_GPIO1 B_GPIO2 B_GPIO3 B_GPIO4 B_SI_O−/ 4.333 pc Signal Names By BGA Position BGA Signal Pos Name AC20 AF21 AF22 AE22 AE21 AD20 AF18 AE19 AD14 U26 V24 V25 V26 W24 AE17 AF17 AC19 AE20 AD17 AE18 AF20 AD19 AB25 AC26 AB23 AD25 AE26 AE24 AF24 AE23 AF16 AE16 AD15 AF14 W26 Y24 Y25 AA26 AB26 AB24 AC25 AD26 AC24 AD23 AD22 AC22 AC17 AD16 AF15 AE15 W23 W25 Y26 AA24 AD21 Y23 AF23 AA25 AD18 AF19 U24 U23 T26 AD4 AF2 AE4 AC5 AF3 AE3 AC1 AA3 AC12 U2 U1 U3 V1 W2 Y3 B_SI_O+/ B_SMSG−/ B_SMSG+/ B_RBIAS− B_RBIAS+ B_SREQ−/ B_SREQ+/ B_SRST−/ B_SRST+/ B_SD0−/ B_SD1−/ B_SD2−/ B_SD3−/ B_SD4−/ B_SD5−/ B_SD6−/ B_SD7−/ B_SD8−/ B_SD9−/ B_SD10−/ B_SD11−/ B_SD12−/ B_SD13−/ B_SD14−/ B_SD15−/ B_SD0+/ B_SD1+/ B_SD2+/ B_SD3+/ B_SD4+/ B_SD5+/ B_SD6+/ B_SD7+/ B_SD8+/ B_SD9+/ B_SD10+/ B_SD11+/ B_SD12+/ B_SD13+/ B_SD14+/ B_SD15+/ B_SDP0−/ B_SDP1−/ B_SDP0+/ B_SDP1+/ B_SSEL−/ B_SSEL+/ C_BE0 C_BE1 C_BE2 C_BE3 CLK DEVSEL/ DRAM_ADDR0 DRAM_ADDR1 DRAM_ADDR2 DRAM_ADDR3 DRAM_ADDR4 DRAM_ADDR5 DRAM_ADDR6 DRAM_ADDR7 DRAM_ADDR8 DRAM_ADDR9 DRAM_ADDR10 DRAM_ADDR11 DRAM_ADDR12 DRAM_CASFB_A DRAM_CASFB_B DRAM_CAS0/ DRAM_CAS1/ DRAM_CAS2/ DRAM_CAS3/ DRAM_CAS4/ DRAM_CAS5/ DRAM_CAS6/ DRAM_CAS7/ DRAM_DATA0 DRAM_DATA1 BGA Signal Pos Name AA2 AB3 AD1 AD5 AF4 AB2 AB1 AC3 AD2 AE10 AD9 AF9 AC8 AE8 AF7 AD6 AE6 AA1 W3 Y2 W1 AD12 AF13 AD11 AE11 AF10 AE9 AD8 AF8 AD7 AE7 AF6 AC7 Y4 Y1 W4 V3 AE13 AE12 AF12 AC10 AF5 AF11 AE5 AD10 AB4 AC2 A23 E24 G23 K26 F25 F24 D5 A3 C5 B3 C4 B1 D3 C2 C1 E4 D2 D1 E3 A5 C7 B6 C8 B7 A8 D7 A7 D8 C9 A11 B11 DRAM_DATA2 DRAM_DATA3 DRAM_DATA4 DRAM_DATA5 DRAM_DATA6 DRAM_DATA7 DRAM_DATA8 DRAM_DATA9 DRAM_DATA10 DRAM_DATA11 DRAM_DATA12 DRAM_DATA13 DRAM_DATA14 DRAM_DATA15 DRAM_DATA16 DRAM_DATA17 DRAM_DATA18 DRAM_DATA19 DRAM_DATA20 DRAM_DATA21 DRAM_DATA22 DRAM_DATA23 DRAM_DATA24 DRAM_DATA25 DRAM_DATA26 DRAM_DATA27 DRAM_DATA28 DRAM_DATA29 DRAM_DATA30 DRAM_DATA31 DRAM_OE/ DRAM_PAR0 DRAM_PAR1 DRAM_PAR2 DRAM_PAR3 DRAM_RAS0/ DRAM_RAS1/ DRAM_RAS2/ DRAM_RAS3/ DRAM_WE/ FRAME/ GNT/ IDSEL INTA INTB IRDY/ MCE2_RD/ MCE2_WR/ MEM_ADDR0 MEM_ADDR1 MEM_ADDR2 MEM_ADDR3 MEM_ADDR4 MEM_ADDR5 MEM_ADDR6 MEM_ADDR7 MEM_ADDR8 MEM_ADDR9 MEM_ADDR10 MEM_ADDR11 MEM_ADDR12 MEM_CE0/ MEM_CE1/ MEM_CE2/ MEM_DATA0 MEM_DATA1 MEM_DATA2 MEM_DATA3 MEM_DATA4 MEM_DATA5 MEM_DATA6 MEM_DATA7 MEM_WE/ MOE/_TESTOUT NC PAR PCI_AD0 PCI_AD1 BGA Signal Pos Name C12 A13 C13 C14 B13 B14 B15 A15 D17 C17 A17 B18 C19 A19 C11 A12 B12 D12 D13 D15 C15 A14 C16 B16 A16 B17 C18 A18 D19 B19 A4 C10 B10 A10 D10 B8 A9 B5 C6 B4 G24 M23 K24 P24 N23 E26 K4 L2 E1 G4 F2 F1 F3 G2 G1 G3 H2 H1 H3 J1 J2 K1 K2 K3 L3 M2 N1 N2 M3 P2 M4 N3 M1 J3 T2 C26 A20 B20 BGA Signal Pos Name PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31 PERR/ PME POWER_FAIL/ REQ/ RST/ RXT SCAN_EN SCAN_RAM_EN SCAN_RST_EN SCAN_TST_CLK_EN SCAN_TRI_EN SCANMODE SCLK SERR/ STOP/ TCK TDI TDO TEST_DRAMCLK TEST_HSC TESTIN TMS TRDY/ TRST/ TXT VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD-A VDDCORE0 VDDCORE1 VDDCORE2 VDDCORE3 VDDCORE4 VDDCORE5 C21 A21 B21 D20 A22 B22 B23 D22 A24 B24 C23 A25 D24 C25 H24 G26 G25 H23 H26 J24 H25 J25 K25 K23 L26 L24 L25 M26 M24 M25 D25 T1 T3 N26 N24 P25 R3 P3 R2 R4 P1 R1 AD13 E23 D26 T25 R26 P26 E2 AC14 P4 T24 E25 R25 R24 D6 D11 D16 D21 F4 F23 L4 L23 T4 T23 AA4 AA23 AC6 AC11 AC16 AC21 AC15 U25 J26 C20 A6 H4 V2 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS-A VSSCORE0 VSSCORE1 VSSCORE2 VSSCORE3 VSSCORE4 VSSCORE5 XINT BGA Pos A1 A2 A26 B2 B25 B26 C3 C24 D4 D9 D14 D18 D23 J4 J23 L11 L12 L13 L14 L15 L16 M11 M12 M13 M14 M15 M16 N4 N11 N12 N13 N14 N15 N16 P11 P12 P13 P14 P15 P16 P23 R11 R12 R13 R14 R15 R16 T11 T12 T13 T14 T15 T16 V4 V23 AC4 AC9 AC13 AC18 AC23 AD3 AD24 AE1 AE2 AE25 AF1 AF25 AF26 AE14 R23 F26 C22 B9 L1 U4 N25 48.583 pc Pinouts and Packaging 7-47 52.5 pc 3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc Figure 7.30 LSI53C1510 388 Ball Grid Array 4.333 pc 44.25 pc 48.583 pc 7-48 Specifications 52.5 pc 3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc 4.333 pc Figure 7.31 388 PBGA (II) Mechanical Drawing 44.25 pc MD97.II Important: This drawing may not be the latest version. For board layout and manufacturing, obtain the most recent engineering drawings from your LSI Logic marketing representative by requesting the outline drawing for package code II. 48.583 pc Pinouts and Packaging 7-49 52.5 pc 3.75 pc 10.25 pc 11.25 pc 38.25 pc 34.5 pc 4.333 pc 44.25 pc 48.583 pc 7-50 Specifications 52.5 pc Appendix A Register Summary Table A.1 lists the LSI53C1510 PCI registers (nonintelligent mode) by register name. Table A.1 LSI53C1510 PCI Registers (Nonintelligent Mode) Register Map Register Name Address Read/Write Page Base Address Register One (MEMORY) 0x14–0x17 Read/Write 5-18 Base Address Register Two (SCRIPTS RAM) 0x18–0x1B Read/Write 5-18 Base Address Register Zero (I/O) 0x10–0x13 Read/Write 5-17 Bridge Support Extensions 0x46 Read Only 5-26 Cache Line Size 0x0C Read/Write 5-15 Capabilities Pointer 0x34 Read Only 5-21 Capability ID 0x40 Read Only 5-23 Class Code 0x09–0x0B Read Only 5-15 Command 0x02–0x03 Read/Write 5-11 Data 0x47 Read Only 5-26 Device ID 0x02–0x03 Read Only 5-11 Expansion ROM Base Address 0x30–0x33 Read/Write 5-20 Header Type 0x0E Read Only 5-17 Interrupt Line 0x3C Read/Write 5-22 Interrupt Pin 0x3D Read Only 5-22 Latency Timer 0x0D Read/Write 5-16 Max_Lat 0x3F Read Only 5-23 LSI53C1510 I2O-Ready PCI RAID Ultra2 SCSI Controller A-1 Table A.1 LSI53C1510 PCI Registers (Nonintelligent Mode) Register Map (Cont.) Register Name Address Read/Write Page Min_Gnt 0x3E Read Only 5-23 Next Item Pointer 0x41 Read Only 5-24 Not Supported 0x0F Power Management Capabilities 0x42–0x43 Read Only 5-24 Power Management Control/Status 0x44–0x45 Read/Write 5-25 Reserved 0x1C–0x2B – 5-18 Reserved 0x35–0x3B – 5-21 Revision ID (Rev ID) 0x08 Read Only 5-15 Status 0x06–0x07 Read/Write 5-13 Subsystem ID 0x2E–0x2F Read Only 5-20 Subsystem Vendor ID 0x2C–0x2D Read Only 5-19 Vendor ID 0x00–0x01 Read Only 5-11 – 5-17 Table A.2 lists the LSI53C1510 PCI registers (intelligent mode) registers by register name. Table A.2 LSI53C1510 PCI Registers (Intelligent Mode) Register Map Register Name Address Read/Write Page Base Address Register One (Shared MEMORY) 0x14–0x17 Read/Write 6-12 Base Address Register Zero (I/O) 0x10–0x13 Read/Write 6-11 BIST (Built-In Self Test) 0x0F Read/Write 6-11 Bridge Support Extensions (PMCSR_BSE) 0x46 Read Only 6-18 Cache Line Size 0x0C Read/Write 6-9 Capabilities Pointer 0x34 Read Only 6-14 Capability ID 0x40 Read Only 6-16 Class Code 0x09–0x0B Read Only 6-9 Command 0x04–0x05 Read/Write 6-5 A-2 Register Summary Table A.2 LSI53C1510 PCI Registers (Intelligent Mode) Register Map (Cont.) Register Name Address Read/Write Page Data 0x47 Read Only 6-18 Device ID 0x02–0x03 Read Only 6-5 Expansion ROM Base Address 0x30–0x33 Read/Write 6-13 Header Type 0x0E Read Only 6-10 Interrupt Line 0x3C Read/Write 6-14 Interrupt Pin 0x3D Read Only 6-15 Latency Timer 0x0D Read/Write 6-10 Max_Lat 0x3F Read Only 6-15 Min_Gnt 0x3E Read Only 6-15 Next Item Pointer 0x41 Read Only 6-16 Power Management Capabilities (PMC) 0x42–0x43 Read Only 6-16 Power Management Control/Status (PMCSR) 0x44–0x45 Read/Write 6-17 Reserved 0x18–0x2B – 6-12 Reserved 0x35–0x3B – 6-14 Revision ID (Rev ID) 0x08 Read Only 6-8 Status 0x06–0x07 Read/Write 6-7 Subsystem ID 0x2E–0x2F Read Only 6-13 Subsystem Vendor ID 0x2C–0x2D Read Only 6-12 Vendor ID 0x00–0x01 Read Only 6-5 Register Summary A-3 Table A.3 lists the LSI53C1510 Host Interface Registers (intelligent mode) by register name. Table A.3 LSI53C1510 Host Interface Registers (Intelligent Mode) Register Name Address Read/Write Page Data 0x08 Read/Write 6-18 DiagINT 0x00 Read/Write 6-20 Host Doorbell 0x20 Read/Write 6-24 Reply Interrupt Mask 0x34 Read/Write 6-25 Reply Interrupt Status 0x30 Read Only 6-25 Test Base Address 0x0C Read/Write 6-23 WRSEQ 0x04 Write Only 6-21 A-4 Register Summary Index Symbols (BARO[31:0]) 6-12 (BART[31:0]) 5-18 (BARZ[31:0]) 5-17, 6-11 (BSE[7:0]) 5-27, 6-18 (CC) 5-15 (CC[23:0]) 6-9 (CID[7:0]) 5-24, 6-16 (CLS) 5-15 (CLS[7:0]) 6-9 (CP[7:0]) 5-22, 6-14 (D1S) 5-25, 6-17 (D2S) 5-25, 6-17 (DATA[7:0]) 5-27, 6-18 (DID[15:0]) 5-11, 6-5 (DPE) 5-13, 6-7 (DPR) 5-14, 6-8 (DSCL[1:0]) 5-26, 6-17 (DSI) 5-25, 6-17 (DSLT) 5-26, 6-17 (DT) 5-13, 6-8 (EBM) 5-12, 6-6 (EIS) 5-12, 6-6 (EMS) 5-12, 6-6 (EPER) 5-12, 6-6 (ERBA[31:0]) 5-20, 6-13 (HT) 5-17 (HT[7:0]) 6-10 (I/O) 6-11 (IL[7:0]) 5-23, 6-14 (IP[7:0]) 5-23, 6-15 (LT) 5-16 (LT[7:0]) 6-10 (MEMORY) 6-12 (MG[7:0]) 5-24, 6-15 (ML[7:0]) 5-24, 6-15 (NC) 5-14, 6-8 (NIP[7:0]) 5-25, 6-16 (PEN) 5-26, 6-17 (PMC) 6-16 (PMCSR) 6-17 (PMCSR_BSE) 6-18 (PMEC) 5-26, 6-17 (PMES[4:0]) 5-25, 6-16 (PST) 5-26, 6-17 (PWS[1:0]) 5-26, 6-18 (RID) 5-15 (RID[7:0]) 6-8 (RMA) 5-13, 6-7 (RTA) 5-13, 6-7 (SE) 6-6 (SID[15:0]) 5-20, 6-13 (SSE) 5-13, 6-7 (VER[2:0]) 5-26, 6-17 (WIE) 5-12, 6-6 A a general purpose I/O 4-9 A_GPIO[4:0] 4-9 absolute maximum stress ratings 7-2 ac characteristics 7-11 address and data signals 4-5 address/data bus 5-4 advanced SCSI protocol interface 1-4 applications 1-11 arbitration signals 4-7 ARM test data output 4-19 ARM test mode select 4-19 ARM test reset 4-19 ARM_TDO 4-19 ARM_TMS 4-19 ARM_TRST/ 4-19 ARM7TDMI 1-1 ARM7TDMI RISC processor 1-4 benefits 1-8 ASPI 1-4 B b general purpose I/O 4-9 B_GPIO[4:0] 4-9 back-to-back read 32-bit address and data 7-24 back-to-back write 32-bit address and data 7-26 base address 5-1 base address register one 5-4 two 5-4 zero 6-12 zero - I/O (BARZ[31:0]) 5-17, 6-11 battery backed up SRAM 1-3 battery backup support and cache recovery 3-8 bidirectional signals 7-5 BIOS 1-4, 5-3 bit 1 DISARM (disable ARM core) 6-22 bridge support extensions (BSE[7:0]) 5-27, 6-18 BsaBlockRead 2-17 BsaBlockReassign 2-17 BsaBlockWrite 2-17 LSI53C1510 I2O-Ready PCI RAID Ultra2 SCSI Controller IX-1 BsaBlockWriteVerify 2-17 BsaCacheFlush 2-17 BsaDeviceReset 2-17 BsaMediaFormat 2-17 BsaMediaVerify 2-17 BsaPowerMgt 2-17 BsaStatusCheck 2-17 burst opcode fetch 32-bits address and data 7-22 burst read 32-bits address and data 7-28 burst write 32-bits address and data 7-30 bus command and byte enables 4-5 C C_BE/[3:0] 4-5, 5-3, 5-4, 5-5 cache line size 5-15 (CLS[7:0]) 6-9 caching 3-5 Cap_ID (CID[7:0]) 5-24, 6-16 capabilities pointer (CP[7:0]) 5-22, 6-14 CD-ROM 1-4 CLK 4-4 clock 4-4 column address strobe feedback 4-17 command configuration read command 5-6 configuration write command 5-7 DAC command 5-7 I/O read command 5-6 I/O write command 5-6 interrupt acknowledge 5-5 memory read command 5-6 memory read line command 5-7 memory read multiple command 5-7 memory write and invalidate command 5-8 memory write command 5-6 reserved command 5-6 special cycle command 5-6 configuration and initialization 2-4 options 2-5 read command 5-6 space 5-3 write command 5-7 current function of input voltage 7-9 function of output voltage 7-10 cycle frame 4-6 D D1_Support (D1S) 5-25, 6-17 D2_Support (D2S) 5-25, 6-17 DAC 1-3 DAC command 5-7 data (DATA[7:0]) 5-27, 6-18 parity error reported 5-14, 6-8 data_scale (DSCL[1:0]) 5-26, 6-17 data_select 5-26, 6-17 dc characteristics 7-1 detected parity error (from slave) (DPE) 5-13, 6-7 device ID (DID[15:0]) 6-5 select 4-6 specific initialization (DSI) 5-25, 6-17 IX-2 Index DEVSEL/ 4-6 timing 5-13, 6-8 DiagINT/CLRINT (diagnostic interrupt (read)/ clear interrupt (write)) 6-20 DIFFSENS SCSI signals 7-4 disk array 3-4 DMA channel 2-9 engine 2-1 unit 2-3 DMMAP (diagnostic memory map) 6-23 DRAM 1-3, 2-12, 2-18 column address strobe 4-17 column address strobe feedback 4-17 data 4-17 data parity 4-17 memory 2-19 memory addresses 4-17 output enable 4-17 row address strobe 4-17 timing parameters 7-32 write enable 4-17 DRAM_ADDR[12:0] 4-17 DRAM_CAS[7:0]/ 4-17 DRAM_CASFB_A 4-17 DRAM_CASFB_B 4-17 DRAM_DATA[31:0] 4-17 DRAM_OE/ 4-17 DRAM_PAR[3:0] 4-17 DRAM_RAS[3:0]/ 4-17 DRAM_WE/ 4-17 drive hot swap 3-7 dual address cycle (DAC) 1-3 DWE (DIAG register write enabled) (read only) 6-22 dword 2-9 dynamic capacity expansion 3-7 dynamic RAID migration (DRM) 3-7 E EDO DRAM 1-3, 2-4, 2-19, 3-9 embedded motherboard application 1-11 enable bus mastering (EBM) 5-12, 6-6 I/O space (EIS) 5-12, 6-6 memory space (EMS) 5-12, 6-6 parity error response (EPER) 5-12, 6-6 expansion ROM base address 6-13 external clock 7-11 interrupt 4-8 external memory interface multiple byte accesses 7-14 timing 7-31 F Fast-20 1-6 features list 1-5 FIFO 2-9, 2-12 depth 5-27 Flash ROM 3-9 flash ROM 1-3, 2-4, 2-18, 2-19, 3-9 FRAME/ 4-6 G L global hot spare drives 3-6 GNT/ 4-7 grant 4-7 latch-up protection 1-10 latency 5-8 timer 5-16 (LT[7:0]) 6-10 low voltage differential 1-6 LSI53C1510 benefits 1-5 summary 1-8 features 1-4 modes 2-2 overview 2-3 protocol engine 2-16 overview 2-9 register map A-1 LVD driver SCSI signals 7-3 receiver SCSI signals 7-3 LVD SCSI 1-4, 1-5 LVDlink benefits 1-6 H hardware assisted parity calculation 3-6 hardware parity assist engine 1-4 header type 5-17, 6-10 high power differential 1-6 host adapter board application 1-12 host doorbell 6-24 host interface 2-1, 2-11 registers 5-1 I I/O processor (IOP) 2-4, 6-1 read command 5-6 space 5-4 write command 5-6 I2O benefits 1-7, 2-7 communications model 2-8 conceptual overview 2-6 message unit 1-3 messages 6-1 overview 2-6 RAID device driver module (DDM) 1-2 RAID software 1-2 ready 1-1, 1-11 IDSEL 4-6, 5-3 signal 5-6 initialization 5-4 device select 4-6 initiator asynchronous receive 7-37 asynchronous send 7-36 ready 4-6 synchronous transfer 7-42 timing 7-20 input current as a function of input voltage 7-9 signals 7-6 INTA/ 4-7 INTB/ 4-7 integration 1-10 intelligent controller 1-4, 5-1 intelligent input/output 1-1, 2-1 interface control signals 4-6 internal arbiter 5-9 interrupt A 4-7 acknowledge command 5-5 B 4-7 line 5-23, 6-14 output 7-13 pin 5-23 (IP[7:0]) 6-15 signals 4-7 IRDY/ 4-6 IxWorks 1-5 Index M management software features 3-3 Max_Lat (ML[7:0]) 5-24, 6-15 maximum stress ratings 7-2 MCE2_RD/ 4-15 MCE2_WR/ 4-15 MEM_ADDR bus 2-4 MEM_ADDR[12:0] 4-15 MEM_CE/[2:0] 4-15 MEM_DATA[7:0] 4-15 MEM_WE/ 4-15 memory 4-15 address 4-15 chip enable 4-15 controller 1-3 data 4-15 read command 5-6 read line command 5-7 read multiple command 5-7 signal 4-15 space 5-4 to memory moves 5-9 write enable 4-15 memory signal 4-15 message frame address (MFA) 2-9 messages 2-11 passing I/O interface 2-1 queuing 2-8 transport 2-11 Min_Gnt (MG[7:0]) 5-24, 6-15 modes of operation 2-2 module overviews 1-3 MOE/_TESTOUT 4-15 moves memory to memory moves 5-9 multiple cache line transfers 5-8 N new capabilities 5-14 (NC) 6-8 Next_Item_Ptr (NIP[7:0]) 5-25, 6-16 IX-3 nonburst opcode fetch 32-bits address and data 7-20 nonintelligent 1-2, 1-4, 6-1 controller 1-4, 5-1 NVRAM 3-9 O online dynamic capacity expansion 3-7 RAID level migration/reconfiguration 3-7 operating conditions 7-2 register/SCRIPTS RAM read 32-bit 7-17 register/SCRIPTS RAM write 32-bit 7-18 operational overview 2-8 OSM 2-8 output current as a function of output voltage 7-10 signals 7-5, 7-6 P packetized 2-1 PAR 4-5 parity 4-5 assist engine (PAE) 1-1, 2-1, 2-4 error 4-8 PCI addressing 5-3 bus commands and functions supported 5-5 cache line size register 5-8 cache mode 5-9 commands 5-5 configuration cycles 5-3 configuration register map 5-10 configuration register read 7-15 configuration register write 7-16 configuration registers 1-3, 5-10, 6-4 configuration space registers 5-3 external memory interface timing diagrams 7-14 functional description (nonintelligent mode) 5-3 I/O space 5-4 interface 1-3 interface registers 5-1 interface signals 4-4 master 1-3 memory space 5-4 performance 1-8 power management 1-3 RAID 3-1 software solutions 3-1 slave 1-3 target disconnect 5-9 target retry 5-8 PCI_AD[31:0] 4-5 PERR/ 4-8 physical dword PCI address and data 4-5 pin type description 4-1 PME clock (PMEC) 5-26, 6-17 enable (PEN) 5-26, 6-17 PME/ 4-8 status (PST) 5-26, 6-17 IX-4 Index support (PMES[4:0]) 5-25, 6-16 power fail 4-19 power management event 4-8 power state (PWS[1:0]) 5-26, 6-18 POWER_FAIL/ 4-19 programming models 6-3 protocol engine 2-9, 2-16 push model 2-9, 2-15 R RAID 1-1, 1-11, 3-4, 6-1 controller 1-2, 1-5 firmware features 3-3 host adapter 1-2 level 3-4 level 0 3-4 level 1 3-4 level 3 3-5 level 5 3-5 levels 0, 1, 3, 5, and 10 3-4 parity assist engine 1-4, 2-1 performance 1-9 SYMplicity 1-5 random block storage class 2-16 read multiple with read line enabled 5-7 receive data 4-18 received master abort (from master) (RMA) 5-13, 6-7 target abort (from master) (RTA) 5-13, 6-7 register differences 5-27 register map A-1 reliability 1-10 reply free 1-3 free list 2-8 message 2-14 post 1-3 post list 2-8 ReplyINT (reply message interrupt) 6-25 ReplyIntMask (reply message interrupt mask) 6-25 REQ/ 4-7 REQ/ - GNT/ 5-3 request 4-7 free 1-3 free list 2-8 message 2-12 message frames 2-9 post 1-3 post list 2-8 reserved command 5-6 reset 4-4 input 7-12 revision ID 5-15 register (RID[7:0]) 6-8 RISC processor 1-1, 1-4, 2-1, 6-1 rise and fall time test condition 7-8 ROM size configurations 2-5 RST/ 4-4 RXT 4-18 S scan 3-state enable 4-16 enable 4-16 scan (Cont.) mode enable 4-16 RAM enable 4-16 reset enable 4-16 test clock enable 4-16 SCAN_EN 4-16 SCAN_RAM_EN 4-16 SCAN_RST_EN 4-16 SCAN_TEST_CLK_EN 4-16 SCAN_TRI_EN 4-16 SCANMODE 4-16 scatter/gather 1-9 SCLK 4-10 SCRIPTS RAM 2-3, 5-1, 5-4, 5-27 SCSI accessed fault-tolerant enclosure (SAF-TE) 3-4, 3-8 clock 4-10 cores 1-4, 5-1 function A 5-3 function B 5-3 hysteresis of receivers 7-9 input filtering 7-8 interface signals 4-10 performance 1-8 SCRIPTS 1-4, 1-8 timing diagrams 7-36 SCSI-1 transfers (differential 4.17 Mbytes) 7-39 (single-ended 5.0 Mbytes) 7-39 SCSI-2 fast transfers 10.0 Mbytes (8-bit transfers) 40 MHz Clock 7-40 50 MHz clock 7-40 20.0 Mbytes (16-bit transfers) 40 MHz Clock 7-40 50 MHz clock 7-40 SCSI-3 parallel interface 1-6 SDMS 1-4, 3-8 send a reply message 2-14 send a request message 2-13 serial EEPROM 2-19, 3-9 SERR/ 4-8 enable (SE) 5-12, 6-6 signal groupings 4-2 signal names and BGA position 7-45, 7-46 by BGA position 7-46 signaled system error (SSE) 5-13, 6-7 single-ended SCSI 1-6 signals 7-7 slave access and messaging unit 2-3 special cycle command 5-6 SRAM 1-3, 2-4, 2-18 STOP/ 4-6 storage manager 1-5 stress ratings 7-2 subsystem ID (SID[15:0]) 5-20, 6-13 subsystem vendor ID (SVID[15:0]) 5-19, 6-12 support components 2-18 supported random block storage Index messages 2-17 SYMplicity I2O RAID 1-5 software 2-16 storage manager 1-2, 3-2 system error 4-8 interface 2-8 programming model 6-3 signals 4-4 T tagged command queuing 3-6 target asynchronous receive 7-38 asynchronous send 7-38 ready 4-6 synchronous transfer 7-42 timing 7-14 TCK 4-18 TDI 4-18 TDO 4-18 test base address 6-23 clock 4-18 data input 4-18 data output 4-18 DRAM clock 4-19 in 4-18 mode select 4-18 reset 4-18 TEST_DRAMCLK 4-19 TEST_HSC 4-19 testability 1-9 TESTIN 4-18 TMS 4-18 TolerANT technology benefits 1-6 technology electrical characteristics 7-7 transmit data 4-18 TRDY/ 4-6 TRST/ 4-18 TTL_INT (select TTL output for PCI-INTA/) 6-22 TXT 4-18 U Ultra SCSI high voltage differential transfers 20.0 Mbytes (8-bit transfers) 80 MHz clock 7-41 40.0 Mbytes (16-bit transfers) 80 MHz clock 7-41 single-ended transfers 20.0 Mbytes (8-bit transfers) quadrupled 40 MHz clock 40.0 Mbytes (16-bit transfers) quadrupled 40 MHz clock Ultra2 SCSI 1-1, 1-4, 1-5, 1-11 benefits 1-5 transfers 40.0 Mbytes (8-bit transfers) quadrupled 40 MHz clock 80.0 Mbytes (16-bit transfers) quadrupled 40 MHz clock 7-41 7-41 7-42 7-42 IX-5 V VDD 4-20 VDD-A 4-20 vendor ID (VID[15:0]) 6-5 version (VER[2:0]) 5-26, 6-17 voltage feed-through protection 1-10 VSS 4-20 VSS-A 4-20 VSS-CORE 4-20 W wide Ultra2 SCSI 1-8, 5-3 Wind River System IxWorks 1-2, 1-5, 3-3 write and invalidate enable (WIE) 5-12, 6-6 X XINT 4-8 Z zero wait-state 2-1 IX-6 Index Customer Feedback We would appreciate your feedback on this document. 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Tel: 505.293.5119 U.S. Distributors by State (Continued) New York Hauppauge I. E. Tel: 516.761.0960 Long Island A. E. Tel: 516.434.7400 W. E. Tel: 800.861.9953 Rochester A. E. Tel: 716.475.9130 I. E. Tel: 716.242.7790 W. E. Tel: 800.319.9953 Smithtown B. M. Tel: 800.543.2008 Syracuse A. E. Tel: 315.449.4927 North Carolina Raleigh A. E. Tel: 919.859.9159 I. E. Tel: 919.873.9922 W. E. Tel: 800.560.9953 North Dakota A. E. Tel: 800.829.0116 W. E. Tel: 612.853.2280 Ohio Cleveland A. E. Tel: 216.498.1100 W. E. Tel: 800.763.9953 Dayton A. E. Tel: 614.888.3313 I. E. Tel: 937.253.7501 W. E. Tel: 800.575.9953 Strongsville B. M. Tel: 440.238.0404 Valley View I. E. Tel: 216.520.4333 Oklahoma W. E. Tel: 972.235.9953 Tulsa A. E. Tel: 918.459.6000 I. E. Tel: 918.665.4664 Oregon Beaverton B. M. Tel: 503.524.1075 I. E. Tel: 503.644.3300 Portland A. E. Tel: 503.526.6200 W. E. Tel: 800.879.9953 Pennsylvania Mercer I. E. Tel: 412.662.2707 Philadelphia A. E. Tel: 800.526.4812 B. M. Tel: 877.351.2355 W. E. Tel: 800.871.9953 Pittsburgh A. E. Tel: 412.281.4150 W. E. Tel: 440.248.9996 Rhode Island A. E. 800.272.9255 W. E. Tel: 781.271.9953 South Carolina A. E. Tel: 919.872.0712 W. E. Tel: 919.469.1502 South Dakota A. E. Tel: 800.829.0116 W. E. Tel: 612.853.2280 Tennessee W. E. Tel: 256.830.1119 East/West A. E. Tel: 800.241.8182 Tel: 800.633.2918 Texas Arlington B. M. Tel: 817.417.5993 Austin A. E. Tel: 512.219.3700 B. M. Tel: 512.258.0725 I. E. Tel: 512.719.3090 W. E. Tel: 800.365.9953 Dallas A. E. Tel: 214.553.4300 B. M. Tel: 972.783.4191 W. E. Tel: 800.955.9953 El Paso A. E. Tel: 800.526.9238 Houston A. E. Tel: 713.781.6100 B. M. Tel: 713.917.0663 W. E. Tel: 800.888.9953 Richardson I. E. Tel: 972.783.0800 Rio Grande Valley A. E. Tel: 210.412.2047 Stafford I. E. Tel: 281.277.8200 Utah Centerville B. M. Tel: 801.295.3900 Murray I. E. Tel: 801.288.9001 Salt Lake City A. E. Tel: 801.365.3800 W. E. Tel: 800.477.9953 Vermont A. E. Tel: 800.272.9255 W. E. Tel: 716.334.5970 Virginia A. E. Tel: 800.638.5988 W. E. Tel: 301.604.8488 Haymarket B. M. Tel: 703.754.3399 Springfield B. M. Tel: 703.644.9045 Washington Kirkland I. E. Tel: 425.820.8100 Maple Valley B. M. Tel: 206.223.0080 Seattle A. E. Tel: 425.882.7000 W. E. Tel: 800.248.9953 West Virginia A. E. Tel: 800.638.5988 Wisconsin Milwaukee A. E. Tel: 414.513.1500 W. E. Tel: 800.867.9953 Wauwatosa I. E. Tel: 414.258.5338 Wyoming A. E. Tel: 800.332.9326 W. E. Tel: 801.974.9953 Direct Sales Representatives by State (Components and Boards) E. A. E. L. GRP I. S. ION R. A. SGY Earle Associates Electrodyne - UT Group 2000 Infinity Sales, Inc. ION Associates, Inc. Rathsburg Associates, Inc. Synergy Associates, Inc. Arizona Tempe E. A. Tel: 480.921.3305 California Calabasas I. S. Tel: 818.880.6480 Irvine I. S. Tel: 714.833.0300 San Diego E. A. Tel: 619.278.5441 Illinois Elmhurst R. A. Tel: 630.516.8400 Indiana Cicero R. A. Tel: 317.984.8608 Ligonier R. A. Tel: 219.894.3184 Plainfield R. A. Tel: 317.838.0360 Massachusetts Burlington SGY Tel: 781.238.0870 Michigan Byron Center R. A. Tel: 616.554.1460 Good Rich R. A. Tel: 810.636.6060 Novi R. A. Tel: 810.615.4000 North Carolina Cary GRP Tel: 919.481.1530 Ohio Columbus R. A. Tel: 614.457.2242 Dayton R. A. Tel: 513.291.4001 Independence R. A. Tel: 216.447.8825 Pennsylvania Somerset R. A. Tel: 814.445.6976 Texas Austin ION Tel: 512.794.9006 Arlington ION Tel: 817.695.8000 Houston ION Tel: 281.376.2000 Utah Salt Lake City E. L. Tel: 801.264.8050 Wisconsin Muskego R. A. Tel: 414.679.8250 Saukville R. A. Tel: 414.268.1152 Sales Offices and Design Resource Centers LSI Logic Corporation Corporate Headquarters 1551 McCarthy Blvd Milpitas CA 95035 Tel: 408.433.8000 Fax: 408.433.8989 Fort Collins 2001 Danfield Court Fort Collins, CO 80525 Tel: 970.223.5100 Fax: 970.206.5549 New Jersey Red Bank 125 Half Mile Road Suite 200 Red Bank, NJ 07701 Tel: 732.933.2656 Fax: 732.933.2643 NORTH AMERICA Florida Boca Raton Cherry Hill - Mint Technology California Irvine 2255 Glades Road Suite 324A Boca Raton, FL 33431 Tel: 561.989.3236 Fax: 561.989.3237 Tel: 856.489.5530 Fax: 856.489.5531 Georgia Alpharetta New York Fairport 2475 North Winds Parkway Suite 200 Alpharetta, GA 30004 550 Willowbrook Office Park Fairport, NY 14450 18301 Von Karman Ave Suite 900 Irvine, CA 92612 ♦ Tel: 949.809.4600 Fax: 949.809.4444 Pleasanton Design Center 5050 Hopyard Road, 3rd Floor Suite 300 Pleasanton, CA 94588 Tel: 925.730.8800 Fax: 925.730.8700 Tel: 770.753.6146 Fax: 770.753.6147 Illinois Oakbrook Terrace 215 Longstone Drive Cherry Hill, NJ 08003 Tel: 716.218.0020 Fax: 716.218.9010 North Carolina Raleigh Phase II 4601 Six Forks Road Suite 528 Raleigh, NC 27609 Tel: 630.954.2234 Fax: 630.954.2235 Tel: 919.785.4520 Fax: 919.783.8909 Kentucky Bowling Green Oregon Beaverton 1551 McCarthy Blvd Sales Office M/S C-500 Milpitas, CA 95035 1262 Chestnut Street Bowling Green, KY 42101 15455 NW Greenbrier Parkway Suite 235 Beaverton, OR 97006 Fax: 408.954.3353 Maryland Bethesda 7585 Ronson Road Suite 100 San Diego, CA 92111 Tel: 858.467.6981 Fax: 858.496.0548 Silicon Valley ♦ Tel: 408.433.8000 Design Center M/S C-410 Tel: 408.433.8000 Fax: 408.433.7695 Wireless Design Center 11452 El Camino Real Suite 210 San Diego, CA 92130 Tel: 858.350.5560 Fax: 858.350.0171 Colorado Boulder 4940 Pearl East Circle Suite 201 Boulder, CO 80301 ♦ Tel: 303.447.3800 Fax: 303.541.0641 Colorado Springs Tel: 270.793.0010 Fax: 270.793.0040 6903 Rockledge Drive Suite 230 Bethesda, MD 20817 Tel: 301.897.5800 Fax: 301.897.8389 Massachusetts Waltham 200 West Street Waltham, MA 02451 ♦ Tel: 781.890.0180 Fax: 781.890.6158 Tel: 503.645.0589 Fax: 503.645.6612 Texas Austin 9020 Capital of TX Highway North Building 1 Suite 150 Austin, TX 78759 Tel: 512.388.7294 Fax: 512.388.4171 Plano 500 North Central Expressway Suite 440 Plano, TX 75074 ♦ Tel: 972.244.5000 Burlington - Mint Technology Fax: 972.244.5001 77 South Bedford Street Burlington, MA 01803 Houston Tel: 781.685.3800 Fax: 781.685.3801 20405 State Highway 249 Suite 450 Houston, TX 77070 4420 Arrowswest Drive Colorado Springs, CO 80907 Minnesota Minneapolis Tel: 719.533.7000 Fax: 719.533.7020 8300 Norman Center Drive Suite 730 Minneapolis, MN 55437 ♦ Tel: 612.921.8300 Fax: 612.921.8399 260 Hearst Way Suite 400 Kanata, ON K2L 3H1 ♦ Tel: 613.592.1263 Fax: 613.592.3253 Two Mid American Plaza Suite 800 Oakbrook Terrace, IL 60181 San Diego Canada Ontario Ottawa Tel: 281.379.7800 Fax: 281.379.7818 INTERNATIONAL France Paris LSI Logic S.A. Immeuble Europa 53 bis Avenue de l'Europe B.P. 139 78148 Velizy-Villacoublay Cedex, Paris ♦ Tel: 33.1.34.63.13.13 Fax: 33.1.34.63.13.19 Germany Munich LSI Logic GmbH Orleansstrasse 4 81669 Munich ♦ Tel: 49.89.4.58.33.0 Fax: 49.89.4.58.33.108 Stuttgart Mittlerer Pfad 4 D-70499 Stuttgart ♦ Tel: 49.711.13.96.90 Fax: 49.711.86.61.428 Italy Milan LSI Logic S.P.A. Centro Direzionale Colleoni Palazzo Orione Ingresso 1 20041 Agrate Brianza, Milano ♦ Tel: 39.039.687371 Fax: 39.039.6057867 Japan Tokyo LSI Logic K.K. Rivage-Shinagawa Bldg. 14F 4-1-8 Kounan Minato-ku, Tokyo 108-0075 ♦ Tel: 81.3.5463.7821 Fax: 81.3.5463.7820 Osaka Crystal Tower 14F 1-2-27 Shiromi Chuo-ku, Osaka 540-6014 ♦ Tel: 81.6.947.5281 Fax: 81.6.947.5287 Sales Offices and Design Resource Centers (Continued) Korea Seoul LSI Logic Corporation of Korea Ltd 10th Fl., Haesung 1 Bldg. 942, Daechi-dong, Kangnam-ku, Seoul, 135-283 Tel: 82.2.528.3400 Fax: 82.2.528.2250 The Netherlands Eindhoven LSI Logic Europe Ltd World Trade Center Eindhoven Building ‘Rijder’ Bogert 26 5612 LZ Eindhoven Tel: 31.40.265.3580 Fax: 31.40.296.2109 Singapore Singapore LSI Logic Pte Ltd 7 Temasek Boulevard #28-02 Suntec Tower One Singapore 038987 Tel: 65.334.9061 Fax: 65.334.4749 Sweden Stockholm LSI Logic AB Finlandsgatan 14 164 74 Kista ♦ Tel: 46.8.444.15.00 Fax: 46.8.750.66.47 Taiwan Taipei LSI Logic Asia, Inc. Taiwan Branch 10/F 156 Min Sheng E. Road Section 3 Taipei, Taiwan R.O.C. Tel: 886.2.2718.7828 Fax: 886.2.2718.8869 United Kingdom Bracknell LSI Logic Europe Ltd Greenwood House London Road Bracknell, Berkshire RG12 2UB ♦ Tel: 44.1344.426544 Fax: 44.1344.481039 ♦ Sales Offices with Design Resource Centers International Distributors Australia New South Wales Reptechnic Pty Ltd Hong Kong Hong Kong AVT Industrial Ltd 3/36 Bydown Street Neutral Bay, NSW 2089 Unit 608 Tower 1 Cheung Sha Wan Plaza 833 Cheung Sha Wan Road Kowloon, Hong Kong ♦ Tel: 612.9953.9844 Fax: 612.9953.9683 Belgium Acal nv/sa Lozenberg 4 1932 Zaventem Tel: 32.2.7205983 Fax: 32.2.7251014 China Beijing LSI Logic International Services Inc. Beijing Representative Office Room 708 Canway Building 66 Nan Li Shi Lu Xicheng District Beijing 100045, China Tel: 86.10.6804.2534 to 38 Fax: 86.10.6804.2521 France Rungis Cedex Azzurri Technology France 22 Rue Saarinen Sillic 274 94578 Rungis Cedex Tel: 33.1.41806310 Fax: 33.1.41730340 Germany Haar EBV Elektronik Tel: 852.2428.0008 Fax: 852.2401.2105 Serial System (HK) Ltd 2301 Nanyang Plaza 57 Hung To Road, Kwun Tong Kowloon, Hong Kong Tel: 852.2995.7538 Fax: 852.2950.0386 India Bangalore Spike Technologies India Private Ltd 951, Vijayalakshmi Complex, 2nd Floor, 24th Main, J P Nagar II Phase, Bangalore, India 560078 ♦ Tel: 91.80.664.5530 Fax: 91.80.664.9748 Macnica Corporation Tel: 44.1628.826826 Fax: 44.1628.829730 Hakusan High-Tech Park 1-22-2 Hadusan, Midori-Ku, Yokohama-City, 226-8505 Milton Keynes Ingram Micro (UK) Ltd Tel: 81.45.939.6140 Fax: 81.45.939.6141 The Netherlands Eindhoven Acal Nederland b.v. Japan Tokyo Daito Electron Tel: 49.89.4600980 Fax: 49.89.46009840 Munich Avnet Emg GmbH Global Electronics Corporation Stahlgruberring 12 81829 Munich Nichibei Time24 Bldg. 35 Tansu-cho Shinjuku-ku, Tokyo 162-0833 Tel: 49.89.45110102 Fax: 49.89.42.27.75 Tel: 81.3.3260.1411 Fax: 81.3.3260.7100 Technical Center Tel: 81.471.43.8200 Tel: 81.3.5778.8662 Fax: 81.3.5778.8669 Shinki Electronics Myuru Daikanyama 3F 3-7-3 Ebisu Minami Shibuya-ku, Tokyo 150-0022 Tel: 81.3.3760.3110 Fax: 81.3.3760.3101 Tel: 44.1908.260422 Swindon EBV Elektronik Tel: 31.40.2.502602 Fax: 31.40.2.510255 12 Interface Business Park Bincknoll Lane Wootton Bassett, Swindon, Wiltshire SN4 8SY Switzerland Brugg LSI Logic Sulzer AG Mattenstrasse 6a CH 2555 Brugg 14F, No. 145, Sec. 2, Chien Kuo N. Road Taipei, Taiwan, R.O.C. Tel: 886.2.2516.7303 Fax: 886.2.2505.7391 Lumax International Corporation, Ltd 7th Fl., 52, Sec. 3 Nan-Kang Road Taipei, Taiwan, R.O.C. Tel: 886.2.2788.3656 Fax: 886.2.2788.3568 Prospect Technology Corporation, Ltd 4Fl., No. 34, Chu Luen Street Taipei, Taiwan, R.O.C. Tel: 886.2.2721.9533 Fax: 886.2.2773.3756 Marubeni Solutions 1-26-20 Higashi Shibuya-ku, Tokyo 150-0001 Garamonde Drive Wymbush Milton Keynes Buckinghamshire MK8 8DF Beatrix de Rijkweg 8 5657 EG Eindhoven Taiwan Taipei Avnet-Mercuries Corporation, Ltd Tel: 81.3.3264.0326 Fax: 81.3.3261.3984 Tel: 49.2957.79.1692 Fax: 49.2957.79.9341 16 Grove Park Business Estate Waltham Road White Waltham Maidenhead, Berkshire SL6 3LW 11 Rozanis Street P.O. Box 39300 Tel Aviv 61392 Tel: 972.3.6458777 Fax: 972.3.6458666 United Kingdom Maidenhead Azzurri Technology Ltd Tel: 81.45.474.9037 Fax: 81.45.474.9065 Tel: 41.32.3743232 Fax: 41.32.3743233 Sogo Kojimachi No.3 Bldg 1-6 Kojimachi Chiyoda-ku, Tokyo 102-8730 Graf-Zepplin-Str 14 D-33181 Wuennenberg-Haaren 2-15-10 Shin Yokohama Kohoku-ku Yokohama-City, 222-8580 Israel Tel Aviv Eastronics Ltd Hans-Pinsel Str. 4 D-85540 Haar Wuennenberg-Haaren Peacock AG Yokohama-City Innotech Wintech Microeletronics Co., Ltd 7F., No. 34, Sec. 3, Pateh Road Taipei, Taiwan, R.O.C. Tel: 886.2.2579.5858 Fax: 886.2.2570.3123 Tel: 44.1793.849933 Fax: 44.1793.859555 ♦ Sales Offices with Design Resource Centers