ETC LSIFC909

LSIFC909
Fibre Channel
I/O Processor
Technical Manual
August 2000
Version 2.1
®
Order Number S14029.A
This document contains proprietary information of LSI Logic Corporation. The
information contained herein is not to be used by or disclosed to third parties
without the express written permission of an officer of LSI Logic Corporation.
LSI Logic products are not intended for use in life-support appliances, devices,
or systems. Use of any LSI Logic product in such applications without written
consent of the appropriate LSI Logic officer is prohibited.
Document number DB14-000150-01, Third Edition (August 2000).
This document describes the LSI Logic Corporation LSIFC909 Fibre Channel I/O
Processor and will remain the official reference source for all revisions/releases
of this product until rescinded by an update.
To receive product literature, visit us at http://www.lsilogic.com.
LSI Logic Corporation reserves the right to make changes to any products herein
at any time without notice. LSI Logic does not assume any responsibility or
liability arising out of the application or use of any product described herein,
except as expressly agreed to in writing by LSI Logic; nor does the purchase or
use of a product from LSI Logic convey a license under any patent rights,
copyrights, trademark rights, or any other of the intellectual property rights of
LSI Logic or third parties.
Copyright © 1999–2000 by LSI Logic Corporation. All rights reserved.
TRADEMARK ACKNOWLEDGMENT
The LSI Logic logo design is a registered trademark of LSI Logic Corporation.
ARM is a registered trademark of Advanced RISC Machines Limited, used under
license. All other brand and product names may be trademarks of their respective
companies.
DB
ii
Preface
This book is the primary reference and technical manual for the
LSIFC909 Fibre Channel I/O Processor. It contains a complete functional
description for the LSIFC909 and includes complete physical and
electrical specifications for the LSIFC909.
Audience
LSI Logic prepared this document for logic designers and applications
engineers to provide an overview of the LSIFC909 and to explain how to
use the LSIFC909 in the initial stages of system design.
This document assumes that you have some familiarity with
microprocessors and related support devices. The people who benefit
from this book are:
•
Engineers and managers who are evaluating the processor for
possible use in a system
•
Engineers who are designing the processor into a system
Organization
This document has the following chapters and appendixes:
•
Chapter 1, Introduction, provides a general description of the
LSIFC909.
•
Chapter 2, Fibre Channel Overview, briefly describes some key
elements of Fibre Channel, including Layers, Topologies, and
Classes of Service.
•
Chapter 3, LSIFC909 Overview, provides an introduction to the
basic features of the LSIFC909, including the host interface, protocol
assist engines, and support components.
Preface
iii
•
Chapter 4, Signal Descriptions, lists and describes the signals on
the LSIFC909, and includes pinout information.
•
Chapter 5, Register Descriptions, briefly describes the PCI address
space, the Configuration Registers, and the Host Interface Registers.
•
Chapter 6, Specifications, describes the electrical specifications of
the LSIFC909, and provides packaging dimensions.
•
Appendix A, Register Summary, is a register summary.
•
Appendix B, Reference Specifications, lists several specifications
and applicable World Wide Web URLs that may be of benefit to the
reader.
•
Appendix C, Glossary of Terms and Abbreviations, is a glossary
of terms and abbreviations.
Related Publications
LSI Logic LSIFC909 Programming Guide.
Conventions Used in This Manual
The word assert means to drive a signal true or active. The word
deassert means to drive a signal false or inactive. Signals that are active
LOW end in an “/.”
Hexadecimal numbers are indicated by the prefix “0x” —for example,
0x32CF. Binary numbers are indicated by the prefix “0b” —for example,
0b0011.0010.1100.1111.
iv
Preface
Revision Record
Revision
Date
Remarks
N/A
12/99
First printing.
2.0
05/00
Second printing. Released internally only. Miscellaneous
changes/corrections to reflect product qualification.
2.1
08/00
Third printing. Released externally to reflect the LSIFC909 general
customer acceptance (GCA).
Preface
v
vi
Preface
Contents
Chapter 1
Chapter 2
Introduction
1.1
Overview
1.1.1
Hardware Features
1.1.2
FC Features
1.1.3
Software Features
1.1.4
OS Support
1.1.5
Targeted Applications
1.2
General Description
1.3
Hardware Overview
1.3.1
PCI Interface
1.3.2
External 32-Bit Memory Controller
1.3.3
Protocol Engine (ARM)
1.3.4
System Interface
1.3.5
Link Controller
1.3.6
Integrated 1 Gbaud Transceiver
1.3.7
Context Manager
1.4
Initiator Operations
1.5
Target Operations
1.6
Diagnostics
1-1
1-1
1-2
1-2
1-3
1-3
1-3
1-4
1-6
1-6
1-6
1-6
1-6
1-7
1-7
1-7
1-7
1-8
Fibre
2.1
2.2
2.3
2.4
2.5
2-1
2-2
2-3
2-5
2-7
Channel Overview
Introduction
FC Layers
Frames
Exchanges
FC Ports
Contents
vii
2.6
2.7
Chapter 3
FC Topologies
2.6.1
Point-to-Point Topology
2.6.2
Fabric Topology
2.6.3
Arbitrated Loop Topology
Classes of Service
LSIFC909 Overview
3.1
Introduction
3.2
Data Flows
3.3
Message Interface
3.3.1
Messages
3.3.2
Message Flow
3.4
SCSI Message Class
3.5
LAN Message Class
3.6
Target Message Class
3.7
Support Components
3.7.1
SSRAM Memory
3.7.2
Flash ROM
3.7.3
Serial EEPROM
Chapter 4
Signal Descriptions
Chapter 5
Registers
5.1
PCI Addressing
5.2
PCI Bus Commands Supported
5.3
PCI Cache Mode
5.3.1
Support for PCI Cache Line Size Register
5.3.2
Selection of Cache Line Size
5.3.3
Memory Write and Invalidate Command
5.3.4
Read Commands
5.4
Unsupported PCI Commands
5.5
Programming Model
5.6
PCI Configuration Registers
5.7
Host Interface Registers
5.8
Shared Memory
viii
Contents
2-8
2-8
2-8
2-9
2-10
3-1
3-2
3-4
3-4
3-5
3-6
3-7
3-8
3-9
3-9
3-10
3-10
5-1
5-2
5-3
5-4
5-4
5-4
5-6
5-7
5-7
5-7
5-23
5-31
Chapter 6
Specifications
6.1
Electrical Requirements
6.2
AC Timings
6.2.1
PCI Interface Timing Diagrams
6.2.2
FC Interface Timings
6.2.3
Memory Interface Timings
6.3
Packaging
Appendix A
Register Summary
Appendix B
Reference Specifications
Appendix C
Glossary of Terms and Abbreviations
6-2
6-5
6-5
6-17
6-20
6-27
Index
Customer Feedback
Figures
1.1
1.2
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.1
3.2
3.3
3.4
LSIFC909 Typical Implementation
LSIFC909 Functional Block Diagram
FC Layers
Link Control Frame
Data Frame
Exchange to Character
FCP Exchange
Write Event Trellis
Point-to-Point Topology
Fabric Topology
Arbitrated Loop Topology
LSIFC909 Functional Block Diagram
LSIFC909 Message Flow
LAN Protocol Stack
LSIFC909 Typical Implementation
Contents
1-4
1-5
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-8
2-9
3-3
3-6
3-8
3-9
ix
4.1
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.13
6.14
6.15
6.16
6.17
6.18
6.19
LSIFC909 Functional Signal Grouping
Configuration Register Read
Configuration Register Write
Operating Register Read
Operating Register Write
Back-to-Back Read
Back-to-Back Write
Burst Read
Burst Write
Read with 64-Bit Initiator and 64-Bit Target
64-Bit Dual Address Cycle
FC OLC Receive Timing Waveforms
FC 10-Bit Receive Timing Waveforms
FC 10-Bit and OLC Transmit Timing Waveforms
SSRAM Read Timing Waveforms
SSRAM Write Timing Waveforms
Flash ROM Read Timing Waveforms
Flash ROM Write Timing Waveforms
LSIFC909 Pinout (329-Pad BGA) Top View
329-Pad Plastic Ball Grid Array
4-2
6-7
6-8
6-9
6-10
6-11
6-12
6-13
6-14
6-15
6-16
6-17
6-18
6-19
6-21
6-23
6-25
6-26
6-28
6-32
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
5.1
5.2
5.3
6.1
6.2
6.3
6.4
PCI Interface Signals
FC 10-Bit Interface Signals
FC G-Bit Interface Signals
Memory Interface Signals
Configuration Signals
Miscellaneous Signals
JTAG Test and IOP Debug Signals
Power and Ground Signals
PCI Bus Commands and Encoding Types
PCI Configuration Register Map
Host Interface Register Map
Absolute Maximum Stress Ratings
Operating Conditions
Input Signals
Capacitance
4-3
4-7
4-8
4-9
4-10
4-12
4-13
4-14
5-3
5-8
5-24
6-2
6-2
6-3
6-3
Tables
x
Contents
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.13
6.14
6.15
6.16
6.17
6.18
6.19
6.20
6.21
A.1
A.2
B.1
PCI Input Signals (PCICLK, RST/, GNT/, IDSEL,
M66EN, FSELPCI)
PCI Output Signals (REQ/, REQ64/, SERR/, INTA/)
8 mA Output Signals (TX[9:0], MCLK, MOE[1:0]/,
TBC, LED[3:0]/)
4 mA Output Signals (EN_CDET, EWRAP, LCK_REF/,
LIPRESET/, BYPASS/, MWE[1:0]/, FLASHCS/, SCL,
TDO_CHIP, TDO_ICE2, RAMCS/, ADSC/, ADV/,
MA[21:0], BWE[3:0]/, ODIS, WmIsoTest[2:0], ZZ)
PCI Bidirectional Signals (ACK64/, AD[63:0], C_BE[7:0]/,
FRAME/, IRDY/, TRDY/, DEVSEL/, STOP/, PERR/,
PAR, PAR64)
4 mA Bidirectional Signals (MD[31:0], MP[3:0], SDA)
8 mA Bidirectional Signals (GPIO[3:0])
PCI Interface Timings
FC OLC Receive Timings
FC 10-Bit Receive Timings
FC 10-Bit and OLC Transmit Timings
SSRAM Read Timings
SSRAM Write Timings
Flash ROM Read Timings
Flash ROM Write Timings
Alphanumeric List by BGA Position
Alphanumeric List by Signal Name
LSIFC909 Configuration Space
LSIFC909 Mem0 and I/O Space
Reference Specifications
Contents
6-3
6-3
6-4
6-4
6-4
6-5
6-5
6-17
6-18
6-19
6-20
6-22
6-24
6-25
6-26
6-30
6-31
A-1
A-2
B-1
xi
xii
Contents
Chapter 1
Introduction
This chapter provides general overview information on the
LSIFC909 Fibre Channel (FC) PCI Protocol Controller chip. The chapter
contains the following sections:
•
Section 1.1, “Overview”
•
Section 1.2, “General Description”
•
Section 1.3, “Hardware Overview”
•
Section 1.4, “Initiator Operations”
•
Section 1.5, “Target Operations”
•
Section 1.6, “Diagnostics”
1.1 Overview
The LSIFC909 is a high-performance cost effective FC PCI protocol
controller. It represents the very latest system level integration
technology in intelligent I/O processors (IOP) from LSI Logic. The
Storage Area Network (SAN) environment is fully supported with both
Fibre Channel Protocol (FCP) for SCSI and LAN/IP.
1.1.1 Hardware Features
The LSIFC909 includes these hardware features:
•
Highly integrated full duplex FCP controller
•
Integrated Bit Error Rate (BER) link testing
•
64-bit/66 MHz host PCI bus
•
Integrated 1 Gbaud FC serial link
•
32-bit ARM RISC processor
LSIFC909 Fibre Channel I/O Processor
1-1
•
Intelligent high-performance context management
•
Synchronous SRAM external memory interface
•
Full target and initiator operations
•
Supports up to 1024 concurrent host commands (with 1 Mbyte
external memory)
•
PC99 compliant
•
PCI 2.2 compliant
•
JTAG debug interface
•
329-pin BGA
1.1.2 FC Features
The LSIFC909 includes these FC features:
•
Class 2 and Class 3 support
•
BB credit of 3, alternate login of 1
•
FC-PH compliance
•
FC-AL2 compliance
•
FC-FCP, FC-PLDA compliance
•
FC-FLA compliance
•
FCA-IP, IETF-IPFC compliance
•
Private Loop Attach
•
Public Loop Attach
•
Fabric Direct Attach
•
Point-to-Point
1.1.3 Software Features
The LSIFC909 includes these software features:
1-2
•
Supports optimum server I/O profile with low CPU utilization
•
Supports optimum workstation I/O profile with maximum I/O
performance
•
Remote diagnostic capability
Introduction
1.1.4 OS Support
The LSIFC909 supports the following:
•
Windows NT 4.0 SP4 and later, and Windows 2000
•
NetWare 4.11 and 5.0
•
UnixWare 2.12 and Gemini
•
Solaris 2.6, 2.7 – X86
•
Linux
1.1.5 Targeted Applications
The LSIFC909 targets the following applications:
•
SANs
•
Server clustering environments
•
Embedded RAID
•
Low cost PCI/FC host adapters
•
Host motherboards
1.2 General Description
The LSI Logic LSIFC909 FCP Controller is a high-performance,
Intelligent IOP designed to simultaneously support mass storage
protocols on a full duplex FC link. The sophisticated design and local
memory architecture work together to reduce the host CPU and PCI
bandwidth required to support FC I/O operations.
From the host CPU perspective, the LSIFC909 manages the FC link at
the exchange level for mass storage (FCP) protocols. The LSIFC909
supports multiple I/O requests per host interrupt in certain applications.
From the FC link perspective, the LSIFC909 is a highly efficient NL_Port
supporting point-to-point, and public and private loop topologies, as well
as the FC switch/attach topology defined under the ANSI X3T11 FC-PH
standard. Both Class 3 and Class 2 levels of service are provided. The
LSIFC909 is uniquely designed to support FC environments where
independent, full duplex transmission is required for maximum FC link
General Description
1-3
efficiency. Special attention has been given to the design to accelerate
context switching and link utilization.
The LSIFC909 includes a 64-bit, 66 MHz PCI interface to the host
environment. This high speed (528 Mbytes/s), industry standard interface
provides sufficient bandwidth to the host CPU and system memory to
support full duplex FC data rates. The host interface design minimizes
the time spent on the PCI bus for nondata moving activities such as
initialization, command, and error recovery. In addition, the host interface
has the inherent flexibility to support the OEM implementation tradeoffs
between CPU, PCI, and I/O bandwidth.
The high level of integration in the LSIFC909 Controller enables low cost
FC implementations. Figure 1.1 shows a typical configuration
incorporating the LSIFC909 Controller to implement a FC NL_Port.
Figure 1.1
LSIFC909 Typical Implementation
2
2
PCI Bus
10
External
Transceiver
10
32/64
LSIFC909
2
Integrated
Transceiver
2
Memory
Controller
32
Clock
(106 MHz)
SSRAM
(1 Mbyte typ.)
Flash
(1 Mbyte)
Serial
EEPROM
(2 Kbyte)
1.3 Hardware Overview
In today’s fast growing server, RAID, and workstation marketplaces,
higher levels of performance, scalability, and reliability are required to
stay competitive in the SAN market.
1-4
Introduction
The LSIFC909 provides the performance and flexibility to meet
tomorrow’s FC connectivity requirements.
The LSIFC909 and the LSI Logic software drivers provide superior
performance and lower host CPU overhead than other competitive
solutions. Because of its high level of integration and streamlined
architecture, the LSIFC909 provides the highest level of performance in
a more overall cost effective FC solution.
Figure 1.2 shows the functional block diagram for the LSIFC909. The
architecture maximizes performance and flexibility by deploying fixed
gates in critical performance areas and utilizing dual ARM RISC
processors (one for context management and the second in the IOP).
Each of the major blocks is briefly described below.
Figure 1.2
LSIFC909 Functional Block Diagram
PCI
Bus
Tx
Transmit
Buffers
Integrated
Transceiver
Link
Controller
Frame
Transmitter
Context
Managers
(ARM)
Data
Mover
Bus
UPI-64
32/64
Interface
Unit
Frame
Receiver
Receive
Buffers
Rx
Internal Module Bus
TX[9:0]
RX[9:0]
External Memory
Controller
Protocol Engine
(ARM)
LSIFC909
= Data Path
= Control Path
Flash
ROM
Hardware Overview
SSRAM
Serial
EEPROM
1-5
1.3.1 PCI Interface
The host PCI interface implements a 64-bit/66 MHz PCI bus. It is
backward compatible with 32-bit and 33 MHz buses. In addition, the PCI
interface provides support for Dual Address Cycle (DAC), PCI power
management, Subsystem Vendor ID and Vendor Product Data (VPD).
Extended access cycles (MRL, MRM, MWI) are also supported.
1.3.2 External 32-Bit Memory Controller
The memory controller provides access to the serial EEPROM, the Flash
ROM, and the 32-bit synchronous SRAM. It supports both interleaved
and noninterleaved configurations up to a maximum of 4 Mbytes of
synchronous SRAM. A general purpose memory expansion bus supports
up to 1 Mbyte of Flash ROM.
1.3.3 Protocol Engine (ARM)
The LSIFC909 uses a 32-bit ARM RISC processor to control all system
interface and message transport functionality. This frees the host CPU
for other processing activity and improves overall I/O performance. The
RISC processor and associated firmware has the ability to manage an
I/O from start to finish without host intervention. The RISC processor also
manages the message passing interface.
1.3.4 System Interface
The system interface efficiently passes messages between the
LSIFC909 and other I/O agents. It consists of four hardware FIFOs for
the message queuing lists: Request Free, Request Post, Reply Free, and
Reply Post. Control logic for the FIFOs is provided within the LSIFC909
system interface with messages stored in external memory.
1.3.5 Link Controller
The integrated Link Controller is FC-AL-2 compatible and performs all
link operations. The controller monitors the link state and strictly adheres
to the loop port state machine ensuring maximum system interoperability.
The link control interfaces to the integrated transceiver and is capable of
supporting the 10b interface specification allowing for an externally
connected 10b (industry standard) FC transceiver.
1-6
Introduction
1.3.6 Integrated 1 Gbaud Transceiver
The integrated 1 Gbaud transceiver provides a FC compliant physical
interface for cost conscience and real estate limited applications.
1.3.6.1 Transmitter
The transmitter builds sequences based on context information and
transmits resulting frames to the FC link using the Link Controller. The
transmitter includes two 2 Kbyte buffers to support frame payloads.
1.3.6.2 Receiver
The receiver accepts frame data from the Link Controller and DMAs the
encapsulated information to local or system memory. The receiver
contains three 2 Kbyte buffers which support a BB-Credit of up to three
or an alternate login BB-Credit of one.
1.3.7 Context Manager
The LSIFC909 uses a second ARM RISC processor to support I/O
context swap to external memory and FCP management for both initiator
and target applications. Context operations include support for transmit
and resource queue management as well as Scatter Gather List (SGL)
management.
1.4 Initiator Operations
The LSIFC909 autonomously handles FCP exchanges upon request
from the host. The LSIFC909 generates appropriated sequences and
frames necessary to complete the request and provides feedback to the
host on the status of the request.
1.5 Target Operations
The LSIFC909 provides for general purpose target functions such as
those required for front-end RAID applications.
Initiator Operations
1-7
1.6 Diagnostics
The LSIFC909 provides the capabilities to do a simplified “link check”
BER test on the link for diagnostic purposes. In a special test mode the
controller can transmit and verify a programmed data pattern for link
evaluation.
1-8
Introduction
Chapter 2
Fibre Channel
Overview
This chapter provides general overview information on FC. The chapter
contains the following sections:
•
Section 2.1, “Introduction”
•
Section 2.2, “FC Layers”
•
Section 2.3, “Frames”
•
Section 2.4, “Exchanges”
•
Section 2.5, “FC Ports”
•
Section 2.6, “FC Topologies”
•
Section 2.7, “Classes of Service”
2.1 Introduction
FC is a high-performance, hybrid interface. It is both a channel and a
network interface that contains network features to provide the required
connectivity, distance, protocol multiplexing, as well as traditional channel
features to retain the required simplicity, repeatable performance, and
guaranteed delivery. Popular industry standard networking protocols
such as Internet Protocol (IP) and channel protocols such as Small
Computer System Interface (SCSI) have been mapped to the FC
standard.
The FC structure is defined by five functional layers. These layers,
shown in Figure 2.1, define the physical media and transmission rates,
encoding scheme, framing protocol and flow control, common services,
and the Upper Layer Protocol (ULP) interfaces.
LSIFC909 Fibre Channel I/O Processor
2-1
Figure 2.1
FC Layers
Behaviors
System
Interface
Logical
Layers
FC-4
Physical
Layers
Upper Layer Protocol
FCP
IPI-3
HIPPI
ESCON
FC-3
Common Services
FC-2
Framing Protocol/Flow Control
FC-1
8b/10b Encode/Decode
FC-0
1062
Mbits/s
Mbytes/s
100
2124
4248
(Full Duplex)
200
400
IP
8496
FC-PH-2
800
2.2 FC Layers
The lowest layer, FC-0, is the media interface layer. It defines the
physical characteristics of the interface. It includes transceivers,
copper-to-optical transducers, connectors, and any other associated
circuitry necessary to transmit or receive at 1062 or greater Mbaud/s
rates over copper or optical cable.
The FC-1 layer defines the 8b/10b encoding/decoding scheme, the
transmission protocol necessary to integrate the data and transmit clock,
and the receive clock recovery. Implementation of this layer is usually
divided between the hardware implementing the FC-0 layer in a
transceiver, and the protocol device which implements the FC-2 layer.
Specifically, the FC-0 transceivers can include the clock recovery circuitry
while the protocol device provides the 8b/10b encoding/decoding.
The FC-2 layer defines the rules for the signaling protocol and describes
transfer of the Frames, Sequences, and Exchanges. The meaning of the
data being transmitted or received is transparent to the FC-2 layer.
However, the FC-2 layer maintains the context between any given set of
2-2
Fibre Channel Overview
frames through the Sequence and Exchange constructs. The framing
protocol creates the constructs necessary to form frames with the data
being packetized within each frame’s payload.
The FC-3 layer defines a set of services that are common across multiple
ports of a node (see Section 2.5, “FC Ports,” page 2-7). All of these
services allow a single port or fabric to communicate to several N_Ports
at one time. For more information regarding the FC-3 layer, please
consult the most current version of FC-PH.
The top layer defined in FC is the FC-4 layer. The FC-4 layer provides a
seamless integration of existing standards. It specifies the mapping of
ULPs to the layers below. Some of these ULPs include SCSI and IP.
Each of these ULPs is defined in its own ANSI document.
2.3 Frames
There are two types of frames used in FC: Link Control frames and Data
frames. Link Control frames contain no payload and are flow control
responses to Data frames. An example of a Link Control frame
(Figure 2.2) is the ACK frame.
Figure 2.2
Link Control Frame
Start
of
Frame
Frame
Header
CRC
End
of
Frame
(4)
(24)
(4)
(4)
( ) = Number of Bytes
Frames
2-3
A Data frame (Figure 2.3) is any frame which contains data in the
payload field. An example of a Data frame is the LOGIN frame.
Figure 2.3
Data Frame
Start
of
Frame
Frame
Header
Data Field
(Optional Headers and
Payload)
CRC
End
of
Frame
(4)
(24)
(0 to 2112)
(4)
(4)
( ) = Number of Bytes
In FC, an ordered set is a group of four 10-bit characters that provide low
level link functions, such as frame demarcation and signaling between
two ends of a link. All frames start with a Start-of-Frame (SOF) and end
with an End-of-Frame (EOF) ordered set. Each frame contains at least a
24-byte header defining such things as destination and source ID, class
of service and type of frame (e.g., FCP or FC-LE). The biggest field
within a frame can be the payload field. If the frame is a Link Control
frame, then there is no payload. If it is a Data frame, then the frame
contains a payload field of up to 2112 bytes. Finally, the frame includes
a Cyclic Redundancy Check (CRC) field used for detection of
transmission errors, followed by the EOF ordered set.
2-4
Fibre Channel Overview
2.4 Exchanges
Figure 2.4 outlines the FC hierarchical data structures. At the most
elemental level, four 8b/10b encoded characters make up a FC Word. A
FC Frame is a collection of FC words. A FC Sequence consists of one
or more frames, and a FC Exchange consists of one or more sequences.
Figure 2.4
Exchange to Character
EXCHANGE
SEQ 1
SEQ 2
SEQ 3
SEQ 4
SEQ N
FRAME 1
FRAME 2
FRAME 3
FRAME 4
FRAME N
SOF
HEADER
K28.5 D21.5 D23.0 D23.0
0 0 1 1 1 1 1 0 1 0
Exchanges
DATA
CRC
EOF
Frame
Word
Character
2-5
The following discussion illustrates an Exchange by considering a typical
parallel SCSI I/O. In parallel SCSI, there are several phases that form the
I/O. These phases include Command, Data, Message, and Status
phases.
The FCP for the SCSI ULP maps these phases into the other lower FC
layers. Figure 2.5 shows the components that form the FCP Exchange.
Figure 2.5
FCP Exchange
FCP EXCHANGE
CMDSEQ
DataReqSEQ
FRAME 1
FRAME 1
FRAME 1
2-6
Fibre Channel Overview
DataSEQ
ResponseSEQ
FRAME 1
FRAME 2
FRAMEn
Figure 2.6 shows how the Exchange flows between the initiator and
target. The initiator starts the FCP Exchange by sending a Command
Sequence containing one frame to the target. The frame’s payload
contains the Command Descriptor Block (CDB). The target responds
with a Data Delivery Request Sequence containing one frame. The
payload of this frame contains a XFER_RDY response. Once the initiator
receives the target’s response, it begins sending the Data Sequence(s),
which may contain one or more frames. This is analogous to parallel
SCSI’s DATA_OUT phase. When the target has received the last frame
of the Data Sequence(s), it sends a Response Sequence containing one
frame to the initiator, thus concluding the FCP Exchange.
Figure 2.6
Write Event Trellis
Initiator
Target
Fabric
CMD SEQ
Data Req SEQ
Data SEQ Frame 1
Data SEQ Frame 2
Data SEQ Frame N
RSP SEQ
2.5 FC Ports
FC devices are called nodes. Each node has at least one port to provide
access to other ports in other nodes. The “port” is the hardware entity
within a node that performs data communications over the FC link.
The FC standard defines a variety of types of ports, based on the
location of the port and the topology associated with it. The most
commonly used ports are N_Ports, NL_Ports, F_Ports, and FL_Ports.
These types of ports appear in Figure 2.7, Figure 2.8 and Figure 2.9.
FC Ports
2-7
2.6 FC Topologies
Topologies are defined based on the capability and the presence or
absence of fabric between the N_Ports:
•
Point-to-Point topology
•
Fabric topology
•
Arbitrated Loop topology
FC-PH protocols are topology independent. Attributes of a fabric may
restrict operation to certain communication models.
2.6.1 Point-to-Point Topology
The topology shown in Figure 2.7, in which communication between
N_Ports occurs without the use of fabric, is defined as point-to-point.
Figure 2.7
Point-to-Point Topology
N_Port A
N_Port B
2.6.2 Fabric Topology
This topology uses the Destination_Identifier (D_ID) embedded in the
frame header to route the frame through a fabric to the desired
destination N_Port. Figure 2.8 illustrates multiple N_Ports interconnected
by a fabric.
Figure 2.8
Fabric Topology
N_Port
F_Port
N_Port
F_Port
Fabric
F_Port
N_Port
F_Port
N_Port
2-8
Fibre Channel Overview
2.6.3 Arbitrated Loop Topology
The arbitrated loop topology permits 2 to 127 L_Ports to communicate
without the use of a fabric, as in fabric topology. The arbitrated loop
supports a maximum of one point-to-point circuit at a time. When two
L_Ports are communicating, the arbitrated loop topology supports
simultaneous, symmetrical bidirectional flow.
Figure 2.9 illustrates two independent arbitrated loop configurations,
each with multiple L_Ports attached. Each line in the figure between
L_Ports represents a single fibre. The lower configuration shows an
arbitrated loop composed of three NL_Ports and one FL_Port (a public
loop).
Figure 2.9
NL_Port
Arbitrated Loop Topology
NL_Port
Private Loop
NL_Port
NL_Port
Fabric
Element
NL_Port
FL_Port
Public Loop
NL_Port
FC Topologies
NL_Port
2-9
2.7 Classes of Service
There are several classes of service in FC. The different classes are
distinguished from each other in three ways: by the level of guarantee for
data being delivered, the order in which data is delivered, and how data
flow control is maintained.
Class 1 is a dedicated connection between two N_Ports. The data
delivered is guaranteed with a required acknowledgement frame (ACK),
which a Class 1 device uses for flow control. All frames are received in
order.
Class 2 is a connectionless class. The data delivered is guaranteed with
an ACK. The frames can be received out of order. Class 2 uses both
ACK frames and the R_RDY ordered set for flow control.
Class 3 is also a connectionless class; however, the data being delivered
is not guaranteed. The frames can be received out of order. Class 3 uses
only the R_RDY ordered set for flow control.
Intermix is an enhancement of Class 1 service. A dedicated Class 1
connection may waste fabric bandwidth while frames are not being
transmitted or received between two N_Ports. In order to recover some
of this bandwidth, Intermix allows Class 2 and Class 3 frames to be
transmitted/received between Class 1 frames. N_Ports advertising
Intermix capability must be capable of receiving Class 2 and Class 3
frames from other N_Ports while maintaining the original Class 1 link.
2-10
Fibre Channel Overview
Chapter 3
LSIFC909 Overview
This chapter provides a general description of the LSIFC909 FC PCI
Protocol Controller firmware. The chapter contains the following sections:
•
Section 3.1, “Introduction”
•
Section 3.2, “Data Flows”
•
Section 3.3, “Message Interface”
•
Section 3.4, “SCSI Message Class”
•
Section 3.5, “LAN Message Class”
•
Section 3.6, “Target Message Class”
•
Section 3.7, “Support Components”
3.1 Introduction
The LSI Logic LSIFC909 connects a host to a high speed FC link. The
LSIFC909 sophisticated firmware implementation supports the FCP
ANSI standard and FC Private Loop Direct Attach (and Fabric Loop
Attach) profiles. All profiles, specifications, and interoperability
maintained by the LSIFC909 are listed in Appendix B, “Reference
Specifications.”
Although optimized for a 64-bit PCI interface to communicate with the
system CPU(s) and memory, the LSIFC909 also supports a 32-bit PCI
environment. The system interface to the LSIFC909 minimizes the
amount of PCI bandwidth required to support I/O requests. A packetized
message passing interface reduces the number of single cycle PCI bus
cycles. All FC Data traffic on the PCI bus occurs with zero wait-state
bursts across the PCI bus.
LSIFC909 Fibre Channel I/O Processor
3-1
The intelligent LSIFC909 architecture allows the system to specify I/Os
at the command level. The LSIFC909 manages I/Os at the Frame,
Sequence and Exchange level. The LSIFC909 also handles error
detection and I/O retries, allowing the system to offload part of the
exception handling work from the system driver.
3.2 Data Flows
The LSIFC909 uses a 64-bit (33 MHz or 64 MHz) PCI interface or a
32-bit (33 MHz or 64 MHz) PCI interface to pass control and data
information between the system and the protocol controller. This
interface is managed by a Universal PCI Interface (UPI) block, as shown
in Figure 3.1. The Data Mover block manages the movement of data
contained in the transmit and receive buffers, from and to the system.
The Data Mover aligns multiple incoming scatter/gather data entries to
the Frame Transmitter. The Frame Transmitter contains separate buffers
for data and control information. The Frame Transmitter uses necessary
context information to create FC frames. Each Data frame contains all or
a portion of a particular scatter/gather entry. The Frame Transmitter also
generates Transmit frames for FC link communication and flow control.
The LSIFC909 Transmit Context Manager block manages the order and
priority of each frame. All frames to be transmitted are passed along to
the Link Controller. Once the Link Controller has been notified of pending
Transmit frames, it begins inserting each frame onto the link. Each byte
within the frame is 8b/10b encoded and transferred to the physical link
using a 10-bit parallel interface or using the serial link with the integrated
transceiver.
3-2
LSIFC909 Overview
Figure 3.1
LSIFC909 Functional Block Diagram
PCI
Bus
Tx
Transmit
Buffers
Integrated
Transceiver
Link
Controller
Frame
Transmitter
Context
Managers
(ARM)
Data
Mover
Bus
UPI-64
32/64
Interface
Unit
Frame
Receiver
Receive
Buffers
Rx
Internal Module Bus
TX[9:0]
RX[9:0]
External Memory
Controller
Protocol Engine
(ARM)
LSIFC909
= Data Path
= Control Path
Flash
ROM
SSRAM
Serial
EEPROM
For incoming serial data, the physical link transfers the data to the Link
Controller using the 10-bit parallel interface or the serial link with the
integrated transceiver. The Link Controller analyzes the received frame
and if appropriate, it passes the frame to the Frame Receiver. The Frame
Receiver strips off the frame header and places it in a separate header
buffer while the data in the frame payload is placed in a data buffer. The
Frame Receiver uses the Receive Context Manager to manage the
received frame’s order and priority. The data contained in the receiver
buffers is associated with a specific scatter/gather entry and passed on
to the Data Mover. The Data Mover aligns the data and passes it on to
the UPI. The UPI requests the PCI bus and bursts the data into system
memory.
The IOP, with its firmware, provides the translation from FC specific
protocols to the high level Block Storage, SCSI and LAN message
interface. This translation integrates the LSIFC909 into the system as if
it were a native parallel SCSI or LAN device, hiding all FC unique
characteristics. Internal communication between the IOP and the Context
Manager occurs over a bus called the Internal Module Bus, which is also
Data Flows
3-3
connected to an External Memory Controller. The IOP uses the External
Memory Controller to access local memory. This memory contains the
firmware, as well as the dynamic data structures used by the firmware.
3.3 Message Interface
The LSIFC909 system interface is a high-performance, packetized,
mailbox architecture which leverages the intelligence in the LSIFC909 to
minimize traffic on the PCI bus.
There are two basic constructs in the message interface. The first
construct, the message, is used to communicate between the system
and the LSIFC909. Messages are moved between the system(s) and the
LSIFC909 using the second construct, a transport mechanism.
3.3.1 Messages
The LSIFC909 uses two types of messages to communicate with the
system. The system creates request messages to “request” an action by
the LSIFC909. The LSIFC909 uses reply messages to send status
information back to the system. Request message data structures are up
to 128 bytes in length. The message includes a message header and a
payload. The header includes information to uniquely identify the
message. The payload is specific to the request itself, and is unique for
Block Storage, SCSI, LAN, and Target messages. For more information
regarding the details of the message format, refer to the LSI Logic
LSIFC909 Programming Guide.
3-4
LSIFC909 Overview
3.3.2 Message Flow
Before requests can be posted to the LSIFC909, the system must
allocate and initialize a pool of message frames, and provide a
mechanism to assign individual message frames, on a per-request basis.
Refer to Figure 3.2. The host must also provide one message frame per
target LUN, and prime the Reply Free FIFO with the physical address of
these message frames. Once allocation has been completed, requests
flow from the host to the LSIFC909, as follows:
1. The host driver receives an I/O request from the operating system.
2. The host driver allocates a system message frame and builds an I/O
request message within the system message frame. The allocation
method is the responsibility of the host driver.
3. The host driver creates the Message Frame Descriptor (MFD), and
writes the MFD to the Request Post FIFO.
4. The Input/Output Controller (IOC) reads the MFD from the Request
Post FIFO and DMA’s the request to a local message frame.
5. The IOC sends the appropriate FC request, and subsequently
receives the reply from the target.
–
If the I/O status is successful, the IOC writes the
MessageContext value, plus turbo reply bits, to the Reply Post
FIFO, which automatically generates a system interrupt.
–
If the I/O status is not successful, the IOC pops a reply message
frame from the Reply Free FIFO, and generates a reply message
in the reply message frame. The IOC then writes the system
physical address of the reply message frame to the Reply Post
FIFO, which generates a system interrupt.
6. The host driver receives an interrupt and reads the Reply Interrupt
bit in the Host Interrupt Status register. If the Reply Interrupt bit = 1,
then the host reads the Reply register. If there are no posted
messages, the system reads the value 0xFFFFFFFF.
7. The host driver responds to the operating system appropriately.
8. If the I/O status is not successful, the host driver returns the
message frame descriptor to the Reply Free FIFO.
Message Interface
3-5
Figure 3.2
LSIFC909 Message Flow
Operating
System
1
1
2
3
7
Message
Frames
2
Host
Driver
6
MFD
3
PCI Bus
1
2
8
6
Request Register
3
N
Reply Register
5
1
2
4
1
2
4
5
N
Request
Post
FIFO
IOC
N
N
Reply
Post
FIFO
Reply
Free
FIFO
3.4 SCSI Message Class
The SCSI message interface provides the most direct interface for
block-oriented storage media. This includes disk drives and tape devices.
The SCSI I/O path translates a SCSI CDB into an FCP exchange. The
LSIFC909 completely manages all FC device and target discovery
operations. FC target devices are assigned a logical (bus, target ID)
identifier, and are accessed by the system as if they were parallel SCSI
devices. The system is responsible for scanning the target devices, and
identifying LUNs on the target devices.
In general, the system is responsible for retrying operations at an I/O
request level. The LSIFC909 is responsible for responding to bus
protocol specific errors and exceptions and retrying bus sequences
within the scope of an I/O operation. The system is also responsible for
maintaining a timer for SCSI I/O operations if this is required by the host
system. The host driver may use the provided SCSI task management
functions to terminate one or more I/O operations when a time-out
occurs. For more information regarding the SCSI message class, refer to
the LSI Logic LSIFC909 Programming Guide.
3-6
LSIFC909 Overview
3.5 LAN Message Class
The LSIFC909 provides a LAN message interface that supports the
system TCP or UDP network driver stack, providing MAC level
communication between FC ports.
The typical network driver stack in the system consists of a socket driver
with a transport driver interface, supported by TCP or UDP and IP
drivers, and a hardware abstraction layer interface to the LSIFC909. The
TCP driver provides data buffer segmentation. The IP driver provides
Message Transfer Unit (MTU) segmentation, adds a header and
checksum to the TCP data, and maps each FC MAC port address to an
IEEE standard address. The TCP driver requires ACKs to ensure all
segments of the data block are transmitted/received.
The LAN message interface may also be used by proprietary protocol
stacks in the host. In this environment, the LSIFC909 transmits and
receives data between FC nodes, without regard to data content. See
Figure 3.3 on page 3-8. For more information regarding the LAN
message class, refer to the LSI Logic LSIFC909 Programming Guide.
LAN Message Class
3-7
Figure 3.3
LAN Protocol Stack
Applications
16 Kbytes
Paged Data
Sockets Interface
Transport
Driver Interface
TCP Header
w/Checksum TCP Data (var.)
Transmission
Control Protocol
IP Header
w/Checksum
TCP Header
w/Checksum TCP Data (var.)
Internet
Protocol Driver
IP Header
w/Checksum
TCP Header
TCP Data (var.)
w/Checksum
Driver Interface
IEEE
Address
HAL
PCI
LSIFC909 LAN Class
MAC Header
FC Sequence/Frame
FC Framer
FC
3.6 Target Message Class
The target interface allows the LSIFC909 to be used as the system
interface for FC bridge controllers. The LSIFC909 provides an FCP
exchange level message interface that routes commands to the system.
The system identifies the appropriate data, and passes an SGL to the
LSIFC909 describing the data to transfer. A single target message
directs the LSIFC909 to send a Xfer Rdy, as needed, and to transfer data
and FCP response. Target specific process login/logout is managed by
the system. For more information regarding the target message class,
refer to the LSI Logic LSIFC909 Programming Guide.
3-8
LSIFC909 Overview
3.7 Support Components
The memory controller block within the LSIFC909 provides access to
external local memory resources required to manage FCP.
The following sections provide guidance in choosing the support
components necessary for a fully functional implementation using the
LSIFC909. A LSIFC909 typical implementation diagram is shown below
in Figure 3.4 for reference.
Figure 3.4
LSIFC909 Typical Implementation
2
PCI Bus
10
External
Transceiver
2
10
32/64
LSIFC909
2
Integrated
Transceiver
2
Memory
Controller
32
Clock
(106 MHz)
SSRAM
(1 Mbyte typ.)
Flash
(1 Mbyte)
Serial
EEPROM
(2 Kbytes)
3.7.1 SSRAM Memory
The SSRAM memory stores a run time image of the LSIFC909 firmware.
This memory also stores data structures used by the LSIFC909 to
manage exchanges and transmit and receive queues.
The LSIFC909 uses a 32-bit nonmultiplexed memory bus to access the
SSRAM. This memory bus has the capability to address up to 4 Mbytes
of SSRAM.
The LSIFC909 firmware also supports optional byte wide parity error
detection. This option is configurable, and is specified as a serial
EEPROM parameter.
Support Components
3-9
The amount of SSRAM (1 Mbyte) determines the maximum number of
outstanding Request Messages (1024). This roughly equates to the
maximum number of outstanding I/O requests pending in the LSIFC909.
3.7.2 Flash ROM
The memory controller in the LSIFC909 also manages an optional Flash
ROM. If present, the Flash ROM is used to store the firmware for the
LSIFC909 IOP, and if desired, the INT 0x13 boot software.
If the Flash ROM is not used, then the host platform is responsible for
downloading the IOP firmware to the LSIFC909 through the PCI
interface. The LSIFC909 supports a diagnostic interface, enabled
through a sequence of commands issued to the PCI configuration space.
Firmware may be directly written to the LSIFC909 internal memory and
external SSRAM through the diagnostic interface. Details of this
implementation are available in the LSI Logic LSIFC909 Programming
Guide. Flash ROM is needed for firmware storage if INT 0x13 boot
software is used.
The Flash ROM is accessed using the upper eight bits of the Memory
Interface. If a Flash ROM is to be used, then it should have a capacity
of 1 Mbyte with a maximum access time of 150 ns. Please see the
LSI Logic LSIFC909 Programming Guide for more information regarding
the programming of the Flash ROM.
3.7.3 Serial EEPROM
The serial EEPROM stores the World Wide Name, VPD, and other
vendor specific information. It is programmed using the host interface of
the LSIFC909. The required size of the EEPROM is 2 Kbytes.
Note:
3-10
The LSIFC909 uses a serial EPROM autodownload that is
set to run at 100 Kbits/s. Please refer to your serial EPROM
vendor data sheet for more information.
LSIFC909 Overview
Chapter 4
Signal Descriptions
This chapter presents the LSIFC909 pin configurations and signal
definitions using tables. A slash (/) indicates an active LOW signal,
I/O = bidirectional signal, I = input signal, O = output signal,
T/S = 3-state, and S/T/S = sustained 3-state. Figure 4.1 on page 4-2 is
a functional signal grouping for the chip.
LSIFC909 Fibre Channel I/O Processor
4-1
Figure 4.1
LSIFC909 Functional Signal Grouping
LSIFC909
Memory
Interface
PCI
Interface
4-2
Signal Descriptions
MD[31:0]
MP[3:0]
MA[21:0]
MOE[1:0]/
MWE[1:0]/
FLASHCS/
MCLK
ADSC/
ADV/
BWE[3:0]/
RAMCS/
ZZ
PCICLK
RST/
GNT/
REQ/
REQ64/
ACK64/
AD[63:0]
C_BE[7:0]/
IDSEL
FRAME/
IRDY/
TRDY/
DEVSEL/
STOP/
PERR/
SERR/
PAR
PAR64
INTA/
M66EN
FSELPCI
TX[9:0]
RX[9:0]
EN_CDET
EWRAP
LCK_REF/
TBC
RBC[1:0]
RXLOS
Fibre Channel
10-Bit Interface
TX+
TX−
RX+
RX−
IREF
LIPRESET/
FAULT/
ODIS
BYPASS/
WMSEL
REFCLK
Fibre Channel
G-Bit Interface
TCK_CHIP
TRST_CHIP/
TDI_CHIP
TDO_CHIP
TMS_CHIP
TMS_ICE1
TCK_ICE2
TRST_ICE2/
TDI_ICE2
TDO_ICE2
TMS_ICE2
JTAG and
Core Debug
ROMSIZE[1:0]
TESTRESET/
ARMEN/
FSELZ
MODE[7:0]
Configuration
GPIO[3:0]
LED[3:0]/
SCL
SDA
ZCLK
WmlsoTest[2:0]
Miscellaneous
Table 4.1 describes the PCI Interface signals.
Table 4.1
PCI Interface Signals
Name
BGA Pos
Type
Strength Description
PCICLK
Y11
I
N/A
Clock provides timing for all transactions on the
PCI bus and is an input to every PCI device. The
LSIFC909 samples all other PCI signals on the
rising edge of PCICLK, and other timing
parameters are defined with respect to this edge.
RST/
V3
I
N/A
Reset forces the PCI sequencer of the device to
a known state. All 3-state and sustained
3-state signals are forced to a high impedance
state, and all internal logic is reset. The RST/
input is synchronized internally to the rising edge
of PCICLK. The PCICLK input must be active
while RST/ is asserted to properly reset the
device.
GNT/
W1
I
N/A
Grant indicates to the agent that access to the
PCI bus has been granted. This is a point-to-point
signal. Every master has its own GNT/.
REQ/
W2
O
16 mA
Request indicates to the system arbiter that this
agent desires use of the PCI bus. This is a pointto-point signal. Every master has its own REQ/.
REQ64/
Y15
O
16 mA
Request64 indicates that the current bus master
desires to transfer data using 64 bits. REQ64/ is
sampled at the end of reset to indicate the
presence of a 64-bit bus.
ACK64/
AA15
S/T/S
16 mA
Acknowledge64 is an input from the target that
decodes the address, and indicates that the
target is willing to complete a 64-bit transfer. The
LSIFC909 may also assert this signal when
accessed as a slave to complete a 64-bit transfer.
4-3
Table 4.1
PCI Interface (Cont.) Signals
Name
BGA Pos
AD[63:0]
AC18, Y16,
AB18, AA18,
AC19, Y19,
AB19, AA19,
AC20, AB20,
AC21, AB21,
AC22, AB22,
AC23, AB23,
AA20, AA22,
AA23, Y21,
Y22, Y23, W20,
W21, W22,
W23, V21, V22,
V23, U21, U23,
T20, W3, Y1,
Y2, Y3, AA1,
AA2, AB1, AB2,
AC3, AB3, AC4,
AB4, AA4, AC5,
AB5, Y5, AA9,
AC10, AC11,
AB11, AA11,
AC12, AB12,
AA12, AB13,
AA13, Y13,
AC14, AB14,
AA14, AB15,
AC15
C_BE[7:0]/ AC16, AA16,
AB16, AC17,
AC2, AA5, Y8,
AC13
IDSEL
4-4
AC1
Type
Strength Description
T/S
16 mA
The physical long word Address and Data are
multiplexed on the same PCI pins. During the first
clock of a transaction, AD[63:0] contains a
physical byte address. During subsequent clocks,
AD[63:0] contain data. A bus transaction consists
of an address phase followed by one or more
data phases. PCI supports both read and write
bursts. AD[7:0] define the least significant byte,
and AD[63:56] define the most significant byte.
AD[63:32] contain an internal 25 µA pull-up.
T/S
16 mA
Bus Command and Byte Enables are
multiplexed on the same PCI pins. During the
address phase of a transaction, C_BE[3:0]/
define the bus command. During the data phase,
C_BE[7:0]/ are used as byte enables. The byte
enables determine which byte lanes carry
meaningful data. C_BE[0]/ applies to the least
significant byte, and C_BE[7]/ to the most
significant byte. Byte enables are active LOW.
C_BE[7:4] contain an internal 25 µA pull-up.
I
N/A
Initialization Device Select is used as a chip
select in place of the upper 24 address lines
during configuration read and write transactions.
Signal Descriptions
Table 4.1
PCI Interface (Cont.) Signals
Name
BGA Pos
Type
Strength Description
FRAME/
AC6
S/T/S
16 mA
Cycle Frame is driven by the current master to
indicate the beginning and duration of an access.
FRAME/ is asserted to indicate a bus transaction
is beginning. While FRAME/ is deasserted, the
transaction is in the final data phase or the bus is
idle.
IRDY/
AB6
S/T/S
16 mA
Initiator Ready indicates the initiating agent’s
(bus master’s) ability to complete the current data
phase of the transaction. IRDY/ is used with
TRDY/. A data phase is completed on any clock
when both IRDY/ and TRDY/ are sampled
asserted. During a write, IRDY/ indicates that
valid data is present on AD[63:0]. During a read,
it indicates that the master is prepared to accept
data. Wait cycles are inserted until both IRDY/
and TRDY/ are asserted together.
TRDY/
AA6
S/T/S
16 mA
Target Ready indicates the target agent’s
(selected device’s) ability to complete the current
data phase of the transaction. TRDY/ is used with
IRDY/. A data phase is completed on any clock
when used with IRDY/. A data phase is
completed on any clock when both TRDY/ and
IRDY/ are sampled asserted. During a read,
TRDY/ indicates that valid data is present on
AD[63:0]. During a write, it indicates that the
target is prepared to accept data. Wait cycles are
inserted until both IRDY/ and TRDY/ are asserted
together.
DEVSEL/
AC7
S/T/S
16 mA
Device Select indicates that the driving device
has decoded its address as the target of the
current access. As an input, it indicates to a
master whether any device on the bus has been
selected.
STOP/
AA7
S/T/S
16 mA
Stop indicates that the selected target is
requesting the master to stop the current
transaction.
4-5
Table 4.1
PCI Interface (Cont.) Signals
Name
BGA Pos
Type
PERR/
AC8
S/T/S
16 mA
Parity Error may be pulsed active by an agent
that detects a parity error. PERR/ can be used by
any agent to signal data corruption. However, on
detection of a PERR/ pulse, the central resource
may generate a nonmaskable interrupt to the
host CPU, which often implies the system will be
unable to continue operation once error
processing is complete.
SERR/
AB8
O
16 mA
System Error is an open drain output used to
report address parity errors and data parity errors
on the Special Cycle command.
PAR
AA8
T/S
16 mA
Parity is the even parity bit that protects the
AD[31:0] and C_BE[3:0]/ lines. Parity covers both
the address and command bits during the
address phase, and both data bits and byte
enables during the data phase.
PAR64
AA17
T/S
16 mA
Parity64 is the even parity bit that protects the
AD[63:32] and C_BE[7:4]/ lines. Parity covers
both the address and command bits during the
address phase, and both data bits and byte
enables during the data phase. This pad contains
an internal 25 µA pull-up.
INTA/
V2
O
16 mA
Interrupt. This signal, when asserted LOW,
indicates that a device is requesting service from
its host device driver.
M66EN
AB10
I
N/A
Enable 66 MHz is asserted HIGH from the
system if the board is in a 66 MHz slot. This pad
contains an internal 100 µA pull-up.
FSELPCI
B8
I
N/A
PCI FSN Select, when asserted HIGH, selects
the PCI FSN output as the internal PCI Clock
Tree source. This FSN is intended to phase shift
the input PCICLK signal for clock insertion
controllability. The FSN is bypassed automatically
in 33 MHz systems (M66EN deasserted). When
this pin is LOW, the PCI Clock Tree is sourced
directly by the PCICLK signal. This pad contains
an internal 100 µA pull-up.
4-6
Strength Description
Signal Descriptions
Table 4.2 describes the FC 10-bit Interface signals.
Table 4.2
FC 10-Bit Interface Signals
Name
BGA Pos
Type Strength Description
TX[9:0]
N4, P3, P2, P1,
R3, R2, R1, T3,
T2, T1
O
8 mA
10-bit parallel data to the PHY serializer device.
Data is clocked out to the PHY on the rising edge of
TBC. These pads contain an internal 100 µA pull-up.
RX[9:0]
C1, C2, D1, D2,
D3, E1, E2, E3,
E4, F1
I
N/A
10-bit parallel data from the PHY serializer device.
Data is clocked into the LSIFC909 on the rising
edge of RBC[0] and RBC[1]. These pads contain an
internal 100 µA pull-up.
EN_CDET
U1
O
4 mA
Enable Comma Detect. This pin enables the
comma detect circuitry on the PHY device to
establish byte synchronization on the next comma
that is received. This pad contains an internal
100 µA pull-up.
EWRAP
R4
O
4 mA
Electrically Wrap. This pin causes the PHY device
to electrically wrap the serialized transmit data to the
deserializer and disables the laser output, if present.
This pad contains an internal 100 µA pull-up.
LCK_REF/ B3
O
4 mA
Lock Reference. This pin causes the PHY device to
lock its receiver PLL to the TBC. This pad contains
an internal 100 µA pull-up.
TBC
N2
O
8 mA
Transmit Buffered Clock. A buffered version of the
REFCLK input that is phase aligned to the TX data.
This pad contains an internal 100 µA pull-up.
RBC[1:0]
G3, F2
I
N/A
Receive Buffered Clock Inputs. RBC[0] is the
clock from the PHY device used to latch RX into the
protocol device. RBC[1] is an optional clock that is
180 degrees out of phase from RBC[0]. This clock is
used to latch alternate bytes for 10-bit interface
compliant modules. These pads contain an internal
100 µA pull-up.
RXLOS
B1
I
N/A
Received Signal Loss. Gigabit Interface Converter
(GBIC) has detected loss of signal.
4-7
Table 4.3 describes the FC G-bit Interface signals.
Table 4.3
FC G-Bit Interface Signals
Name
BGA Pos Type Strength Description
TX+
M2
O
N/A
Transmit differential data.
TX−
L2
O
N/A
Transmit differential data.
RX+
J2
I
N/A
Receive differential data.
RX−
H2
I
N/A
Receive differential data.
IREF
K1
I
N/A
Analog current reference for the integrated transceiver
core. A 2.74 kΩ resistor should be tied from the IREF pad
to ground.
LIPRESET/ J3
O
4 mA
LIP Reset. This pin is asserted LOW when a selective
reset is received that is targeted to one of this device’s
aliases. This pin is asserted for 1–2 ms after the last LIP
Reset is received.
FAULT/
U3
I
N/A
Fault. This pin indicates that an electrical fault has been
detected by the PHY device/module and, if the module
has a laser, the laser has been turned off. This pad
contains an internal 100 µA pull-up.
ODIS
C4
O
4 mA
Output Disable. This output, when asserted, disables an
external GBIC or Media Interface Adapter (MIA)
transmitter. This output is also used to clear a module
fault.
BYPASS/
H4
O
4 mA
Bypass. This line is driven LOW when the LSIFC909 Link
Controller block has determined that the device is
operating in a loop environment and the device has
entered a bypass mode. This may be caused by an
internal request or a loop primitive generated by another
node.
WMSEL
C8
I
N/A
WaveMaker (Integrated Transceiver) Select. When
asserted HIGH, the integrated transceiver is enabled.
When deasserted, the 10-bit interface is enabled, and an
external PHY device is required. This pad contains an
internal 100 µA pull-up.
REFCLK
N1
I
N/A
FC reference clock. (106.25 MHz ± 100 ppm).
4-8
Signal Descriptions
Table 4.4 describes the Memory Interface signals.
Table 4.4
Memory Interface Signals
Name
BGA Pos
MD[31:0]
MD[31:24]
T21, T22,
T23, R20,
R21, R22,
R23, P21,
P22, P23,
N20, N21,
N22, N23,
M21, M22,
M23, L20,
L21, L22,
L23, K21,
K22, K23,
J20, J21,
J22, J23,
H20, H21,
H22, G21
I/O
4 mA
SSRAM Read/Write Data.
Flash ROM Read/Write Data.
MP[3:0]
F21, F22,
E22, E23
I/O
4 mA
Memory Parity. Byte lane parity as follows:
MP [0]: Parity for MD[7:0]
MP [1]: Parity for MD[15:8]
MP [2]: Parity for MD[23:16]
MP [3]: Parity for MD[31:24]
Memory Parity may be optionally even, odd, or none (not
used) as defined in the LSI Logic LSIFC909
Programming Guide. These pins contain an internal
100 µA pull-up.
MA[21:0]
B21,
C20,
A20,
C19,
A19,
B18,
C17,
D16,
B16,
D15,
B15,
O
4 mA
SSRAM/Flash ROM Address.
MOE[1:0]/
C22, B22
O
8 mA
Memory Output Enable. When asserted LOW, the
selected SRAM or Flash (MOE[1]/) device may drive
data. This signal is typically an asynchronous input to
SRAM and/or Flash devices. The two output enables
allow for interleaving configurations.
A21,
B20,
D19,
B19,
C18,
A18,
A17,
C16,
A16,
C15,
A15
Type Strength Description
4-9
Table 4.4
Memory Interface (Cont.) Signals
Name
BGA Pos
MWE[1:0]/
D23, C23
Type Strength Description
O
4 mA
Memory Write Enables. These active LOW bank write
enables are required for interleaving configurations.
FLASHCS/ A22
O
4 mA
Flash Chip Select. This active LOW chip select allows
connection of a single 8-bit Flash device.
MCLK
G23
O
8 mA
Memory Clock. All synchronous RAM control/data
signals are referenced to the rising edge of this clock.
Exceptions are MOE/ and ZZ which are typically
asynchronous inputs to SRAM and/or Flash devices.
ADSC/
H23
O
4 mA
Address-Strobe-Controller. Initiates read, write, or chip
deselect cycles, and latches in the current address.
ADV/
F23
O
4 mA
Advance. When asserted LOW, the ADV/ input causes a
selected synchronous SRAM to increment its burst
address counter.
BWE[3:0]/
D21, D22,
E20, E21
O
4 mA
Memory Byte Write Enables. Active LOW, byte lane
write enables to allow writing of partial words to memory.
RAMCS/
B23
O
4 mA
RAM Chip Select. Active LOW synchronous chip select
for all SSRAMS (up to four SSRAMS for interleaved and
depth expanded configuration).
ZZ
A23
O
4 mA
Snooze Control. Asserting this output HIGH causes a
synchronous SRAM to enter its lowest power state (not
all RAMs support this function).
Table 4.5 describes the Configuration signals.
Table 4.5
Configuration Signals
Name
ROMSIZE[1:0]
4-10
BGA
Pos Type
C13,
D13
I
Strength
N/A
Signal Descriptions
Description
ROM Size. This field identifies the size of the ROM that is
connected to the device. The value of this bus should be
established at chip reset and should remain unchanged
until another chip reset. The encoding of this field is as
follows:
Bits [1:0] ROM Size
00
256 Kbytes
01
512 Kbytes
10
1024 Kbytes
11
No external memory present
These pads contain an internal 100 µA pull-up.
Table 4.5
Configuration Signals (Cont.)
Name
BGA
Pos Type
TESTRESET/
B13
I
N/A
Test Reset. Forces chip into Power-On-Reset state or
Soft-Reset state, depending on the state of the Mode pins.
This pad contains an internal 100 µA pull-up.
ARMEN/
C14
I
N/A
ARM Enable. When this pin is asserted LOW, the ARM
RISC processor core (IOP) is enabled and will boot from
Flash ROM following chip reset. If this configuration pin is
held HIGH, the IOP core will be held reset until the
DisARM bit in the Diagnostic register is cleared by the
host CPU. This pad contains an internal 100 µA pull-up.
FSELZ
B6
I
N/A
Frequency Select. This pin when HIGH indicates that the
REFCLK input shall be internally divided by 2 to generate
the internal ZCLK source (106.25 / 2 = 53.125 MHz).
When this pin is LOW, the internal ZCLK tree is sourced
directly from the ZCLK input signal. This pad contains an
internal 100 µA pull-up.
MODE[7:0]
D8,
A9,
B9,
C9,
D9,
A10,
B10,
C10
I
N/A
Mode Select. This 8-bit bus defines operational and test
modes for the chip. For Normal Mode, MODE7 and
MODE6 should be tied LOW. The Mode encodings are
given below:
Strength
Description
Normal Mode
Mode[7:0] = 0011xxxx==Interleaved BSRAM
Mode[7:0] = 0001xxxx==Noninterleaved BSRAM
Mode[7:0] = 00x11xxx==GBIC (Fault is active HIGH)
Mode[7:0] = 00x10xxx==MIA (Fault is active LOW)
Mode[7:0] = 00x1x1xx==Soft Reset Mode
Mode[7:0] = 00x1xx11==Normal SEPROM Auto Load
Mode[7:0] = 00x1xx01==Firmware PCI Config Mode
(ARMEN/ must also be LOW)
Mode[7:0] = 00x1xx00 ==PCI Config use default values
All other combinations are reserved.
Each of these pads contains an internal 100 µA pull-up.
4-11
Table 4.6 describes the Miscellaneous signals.
Table 4.6
Miscellaneous Signals
Name
BGA Pos Type Strength Description
GPIO[3:0]
C12, B12,
A12, A13
I/O
8 mA
General purpose I/O pins. These pins default to input
mode on reset. These signals are controlled/observed
by firmware and may be configured as inputs or
outputs. GPIO[3] may be optionally enabled as an
external interrupt source to the ARM RISC Processor
core. These pads contain an internal 100 µA pull-up.
LED[3:0]/
D11,
C11,
B11, A11
O
8 mA
LED Outputs. These output signals may be controlled
by firmware or driven by chip activity. When configured
as activity driven, the LED[n] outputs have the following
meaning when asserted LOW:
LED[3]: Link Fault – Word Sync not detected
LED[2]: Receive Channel Active
LED[1]: Transmit Channel Active
LED[0]: Firmware controlled
SCL
A14
O
4 mA
Serial EEPROM clock. This pad contains an internal
100 µA pull-up to provide a HIGH level on this pin, if it
is not used. If used, an external pull-up is also required.
SDA
B14
I/O
4 mA
Serial EEPROM data. This pad contains an internal
100 µA pull-up to provide a HIGH level on this pin, if it
is not used. If used, an external pull-up is also required.
ZCLK
A6
I
N/A
External ZBus reference clock. When FSELZ is held
LOW, this input pin provides the reference timing for the
internal ZBus, IOP and CtxMgr processors, and
memory interface. This pad contains an internal 100 µA
pull-up.
WmlsoTest[2]
B2
O
4 mA
Test mode output. Leave unconnected. This pad
contains an internal 100 µA pull-up.
WmlsoTest[1]
A1
O
4 mA
Test mode output. Leave unconnected. This pad
contains an internal 100 µA pull-up.
WmlsoTest[0]
A2
O
4 mA
Test mode output. Leave unconnected. This pad
contains an internal 100 µA pull-up.
4-12
Signal Descriptions
Table 4.7 describes the JTAG Test and IOP Debug signals.
Table 4.7
JTAG Test and IOP Debug Signals
Name
BGA Pos Type
Strength Description
TCK_CHIP
A7
I
N/A
JTAG/CtxMgr Debug Test Clock. This pad contains
an internal 100 µA pull-up to provide a HIGH level on
this pin, if it is not used. If used, an external pull-up is
also required.
TRST_CHIP/
C7
I
N/A
JTAG/Debug Test Reset. Asynchronous active LOW.
This pad contains an internal 100 µA pull-up to provide
a HIGH level on this pin, if it is not used. If used, an
external pull-up is also required.
TDI_CHIP
A5
I
N/A
JTAG/CtxMgr Debug Test Data In. This pad contains
an internal 100 µA pull-up to provide a HIGH level on
this pin, if it is not used. If used, an external pull-up is
also required.
TDO_CHIP
B5
O
4mA
JTAG/CtxMgr Debug Test Data Out. This pad
contains an internal 100 µA pull-up.
TMS_CHIP
A8
I
N/A
JTAG Test Mode Select. This pad contains an internal
100 µA pull-up to provide a HIGH level on this pin, if it
is not used. If used, an external pull-up is also
required.
TMS_ICE1
C6
I
N/A
CtxMgr Debug Test Mode Select. This pad contains
an internal 100 µA pull-up to provide a HIGH level on
this pin, if it is not used. If used, an external pull-up is
also required.
TCK_ICE2
A3
I
N/A
IOP Debug Test Clock. This pad contains an internal
100 µA pull-up to provide a HIGH level on this pin, if it
is not used. If used, an external pull-up is also
required.
TRST_ICE2/
D5
I
N/A
IOP Debug Test Reset. Asynchronous active LOW.
This pad contains an internal 100 µA pull-up to provide
a HIGH level on this pin, if it is not used. If used, an
external pull-up is also required.
4-13
Table 4.7
JTAG Test and IOP Debug Signals (Cont.)
Name
BGA Pos Type
Strength Description
TDI_ICE2
A4
I
N/A
IOP Debug Test Data In. This pad contains an internal
100 µA pull-up to provide a HIGH level on this pin, if it
is not used. If used, an external pull-up is also
required.
TDO_ICE2
B4
O
4mA
IOP Debug Test Data Out. This pad contains an
internal 100 µA pull-up.
TMS_ICE2
C5
I
N/A
IOP Test Mode Select. This pad contains an internal
100 µA pull-up to provide a HIGH level on this pin, if it
is not used. If used, an external pull-up is also
required.
Table 4.8 describes the Power and Ground signals.
Table 4.8
Power and Ground Signals
Name
BGA Pos
Description
Voltage
VDD
D7, D10, D14, D17,
G4, G20, K4, K20,
P4, P20, U4, U20,
Y7, Y10, Y14, Y17
I/O power.
3.3 V
VSS
AA3, AA21, AC9, C3,
C21, D4, D12, D20,
K10, K11, K12, K13,
K14, L10, L11, L12,
L13, L14, M4, M10,
M11, M12, M13, M14,
M20, N10, N11, N12,
N13, N14, P10, P11,
P12, P13, P14, Y4,
Y12, Y20
I/O ground.
0V
VDDA1
L4
Analog power for integrated transceiver core.
3.3 V
VSSA1
K2
Analog ground for integrated transceiver core.
0V
VDDA2
K3
Analog power for integrated transceiver core.
3.3 V
VSSA2
J1
Analog ground for integrated transceiver core.
0V
VDDA3
J4
Analog power for integrated transceiver core.
3.3 V
VSSA3
H1
Analog ground for integrated transceiver core.
0V
4-14
Signal Descriptions
Table 4.8
Power and Ground Signals (Cont.)
Name
BGA Pos
Description
Voltage
VDDC
D6, D18, F3, F20,
V4, V20, Y6, Y18
Core power.
3.3 V
VSSC
AB7, AB17, B7, B17,
G1, G22, U22, V1
Core ground.
0V
VDDQ
F4
Isolation power.
3.3 V
VSSQ
G2
Isolation ground.
0V
VDD_FSN
AB9
Analog power for FSN.
3.3 V
VSS_FSN
AA10
Analog ground for FSN.
0V
VDDL1
T4
Digital power for integrated transceiver core.
3.3 V
VSSL1
U2
Digital ground for integrated transceiver core.
0V
VDDL2
H3
Digital power for integrated transceiver core.
3.3 V
VSSL2
N3
Digital ground for integrated transceiver core.
0V
VDDP
L3
Serial driver power for integrated transceiver core. 3.3 V
VSSP
L1
Serial driver ground for integrated transceiver core. 0 V
4-15
4-16
Signal Descriptions
Chapter 5
Registers
This chapter provides a description of the registers in the LSIFC909 FC
PCI Protocol Controller chip. The chapter contains the following sections:
•
Section 5.1, “PCI Addressing”
•
Section 5.2, “PCI Bus Commands Supported”
•
Section 5.3, “PCI Cache Mode”
•
Section 5.4, “Unsupported PCI Commands”
•
Section 5.5, “Programming Model”
•
Section 5.6, “PCI Configuration Registers”
•
Section 5.7, “Host Interface Registers”
•
Section 5.8, “Shared Memory”
5.1 PCI Addressing
There are three types of PCI-defined address space:
•
Configuration space
•
Memory space
•
I/O space
Configuration space is a contiguous 256 x 8-bit set of addresses
dedicated to each “slot” or “stub” on the bus. Decoding C_BE[7:0]/
determines if a PCI cycle is intended to access configuration register
space. The IDSEL bus signal is a “chip select” that allows access to the
configuration register space only. The LSIFC909 ignores a configuration
read/write cycle without IDSEL. The eight lower order addresses select
a specific 8-bit register. AD[10:8] are decoded as well, but they must be
for the LSIFC909 to respond. According to the PCI specification,
LSIFC909 Fibre Channel I/O Processor
5-1
AD[10:8] are to be used for multifunction devices. The host processor
uses the PCI configuration space to initialize the LSIFC909.
At initialization time, each PCI device is assigned a base address for
memory accesses and I/O accesses. On every access, the LSIFC909
compares its assigned base addresses with the value on the
Address/Data bus during the PCI address phase. A decode of
C_BE[7:0]/ determines which registers and what type of access is to be
performed.
5.2 PCI Bus Commands Supported
Bus commands indicate to the target the type of transaction the master
is requesting. Bus commands are encoded on the C_BE[7:0]/ lines
during the address phase. PCI bus command encoding and types appear
in Table 5.1.
The Memory Read, Memory Read Line, and Memory Read Multiple
commands read data from an agent mapped in memory address space.
The Memory Write, and Memory Write and Invalidate commands write
data to an agent when mapped in memory address space.
5-2
Registers
Table 5.1
PCI Bus Commands and Encoding Types
C_BE[3:0]
Command Type
Supported as Master
Supported as Slave
0000
Special Interrupt Acknowledge
No
No
0001
Special Cycle
No
No
0010
I/O Read Cycle
Yes
Yes
0011
I/O Write Cycle
Yes
Yes
0100
Reserved
N/A
N/A
0101
Reserved
N/A
N/A
0110
Memory Read
Yes
Yes
0111
Memory Write
Yes
Yes
1000
Reserved
N/A
N/A
1001
Reserved
N/A
N/A
1010
Configuration Read
N/A
Yes
1011
Configuration Write
N/A
Yes
1100
Memory Read Multiple
Yes
Yes
1101
Dual Address Cycle
Yes
Yes
1110
Memory Read Line
Yes
Yes
1111
Memory Write and Invalidate
Yes
Yes
5.3 PCI Cache Mode
The LSIFC909 supports the PCI specification for an 8-bit Cache Line
Size register located in PCI configuration space. The Cache Line Size
register provides the ability to sense and react to nonaligned addresses
corresponding to cache line boundaries. Bit 4 of the Command register
in PCI configuration space enables the Memory Write and Invalidate
command. Cache Read commands cannot be disabled. Slaves, however,
can alias the Memory Read Line and Memory Read Multiple commands
to Memory Read.
PCI Cache Mode
5-3
5.3.1 Support for PCI Cache Line Size Register
The LSIFC909 supports the PCI specification for an 8-bit Cache Line
Size register in PCI configuration space; it can sense and react to
nonaligned addresses corresponding to cache line boundaries.
5.3.2 Selection of Cache Line Size
The cache logic will select a cache line size based on the value specified
in the Cache Line Size register.
Note:
If an illegal value is specified in the PCI Cache Line Size
register (something other than 2, 4, 8, 16, 32, 64, or 128),
caching is disabled. Otherwise, the LSIFC909 uses this
value for all aligned burst data transfers.
5.3.3 Memory Write and Invalidate Command
The Memory Write and Invalidate command is identical to the Memory
Write command, except that it additionally guarantees a minimum
transfer of one complete cache line; i.e., the master intends to write all
bytes within the addressed cache line in a single PCI transaction, unless
interrupted by the target. This command requires implementation of the
PCI Cache Line Size register at address 0x0C in the PCI configuration
space.
5.3.3.1 Alignment
The LSIFC909 uses the calculated line size value to monitor the current
address for alignment to the cache line size. When it is not aligned, the
chip attempts to align to the cache boundary by using a noncache
command.
For nonaligned initial addresses, the chip will execute a burst to bring the
address counter to an aligned value. Once a cache line boundary is
reached, the chip will use the cache line size as the burst size from then
on, except in the case of Multiple Cache Line Transfers. The alignment
process is finished at this point. Memory Write and Invalidate commands
are issued when the following conditions are met:
5-4
Registers
•
The PCI configuration Command register, bit 4 must be set.
•
The Cache Line Size register must contain a legal burst size (2, 4,
8, 16, 32, 64, or 128) value.
•
The chip must have enough bytes in the DMA FIFO to complete at
least one full cache line burst.
•
The chip must be aligned to a cache line boundary.
When these conditions have been met, the LSIFC909 issues a Write and
Invalidate command instead of a Memory Write command during all PCI
write cycles.
5.3.3.2 Multiple Cache Line Transfers
The Write and Invalidate command can write multiple cache lines of data
in a single bus ownership. The chip issues a burst transfer as soon as it
reaches a cache line boundary. The size of the transfer is not
automatically the cache line size, but rather a multiple of the cache line
size as allowed for in Revision 2.1 of the PCI specification. The logic
selects the largest multiple of the cache line size based on the amount
of data to transfer.
When the DMA buffer contains less data than the value specified in the
Cache Line Size register, the LSIFC909 throttles back to a Memory Write
command on the next cache line boundary.
5.3.3.3 Latency
In accordance with the PCI specification, the chip's latency timer is
ignored when issuing a Write and Invalidate command such that when a
latency time-out has occurred, the LSIFC909 continues to transfer up
until a cache line boundary. At that point, the chip relinquishes the bus,
and finishes the transfer at a later time using another bus ownership. If
the chip is transferring multiple cache lines it continues to transfer until
the next cache boundary is reached.
5.3.3.4 PCI Target Retry
During a Write and Invalidate transfer, if the target device issues a retry
(STOP with no TRDY, indicating that no data was transferred), the
LSIFC909 relinquishes the bus and immediately tries to finish the
PCI Cache Mode
5-5
transfer on another bus ownership. The chip issues another Write and
Invalidate command on the next ownership, in accordance with the PCI
specification.
5.3.3.5 PCI Target Disconnect
If the target device issues a disconnect during a Write and Invalidate
transfer, the LSIFC909 relinquishes the bus and immediately tries to
finish the transfer on another bus ownership. The chip does not issue
another Write and Invalidate command on the next ownership unless the
address is aligned.
5.3.4 Read Commands
Memory Read Line and Memory Read Multiple commands are issued
with burst transfers where the memory system and the requesting master
may gain some performance advantage by prefetching read data. Cache
command usage is described below.
5.3.4.1 Memory Read Line
The Memory Read Line command is issued on any burst read of two or
more Dwords in which a cache line boundary is not crossed. The starting
address of the burst need not be aligned to a cache line boundary. This
command allows a capable bridge to prefetch and burst up to an entire
cache line of data, as opposed to disconnecting after every data phase.
5.3.4.2 Memory Read Multiple
The Memory Read Multiple command is issued on any burst read which
crosses a cache line boundary. The starting address of the burst need
not be aligned to a cache line boundary. This command allows a capable
bridge to prefetch multiple cache lines of data, maximizing read burst
potential.
5.3.4.3 Memory Read
For single Dword (nonburst) transfers, the Memory Read command is
used.
5-6
Registers
5.4 Unsupported PCI Commands
The LSIFC909 does not respond to reserved commands, special cycle,
or interrupt acknowledge commands as a slave. It never generates these
commands as a master.
5.5 Programming Model
The LSIFC909 host programming model includes all necessary hardware
registers, shared memory and associated memory addresses from the
host (using System Addresses) viewpoint. The host programming model
consists of PCI Configuration Registers, Host Interface Registers, and a
Shared Memory region.
5.6 PCI Configuration Registers
The configuration registers are accessible only by the system BIOS
during PCI configuration cycles, and are not available to the user at any
time. No other cycles can access these registers.
Note:
The configuration register descriptions provide general
information only, to indicate which PCI configuration
addresses are supported in the LSIFC909. Table 5.2 shows
the PCI configuration registers implemented by the
LSIFC909. Addresses 0x48 through 0x7F are not defined.
All PCI-compliant devices, such as the LSIFC909, must support the
Vendor ID, Device ID, Command, and Status registers. Support of other
PCI-compliant registers is optional. In the LSIFC909, registers that are
not supported are not writable and will return all zeros when read. Only
those registers and bits that are currently supported by the LSIFC909 are
described in this chapter. For more detailed information on PCI registers,
please see the PCI Specification.
PCI configuration space provides identification, configuration,
initialization, and error management functions for PCI devices. The
LSIFC909 provides configuration registers as defined in Table 5.2.
Unsupported PCI Commands
5-7
Table 5.2
PCI Configuration Register Map
31
16 15
0
Device ID
Status
Vendor ID
Command
0x00
0x04
Revision ID
Class Code
Head Type
Latency Timer
Cache Line Size
I/O Base Address
Mem0 Base Address Low
Mem0 Base Address High
Mem1 Base Address Low
Mem1 Base Address High
Reserved
Reserved
Subsystem ID
Subsystem Vendor ID
Expansion ROM Base Address
Reserved
Capabilities Pointer
Reserved
Max_Lat
Min_Gnt
Interrupt Pin
Interrupt Line
Power Management Capabilities
Next Item Pointer
Capability ID
Bridge Support
Data
Power Management Capabilities
Extensions
0x08
BIST
Reserved
0x0C
0x10
0x14
0x18
0x1C
0x20
0x24
0x28
0x2C
0x30
0x34
0x38
0x3C
0x40
0x44
0x48–0x7F
Register: 0x00
Device ID/Vendor ID
Read Only
31
16
DevID (Most Significant)
0
0
0
0
0
1
1
0
0
0
1
0
0
0
0
15
1
0
VenID (Least Significant)
0
0
0
1
0
DevID
5-8
Registers
0
0
0
0
0
0
0
0
0
0
0
Device ID (Read Only)
[31:16]
The most significant half of this register identifies the
particular device. The LSIFC909 Device ID is 0x0621.
The 0x06XX indicates FC device. The 0xXX21 indicates
a specific device, in this case, the LSIFC909.
VenID
Vendor ID (Read Only)
[15:0]
The least significant half of this register identifies the
manufacturer of the device. The LSI Logic Vendor ID is
0x1000.
Register: 0x04
Status/Command
Read/Write
31
30
29
28
27
DPE
SSE
MA
RTA
R
0
0
0
0
0
26
25
DevSEL/Tim
0
15
0
0
0
0
0
23
16
R
1
0
0
0
0
0
0
0
0
0
9
8
7
6
5
4
3
2
1
0
SERR
R
EPER
R
WIM
R
EBM
0
0
0
0
0
0
0
R
0
24
DPR
0
EMS EIOS
0
0
The most significant half of the Status/Command register is used to
record status information for PCI bus-related events.
Reads to this register behave normally. Writes are slightly different in that
bits can be cleared, but not set. A bit is reset whenever the register is
written, and the data in the corresponding bit location is a one. For
instance, to clear bit 31 and not affect any other bits, write the value
0x8000 to the register.
The least significant half of the Status/Command register provides
coarse control over a device’s ability to generate and respond to PCI
cycles. When a zero is written to this register, the LSIFC909 is logically
disconnected from the PCI bus for all accesses except configuration
accesses.
DPE
Detected Parity Error (Read/Write)
31
This bit will be set by the LSIFC909 whenever it detects
a data parity error, even if parity error handling is
disabled.
SSE
Signaled System Error (Read/Write)
30
This bit is set whenever a device asserts the SERR/
signal.
PCI Configuration Registers
5-9
MA
Master Abort (Read/Write)
29
This bit should be set by a master device whenever its
transaction (except for Special Cycle) is terminated with
a master abort. All master devices should implement this
bit.
RTA
Received Target Abort (Read/Write)
28
This bit should be set by a master device whenever its
transaction is terminated with a target abort. All master
devices should implement this bit.
R
Reserved (Read/Write)
Reserved for future use.
DevSEL/Tim
DevSEL/ Timing (Read/Write)
[26:25]
These bits encode the timing of DEVSEL/. These are
encoded as:
0b00
fast
0b01
medium
0b10
slow
0b11
reserved
27
These bits are read only and should indicate the slowest
time that a device asserts DEVSEL/ for any bus
command except Configuration Read and Configuration
Write. In the LSIFC909, 0b01 is supported.
DPR
Data Parity Reported (Read/Write)
24
This bit is set when the following three conditions are
met:
1. The bus agent asserted PERR/ itself or observed
PERR/ asserted;
2. The agent setting this bit acted as the bus master for
the operation in which the error occurred;
3. The Parity Error Response bit in the Command
register is set.
R
5-10
Registers
Reserved (Read/Write)
Reserved for future use.
[23:9]
SERR
SERR/ Enable (Read/Write)
8
This bit enables the SERR/ driver. SERR/ is disabled
when this bit is clear. The default value of this bit is zero.
This bit and bit 6 must be set to report address parity
errors.
R
Reserved (Read/Write)
Reserved for future use.
EPER
Enable Parity Error Response (Read/Write)
6
This bit allows the LSIFC909 to detect parity errors on
the PCI bus and report these errors to the system. Only
data parity checking is enabled. The LSIFC909 always
generates parity for the PCI bus.
R
Reserved (Read/Write)
Reserved for future use.
WIM
Write and Invalidate Mode (Read/Write)
4
This bit, when set, will cause Memory Write and
Invalidate cycles to be issued on the PCI bus after certain
conditions have been met. For more information on these
conditions, refer to Section 5.3.3, “Memory Write and
Invalidate Command.”
R
Reserved (Read/Write)
Reserved for future use.
EBM
Enable Bus Mastering (Read/Write)
2
This bit controls the LSIFC909 ability to act as a master
on the PCI bus. A value of zero disables the device from
generating PCI bus master accesses. A value of one
allows the LSIFC909 to behave as a bus master.
EMS
Enable Memory Space (Read/Write)
This bit controls the LSIFC909 response to Memory
Space accesses. A value of zero disables the device
response. A value of one allows the LSIFC909 to
respond to Memory Space accesses at the address
specified by Base Address One.
EIOS
Enable I/O Space (Read Only)
0
This bit controls the LSIFC909 response to I/O space
accesses. A value of zero disables the response. A value
of one allows the LSIFC909 to respond to I/O space
accesses at the address specified in Base Address Zero.
PCI Configuration Registers
7
5
3
1
5-11
Register: 0x08
Class Code/Revision ID
Read/Write
31
16
ClCode (Most Significant)
0
0
0
0
1
1
1
15
0
0
8
7
0
0
5-12
0
0
0
0
0
0
0
0
0
0
ClCode (Least Significant)
0
0
RevID
0
1
0
0
0
0
x
x
x
x
ClCode
Class Code (Read Only)
[31:8]
This register is used to identify the generic function of the
device. The upper byte of this register is a base class
code, the middle byte is a subclass code, and the lower
byte identifies a specific register level programming
interface. The value defaults to 0x0E0001 unless
firmware programs it to a different value prior to PCI
configuration, or it gets changed using serial EPROM.
RevID
Revision ID (Read Only)
[7:0]
This register specifies device and revision identifiers. In
the LSIFC909, the upper nibble will be 0b0000. The lower
nibble reflects the current revision level of the device.
Registers
Register: 0x0C
BIST/Header/Latency/Cache Line
Read/Write
31
24
23
16
BIST
0
0
0
0
HdTyp
0
0
0
15
0
0
8
7
0
0
0
0
0
0
0
0
0
0
0
LatTim
0
0
Cache
0
0
0
0
0
0
0
0
0
0
0
BIST
Built-In Self-Test (Read Only)
[31:24]
HdTyp
Header Type (Read Only)
[23:16]
This register identifies the layout of bytes 0x10 through
0x3F in configuration space and also whether or not the
device contains multiple functions. The value of this
register is 0x00.
LatTim
Latency Timer (Read/Write)
[15:8]
The Latency Timer register specifies, in units of PCI bus
clocks, the value of the Latency Timer for this PCI bus
master. The LSIFC909 supports this timer. All eight bits
are writable, allowing latency values of 0–255 PCI clocks.
Use the following equation to calculate an optimum
latency value for the LSIFC909:
Latency = 2 + (Burst Size * (typical wait states + 1)).
Values greater than optimum are also acceptable.
Cache
Cache Line Size (Read/Write)
[7:0]
This register specifies the system cache line size in units
of 32-bit words. Setting this bit causes the LSIFC909 to
align to cache line boundaries before allowing any
bursting, except during Memory Moves in which the read
and write addresses are not aligned to a burst size
boundary. For more information on this register, see
Section 5.3.3, “Memory Write and Invalidate Command.”
PCI Configuration Registers
5-13
Register: 0x10
I/O Base Address
Read/Write
31
16
IOBAdd (Most Significant)
0
0
0
0
0
0
0
15
0
8
0
0
0
0
0
0
0
0
0
0
7
0
1
IOBAdd (Least Significant)
0
0
0
R
0
0
0
0
0
0
IOMemSp
0
0
0
0
1
Note that this register is only 32 bits, because I/O must be mapped into
the lower 4 Gbytes of address space.
IOBAdd
I/O Base Address (Read/Write)
[31:8]
Indicates location of the I/O space required by the device
and is fixed at a size of 256 bytes.
R
Reserved (Read Only)
[7:1]
Indicates location of I/O space required by the device and
is fixed at a size of 256 bytes.
IOMemSp
I/O or Memory Space Indicator (Read Only)
0
This bit is set to 1 to indicate the I/O space mapping.
Register: 0x14
Mem0 Base Address Low
Read/Write
31
16
Mem0BAddL (Most Significant)
0
0
0
0
0
0
0
0
0
0
0
15
0
4
Mem0BAddL (Least Significant)
0
0
0
0
0
0
0
0
0
3
Prefetch
0
0
0
0
0
0
2
0
1
Type
1
0
0
0
IOMemSp
0
Mem0BAddL Mem0 Base Address Low (Read/Write)
[31:4]
Indicates the lower 32 bits of the 64-bit memory address
width, and the location of memory required by the device.
5-14
Registers
Its size is programmable from 16 Kbytes (214) through
512 Kbytes (219) in steps of powers of 2. The default
value indicated is 64 Kbytes, unless firmware programs a
different value prior to PCI configuration, or if
programmed with the serial EPROM.
Prefetch
Prefetchable Memory Block
3
With this bit set, there are no side effects to prefetching.
For reads, all bytes can be sent regardless of the state of
the byte enables. For writes, sequential writes can be
combined into a burst.
Type
Location of Memory
[2:1]
With bit 2 = 1 and bit 1 = 0, the user can map this device
anywhere in the 64-bit space.
IOMemSp
I/O or Memory Space Indicator (Read Only)
0
This bit is set to 0 to indicate Memory Space mapping.
Register: 0x18
Mem0 Base Address High
Read/Write
31
16
Mem0BAddH (Most Significant)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
0
0
Mem0BAddH (Least Significant)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Mem0BAddH Mem0 Base Address High (Read/Write)
[31:0]
Indicates the upper 32 bits of the 64-bit memory address
width, and the location of memory required by the device.
This allows the LSIFC909 to be mapped above the
4 Gbytes boundary.
PCI Configuration Registers
5-15
Register: 0x1C
Mem1 Base Address Low
Read/Write
31
16
Mem1BAddL (Most Significant)
0
0
0
0
0
0
0
0
0
0
0
15
0
4
Mem1BAddL (Least Significant)
0
0
0
0
0
0
0
0
0
3
Prefetch
0
0
0
0
0
0
2
0
1
Type
1
0
0
0
IOMemSp
0
Mem1BAddL Mem0 Base Address Low (Read/Write)
[31:4]
Indicates the lower 32 bits of the 64-bit memory address
width, and the location of memory required by the device.
Its size is programmable from 16 Kbytes (214) through
512 Kbytes (219) bytes in steps of powers of 2. The
default value indicated is 64 Kbytes, unless firmware
programs a different value prior to PCI configuration, or if
programmed with the serial EPROM.
5-16
Prefetch
Prefetchable Memory Block
3
With this bit set, there are no side effects to prefetching.
For reads, all bytes can be sent regardless of the state of
the byte enables. For writes, sequential writes can be
combined into a burst.
Type
Location of Memory
[2:1]
With bit 2 = 1 and bit 1 = 0, the user can map this device
anywhere in the 64-bit space.
IOMemSp
I/O or Memory Space Indicator (Read Only)
0
This bit is set to 0 to indicate Memory Space mapping.
Registers
Register: 0x20
Mem1 Base Address High
Read/Write
31
16
Mem1BAddH (Most Significant)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
0
0
Mem1BAddH (Least Significant)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Mem1BAddH Mem0 Base Address High (Read/Write)
[31:0]
Indicates the upper 32 bits of the 64-bit memory address
width, and the location of memory required by the device.
This allows the LSIFC909 to be mapped above the
4 Gbytes boundary.
Registers: 0x24–0x28
Reserved
PCI Configuration Registers
5-17
Register: 0x2C
Subsystem ID/Vendor ID
Read Only
31
16
Subsystem ID
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
0
Subsystem Vendor ID
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SID
Subsystem ID
[31:16]
These bits are used to uniquely identify the add-in board
or subsystem where this PCI device resides.
SVID
Subsystem Vendor ID
[15:0]
These bits are used to uniquely identify the vendor
manufacturing the add-in board or subsystem where this
PCI device resides.
Register: 0x30
Expansion ROM Base Address
Read/Write
31
16
ExpROMBAdd (Most Significant)
0
0
0
0
0
0
15
0
11
0
0
0
0
0
0
0
0
0
10
0
1
R
ExpROMBAdd (Least Significant)
0
0
0
0
0
0
0
0
0
0
ExpROMEn
0
0
0
0
0
0
See Section 3.7.2, “Flash ROM,” of this manual for more details
regarding the Expansion ROM.
ExpROMBAdd
Expansion ROM Base Address (Read/Write) [31:11]
Indicates location of Expansion ROM device and is
programmable from 256 Kbytes (218) through 1 Mbyte
(220) in steps of powers of 2 (using the ROMSIZE[1:0]
input bus).
5-18
Registers
R
Reserved (Read Only)
[10:1]
ExpROMEn
Expansion ROM Enable (Read/Write)
0
Memory access must be enabled using the MemSpace
bit in the Command register, unless ROMSIZE[1:0] = 11
(in which case there is no Expansion ROM).
Register: 0x34
Capabilities Pointer
Read/Write
31
16
R
0
0
0
0
0
0
0
15
0
0
8
7
0
0
0
0
0
0
0
0
0
0
R
0
0
CapPtr
0
0
0
0
0
1
0
0
0
0
0
0
R
Reserved (Read Only)
Reserved for future use.
[31:8]
CapPtr
Capabilities Pointer (Read Only)
[7:0]
These bits indicate that the first extended capability
register is located at offset 0x40 in the PCI Configuration.
Register: 0x38
Reserved
Read Only
PCI Configuration Registers
5-19
Register: 0x3C
Latency/Interrupt
Read/Write
31
24
23
16
MaxLat
0
0
0
0
0
MinGnt
0
0
15
0
0
8
7
0
0
0
5-20
0
0
0
0
0
0
0
IntPin
0
0
IntLin
0
0
0
0
0
0
0
0
0
0
0
0
MaxLat
Maximum Latency (Read Only)
[31:24]
This value has been set to a small number (0x08) to
request small latencies for PCI arbitration.
MinGnt
Minimum Grant (Read Only)
[23:16]
This value has been set to a large number (0x1E) to
indicate that the LSIFC909 is capable of large burst
transfers.
IntPin
Interrupt Pin (Read Only)
[15:8]
This register tells which interrupt pin the device uses. Its
value is set to 0x01, for the INTA/ signal.
IntLin
Interrupt Line (Read/Write)
[7:0]
This register is used to communicate interrupt line routing
information. POST software will write the routing
information into this register as it initiates and configures
the system. The value in this register tells which input of
the system interrupt controller(s) the device interrupt pin
has been connected to. Values in this register are
specified by system architecture.
Registers
Register: 0x40
Power Management Configuration
Read/Write
31
27
PMES
0
0
0
0
0
26
25
D2S
D1S
0
0
15
24
22
AUXC
0
0
8
7
0
21
20
19
DSI
R
PMEC
0
0
0
0
0
0
16
VER[2:0]
0
1
0
0
NIPtr
0
18
CapID
0
0
0
0
0
0
0
0
0
0
0
1
PMES
PME_Support
[31:27]
Bits [31:27] define the power management states in
which the LSIFC909 will assert the PME pin. These bits
are all set to zero because the LSIFC909 does not
provide a PME signal.
D2S
D2_Support
26
The LSIFC909 does not support power management
state D2.
D1S
D1_Support
25
The LSIFC909 does not support power management
state D1.
AUXC
Aux_Current
[24:22]
The LSIFC909 always returns zeros. The LSIFC909 does
not support this feature.
DSI
Device Specific Initialization
21
The LSIFC909 does not support power management
state D1.
R
Reserved
PMEC
PME Clock
19
Bit 19 is cleared because the LSIFC909 does not provide
a PME pin.
VER[2:0]
Version
[18:16]
These three bits are set to 0b010 to indicate that the
LSIFC909 complies with Revision 1.1 of the PCI Power
Management Interface Specification.
PCI Configuration Registers
20
5-21
NIPtr
Next_Item_Pointer
[15:8]
Bits [15:8] contain the offset location of the next item in
the function capabilities list. The LSIFC909 has these bits
set to zero indicating no further extended capabilities
registers exist.
CapID
Capabilities ID
[7:0]
These bits indicate the type of data structure currently
being used. The bits are set to 0x01, indicating the Power
Management Data Structure.
Register: 0x44
Power Management Control/Status
Read/Write
31
24
23
0
0
0
9
8
7
16
PMData
0
0
0
0
15
14
13
12
PST
0
DSCL[1:0]
0
0
0
PMCSR-BSE
0
DSLT[3:0]
0
0
PMData
0
0
0
PEN
0
0
0
0
0
0
0
2
1
0
R
0
0
0
PWS[1:0]
0
0
0
0
0
Power Management Data
[31:24]
These bits provide an optional mechanism for the
function to report state-dependent operating data. The
LSIFC909 always returns 0x00. These bits are read only.
PMCSR-BSE Bridge Support Extensions
[23:16]
These bits indicate PCI Bridge specific functionality. The
LSIFC909 always returns 0x00. These bits are read only.
5-22
PST
PME_Status
15
The LSIFC909 always returns a zero for this bit,
indicating that PME signal generation is not supported
from D3cold.
DSCL[1:0]
Data_Scale
[14:13]
The LSIFC909 does not support the data register.
Therefore, these two bits default to 0. The host can
program these bits and the LSIFC909 will retain the
programmed value; however, the value is not used since
the data register is not implemented in the LSIFC909.
Registers
DSLT[1:0]
Data_Select
[12:9]
The LSIFC909 does not support the data register.
Therefore, these two bits default to 0. The host can
program these bits and the LSIFC909 will retain the
programmed value; however, the value is not used since
the data register is not implemented in the LSIFC909.
PEN
PME_Enable
8
The LSIFC909 always returns zero for this bit to indicate
that PME assertion is disabled.
R
Reserved
PWS[1:0]
Power State
[1:0]
Bits [1:0] are used to determine the current power state
of the LSIFC909. They are used to place the LSIFC909
in a new power state. Power states are defined as:
[7:2]
0b00
D0
0b01
D1
0b10
D2
0b11
D3 hot
Registers: 0x48–0x7F
Reserved
Read Only
5.7 Host Interface Registers
The first 128 bytes of PCI Memory 0 address space contain the Host
Interface register set as specified in Table 5.3. Both 32-bit and 64-bit
accesses are allowed to the Host register set. The LSIFC909 design
supports only nonburst accesses to the Host Interface register set and
will Disconnect-with-data (TRDY/ and STOP/ both asserted) after the first
transfer of any burst attempt.
The LSIFC909 also specifies an I/O space requirement of 128 bytes of
I/O mapped space which the system is required to assign during PCI
configuration. The 128 bytes of I/O space are mapped onto the first
128 bytes of Memory 0 space; they provide an alternate access path to
Host Interface Registers
5-23
the Host Interface register set. I/O write/read transactions are not
expected to be utilized during normal usage of the LSIFC909 design;
they are included as a result of using the UPI-64 PCI core.
Table 5.3
Host Interface Register Map
31
16 15
System Doorbell Register
Write Sequence Register
0
0x00
0x04
0x08
Host Diagnostic Register
Test Base Address Register
Reserved
Host Interrupt Status Register
Host Interrupt Mask Register
Reserved
Request FIFO
Reply FIFO
Reserved
Host Index Register
Reserved
0x0C
0x10–0x2F
0x30
0x34
0x38–0x3F
0x40
0x44
0x48–0x4F
0x50
0x54–0x7F
Register: 0x00
System Doorbell
Read/Write
31
16
HDV (Most Significant)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
0
0
HDV (Least Significant)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
The System Doorbell register is a simple message passing mechanism
to allow the System to pass single word messages to the embedded IOP
and vice versa. When a PCI master writes to the HostRegs->Doorbell
register, a maskable interrupt is generated to the IOP. The value written
by the System master is available for the IOP to read in the
SysIfRegs->Doorbell register. The interrupt status will be cleared when
the IOP writes any value to the SysIfRegs->DoorbellClear register.
Conversely, when the IOP writes to the SysIfRegs->Doorbell register, a
maskable interrupt is generated to the PCI system using the INTA/ signal
5-24
Registers
pin. The value written by the IOP is available to the System for reading
from the HostRegs->Doorbell register. The interrupt status/pin is cleared
when the System writes any value to the HostRegs->IntStatus register.
HDV
Host Doorbell Value (Read/Write)
Write: Doorbell value passed to IOP.
[31:0]
Read: Doorbell value received from IOP.
Register: 0x04
Write Sequence
Read/Write
31
16
R
0
0
0
0
0
0
0
0
0
0
0
15
0
0
4
3
R
0
0
0
0
0
0
0
0
0
0
WSKEY
0
0
0
0
0
0
1
0
1
1
The Write Sequence register provides a protection mechanism against
inadvertent writes to the Host Diagnostic register. A sequence of five
data specific writes must be written into the Write Sequence KEY field in
order to enable writes to the Host Diagnostic register. Any data value
written incorrectly will cause the Write Sequence register to restart by
looking for the first sequence value. The required data sequence is:
0x4, 0xB, 0x2, 0x7, 0xD
After the last value (0xD) is written, the Host Diagnostic register may be
written to until another write occurs to the Write Sequence register (of
any value). A bit is provided in the Host Diagnostic register which
indicates if write access has been enabled for the Host Diagnostic
register (e.g. to verify that the Write Sequence data sequence was
correct or to verify that writes to the Host Diagnostic register have been
disabled).
R
Reserved (Read Only)
Reserved for future use.
WSKEY
Write Sequence KEY (Read/Write)
[3:0]
KEY field for Write Sequence as described above.
Host Interface Registers
[31:4]
5-25
Register: 0x08
Host Diagnostic
Read/Write
31
16
R
0
0
0
0
0
0
0
15
0
8
R
0
0
0
0
0
0
0
0
0
0
7
6
DWE
FBS
0
0
0
0
5
4
R
0
0
0
0
3
2
TTLI
RA
0
0
0
1
0
0
DisARM DME
x
0
The Host Diagnostic register contains low level diagnostic controls and
status information.
5-26
R
Reserved (Read Only)
Reserved for future use.
DWE
Diagnostic Write Enable (Read Only)
7
This bit, when set to 1, indicates that write access to the
Host Diagnostic register may occur. This bit is set as a
result of writing the correct key sequence into the Write
Sequence register.
FBS
Flash Bad Signature (Read Only)
6
This bit, when set to 1, indicates that the IOP ARM has
attempted to boot from Flash ROM but encountered a
bad Flash signature. When this occurs, the DisARM bit in
this register is set to 1 (holding the IOP ARM reset) until
both the FlashBadSignature and DisARM conditions are
cleared by the host.
R
Reserved (Read Only)
Reserved for future use.
TTLI
TTL Interrupt (Read/Write)
3
This bit configures the PCI INTA/ pin as either open drain
or TTL. This bit defaults to 0 (open drain) on reset and
should only be set to 1 when the device is being tested
on a tester.
Registers
[31:8]
[5:4]
RA
Reset Adapter (Write Only)
2
This write only bit will cause a Soft Reset condition within
the LSIFC909 design. The bit will be self-cleared after
eight PCI clock periods. After this bit is deasserted, the
IOP ARM will be executing from its default Reset Vector.
DisARM
Disable ARM (Read/Write)
1
The DisARM bit when set to 1 causes the IOP ARM to
be held reset. This bit is used primarily to enable
downloading of code/data by a host resident utility.
DME
Diagnostic Memory Enable (Read/Write)
0
This bit when set to 1 enables Diagnostic Memory
accesses using PCI Memory 1 address space. If
writes/reads to Memory 1 space are attempted with this
bit cleared to 0, they will be properly terminated on the
PCI bus but be NOP’d by the chip.
Register: 0x0C
Test Base Address
Read/Write
31
16
TBAddr
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
0
0
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
The Test Base Address register is used to specify the base address for
Diagnostic Memory (Memory 1) access.
TBAddr
Test Base Address (Read/Write)
[31:16]
Significant bits determined by the size of Diagnostic
Memory (refer to DiagMemSize field of Config0 register).
R
Reserved (Read Only)
Reserved for future use.
Host Interface Registers
[15:0]
5-27
Register: 0x30
Host Interrupt Status
Read Only
31
30
16
IOPDS
0
R
0
0
0
0
0
0
0
0
0
0
15
0
0
0
0
0
4
3
2
1
0
R
0
0
0
0
0
0
RI
0
0
0
0
0
0
0
R
0
DI
0
0
The Host Interrupt Status register provides read only interrupt status
information to the PCI host. A write of any value to this register will clear
the interrupt associated with the System Doorbell.
IOPDS
IOP Doorbell Status (Read Only)
31
This bit when set to 1 indicates that the IOP has received
a System->IOP Doorbell message but has not yet
processed it (has not cleared the corresponding SysReq
interrupt).
R
Reserved (Read Only)
Reserved for future use.
RI
Reply Interrupt (Read Only)
Reply Interrupt – set to 1 when:
[30:4]
3
• Std reply option – whenever the ReplyPostFIFO is not
empty.
• Alt reply option – whenever the Host Index register is
not equal to the ReplyPostWrPtr register.
If this bit is set to 1 and the corresponding mask bit in the
Host Interrupt Mask is cleared to 0, a PCI INTA/ interrupt
will be generated.
5-28
R
Reserved (Read Only)
Reserved for future use.
DI
Doorbell Interrupt (Read Only)
0
System Doorbell Interrupt – set to 1 when the IOP writes
a value to the System Doorbell. Cleared by a write of any
value to this register. If this bit is set to 1 and the
Registers
[2:1]
corresponding mask bit in the Host Interrupt Mask
register is cleared to 0, a PCI INTA/ interrupt will be
generated.
Register: 0x34
Host Interrupt Mask
Read/Write
31
16
R
0
0
0
0
0
0
0
0
0
0
0
15
0
0
0
0
0
4
3
2
1
0
R
0
0
0
0
0
0
RIM
0
0
0
0
0
0
1
R
0
DIM
0
1
The Host Interrupt Mask register is used to mask the interrupt conditions
reported in the Host Interrupt Status register.
R
Reserved (Read Only)
Reserved for future use.
RIM
Reply Interrupt Mask (Read/Write)
3
This bit when set to 1 masks the Reply Interrupt condition
(prevents the assertion of PCI INTA/).
R
Reserved (Read Only)
Reserved for future use.
DIM
Doorbell Interrupt Mask (Read/Write)
0
This bit when set to 1 masks the System Doorbell
Interrupt condition (prevents the assertion of PCI INTA/).
Host Interface Registers
[31:4]
[2:1]
5-29
Register: 0x40
Request FIFO
Read/Write
31
16
ReqMFA (Most Significant)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
15
1
0
ReqMFA (Least Significant)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
The Request FIFO is used to provide Request Free MFAs to the host on
reads and to accept Request Post MFAs from the host on writes.
ReqMFA
Request MFA (Read/Write)
[31:0]
Reads: Request Free MFA (0xFFFFFFFF == EMPTY).
Writes: Request Post MFA.
Register: 0x44
Reply FIFO
Read/Write
31
16
RepMFA (Most Significant)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
15
1
0
RepMFA (Least Significant)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
The Reply FIFO is used to provide Reply Post MFAs to the host on reads
and to accept Reply Free MFAs from the host on writes.
RepMFA
Reply MFA (Read/Write)
[31:0]
Reads: Reply Post MFA (0xFFFFFFFF == EMPTY).
Writes: Reply Free MFA.
5-30
Registers
Register: 0x50
Host Index
Read/Write
31
16
R
0
0
0
15
14
13
0
0
0
0
0
0
0
0
0
0
0
0
0
R
0
0
HIVal
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
The Host Index register is used with the Outbound Reply Option
(AltReplyPost method) to enable host resident reply post queues. The
Host Index provides an indication of which Reply Post MFA the host has
processed and is used to generate Reply Interrupts when the
AltReplyPost option is enabled.
R
Reserved (Read Only)
Reserved for future use.
HIVal
Host Index Value (Read/Write)
[31:14]
[13:0]
5.8 Shared Memory
The host writes Request Message Frames into a region of Shared
Memory (LSIFC909 local memory mapped to System Addresses). This
is the default method (PUSH model) for Request Message Frame
transport, where the host itself copies the Request Message Frame into
the LSIFC909 local memory. The total size of Shared Memory is
configured by the IOP on reset. Supported values are 32 Kbytes,
64 Kbytes, 128 Kbytes (default), 256 Kbytes, and 512 Kbytes. Shared
memory is accessible only through Mem0 space starting at address
0x80.
Shared Memory
5-31
5-32
Registers
Chapter 6
Specifications
This chapter provides a description of the DC and AC Electrical
Characteristics of the LSIFC909 FC PCI Protocol Controller chip, and the
available packaging. The chapter contains the following sections:
•
Section 6.1, “Electrical Requirements”
•
Section 6.2, “AC Timings”
•
Section 6.3, “Packaging”
LSIFC909 Fibre Channel I/O Processor
6-1
6.1 Electrical Requirements
Table 6.1 provides absolute maximum stress ratings for the LSIFC909,
while Table 6.2 specifies the normal operating conditions. Tables 6.3
through 6.11 specify the input and output electrical characteristics.
Table 6.1
Symbol
Absolute Maximum Stress Ratings1
Parameter
Min
Max
Unit
Test Conditions
TSTG
Storage temperature
−55
150
C
–
VDD
Supply voltage
−0.5
4.5
V
–
VIN
Input voltage
VSS −0.3
5.25 +0.3
V
–
Output voltage
VSS −0.3
VDD +0.3
V
–
VOUT
ILP2
Latch-up current
150
–
mA
–
ESD
Electrostatic discharge
–
2K
V
MIL-STD 883C,
Method 3015.7
1. Stresses beyond those listed above may cause permanent damage to the device. These are stress
ratings only; functional operation of the device at these or any other conditions beyond those
indicated in the Operating Conditions section of the manual is not implied.
2. −3 V < VPIN < 6.6 V.
Table 6.2
Symbol
VDD
Operating Conditions1
Parameter
Min
Max
Unit
Test Conditions
Supply voltage
3.13
3.47
V
–
TA
Operating free air
0
70
C
–
IDD
Supply current (dynamic)
Supply current (static)
–
–
1
500
A
µA
–
–
θJA2
Thermal resistance
(junction to ambient air)
–
18
C/W
–
1. Conditions that exceed the operating limits may cause the device to function incorrectly.
2. θJAmax assumes a 4-layer package substrate, a 329-pad PBGA, and a 4-layer PCB design
(10–12 watt/meter ˚K). The specified θJAmax represents a worst case number in still air, with no
heat sinking. θJAmax improves with heat sinking and forced airflow.
6-2
Specifications
Table 6.3
Symbol
Input Signals
Parameter
Min
Max
Unit
Test Conditions
VIH
Input high voltage
2.0
5.25
V
–
VIL
Input low voltage
VSS −0.3
0.8
V
–
IIN
Input leakage
−10
10
µA
–
Table 6.4
Symbol
CI
CIO
Table 6.5
Symbol
Capacitance
Parameter
Min
Max
Unit
Test Conditions
Input capacitance of input pads
–
7
pF
–
Input capacitance of I/O pads
–
10
pF
–
PCI Input Signals (PCICLK, RST/, GNT/, IDSEL, M66EN, FSELPCI)
Parameter
Min
Max
Unit
Test Conditions
VIH
Input high voltage
1.5
5.25
V
–
VIL
Input low voltage
VSS −0.3
0.8
V
–
IIN
Input leakage
−10
10
µA
–
Table 6.6
Symbol
PCI Output Signals (REQ/, REQ64/, SERR/, INTA/)
Parameter
Min
Max
Unit
Test Conditions
VOH
Output high voltage
0.9 VDD
VDD
V
IOUT = −500 µA
VOL
Output low voltage
VSS
0.1 VDD
V
IOUT = 1500 µA
IOZ
3-state leakage
−10
10
µA
–
Electrical Requirements
6-3
Table 6.7
Symbol
Parameter
Min
Max
Unit
Test Conditions
VOH
Output high voltage
2.4
VDD
V
−8 mA
VOL
Output low voltage
VSS
0.4
V
8 mA
IOZ
3-state leakage
−10
10
µA
–
Table 6.8
Symbol
4 mA Output Signals (EN_CDET, EWRAP, LCK_REF/, LIPRESET/,
BYPASS/, MWE[1:0]/, FLASHCS/, SCL, TDO_CHIP, TDO_ICE2, RAMCS/,
ADSC/, ADV/, MA[21:0], BWE[3:0]/, ODIS, WmIsoTest[2:0], ZZ)
Parameter
Min
Max
Unit
Test Conditions
VOH
Output high voltage
2.4
VDD
V
−4 mA
VOL
Output low voltage
VSS
0.4
V
4 mA
IOZ
3-state leakage
−10
10
µA
–
Table 6.9
Symbol
6-4
8 mA Output Signals (TX[9:0], MCLK, MOE[1:0]/, TBC, LED[3:0]/)
PCI Bidirectional Signals (ACK64/, AD[63:0], C_BE[7:0]/, FRAME/, IRDY/,
TRDY/, DEVSEL/, STOP/, PERR/, PAR, PAR64)
Parameter
Min
Max
Unit
Test Conditions
VIH
Input high voltage
1.5
5.25
V
–
VIL
Input low voltage
−0.5
0.8
V
–
VOH
Output high voltage
0.9 VDD
VDD
V
IOUT = −500 µA
VOL
Output low voltage
VSS
0.1 VDD
V
IOUT = 1500 µA
IOZ
3-state leakage
−10
10
µA
–
Specifications
Table 6.10
Symbol
4 mA Bidirectional Signals (MD[31:0], MP[3:0], SDA)
Parameter
Min
Max
Unit
Test Conditions
VIH
Input high voltage
2.0
5.25
V
–
VIL
Input low voltage
VSS −0.3
0.8
V
–
VOH
Output high voltage
2.4
VDD
V
−4 mA
VOL
Output low voltage
VSS
0.4
V
4 mA
IOZ
3-state leakage
−10
10
µA
–
Table 6.11
Symbol
8 mA Bidirectional Signals (GPIO[3:0])
Parameter
Min
Max
Unit
Test Conditions
VIH
Input high voltage
2.0
5.25
V
–
VIL
Input low voltage
VSS −0.3
0.8
V
–
VOH
Output high voltage
2.4
VDD
V
−8 mA
VOL
Output low voltage
VSS
0.4
V
8 mA
IOZ
3-state leakage
−10
10
µA
–
6.2 AC Timings
The AC characteristics described in this section apply over the entire
range of operating conditions. Chip timings are based on simulation at
worst case voltage, temperature, and processing. Timings were
developed with a load capacitance of 50 pF.
6.2.1 PCI Interface Timing Diagrams
Figure 6.1 through Figure 6.10 represent signal activity when the
LSIFC909 accesses the PCI bus. The timings for the PCI bus are listed
in Table 6.12 on page 6-17. The LSIFC909 conforms to Revision 2.2 of
the PCI Local Bus Specification. The timing specifications are provided
here for ease of reference only.
AC Timings
6-5
Timing diagrams included in this section:
6-6
•
Configuration Register Read
•
Configuration Register Write
•
Operating Register Read
•
Operating Register Write
•
Back-to-Back Read
•
Back-to-Back Write
•
Burst Read
•
Burst Write
•
Read with 64-Bit Initiator and 64-Bit Target
•
64-Bit Dual Address Cycle
Specifications
Figure 6.1
Configuration Register Read
PCICLK
(Driven by System)
t1
FRAME/
(Driven by Master)
t2
t1
AD[31:0]
(Driven by Master-Address;
LSIFC909-Data)
t3
Addr
In
Data Out
t2
t1
C_BE/
(Driven by Master)
Byte Enable
CMD
t2
t2
t1
PAR
(Driven by Master-Address;
LSIFC909-Data)
t3
Addr
Parity
Data
Parity
t2
t1
IRDY/
(Driven by Master)
t2
t3
TRDY/
(Driven by LSIFC909)
t3
STOP/
(Driven by LSIFC909)
Note
t3
DEVSEL/
(Driven by LSIFC909)
t1
IDSEL
(Driven by Master)
t2
Note: STOP/ is only asserted LOW if the Master attempts a burst
(i.e., FRAME/ is still asserted LOW) or if the LSIFC909
issues a retry.
AC Timings
6-7
Figure 6.2
Configuration Register Write
PCICLK
(Driven by System)
t1
FRAME/
(Driven by Master)
AD[31:0]
(Driven by Master-Address;
LSIFC909-Data)
t2
t1
t1
Addr
In
t2
t1
C_BE/
(Driven by Master)
Data In
t2
t1
Byte Enable
CMD
t2
t1
t2
t1
PAR
(Driven by Master-Address;
LSIFC909-Data)
Addr
Parity
Data
Parity
t2
t2
t1
IRDY/
(Driven by Master)
t2
t3
TRDY/
(Driven by LSIFC909)
t3
STOP/
(Driven by LSIFC909)
Note
t3
DEVSEL/
(Driven by LSIFC909)
t1
IDSEL
(Driven by Master)
t2
Note: STOP/ is only asserted LOW if the Master attempts a burst
(i.e., FRAME/ is still asserted LOW).
6-8
Specifications
Figure 6.3
Operating Register Read
PCICLK
(Driven by System)
FRAME/
(Driven by Master)
t1
AD[31:0]
(Driven by Master-Address;
LSIFC909-Data)
t1
t2
t3
Data
Out
Addr
In
t2
t1
C_BE/
(Driven by Master)
Byte Enable
CMD
t2
t2
t1
PAR
(Driven by Master-Address;
LSIFC909-Data)
t3
Addr
Parity
Data
Parity
t2
IRDY/
(Driven by Master)
t1
t2
TRDY/
(Driven by LSIFC909)
t3
STOP/
(Driven by LSIFC909)
t3
Note
t3
DEVSEL/
(Driven by LSIFC909)
Note: STOP/ is only asserted LOW if the Master attempts a burst
(i.e., FRAME/ is still asserted LOW).
AC Timings
6-9
Figure 6.4
Operating Register Write
PCICLK
(Driven by System)
t1
FRAME/
(Driven by Master)
t2
AD[31:0]
(Driven by Master-Address;
LSIFC909 - Data)
t1
t1
Addr
In
t2
t1
C_BE/
(Driven by Master)
Data In
t2
t1
Byte Enable
CMD
t2
t2
t1
t1
PAR
(Driven by Master-Address;
LSIFC909-Data)
Addr
Parity
Data
Parity
t2
t2
t1
IRDY/
(Driven by Master)
t2
t3
TRDY/
(Driven by LSIFC909)
t3
STOP/
(Driven by LSIFC909)
Note
t3
DEVSEL/
(Driven by LSIFC909)
Note: STOP/ is only asserted LOW if the Master attempts a burst (i.e.,
FRAME/ is still asserted LOW) or if the LSIFC909 issues a retry.
6-10
Specifications
Figure 6.5
Back-to-Back Read
PCICLK
(Driven by System)
t6
REQ/
(Driven by LSIFC909)
AC Timings
t4
GNT/
(Driven by Arbiter)
t5
t3
FRAME/
(Driven by LSIFC909)
AD[31:0]
(Driven by LSIFC909-Address;
Target - Data)
t1
t3
Addr
Out
PAR
(Driven by LSIFC909-Address;
Target - Data)
CMD
Byte Enable
CMD
Byte Enable
t1
t3
Data
Parity
Addr
Parity
Addr
Parity
t2
t3
IRDY/
(Driven by LSIFC909)
t1
t2
TRDY/
(Driven by Target)
STOP/
(Driven by Target)
t1
6-11
DEVSEL/
(Driven by Target)
Data
In
t2
t3
C_BE/
(Driven by LSIFC909)
Addr
Out
Data
In
t2
Data
Parity
6-12
Figure 6.6
Back-to-Back Write
PCICLK
(Driven by System)
t6
REQ/
(Driven by LSIFC909)
AC Timings
t4
GNT/
(Driven by Arbiter)
t5
t3
FRAME/
(Driven by LSIFC909)
AD[31:0]
(Driven by LSIFC909-Address;
Target-Data)
t3
Addr
Out
Data
Out
Addr
Out
Data
Out
CMD
Byte
Enable
CMD
Byte
Enable
t3
C_BE/
(Driven by LSIFC909)
PAR
(Driven by LSIFC909-Address;
Target - Data)
t3
t3
Addr
Parity
Data
Parity
t3
IRDY/
(Driven by LSIFC909)
t1
TRDY/
(Driven by Target)
STOP/
(Driven byTarget)
DEVSEL/
(Driven by Target)
t1
t2
t2
Addr
Parity
Data
Parity
Figure 6.7
Burst Read
PCICLK
(Driven by System)
t6
REQ/
(Driven by LSIFC909)
AC Timings
t4
GNT/
(Driven by Arbiter)
t3
t5
FRAME/
(Driven by LSIFC909)
AD[31:0]
(Driven by LSIFC909-Address;
Target - Data)
t1
t3
Addr
Out
Data
In
PAR
(Driven by LSIFC909-Address;
Target - Data)
Data
In
CMD
Byte Enable
Data
In
t2
t3
C_BE/
(Driven by LSIFC909)
Address
Out
CMD
Byte
Enable
t1
t3
Data
Parity
Address
Parity
Data
Parity
Address
Parity
Data
Parity
t2
t3
IRDY/
(Driven by LSIFC909)
t1
t1
TRDY/
(Driven by Target)
t2
t2
STOP/
(Driven byTarget)
t1
6-13
DEVSEL/
(Driven by Target)
t2
6-14
Figure 6.8
Burst Write
PCICLK
(Driven by System)
t6
REQ/
(Driven by LSIFC909)
t4
AC Timings
GNT/
(Driven by Arbiter)
t3
t5
FRAME/
(Driven by LSIFC909)
AD[31:0]
(Driven by LSIFC909-Address;
Target-Data)
t3
Address
Out
t3
C_BE/
(Driven by LSIFC909)
PAR
(Driven by LSIFC909-Address;
Target-Data)
t3
Data
Out
Address
Out
Byte
Enable
CMD
Data
Out
Data
Out
t3
CMD
t3
Byte Enable
t3
Address
Parity
Data
Parity
Address
Parity
Data
Parity
Data
Parity
t3
IRDY/
(Driven by LSIFC909)
t1
t2
t1
t2
TRDY/
(Driven by Target)
STOP/
(Driven byTarget)
DEVSEL/
(Driven by Target)
Figure 6.9
Read with 64-Bit Initiator and 64-Bit Target
PCICLK
(Driven by System)
t3
REQ64/
(Driven by LSIFC909)
t3
AC Timings
FRAME/
(Driven by LSIFC909)
AD[31:0]
(Driven by LSIFC909-Address;
Target-Data)
t3
t1
Address
Out
Data
In
PAR
(Driven by LSIFC909-Address;
Target-Data)
Data
In
t2
t3
C_BE[7:4]/
(Driven by LSIFC909)
Byte Enable
CMD
t3
CMD
Byte Enable
Byte Enable
Byte Enable
t1
t3
Address
Out
Address
Out
Data
In
t2
t3
IRDY/
(Driven by LSIFC909)
t1
TRDY/
(Driven by Target)
t2
STOP/
(Driven by Target)
t1
t2
DEVSEL/
(Driven by Target)
t1
6-15
ACK64/
(Driven by Target)
Data
In
t2
t1
AD[63:32]
(Driven by Target)
C_BE[3:0/]
(Driven by LSIFC909)
Address
Out
Data
In
t2
Data
In
Figure 6.10 64-Bit Dual Address Cycle
PCICLK
(Driven by System)
t3
REQ64/
(Driven by LSIFC909)
t3
FRAME/
(Driven by LSIFC909)
AD[31:0]
(Driven by LSIFC909-Address;
Target-Data)
t1
t3
Low
Address
High
Address
Data
In
t1
AD[63:32]
(Driven by Target)
Data
In
High Address
t2
t3
C_BE[3:0]/
(Driven by LSIFC909)
t2
Dual
Address
Bus
CMD
Byte Enable
t3
C_BE [7:4]/
(Driven by LSIFC909)
PAR
(Driven by LSIFC909-Address;
Target-Data)
Byte Enable
Bus CMD
t1
t3
Data
Parity
Address
Parity
t2
t3
IRDY/
(Driven by LSIFC909)
t1
TRDY/
(Driven by Target)
t2
STOP/
(Driven by Target)
t1
DEVSEL/
(Driven by Target)
t1
t2
ACK64/
(Driven by Target)
t2
6-16
Specifications
Table 6.12
PCI Interface Timings
33 MHz
Symbol
Parameter
66 MHz
Min
Max
Min
Max
Unit
t1
Shared signal input setup time
7
–
3
–
ns
t2
Shared signal input hold time
0
–
0
–
ns
t3
PCICLK to shared signal output valid
2
11
2
6
ns
t4
Side signal input setup time
10
–
5
–
ns
t5
Side signal input hold time
0
–
0
–
ns
t6
PCICLK to side signal output valid
2
12
2
6
ns
6.2.2 FC Interface Timings
Figures 6.11 through 6.13 and tables 6.13 through 6.15 represent the FC
transmit and receive timings for the LSIFC909.
Figure 6.11 FC OLC Receive Timing Waveforms
t1
t3
t2
2.0 V
1.5 V
0.8 V
RBC0
t4
RX[9:0]
AC Timings
t5
Valid
Data
tf
tr
Valid
Data
1.5 V
6-17
Table 6.13
Symbol
FC OLC Receive Timings
Parameter
Min
Max
Unit
9.411
9.413
ns
t1
Period
t2
RBC0 Low Time
3.8
–
ns
t3
RBC0 High Time
3.8
–
ns
t4
RX Setup to RBC0
3.0
–
ns
t5
RX Hold from RBC0
1.5
–
ns
tr
RBC0 Rise Time
0.7
3.0
ns
tf
RBC0 Fall Time
0.7
2.4
ns
Figure 6.12 FC 10-Bit Receive Timing Waveforms
t1
t2
t3
2.0 V
1.5 V
0.8 V
RBC1
t4
t8
6-18
Specifications
tr
tf
Comma
Character
RX[9:0]
RBC0
t5
Valid
Data
t6
Valid
Data
Valid
Data
1.5 V
t7
2.0 V
1.5 V
0.8 V
Table 6.14
Symbol
FC 10-Bit Receive Timings
Parameter
Min
Max
Unit
18.821
18.825
ns
t1
Period
t2
RBC0 Low Time
7.5
–
ns
t3
RBC0 High Time
7.5
–
ns
t4
RX Setup to RBC1
3.0
–
ns
t5
RX Hold from RBC1
1.5
–
ns
t6
RX Setup to RBC0
3.0
–
ns
t7
RX Hold from RBC0
1.5
–
ns
t8
RBC Skew
8.9
9.9
ns
tr
RBC0, RBC1 Rise Time
0.7
3.0
ns
tf
RBC0, RBC1 Fall Time
0.7
2.4
ns
Figure 6.13 FC 10-Bit and OLC Transmit Timing Waveforms
t1
t2
t3
2.0 V
1.5 V
0.8 V
TBC0
t4
TX[9:0]
AC Timings
t5
Valid
Data
tr
tf
Valid
Data
1.5 V
6-19
Table 6.15
Symbol
FC 10-Bit and OLC Transmit Timings
Parameter
Min
Max
Unit
9.411
9.413
ns
t1
Period
t2
TBCO Low Time
3.7
–
ns
t3
TBCO High Time
3.7
–
ns
t4
TX Setup to TBCO
2.0
–
ns
t5
TX Hold from TBCO
1.5
–
ns
tr
TBCO Rise Time
0.5
3.2
ns
tf
TBCO Fall Time
0.5
3.2
ns
6.2.3 Memory Interface Timings
This section provides SSRAM read and write timing interfaces and
Flash ROM read and write timing interfaces for the LSIFC909.
6.2.3.1 SSRAM Timings
Figures 6.14 and 6.15 and tables 6.16 and 6.17 represent the SSRAM
read and write timings for the LSIFC909.
6-20
Specifications
Figure 6.14 SSRAM Read Timing Waveforms
tcl
tcyc
tch
MCLK
tcss
tcsh
RAMCS/
tas
MA[21:0]
tah
A2
A1
tss
tsh
ADSC/
MOE[0]/
tadvs
tadvh
ADV/
tlzoe
MD[31:0]
MP[3:0]
toe
tcd
D1
D2-1
thzoe
AC Timings
D2-2
D2-3
D2-4
toh
6-21
Table 6.16
Symbol
tcyc
SSRAM Read Timings
Parameter
MCLK cycle time
Min
Max
Unit
18.821
18.825
ns
tcl
MCLK low
7.5
11.5
ns
tch
MCLK high
7.5
11.5
ns
tas, tadvs,
tcss, tss
Control output setup times
3.0
–
ns
tah, tadvh,
tcsh, tsh
Control output hold times
1.0
–
ns
tcd
Clock to data valid
–
5.0
ns
toe
Output enable to low data valid
–
5.0
ns
tlzoe
Output enable low to memory output
LOW-Z
0
–
ns
thzoe
Output enable high to memory output
HIGH-Z
–
4.0
ns
1.5
–
ns
toh
6-22
Data hold from MCLK
Specifications
Figure 6.15 SSRAM Write Timing Waveforms
tcl
tcyc
tch
MCLK
tcss
tcsh
RAMCS/
tas
MA[21:0]
tah
A2
A1
tss
tsh
ADSC/
twh
MWE[0]/
tws
MOE[0]/
tadvs
tadvh
ADV/
tdh
thzoe
MD[31:0]
D1-1
D2-1
D2-2
D2-3
D2-4
D2-5
tds
AC Timings
6-23
Table 6.17
Symbol
tcyc
SSRAM Write Timings
Parameter
MCLK cycle time
Min
Max
Unit
18.821
18.825
ns
tcl
MCLK low
7.5
11.5
ns
tch
MCLK high
7.5
11.5
ns
tas, tadvs,
tcss, tss, tws
Control output setup times
3.0
–
ns
tah, tadvh,
tcsh, tsh, twh
Control output hold times
1.0
–
ns
tds
Data setup time
3.0
–
ns
tdh
Data hold time
1.0
–
ns
–
4.0
ns
thzoe
Output enable high to output HIGH-Z
6.2.3.2 Flash ROM Timings
Figures 6.16 and 6.17 and tables 6.18 and 6.19 represent the
Flash ROM read and write timings for the LSIFC909.
6-24
Specifications
Figure 6.16 Flash ROM Read Timing Waveforms
tcyc
MCLK
Addr(?)
MA
Addr(x)
Addr(y)
tas
MD
trs
Read/Write
Data
trh
Data(x)
tah
FLASHCS/
thz
MOE[1]/
BWE[3]/
M-STATE
Table 6.18
Symbol
Idle or
S-Xfer
F-Addr
F-Addr
F-Wait(n)
n=9
F-Data
F-Turn
F-Turn
F-Addr
F-Addr
Flash ROM Read Timings
Parameter
Min
Max
Unit
18.821
18.825
ns
tcyc
MCLK cycle time
tas
Address setup time
16
18
ns
tah
Address hold time
0
–
ns
trs
Read setup time
7
–
ns
trh
Read hold time
0
–
ns
thz
Data high impedance
0
32
ns
AC Timings
6-25
Figure 6.17 Flash ROM Write Timing Waveforms
tcyc
MCLK
Addr(?)
MA
Addr(y)
Addr(x)
tah
MD
Read/Write
Data
Data(x)
Data(y)
twh
tws
FLASHCS/
tas
MOE[1]/
BWE[3]/
M-STATE
Table 6.19
Symbol
Idle or
S-Xfer
F-Addr
F-Addr
F-Wait(n)
n=9
F-Data
F-Turn
Idle
F-Addr
F-Addr
Flash ROM Write Timings
Parameter
Min
Max
Unit
18.821
18.825
ns
tcyc
MCLK cycle time
tas
Address setup time
16
18
ns
tah
Address hold time
1
21
MCLK
tws
Write setup time
2
92
MCLK
twh
Write hold time
37
–
ns
1. The user can program the address hold time to be either 1 MCLK or 2 MCLKs (default = 2).
2. The user can program the write setup time to be between 2 MCLKs and 9 MCLKs (default = 9).
6-26
Specifications
6.3 Packaging
The signal locations for the 329 Ball Grid Array (BGA) are illustrated in
Figure 6.18. Table 6.20 lists the LSIFC909 signals in alphanumeric order
by BGA position. Table 6.21 lists the LSIFC909 signals alphanumerically
by signal name. Figure 6.19 is the mechanical drawing of the LSIFC909.
Packaging
6-27
Figure 6.18 LSIFC909 Pinout (329-Pad BGA) Top View
A1
A2
WmIso
Test[1]
B1
WmIso
Test[0]
B2
RX_LOS
C1
WmIso
Test[2]
C2
RX9
D1
VSSC
RX+
K2
IREF
L1
L2
NC
N2
REFCLK
P1
P2
V2
TX5
T3
VSSL1
REQ/
LED[3]/
VSS
K10
K11
VSS
VDDA1
M4
M10
L11
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VSS
M12
N11
P10
VSS
L12
M11
N10
TX9
K12
VSS
VSS
N12
VSS
P11
VSS
VSS
P12
VSS
VSS
EWRAP
T4
VDDL1
VDD
VDDC
W4
AD[31]
Y2
Y3
AD[30]
AA1
AD[29]
AA2
AD[28]
AA3
AD[27]
AB1
AD[26]
AB2
AD[25]
AC1
AD[24]
AC2
6-28
VDD
L10
RST/
W3
C_BE[3]/
MODE[3]
V4
Y1
IDSEL
MODE[7]
L4
FAULT/
INTA/
GNT/
VDD
U4
V3
W2
VDDC
VDD
TX2
U3
VSSC
W1
TRST_ICE2/
R4
TX1
ENCDET
V1
VSS
BYPASS
J4
TX8
TX4
U2
GPIO[3]
D12
P4
R3
TX0
LED[2]/
D11
VSSL2
TX7
U1
MODE[0]
D10
N4
P3
T2
MODE[4]
D9
NC
TBC
TX3
T1
VDDP
M3
R2
TMS_ICE2 TMS_ICE1 TRST_CHIP/
WMSEL
D5
D6
D7
D8
VDD
VDDA2
N3
TX6
ODIS
LIPRESET/
VDDA3
K3
K4
TX+
N1
R1
VDDL2
TXM2
GPIO[2]
C12
H4
L3
VSSP
M1
LED[1]/
C11
C7
VDDQ
RBC1
VSSA1
GPIO[1]
B12
G4
J3
VSSA2
K1
A12
LED[0]/
B11
RX1
VDDC
RX-
A11
MODE[2]
B10
F4
H3
J2
VSSC
A10
MODE[1]
C10
RX2
VSSQ
VSSA3
A9
E4
G3
H2
B6
A8
TCK_CHIP TMS_CHIP
MODE[6]
B7
B8
B9
MODE[5]
C9
RX5
RBC0
G2
A7
ZCLK
FSELPCI
C8
D4
F3
RX0
J1
VSS
RX3
F2
A6
LOCKREF/ TDO_ICE2 TDO_CHIP
FSELZ
C3
C4
C5
C6
E3
RX4
H1
TDI_CHIP
B5
RX6
E2
G1
A5
TDI_ICE2
B4
D3
RX7
F1
A4
TCK_ICE2
B3
RX8
D2
E1
A3
NC
Y4
Y5
Y6
AA4
AD[16]
AA5
VDDC
AA6
AA7
C_BE[1]/
AA8
AB3
AD[19]
AB4
C_BE[2]/
AB5
TRDY/
AB6
STOP/
AB7
AD[22]
AC3
AD[20]
AC4
AD[17]
AC5
IRDY/
AC6
Y7
AD[23]
AD[21]
AD[18]
VSS
VSS
Specifications
FRAME/
Y7
Y8
VDD
VSSC
DEVSEL/
Y9
Y10
Y11
Y12
AA9
VDD
AA10
PCICLK
AA11
VSS
AA12
AB8
AD[15]
AB9
VSS_FSN
AB10
AD[11]
AB11
AD[08]
AB12
SERR/
AC8
VDD_FSN
AC9
M66EN
AC10
AD[12]
AC11
AD[09]
AC12
AD[14]
AD[13]
AD[10]
PAR
PERR/
NC
VSS
Figure 6.18 LSIFC909 Pinout (329-Pad BGA) Top View (cont.)
A13
A14
GPIO[0]
B13
TESTRESET/
C13
A15
A16
A17
A18
A19
A20
A21
A22
SCL
MA[00]
B15
MA[04]
B16
MA[08]
B17
MA[10]
B18
MA[13]
B19
MA[17]
B20
MA[20]
B21
FLASHCS/
ZZ
B22
B23
SDA
MA[01]
C15
MA[05]
C16
VSSC
C17
MA[11]
C18
MA[14]
C19
MA[18]
C20
MA[21]
C21
MOE[0]/
C22
RAMCS/
C23
MA[02]
D15
MA[06]
D16
MA[09]
D17
MA[12]
D18
MA[15]
D19
MA[19]
D20
D21
MOE[1]/
D22
MWE[0]/
D23
MA[03]
MA[07]
VDDC
MA[16]
E20
BWE[3]/
E21
BWE[2]/
E22
MWE[1]/
E23
BWE[1]/
F20
BWE[0]/
F21
MP[1]
F22
MP[0]
F23
VDDC
G20
MP[3]
G21
MP[2]
G22
ADV/
G23
H20
MD[00]
H21
VSSC
H22
MCLK
H23
MD[03]
J20
MD[02]
J21
MD[01]
J22
ADSC/
J23
MD[07]
K20
MD[06]
K21
MD[05]
K22
MD[04]
K23
L20
MD[10]
L21
MD[09]
L22
MD[08]
L23
MD[14]
M20
MD[13]
M21
MD[12]
M22
MD[11]
M23
N20
MD[17]
N21
MD[16]
N22
MD[15]
N23
MD[21]
P20
MD[20]
P21
MD[19]
P22
MD[18]
P23
R20
MD[24]
R21
MD[23]
R22
MD[22]
R23
MD[28]
T20
MD[27]
T21
MD[26]
T22
MD[25]
T23
AD[32]
U20
MD[31]
U21
MD[30]
U22
MD[29]
U23
V20
AD[34]
V21
VSSC
V22
AD[33]
V23
VDDC
W20
AD[37]
W21
AD[36]
W22
AD[35]
W23
B14
C14
ROMSIZE[1]
ARMEN/
D13
D14
ROMSIZE[0]
VDD
VDD
VSS
VDD
K13
K14
VSS
L13
VSS
VDD
L14
VSS
M13
VSS
M14
VSS
N13
VSS
VSS
N14
VSS
P13
VSS
P14
VSS
VSS
VDD
VDD
VSS
A23
Y13
Y14
Y15
Y16
Y17
Y18
Y19
AD[41]
Y20
AD[40]
Y21
AD[39]
Y22
AD[38]
Y23
AD[05]
AA13
VDD
AA14
REQ64/
AA15
AD[62]
AA16
VDD
AA17
VDDC
AA18
AD[58]
AA19
VSS
AA20
AD[44]
AA21
AD[43]
AA22
AD[42]
AA23
AD[06]
AB13
AD[02]
AB14
ACK64/
AB15
C_BE[6]/
AB16
PAR64
AB17
AD[60]
AB18
AD[56]
AB19
AD[47]
AB20
VSS
AB21
AD[46]
AB22
AD[45]
AB23
AD[07]
AC13
AD[03]
AC14
AD[01]
AC15
C_BE[5]/
AC16
VSSC
AC17
AD[61]
AC18
AD[57]
AC19
AD[54]
AC20
AD[52]
AC21
AD[50]
AC22
AD[48]
AC23
AD[04]
AD[00]
C_BE[7]/
AD[63]
AD[59]
AD[55]
AD[53]
AD[51]
AD[49]
C_BE[0]/
Packaging
C_BE[4]/
6-29
Table 6.20
Alphanumeric List by BGA Position
329-BGA
Grid
Position
Signal
Name
329-BGA
Grid
Position
Signal
Name
329-BGA
Grid
Position
Signal
Name
329-BGA
Grid
Position
Signal
Name
329-BGA
Grid
Position
Signal
Name
329-BGA
Grid
Position
Signal
Name
A1
WmlsoTest[1]
C10
MODE[0]
G3
RBC1
M13
VSS
U23
AD[33]
AA16
C_BE[6]/
A2
WmlsoTest[0]
C11
LED[2]/
G4
VDD
M14
VSS
V1
VSSC
AA17
PAR64
A3
TCK_ICE2
C12
GPIO[3]
G20
VDD
M20
VSS
V2
INTA/
AA18
AD[60]
A4
TDI_ICE2
C13
ROMSIZE[1]
G21
MD[00]
M21
MD[17]
V3
RST/
AA19
AD[56]
A5
TDI_CHIP
C14
ARMEN/
G22
VSSC
M22
MD[16]
V4
VDDC
AA20
AD[47]
A6
ZCLK
C15
MA[02]
G23
MCLK
M23
MD[15]
V20
VDDC
AA21
VSS
A7
TCK_CHIP
C16
MA[06]
H1
VSSA3
N1
REFCLK
V21
AD[37]
AA22
AD[46]
A8
TMS_CHIP
C17
MA[09]
H2
RX−
N2
TBC
V22
AD[36]
AA23
AD[45]
A9
MODE[6]
C18
MA[12]
H3
VDDL2
N3
VSSL2
V23
AD[35]
AB1
AD[25]
A10
MODE[2]
C19
MA[15]
H4
BYPASS
N4
TX9
W1
GNT/
AB2
AD[24]
A11
LED[0]/
C20
MA[19]
H20
MD[03]
N10
VSS
W2
REQ/
AB3
AD[22]
A12
GPIO[1]
C21
VSS
H21
MD[02]
N11
VSS
W3
AD[31]
AB4
AD[20]
A13
GPIO[0]
C22
MOE[1]/
H22
MD[01]
N12
VSS
W4
NC
AB5
AD[17]
A14
SCL
C23
MWE[0]/
H23
ADSC/
N13
VSS
W20
AD[41]
AB6
IRDY/
A15
MA[00]
D1
RX7
J1
VSSA2
N14
VSS
W21
AD[40]
AB7
VSSC
A16
MA[04]
D2
RX6
J2
RX+
N20
MD[21]
W22
AD[39]
AB8
SERR/
A17
MA[08]
D3
RX5
J3
LIPRESET/
N21
MD[20]
W23
AD[38]
AB9
VDD_FSN
A18
MA[10]
D4
VSS
J4
VDDA3
N22
MD[19]
Y1
AD[30]
AB10
M66EN
A19
MA[13]
D5
TRST_ICE2/
J20
MD[07]
N23
MD[18]
Y2
AD[29]
AB11
AD[12]
A20
MA[17]
D6
VDDC
J21
MD[06]
P1
TX6
Y3
AD[28]
AB12
AD[09]
A21
MA[20]
D7
VDD
J22
MD[05]
P2
TX7
Y4
VSS
AB13
AD[07]
A22
FLASHCS/
D8
MODE[7]
J23
MD[04]
P3
TX8
Y5
AD[16]
AB14
AD[03]
A23
ZZ
D9
MODE[3]
K1
IREF
P4
VDD
Y6
VDDC
AB15
AD[01]
B1
RX_LOS
D10
VDD
K2
VSSA1
P10
VSS
Y7
VDD
AB16
C_BE[5]/
B2
WmlsoTest[2]
D11
LED[3]/
K3
VDDA2
P11
VSS
Y8
C_BE[1]/
AB17
VSSC
B3
LOCKREF/
D12
VSS
K4
VDD
P12
VSS
Y9
NC
AB18
AD[61]
B4
TDO_ICE2
D13
ROMSIZE[0]
K10
VSS
P13
VSS
Y10
VDD
AB19
AD[57]
B5
TDO_CHIP
D14
VDD
K11
VSS
P14
VSS
Y11
PCICLK
AB20
AD[54]
B6
FSELZ
D15
MA[03]
K12
VSS
P20
VDD
Y12
VSS
AB21
AD[52]
B7
VSSC
D16
MA[07]
K13
VSS
P21
MD[24]
Y13
AD[05]
AB22
AD[50]
B8
FSELPCI
D17
VDD
K14
VSS
P22
MD[23]
Y14
VDD
AB23
AD[48]
B9
MODE[5]
D18
VDDC
K20
VDD
P23
MD[22]
Y15
REQ64/
AC1
IDSEL
B10
MODE[1]
D19
MA[16]
K21
MD[10]
R1
TX3
Y16
AD[62]
AC2
C_BE[3]/
B11
LED[1]/
D20
VSS
K22
MD[09]
R2
TX4
Y17
VDD
AC3
AD[23]
B12
GPIO[2]
D21
BWE[3]/
K23
MD[08]
R3
TX5
Y18
VDDC
AC4
AD[21]
B13
TESTRESET/
D22
BWE[2]/
L1
VSSP
R4
EWRAP
Y19
AD[58]
AC5
AD[18]
B14
SDA
D23
MWE[1]/
L2
TX−
R20
MD[28]
Y20
VSS
AC6
FRAME/
B15
MA[01]
E1
RX4
L3
VDDP
R21
MD[27]
Y21
AD[44]
AC7
DEVSEL/
B16
MA[05]
E2
RX3
L4
VDDA1
R22
MD[26]
Y22
AD[43]
AC8
PERR/
B17
VSSC
E3
RX2
L10
VSS
R23
MD[25]
Y23
AD[42]
AC9
VSS
B18
MA[11]
E4
RX1
L11
VSS
T1
TX0
AA1
AD[27]
AC10
AD[14]
B19
MA[14]
E20
BWE[1]/
L12
VSS
T2
TX1
AA2
AD[26]
AC11
AD[13]
B20
MA[18]
E21
BWE[0]/
L13
VSS
T3
TX2
AA3
VSS
AC12
AD[10]
B21
MA[21]
E22
MP[1]
L14
VSS
T4
VDDL1
AA4
AD[19]
AC13
C_BE[0]/
B22
MOE[0]/
E23
MP[0]
L20
MD[14]
T20
AD[32]
AA5
C_BE[2]/
AC14
AD[04]
B23
RAMCS/
F1
RX0
L21
MD[13]
T21
MD[31]
AA6
TRDY/
AC15
AD[00]
C1
RX9
F2
RBC0
L22
MD[12]
T22
MD[30]
AA7
STOP/
AC16
C_BE[7]/
C2
RX8
F3
VDDC
L23
MD[11]
T23
MD[29]
AA8
PAR
AC17
C_BE[4]/
C3
VSS
F4
VDDQ
M1
NC
U1
ENCDET
AA9
AD[15]
AC18
AD[63]
C4
ODIS
F20
VDDC
M2
TX+
U2
VSSL1
AA10
VSS_FSN
AC19
AD[59]
C5
TMS_ICE2
F21
MP[3]
M3
NC
U3
FAULT/
AA11
AD[11]
AC20
AD[55]
C6
TMS_ICE1
F22
MP[2]
M4
VSS
U4
VDD
AA12
AD[08]
AC21
AD[53]
C7
TRST_CHIP/
F23
ADV/
M10
VSS
U20
VDD
AA13
AD[06]
AC22
AD[51]
C8
WMSEL
G1
VSSC
M11
VSS
U21
AD[34]
AA14
AD[02]
AC23
AD[49]
C9
MODE[4]
G2
VSSQ
M12
VSS
U22
VSSC
AA15
ACK64/
6-30
Specifications
Table 6.21
Alphanumeric List by Signal Name
329-BGA
Grid
Position
Signal
Name
329-BGA
Grid
Position
Signal
Name
329-BGA
Grid
Position
Signal
Name
329-BGA
Grid
Position
Signal
Name
329-BGA
Grid
Position
Signal
Name
329-BGA
Grid
Position
ACK64/
AA15
AD[00]
AC15
AD[54]
AB20
AD[55]
AC20
MA[05]
B16
MODE[5]
B9
TMS_ICE1
C6
VSS
D12
MA[06]
C16
MODE[6]
A9
TMS_ICE2
C5
VSS
AD[01]
AB15
AD[56]
D20
AA19
MA[07]
D16
MODE[7]
D8
TRDY/
AA6
VSS
AD[02]
AA14
AD[57]
K10
AB19
MA[08]
A17
MOE[0]/
B22
TRST_CHIP/
C7
VSS
K11
AD[03]
AB14
AD[58]
AD[04]
AC14
AD[59]
Y19
MA[09]
C17
MOE[1]/
C22
TRST_ICE2/
D5
VSS
K12
AC19
MA[10]
A18
MP[0]
E23
TX−
L2
VSS
AD[05]
Y13
AD[60]
K13
AA18
MA[11]
B18
MP[1]
E22
TX+
M2
VSS
K14
AD[06]
AA13
AD[07]
AB13
AD[61]
AB18
MA[12]
C18
MP[2]
F22
TX0
T1
VSS
L10
AD[62]
Y16
MA[13]
A19
MP[3]
F21
TX1
T2
VSS
L11
AD[08]
AD[09]
AA12
AD[63]
AC18
MA[14]
B19
MWE[0]/
C23
TX2
T3
VSS
L12
AB12
ADSC/
H23
MA[15]
C19
MWE[1]/
D23
TX3
R1
VSS
L13
AD[10]
AC12
ADV/
F23
MA[16]
D19
NC
M1
TX4
R2
VSS
L14
AD[11]
AA11
ARMEN/
C14
MA[17]
A20
NC
M3
TX5
R3
VSS
M4
AD[12]
AB11
BWE[0]/
E21
MA[18]
B20
NC
W4
TX6
P1
VSS
M10
AD[13]
AC11
BWE[1]/
E20
MA[19]
C20
NC
Y9
TX7
P2
VSS
M11
AD[14]
AC10
BWE[2]/
D22
MA[20]
A21
ODIS
C4
TX8
P3
VSS
M12
AD[15]
AA9
BWE[3]/
D21
MA[21]
B21
PAR
AA8
TX9
N4
VSS
M13
AD[16]
Y5
BYPASS
H4
MCLK
G23
PAR64
AA17
VDD
D7
VSS
M14
AD[17]
AB5
C_BE[0]/
AC13
MD[00]
G21
PCICLK
Y11
VDD
D10
VSS
M20
AD[18]
AC5
C_BE[1]/
Y8
MD[01]
H22
PERR/
AC8
VDD
D14
VSS
N10
AD[19]
AA4
C_BE[2]/
AA5
MD[02]
H21
RAMCS/
B23
VDD
D17
VSS
N11
AD[20]
AB4
C_BE[3]/
AC2
MD[03]
H20
RBC0
F2
VDD
G4
VSS
N12
AD[21]
AC4
C_BE[4]/
AC17
MD[04]
J23
RBC1
G3
VDD
G20
VSS
N13
AD[22]
AB3
C_BE[5]/
AB16
MD[05]
J22
REFCLK
N1
VDD
K4
VSS
N14
AD[23]
AC3
C_BE[6]/
AA16
MD[06]
J21
REQ/
W2
VDD
K20
VSS
P10
AD[24]
AB2
C_BE[7]/
AC16
MD[07]
J20
REQ64/
Y15
VDD
P4
VSS
P11
AD[25]
AB1
DEVSEL/
AC7
MD[08]
K23
ROMSIZE[0]
D13
VDD
P20
VSS
P12
AD[26]
AA2
ENCDET
U1
MD[09]
K22
ROMSIZE[1]
C13
VDD
U4
VSS
P13
AD[27]
AA1
EWRAP
R4
MD[10]
K21
RST/
V3
VDD
U20
VSS
P14
AD[28]
Y3
FAULT/
U3
MD[11]
L23
RX−
H2
VDD
Y7
VSS
Y4
AD[29]
Y2
FLASHCS/
A22
MD[12]
L22
RX_LOS
B1
VDD
Y10
VSS
Y12
Signal
Name
AD[30]
Y1
FRAME/
AC6
MD[13]
L21
RX+
J2
VDD
Y14
VSS
Y20
AD[31]
W3
FSELPCI
B8
MD[14]
L20
RX0
F1
VDD
Y17
VSSA1
K2
AD[32]
T20
FSELZ
B6
MD[15]
M23
RX1
E4
VDDA1
L4
VSSA2
J1
AD[33]
U23
GNT/
W1
MD[16]
M22
RX2
E3
VDDA2
K3
VSSA3
H1
AD[34]
U21
GPIO[0]
A13
MD[17]
M21
RX3
E2
VDDA3
J4
VSSC
AB7
AD[35]
V23
GPIO[1]
A12
MD[18]
N23
RX4
E1
VDDC
D6
VSSC
AB17
AD[36]
V22
GPIO[2]
B12
MD[19]
N22
RX5
D3
VDDC
D18
VSSC
B7
AD[37]
V21
GPIO[3]
C12
MD[20]
N21
RX6
D2
VDDC
F3
VSSC
B17
AD[38]
W23
IDSEL
AC1
MD[21]
N20
RX7
D1
VDDC
F20
VSSC
G1
AD[39]
W22
INTA/
V2
MD[22]
P23
RX8
C2
VDDC
V4
VSSC
G22
AD[40]
W21
IRDY/
AB6
MD[23]
P22
RX9
C1
VDDC
V20
VSSC
U22
AD[41]
W20
IREF
K1
MD[24]
P21
SCL
A14
VDDC
Y6
VSSC
V1
AD[42]
Y23
LED[0]/
A11
MD[25]
R23
SDA
B14
VDDC
Y18
VSSQ
G2
AD[43]
Y22
LED[1]/
B11
MD[26]
R22
SERR/
AB8
VDDQ
F4
VSS_FSN
AA10
AD[44]
Y21
LED[2]/
C11
MD[27]
R21
STOP/
AA7
VDD_FSN
AB9
VSSL1
U2
AD[45]
AA23
LED[3]/
D11
MD[28]
R20
TBC
N2
VDDL1
T4
VSSL2
N3
AD[46]
AA22
LIPRESET/
J3
MD[29]
T23
TCK_CHIP
A7
VDDL2
H3
VSSP
L1
AD[47]
AA20
LOCKREF/
B3
MD[30]
T22
TCK_ICE2
A3
VDDP
L3
WmlsoTest[0]
A2
AD[48]
AB23
M66EN
AB10
MD[31]
T21
TDI_CHIP
A5
VSS
AA3
WmlsoTest[1]
A1
AD[49]
AC23
MA[00]
A15
MODE[0]
C10
TDI_ICE2
A4
VSS
AA21
WmlsoTest[2]
B2
AD[50]
AB22
MA[01]
B15
MODE[1]
B10
TDO_CHIP
B5
VSS
AC9
WMSEL
C8
AD[51]
AC22
MA[02]
C15
MODE[2]
A10
TDO_ICE2
B4
VSS
C3
ZCLK
A6
AD[52]
AB21
MA[03]
D15
MODE[3]
D9
TESTRESET/
B13
VSS
C21
ZZ
A23
AD[53]
AC21
MA[04]
A16
MODE[4]
C9
TMS_CHIP
A8
VSS
D4
Packaging
6-31
Figure 6.19 329-Pad Plastic Ball Grid Array
Important:
6-32
This drawing may not be the latest version. For board layout and manufacturing, obtain the
most recent engineering drawings from your LSI Logic marketing representative by
requesting the outline drawing for package code BL.
Specifications
Appendix A
Register Summary
Tables A.1 and A.2 list the register summary by register name for the
LSIFC909.
Table A.1
LSIFC909 Configuration Space
Register Name
Address
Read/Write
Page
BIST/Header/Latency/Cache Line
0x0C
Read/Write
5-13
Capabilities Pointer
0x34
Read/Write
5-19
Class Code/Revision ID
0x08
Read/Write
5-12
Device ID/Vendor ID
0x00
Read Only
5-8
Expansion ROM Base Address
0x30
Read/Write
5-18
I/O Base Address
0x10
Read/Write
5-14
Latency/Interrupt
0x3C
Read/Write
5-20
Mem0 Base Address High
0x18
Read/Write
5-15
Mem0 Base Address Low
0x14
Read/Write
5-14
Mem1 Base Address High
0x20
Read/Write
5-17
Mem1 Base Address Low
0x1C
Read/Write
5-16
Power Management Configuration
0x40
Read/Write
5-21
LSIFC909 Fibre Channel I/O Processor
A-1
Table A.1
LSIFC909 Configuration Space
Register Name
Address
Read/Write
Page
Power Management Control/Status
0x44
Read/Write
5-22
Reserved
0x24–0x28
Reserved
0x38
Read Only
5-19
Reserved
0x48–0x7F
Read Only
5-23
Status/Command
0x04
Read/Write
5-9
Subsystem ID/Vendor ID
0x2C
Read Only
5-18
Register Name
Address
Read/Write
Page
Host Diagnostic
0x08
Read/Write
5-26
Host Index
0x50
Read/Write
5-31
Host Interrupt Mask
0x34
Read/Write
5-29
Host Interrupt Status
0x30
Read Only
5-28
Reply FIFO
0x44
Read/Write
5-30
Request FIFO
0x40
Read/Write
5-30
System Doorbell
0x00
Read/Write
5-24
Test Base Address
0x0C
Read/Write
5-27
Write Sequence
0x04
Read/Write
5-25
Table A.2
5-17
LSIFC909 Mem0 and I/O Space
.
A-2
–
Register Summary
Appendix B
Reference
Specifications
The LSIFC909 is compliant with the specifications listed in Table B.1:
Table B.1
Reference Specifications
Specification
Revision
FC Physical and Signaling Interface (FC-PH)
4.3
FC Arbitrated Loop (FC-AL-2)
7.0
FC Private Loop Direct Attach (FC-PLDA)
1.5
FCP for SCSI (FCP)
12
GBIC
5.4
PCI Local Bus Specification
2.2
LSIFC909 Fibre Channel I/O Processor
B-1
B-2
Reference Specifications
Appendix C
Glossary of Terms and
Abbreviations
8B/10B
A data encoding scheme developed by IBM, translating byte wide data
to an encoded 10-bit format.
ANSI
American National Standards Institute, the coordinating organization for
voluntary standards in the United States.
Arbitrated loop
topology
(FC-AL)
A FC Topology that provides a low cost solution to attach multiple ports
in a loop without hubs and switches.
BER
Bit Error Rate.
Bit
A binary digit. The smallest unit of information a computer uses. The
value of a bit (0 or 1) represents a two-way choice, such as on or off,
true or false, and so on.
Broadcast
Sending a transmission to all N_Ports on a fabric.
Bus
A collection of unbroken signal lines across which information is
transmitted from one part of a computer system to another. Connections
to the bus are made using taps on the lines.
Bus Mastering
A high-performance way to transfer data. The host adapter controls the
transfer of data directly to and from system memory without bothering
the computer’s microprocessor. This is the fastest way for multitasking
operating systems to transfer data.
Byte
A unit of information consisting of eight bits.
Channel
A point-to-point link, the main task of which is to transport data from one
point to another.
LSIFC909 Fibre Channel I/O Processor
C-1
Configuration
Refers to the way a computer is setup; the combined hardware
components (computer, monitor, keyboard, and peripheral devices) that
make up a computer system; or the software settings that allow the
hardware components to communicate with each other.
CPU
Central Processing Unit. The “brain” of the computer that performs the
actual computations. The term Microprocessor Unit (MPU) is also used.
Crosspointswitched
topology
(FC-XS)
Highest performance FC fabric, providing a choice of multiple path
routings between pairs of F_Ports.
Device Driver
A program that allows a microprocessor (through the operating system)
to direct the operation of a peripheral device.
DMA
Direct Memory Access. A method of moving data from a storage device
directly to RAM, without using the CPU’s resources.
DMA Bus
Master
A feature that allows a peripheral to control the flow of data to and from
system memory by blocks, as opposed to PIO (Programmed I/O) where
the processor is in control and the flow is by byte.
EEPROM
Electronically Erasable Programmable Read Only Memory. A memory
chip typically used to store configuration information.
EISA
Extended Industry Standard Architecture. An extension of the 16-bit ISA
bus standard. It allows devices to perform 32-bit data transfers.
Exchange
A term that refers to one of the FC “building blocks”, composed of one
or more nonconcurrent sequences for a single operation.
Fabric
FC defined interconnection methodology that handles routing in FC
networks.
FC-0
Lowest level of the FC Physical standard, covering the physical
characteristics of the interface and media.
FC-1
Middle level of the FC-PH standard, defining the 8B/10B
encoding/decoding and transmission protocol.
FC-2
Highest level of FC-PH, defining the rules for signaling protocol and
describing transfer of the frame, sequence, and exchanges.
C-2
Glossary of Terms and Abbreviations
FC-3
The hierarchical level in the FC standard that provides common services,
such as striping definition.
FC-4
The hierarchical level in the FC standard that specifies the mapping of
Upper Layer Protocols (ULPs) to levels below.
FCC
Federal Communications Commission.
FC-EP
The future FC Enhanced Physical standard, which will build on and is
compatible with FC-PH.
FCP
Fibre Channel Protocol.
FC-PH
FC Physical standard, consisting of the three lower levels; FC-0, FC-1,
and FC-2.
Fibre Channel
Service
Protocol (FSP)
The common FC-4 level protocol for all services, transparent to the fabric
type or topology.
FDDI
Fiber Distributed Data Interface. ANSI option for a Metropolitan Area
Network (MAN); a network based on the use of optical fiber cable to
transmit data at 100 Mbits/s.
File
A named collection of information stored on a disk.
Firmware
Software that is permanently stored in ROM. Therefore, it can be
accessed during boot time.
F_Port
“Fabric” port, the access point of the fabric for physically connecting the
user’s N_Port.
FL_Port
An F_Port that contains arbitrated loop functions.
Frame
A linear set of transmitted bits that define a basic transport element.
GBIC
Gigabit Interface Converter.
HAL
Hardware Abstraction Layer.
Hard Disk
A disk made of metal and permanently sealed into a drive cartridge. A
hard disk can store very large amounts of information.
HIPPI
High Performance Parallel Interface, an 800 Mbits/s interface to
supercomputer networks (formerly known as high speed channel)
developed by ANSI.
C-3
Host
The computer system in which a SCSI host adapter is installed. It uses
the SCSI host adapter to transfer information to and from devices
attached to the SCSI bus.
Host Adapter
A circuit board or integrated circuit that provides a SCSI bus connection
to the computer system.
IOC
Input/Output Controller.
IP
Internet Protocol.
IPI
Intelligent Peripheral Interface.
ISA
Industry Standard Architecture. A type of computer bus used in most
PCs. It allows devices to send and receive data up to 16 bits at a time.
Kbyte
Kilobyte. A measure of computer storage equal to 1024 bytes.
LCT
Logical Configuration Table.
Link_Control_
Facility
A termination card that handles the logical and physical control of the FC
link for each mode of use.
LLC
Logical Link Control.
Local Bus
A way to connect peripherals directly to computer memory. It bypasses
the slower ISA and EISA buses. PCI is a local bus standard.
Login server
Entity within the FC fabric that receives and responds to login requests.
L_Port
A FC port which supports the arbitrated loop topology.
LUN
Logical Unit Number. An identifier, zero to seven, for a logical unit.
Mbyte
Megabyte. A measure of computer storage equal to 1024 kilobytes.
MFA
Message Frame Address.
MIA
Media Interface Adapter.
MTU
Message Transfer Unit.
Multicast
Refers to delivering a single transmission to multiple destination N_Ports.
NIC
Network Interface Card.
N_Port
“Node” port, a FC defined hardware entity at the node end of a link.
C-4
Glossary of Terms and Abbreviations
NL_Port
An N_Port that contains arbitrated loop functions.
Operating
System
A program that organizes the internal activities of the computer and its
peripheral devices. An operating system performs basic tasks such as
moving data to and from devices, and managing information in memory.
It also provides the user interface.
Operation
A term, defined in FC-2, that refers to one of the FC “building blocks”
composed of one or more, possibly concurrent, exchanges.
Ordered Set
A FC term referring to four 10-bit characters (a combination of data and
special characters) that provide low level link functions, such as frame
demarcation and signaling between two ends of a link. It provides for
initialization of the link after power-on and for some basic recovery
actions.
Originator
A FC term referring to the initiating device.
Parity Checking
A way to verify the accuracy of data transmitted over the SCSI bus. One
bit in the transfer is used to make the sum of all the 1 bits either odd or
even (for odd or even parity). If the sum is not correct, an error message
appears.
PCI
Peripheral Component Interconnect. A local bus specification that allows
connection of peripherals directly to computer memory. It bypasses the
slower ISA and EISA buses.
PDB
Packet Descriptor Block.
PIO
Programmed Input/Output. A way the CPU can transfer data to and from
memory using the computer’s I/O ports. PIO is usually faster than DMA,
but requires CPU time.
Port
The hardware entity within a node that performs data communications
over the FC link.
Port Address
Also Port Number. The address through which commands are sent to a
host adapter board. This address is assigned by the PCI bus.
Port Number
See Port Address.
C-5
RAM
Random Access Memory. The computer’s primary working memory in
which program instructions and data are stored and are accessible to the
CPU. Information can be written to and read from RAM. The contents of
RAM are lost when the computer is turned off.
Responder
A FC term referring to the answering device.
RISC Core
LSIFC909 chips contain a RISC (Reduced Instruction Set Computer)
processor, programmed through microcode scripts.
ROM
Read Only Memory. Memory from which information can be read but not
changed. The contents of ROM are not erased when the computer is
turned off.
SAN
Storage Area Network.
SCAM
SCSI Configured AutoMatically. A method to automatically allocate SCSI
IDs using software when SCAM compliant SCSI devices are attached.
Scatter/Gather
A device driver feature that lets the host adapter modify a transfer data
pointer so that a single host adapter transfer can access many segments
of memory. This minimizes interrupts and transfer overhead.
SCB
SCSI Command Block.
SCSI
Small Computer System Interface. A specification for a high-performance
peripheral bus and command set. The original standard is referred to as
SCSI-1.
SCSI-2
The current SCSI specification which adds features to the original
SCSI-1 standard.
SCSI ID
A way to uniquely identify each SCSI device on the SCSI bus. Each
SCSI bus has eight available SCSI IDs numbered 0 through 7 (or 0
through 15 for Wide SCSI). The host adapter usually gets ID 7 giving it
priority to control the bus.
Sequence
A term referring to one of the FC “building blocks”, composed of one or
more related frames for a single operation.
SGL
Scatter Gather List.
SNAP
SubNetwork Access Protocol.
C-6
Glossary of Terms and Abbreviations
Synchronous
Data Transfer
One of the ways data is transferred over the SCSI bus. Transfers are
clocked with fixed frequency pulses. This is faster than asynchronous
data transfer. Synchronous data transfers are negotiated between the
SCSI host adapter and each SCSI device.
System BIOS
Controls the low level POST (Power-On Self-Test), and basic operation
of the CPU and computer system.
TID
Target ID.
Topology
The logical and/or physical arrangement of stations on a network.
ULP
Upper Layer Protocol.
VCCI
Voluntary Control Council for Interference.
Virtual Memory
Space on a hard disk that can be used as if it were RAM.
VPD
Vendor Product Data.
Word
A two byte (or 16 bit) unit of information.
X3T9
A technical committee of the Accredited Standards Committee X3, titled
X3T9 I/O Interfaces. It is tasked with developing standards for moving
data in and out of central computers.
C-7
C-8
Glossary of Terms and Abbreviations
Index
Numerics
4 mA bidirectional signals 6-5
4 mA output signals 6-4
8 mA bidirectional signals 6-5
8 mA output signals 6-4
8b/10b decoding 2-2
8b/10b encoding 2-2
A
configuration
registers 5-7
space 5-1
context manager 1-7
controller
link 1-6
memory 1-6
CRC 2-4
cyclic redundancy check 2-4
D
AC timing 6-5
ACK64/ 4-3
AD[10:8] 5-1, 5-2
AD[63:0] 4-4
ADSC/ 4-10
ADV/ 4-10
arbitrated loop topology 2-9
architecture 1-5
ARMEN/ 4-11
data frames 2-3, 2-4
data parity reported (DPR) 5-10
data sequence 2-7
decoding 8b/10b 2-2
destination identifier (D_ID) 2-8
detected parity error (DPE) 5-9
device ID (DevID) 5-8
DEVSEL/ 4-5
DevSEL/ timing (DevSEL/Tim) 5-10
diagnostic memory enable (DME) 5-27
diagnostic write enable (DWE) 5-26
disable ARM (DisARM) 5-27
doorbell interrupt (DI) 5-28
doorbell interrupt mask (DIM) 5-29
dual address cycle (DAC) 1-6
B
BER 1-8
bit error rate 1-8
built-in self-test (BIST) 5-13
BWE[3:0]/ 4-10
BYPASS/ 4-8
E
C
C_BE[3:0] 5-3
C_BE[7:0]/ 4-4, 5-1, 5-2
cache
boundary alignment 5-4
line multiple transfers 5-5
cache line size 5-13
register 5-3
register support 5-4
selection 5-4
capabilities pointer (CapPtr) 5-19
capacitance 6-3
channel protocol 2-1
class 1 2-10
class 2 2-10
class 3 2-10
class code (ClCode) 5-12
class intermix 2-10
classes of service 2-10
command descriptor block (CDB) 2-7
EN_CDET 4-7
enable
bus mastering (EBM) 5-11
I/O space (EIOS) 5-11
memory space (EMS) 5-11
parity error response (EPER) 5-11
encode/decode 2-2
end-of-frame (EOF) 2-4
EWRAP 4-7
exchanges transfer 2-2
expansion ROM base address (ExpROMBAdd) 5-18
expansion ROM enable 5-19
F
fabric topology 2-8
FAULT/ 4-8
FC
(fibre channel) 2-1
10-bit and OLC transmit timing 6-20
10-bit receive timing 6-19
LSIFC909 Fibre Channel I/O Processor
IX-1
FC (Cont.)
data structure 2-5
devices 2-7
exchange 2-5
frames 2-5
interface 2-1
layer 2-2
link 1-7
N_Ports 2-3
NL_Port 1-4
sequence 2-5
structure 2-1
word 2-5
FCP 2-6
exchange 2-7
fibre channel protocol 1-1
fibre channel (FC) 2-1
fibre channel protocol (FCP) 1-1
flash bad signature (FBS) 5-26
flash ROM read timing 6-22, 6-24, 6-25
flash ROM write timing 6-26
FLASHCS/ 4-10
frame
data 2-3
end of 2-4
link control 2-3
payload 2-7
start of 2-4
transfer 2-2
FRAME/ 4-5
FSELPCI 4-6
FSELZ 4-11
functional block diagram 1-5
G
GNT/ 4-3
GPIO[3:0] 4-12
H
host doorbell value (HDV) 5-25
host index value (HIVal) 5-31
host interface register set 5-23
I
I/O base address (IOBAdd) 5-14
I/O or memory space indicator (IOMemSP) 5-14, 5-15
I/O processor (IOP) 5-24
IDSEL 4-4
initiator command sequence 2-7
input signals 6-3
INTA/ 4-6
integrated transceiver 1-7
integration 2-3
interface 2-3
FC 2-1
media 2-2
PCI 1-6
system 1-6
upper layer protocol (ULP) 2-1
interface timing
FC 10-bit and OLC transmit 6-20
FC 10-bit receive 6-19
IX-2
Index
FC OLC receive 6-18
intermix class 2-10
internet protocol (IP) 2-1
interrupt line (IntLin) 5-20
interrupt pin (IntPin) 5-20
IOP doorbell status (IOPDS) 5-28
IRDY/ 4-5
IREF 4-8
L
latency timer 5-5
(LatTim) 5-13
LCK_REF/ 4-7
LED[3:0]/ 4-12
link control frames 2-3, 2-4
link controller 1-6
LIPRESET/ 4-8
location of memory (type) 5-15
M
M66EN 4-6
MA[21:0] 4-9
master abort (MA) 5-10
maximum latency (MaxLat) 5-20
maximum stress ratings 6-2
MCLK 4-10
MD[31:0] 4-9
media interface 2-2
mem0 base address high (Mem0BAddH) 5-15
mem0 base address low (Mem0BAddL) 5-14
memory
controller 1-6
read command 5-6
read line command 5-6
read multiple 5-6
write and invalidate command 5-4
message
queueing models 3-5
transport 1-6
minimum grant (MinGnt) 5-20
MODE[7:0] 4-11
MOE[1:0] 4-9
MP[3:0] 4-9
MWE[1:0]/ 4-10
O
ODIS 4-8
operating conditions 6-2
overview 1-1 to 1-3
P
packaging 6-27
PAR 4-6
PAR64 4-6
payload 2-4, 2-7
PCI
bidirectional signals 6-4
bus commands 5-3
cache line size register support 5-4
commands 5-2
configuration registers 5-7 to 5-23
PCI (Cont.)
configuration space 5-1
device base address 5-2
interface 1-6
output signals 6-3
target disconnect 5-6
target retry 5-5
PCI cache mode
memory read line command 5-6
memory write and invalidate command 5-4
PCICLK 4-3
PERR/ 4-6, 5-10
point-to-point topology 2-8
ports 2-7
power management configuration
(PMCap) (NIPtr) (CapID) 5-21
power management control/status
(PMData) (PMCSR-BSE) (PMCtrl/St) 5-22
power state (PWS[1:0]) 5-23
prefetchable memory block (prefetch) 5-15
processor
ARM RISC 1-5, 1-6, 1-7
I/O 1-6
protocol
channel 2-1
fibre channel (FCP) 1-1, 2-6
internet 2-1
signaling 2-2
transmission 2-2
upper layer 2-1, 2-3
PWS[1:0] 5-23
R
RAMCS/ 4-10
RBC[1:0] 4-7
received target abort (RTA) 5-10
receiver 1-7
REFCLK 4-8
reference specifications B-1
register map A-1, A-2
reply
interrupt (RI) 5-28
interrupt mask (RIM) 5-29
MFA (RepMFA) 5-30
REQ/ 4-3
REQ64/ 4-3
request MFA (ReqMFA) 5-30
request status 1-7
reset adapter (RA) 5-27
response sequence 2-7
revision ID (RevID) 5-12
ROMSIZE [1:0] 4-10
RST/ 4-3
RX[9:0] 4-7
RXLOS 4-7
RXNEG 4-8
RXPOS 4-8
S
shared memory 5-31
signaled system error (SSE) 5-9
signaling protocol 2-2
SSRAM Memory 3-9
start-of-frame (SOF) 2-4
status/command register 5-9
STOP/ 4-5
support components
flash ROM 3-10
serial EEPROM 3-10
SSRAM Memory 3-9
system interface 1-6
T
target operation 1-7
target response 2-7
TBC 4-7
TCK_CHIP 4-13
TCK_ICE2 4-13
TDI_CHIP 4-13
TDI_ICE2 4-14
TDO_CHIP 4-13
TDO_ICE2 4-14
test base address (TBAddr) 5-27
TESTRESET/ 4-11
timing diagram
64-bit dual address cycle 6-15
64-bit initiator and 64-bit target (read) 6-14, 6-15
back-to-back (read) 6-11
back-to-back (write) 6-12
burst (read) 6-13
burst (write) 6-14
FC 10-bit and OLC transmit 6-19
FC 10-bit receive 6-18
FC OLC receive 6-17
flash ROM read 6-21, 6-23, 6-25
flash ROM write 6-26
TMS_CHIP 4-13
TMS_ICE1 4-13
TMS_ICE2 4-14
topology
arbitrated loop 2-8
fabric 2-8
point-to-point 2-8
transceiver 1-7
transfer
exchanges 2-2
frames 2-2
sequences 2-2
transmission protocol 2-2
transmitter 1-7
TRDY/ 4-5
TRST_CHIP/ 4-13
TRST_ICE2/ 4-13
TTL interrupt (TTLI) 5-26
TX[9:0] 4-7
TXNEG 4-8
TXPOS 4-8
typical implementation 1-4
SCL 4-12
SDA 4-12
sequences transfer 2-2
SERR/ 4-6, 5-11
SERR/ Enable (SERR) 5-11
Index
IX-3
U
upper layer protocol (ULP) 2-3
V
vendor ID (VenID) 5-9
W
WmlsoTest[2:0] 4-12
WMSEL 4-8
write and invalidate mode (WIM) 5-11
write sequence KEY (WSKEY) 5-25
Z
ZCLK 4-12
ZZ 4-10
IX-4
Index
Customer Feedback
We would appreciate your feedback on this document. Please copy the
following page, add your comments, and fax it to us at the number
shown.
If appropriate, please also fax copies of any marked-up pages from this
document.
Important:
Please include your name, phone number, fax number, and
company address so that we may contact you directly for
clarification or additional information.
Thank you for your help in improving the quality of our documents.
Reader’s Comments
Fax your comments to:
LSI Logic Corporation
Technical Publications
M/S E-198
Fax: 408.433.4333
Please tell us how you rate this document: LSIFC909 Fibre Channel I/O
Processor Technical Manual. Place a check mark in the appropriate
blank for each category.
Excellent Good Average
Completeness of information
Clarity of information
Ease of finding information
Technical content
Usefulness of examples and
illustrations
Overall manual
Fair
Poor
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
What could we do to improve this document?
If you found errors in this document, please specify the error and page
number. If appropriate, please fax a marked-up copy of the page(s).
Please complete the information below so that we may contact you
directly for clarification or additional information.
Name
Telephone
Title
Department
Company Name
Street
City, State, Zip
Customer Feedback
Date
Fax
Mail Stop
U.S. Distributors
by State
A. E.
Avnet Electronics
http://www.hh.avnet.com
B. M.
Bell Microproducts,
Inc. (for HAB’s)
http://www.bellmicro.com
I. E.
Insight Electronics
http://www.insight-electronics.com
W. E.
Wyle Electronics
http://www.wyle.com
Alabama
Daphne
I. E.
Tel: 334.626.6190
Huntsville
A. E.
Tel: 256.837.8700
B. M.
Tel: 256.705.3559
I. E.
Tel: 256.830.1222
W. E. Tel: 800.964.9953
Alaska
A. E.
Tel: 800.332.8638
Arizona
Phoenix
A. E.
Tel: 480.736.7000
B. M.
Tel: 602.267.9551
W. E. Tel: 800.528.4040
Tempe
I. E.
Tel: 480.829.1800
Tucson
A. E.
Tel: 520.742.0515
Arkansas
W. E. Tel: 972.235.9953
California
Agoura Hills
B. M.
Tel: 818.865.0266
Granite Bay
B. M.
Tel: 916.523.7047
Irvine
A. E.
Tel: 949.789.4100
B. M.
Tel: 949.470.2900
I. E.
Tel: 949.727.3291
W. E. Tel: 800.626.9953
Los Angeles
A. E.
Tel: 818.594.0404
W. E. Tel: 800.288.9953
Sacramento
A. E.
Tel: 916.632.4500
W. E. Tel: 800.627.9953
San Diego
A. E.
Tel: 858.385.7500
B. M.
Tel: 858.597.3010
I. E.
Tel: 800.677.6011
W. E. Tel: 800.829.9953
San Jose
A. E.
Tel: 408.435.3500
B. M.
Tel: 408.436.0881
I. E.
Tel: 408.952.7000
Santa Clara
W. E. Tel: 800.866.9953
Woodland Hills
A. E.
Tel: 818.594.0404
Westlake Village
I. E.
Tel: 818.707.2101
Colorado
Denver
A. E.
Tel: 303.790.1662
B. M.
Tel: 303.846.3065
W. E. Tel: 800.933.9953
Englewood
I. E.
Tel: 303.649.1800
Idaho Springs
B. M.
Tel: 303.567.0703
Illinois
North/South
A. E.
Tel: 847.797.7300
Tel: 314.291.5350
Chicago
B. M.
Tel: 847.413.8530
W. E. Tel: 800.853.9953
Schaumburg
I. E.
Tel: 847.885.9700
Connecticut
Cheshire
A. E.
Tel: 203.271.5700
I. E.
Tel: 203.272.5843
Wallingford
W. E. Tel: 800.605.9953
Indiana
Fort Wayne
I. E.
Tel: 219.436.4250
W. E. Tel: 888.358.9953
Indianapolis
A. E.
Tel: 317.575.3500
Delaware
North/South
A. E.
Tel: 800.526.4812
Tel: 800.638.5988
B. M.
Tel: 302.328.8968
W. E. Tel: 856.439.9110
Iowa
W. E. Tel: 612.853.2280
Cedar Rapids
A. E.
Tel: 319.393.0033
Florida
Altamonte Springs
B. M.
Tel: 407.682.1199
I. E.
Tel: 407.834.6310
Boca Raton
I. E.
Tel: 561.997.2540
Bonita Springs
B. M.
Tel: 941.498.6011
Clearwater
I. E.
Tel: 727.524.8850
Fort Lauderdale
A. E.
Tel: 954.484.5482
W. E. Tel: 800.568.9953
Miami
B. M.
Tel: 305.477.6406
Orlando
A. E.
Tel: 407.657.3300
W. E. Tel: 407.740.7450
Tampa
W. E. Tel: 800.395.9953
St. Petersburg
A. E.
Tel: 727.507.5000
Georgia
Atlanta
A. E.
Tel: 770.623.4400
B. M.
Tel: 770.980.4922
W. E. Tel: 800.876.9953
Duluth
I. E.
Tel: 678.584.0812
Hawaii
A. E.
Tel: 800.851.2282
Idaho
A. E.
W. E.
Tel: 801.365.3800
Tel: 801.974.9953
Kansas
W. E. Tel: 303.457.9953
Kansas City
A. E.
Tel: 913.663.7900
Lenexa
I. E.
Tel: 913.492.0408
Kentucky
W. E. Tel: 937.436.9953
Central/Northern/ Western
A. E.
Tel: 800.984.9503
Tel: 800.767.0329
Tel: 800.829.0146
Louisiana
W. E. Tel: 713.854.9953
North/South
A. E.
Tel: 800.231.0253
Tel: 800.231.5775
Maine
A. E.
W. E.
Tel: 800.272.9255
Tel: 781.271.9953
Maryland
Baltimore
A. E.
Tel: 410.720.3400
W. E. Tel: 800.863.9953
Columbia
B. M.
Tel: 800.673.7461
I. E.
Tel: 410.381.3131
Massachusetts
Boston
A. E.
Tel: 978.532.9808
W. E. Tel: 800.444.9953
Burlington
I. E.
Tel: 781.270.9400
Marlborough
B. M.
Tel: 800.673.7459
Woburn
B. M.
Tel: 800.552.4305
Michigan
Brighton
I. E.
Tel: 810.229.7710
Detroit
A. E.
Tel: 734.416.5800
W. E. Tel: 888.318.9953
Clarkston
B. M.
Tel: 877.922.9363
Minnesota
Champlin
B. M.
Tel: 800.557.2566
Eden Prairie
B. M.
Tel: 800.255.1469
Minneapolis
A. E.
Tel: 612.346.3000
W. E. Tel: 800.860.9953
St. Louis Park
I. E.
Tel: 612.525.9999
Mississippi
A. E.
Tel: 800.633.2918
W. E. Tel: 256.830.1119
Missouri
W. E. Tel: 630.620.0969
St. Louis
A. E.
Tel: 314.291.5350
I. E.
Tel: 314.872.2182
Montana
A. E.
Tel: 800.526.1741
W. E. Tel: 801.974.9953
Nebraska
A. E.
Tel: 800.332.4375
W. E. Tel: 303.457.9953
Nevada
Las Vegas
A. E.
Tel: 800.528.8471
W. E. Tel: 702.765.7117
New Hampshire
A. E.
Tel: 800.272.9255
W. E. Tel: 781.271.9953
New Jersey
North/South
A. E.
Tel: 201.515.1641
Tel: 609.222.6400
Mt. Laurel
I. E.
Tel: 856.222.9566
Pine Brook
B. M.
Tel: 973.244.9668
W. E. Tel: 800.862.9953
Parsippany
I. E.
Tel: 973.299.4425
Wayne
W. E. Tel: 973.237.9010
New Mexico
W. E. Tel: 480.804.7000
Albuquerque
A. E.
Tel: 505.293.5119
U.S. Distributors
by State
(Continued)
New York
Hauppauge
I. E.
Tel: 516.761.0960
Long Island
A. E.
Tel: 516.434.7400
W. E. Tel: 800.861.9953
Rochester
A. E.
Tel: 716.475.9130
I. E.
Tel: 716.242.7790
W. E. Tel: 800.319.9953
Smithtown
B. M.
Tel: 800.543.2008
Syracuse
A. E.
Tel: 315.449.4927
North Carolina
Raleigh
A. E.
Tel: 919.859.9159
I. E.
Tel: 919.873.9922
W. E. Tel: 800.560.9953
North Dakota
A. E.
Tel: 800.829.0116
W. E. Tel: 612.853.2280
Ohio
Cleveland
A. E.
Tel: 216.498.1100
W. E. Tel: 800.763.9953
Dayton
A. E.
Tel: 614.888.3313
I. E.
Tel: 937.253.7501
W. E. Tel: 800.575.9953
Strongsville
B. M.
Tel: 440.238.0404
Valley View
I. E.
Tel: 216.520.4333
Oklahoma
W. E. Tel: 972.235.9953
Tulsa
A. E.
Tel: 918.459.6000
I. E.
Tel: 918.665.4664
Oregon
Beaverton
B. M.
Tel: 503.524.1075
I. E.
Tel: 503.644.3300
Portland
A. E.
Tel: 503.526.6200
W. E. Tel: 800.879.9953
Pennsylvania
Mercer
I. E.
Tel: 412.662.2707
Philadelphia
A. E.
Tel: 800.526.4812
B. M.
Tel: 877.351.2355
W. E. Tel: 800.871.9953
Pittsburgh
A. E.
Tel: 412.281.4150
W. E. Tel: 440.248.9996
Rhode Island
A. E.
800.272.9255
W. E. Tel: 781.271.9953
South Carolina
A. E.
Tel: 919.872.0712
W. E. Tel: 919.469.1502
South Dakota
A. E.
Tel: 800.829.0116
W. E. Tel: 612.853.2280
Tennessee
W. E. Tel: 256.830.1119
East/West
A. E.
Tel: 800.241.8182
Tel: 800.633.2918
Texas
Arlington
B. M.
Tel: 817.417.5993
Austin
A. E.
Tel: 512.219.3700
B. M.
Tel: 512.258.0725
I. E.
Tel: 512.719.3090
W. E. Tel: 800.365.9953
Dallas
A. E.
Tel: 214.553.4300
B. M.
Tel: 972.783.4191
W. E. Tel: 800.955.9953
El Paso
A. E.
Tel: 800.526.9238
Houston
A. E.
Tel: 713.781.6100
B. M.
Tel: 713.917.0663
W. E. Tel: 800.888.9953
Richardson
I. E.
Tel: 972.783.0800
Rio Grande Valley
A. E.
Tel: 210.412.2047
Stafford
I. E.
Tel: 281.277.8200
Utah
Centerville
B. M.
Tel: 801.295.3900
Murray
I. E.
Tel: 801.288.9001
Salt Lake City
A. E.
Tel: 801.365.3800
W. E. Tel: 800.477.9953
Vermont
A. E.
Tel: 800.272.9255
W. E. Tel: 716.334.5970
Virginia
A. E.
Tel: 800.638.5988
W. E. Tel: 301.604.8488
Haymarket
B. M.
Tel: 703.754.3399
Springfield
B. M.
Tel: 703.644.9045
Washington
Kirkland
I. E.
Tel: 425.820.8100
Maple Valley
B. M.
Tel: 206.223.0080
Seattle
A. E.
Tel: 425.882.7000
W. E. Tel: 800.248.9953
West Virginia
A. E.
Tel: 800.638.5988
Wisconsin
Milwaukee
A. E.
Tel: 414.513.1500
W. E. Tel: 800.867.9953
Wauwatosa
I. E.
Tel: 414.258.5338
Wyoming
A. E.
Tel: 800.332.9326
W. E. Tel: 801.974.9953
Direct Sales
Representatives by State
(Components and Boards)
E. A.
E. L.
GRP
I. S.
ION
R. A.
SGY
Earle Associates
Electrodyne - UT
Group 2000
Infinity Sales, Inc.
ION Associates, Inc.
Rathsburg Associates, Inc.
Synergy Associates,
Inc.
Arizona
Tempe
E. A.
Tel: 480.921.3305
California
Calabasas
I. S.
Tel: 818.880.6480
Irvine
I. S.
Tel: 714.833.0300
San Diego
E. A.
Tel: 619.278.5441
Illinois
Elmhurst
R. A.
Tel: 630.516.8400
Indiana
Cicero
R. A.
Tel: 317.984.8608
Ligonier
R. A.
Tel: 219.894.3184
Plainfield
R. A.
Tel: 317.838.0360
Massachusetts
Burlington
SGY
Tel: 781.238.0870
Michigan
Byron Center
R. A.
Tel: 616.554.1460
Good Rich
R. A.
Tel: 810.636.6060
Novi
R. A.
Tel: 810.615.4000
North Carolina
Cary
GRP
Tel: 919.481.1530
Ohio
Columbus
R. A.
Tel: 614.457.2242
Dayton
R. A.
Tel: 513.291.4001
Independence
R. A.
Tel: 216.447.8825
Pennsylvania
Somerset
R. A.
Tel: 814.445.6976
Texas
Austin
ION
Tel: 512.794.9006
Arlington
ION
Tel: 817.695.8000
Houston
ION
Tel: 281.376.2000
Utah
Salt Lake City
E. L.
Tel: 801.264.8050
Wisconsin
Muskego
R. A.
Tel: 414.679.8250
Saukville
R. A.
Tel: 414.268.1152
Sales Offices and Design
Resource Centers
LSI Logic Corporation
Corporate Headquarters
1551 McCarthy Blvd
Milpitas CA 95035
Tel: 408.433.8000
Fax: 408.433.8989
Fort Collins
2001 Danfield Court
Fort Collins, CO 80525
Tel: 970.223.5100
Fax: 970.206.5549
New Jersey
Red Bank
125 Half Mile Road
Suite 200
Red Bank, NJ 07701
Tel: 732.933.2656
Fax: 732.933.2643
NORTH AMERICA
Florida
Boca Raton
Cherry Hill - Mint Technology
California
Irvine
2255 Glades Road
Suite 324A
Boca Raton, FL 33431
Tel: 561.989.3236
Fax: 561.989.3237
Tel: 856.489.5530
Fax: 856.489.5531
Georgia
Alpharetta
New York
Fairport
2475 North Winds Parkway
Suite 200
Alpharetta, GA 30004
550 Willowbrook Office Park
Fairport, NY 14450
18301 Von Karman Ave
Suite 900
Irvine, CA 92612
♦ Tel: 949.809.4600
Fax: 949.809.4444
Pleasanton Design Center
5050 Hopyard Road, 3rd Floor
Suite 300
Pleasanton, CA 94588
Tel: 925.730.8800
Fax: 925.730.8700
Tel: 770.753.6146
Fax: 770.753.6147
Illinois
Oakbrook Terrace
215 Longstone Drive
Cherry Hill, NJ 08003
Tel: 716.218.0020
Fax: 716.218.9010
North Carolina
Raleigh
Phase II
4601 Six Forks Road
Suite 528
Raleigh, NC 27609
Tel: 630.954.2234
Fax: 630.954.2235
Tel: 919.785.4520
Fax: 919.783.8909
Kentucky
Bowling Green
Oregon
Beaverton
1551 McCarthy Blvd
Sales Office
M/S C-500
Milpitas, CA 95035
1262 Chestnut Street
Bowling Green, KY 42101
15455 NW Greenbrier Parkway
Suite 235
Beaverton, OR 97006
Fax: 408.954.3353
Maryland
Bethesda
7585 Ronson Road
Suite 100
San Diego, CA 92111
Tel: 858.467.6981
Fax: 858.496.0548
Silicon Valley
♦ Tel: 408.433.8000
Design Center
M/S C-410
Tel: 408.433.8000
Fax: 408.433.7695
Wireless Design Center
11452 El Camino Real
Suite 210
San Diego, CA 92130
Tel: 858.350.5560
Fax: 858.350.0171
Colorado
Boulder
4940 Pearl East Circle
Suite 201
Boulder, CO 80301
♦ Tel: 303.447.3800
Fax: 303.541.0641
Colorado Springs
Tel: 270.793.0010
Fax: 270.793.0040
6903 Rockledge Drive
Suite 230
Bethesda, MD 20817
Tel: 301.897.5800
Fax: 301.897.8389
Massachusetts
Waltham
200 West Street
Waltham, MA 02451
♦ Tel: 781.890.0180
Fax: 781.890.6158
Tel: 503.645.0589
Fax: 503.645.6612
Texas
Austin
9020 Capital of TX Highway North
Building 1
Suite 150
Austin, TX 78759
Tel: 512.388.7294
Fax: 512.388.4171
Plano
500 North Central Expressway
Suite 440
Plano, TX 75074
♦ Tel: 972.244.5000
Burlington - Mint Technology
Fax: 972.244.5001
77 South Bedford Street
Burlington, MA 01803
Houston
Tel: 781.685.3800
Fax: 781.685.3801
20405 State Highway 249
Suite 450
Houston, TX 77070
4420 Arrowswest Drive
Colorado Springs, CO 80907
Minnesota
Minneapolis
Tel: 719.533.7000
Fax: 719.533.7020
8300 Norman Center Drive
Suite 730
Minneapolis, MN 55437
♦ Tel: 612.921.8300
Fax: 612.921.8399
260 Hearst Way
Suite 400
Kanata, ON K2L 3H1
♦ Tel: 613.592.1263
Fax: 613.592.3253
Two Mid American Plaza
Suite 800
Oakbrook Terrace, IL 60181
San Diego
Canada
Ontario
Ottawa
Tel: 281.379.7800
Fax: 281.379.7818
INTERNATIONAL
France
Paris
LSI Logic S.A.
Immeuble Europa
53 bis Avenue de l'Europe
B.P. 139
78148 Velizy-Villacoublay
Cedex, Paris
♦ Tel: 33.1.34.63.13.13
Fax: 33.1.34.63.13.19
Germany
Munich
LSI Logic GmbH
Orleansstrasse 4
81669 Munich
♦ Tel: 49.89.4.58.33.0
Fax: 49.89.4.58.33.108
Stuttgart
Mittlerer Pfad 4
D-70499 Stuttgart
♦ Tel: 49.711.13.96.90
Fax: 49.711.86.61.428
Italy
Milan
LSI Logic S.P.A.
Centro Direzionale Colleoni Palazzo
Orione Ingresso 1
20041 Agrate Brianza, Milano
♦ Tel: 39.039.687371
Fax: 39.039.6057867
Japan
Tokyo
LSI Logic K.K.
Rivage-Shinagawa Bldg. 14F
4-1-8 Kounan
Minato-ku, Tokyo 108-0075
♦ Tel: 81.3.5463.7821
Fax: 81.3.5463.7820
Osaka
Crystal Tower 14F
1-2-27 Shiromi
Chuo-ku, Osaka 540-6014
♦ Tel: 81.6.947.5281
Fax: 81.6.947.5287
Sales Offices and Design
Resource Centers
(Continued)
Korea
Seoul
LSI Logic Corporation of
Korea Ltd
10th Fl., Haesung 1 Bldg.
942, Daechi-dong,
Kangnam-ku, Seoul, 135-283
Tel: 82.2.528.3400
Fax: 82.2.528.2250
The Netherlands
Eindhoven
LSI Logic Europe Ltd
World Trade Center Eindhoven
Building ‘Rijder’
Bogert 26
5612 LZ Eindhoven
Tel: 31.40.265.3580
Fax: 31.40.296.2109
Singapore
Singapore
LSI Logic Pte Ltd
7 Temasek Boulevard
#28-02 Suntec Tower One
Singapore 038987
Tel: 65.334.9061
Fax: 65.334.4749
Sweden
Stockholm
LSI Logic AB
Finlandsgatan 14
164 74 Kista
♦ Tel: 46.8.444.15.00
Fax: 46.8.750.66.47
Taiwan
Taipei
LSI Logic Asia, Inc.
Taiwan Branch
10/F 156 Min Sheng E. Road
Section 3
Taipei, Taiwan R.O.C.
Tel: 886.2.2718.7828
Fax: 886.2.2718.8869
United Kingdom
Bracknell
LSI Logic Europe Ltd
Greenwood House
London Road
Bracknell, Berkshire RG12 2UB
♦ Tel: 44.1344.426544
Fax: 44.1344.481039
♦ Sales Offices with
Design Resource Centers
International Distributors
Australia
New South Wales
Reptechnic Pty Ltd
Hong Kong
Hong Kong
AVT Industrial Ltd
3/36 Bydown Street
Neutral Bay, NSW 2089
Unit 608 Tower 1
Cheung Sha Wan Plaza
833 Cheung Sha Wan Road
Kowloon, Hong Kong
♦ Tel: 612.9953.9844
Fax: 612.9953.9683
Belgium
Acal nv/sa
Lozenberg 4
1932 Zaventem
Tel: 32.2.7205983
Fax: 32.2.7251014
China
Beijing
LSI Logic International
Services Inc.
Beijing Representative
Office
Room 708
Canway Building
66 Nan Li Shi Lu
Xicheng District
Beijing 100045, China
Tel: 86.10.6804.2534 to 38
Fax: 86.10.6804.2521
France
Rungis Cedex
Azzurri Technology France
22 Rue Saarinen
Sillic 274
94578 Rungis Cedex
Tel: 33.1.41806310
Fax: 33.1.41730340
Germany
Haar
EBV Elektronik
Tel: 852.2428.0008
Fax: 852.2401.2105
Serial System (HK) Ltd
2301 Nanyang Plaza
57 Hung To Road, Kwun Tong
Kowloon, Hong Kong
Tel: 852.2995.7538
Fax: 852.2950.0386
India
Bangalore
Spike Technologies India
Private Ltd
951, Vijayalakshmi Complex,
2nd Floor, 24th Main,
J P Nagar II Phase,
Bangalore, India 560078
♦ Tel: 91.80.664.5530
Fax: 91.80.664.9748
Macnica Corporation
Tel: 44.1628.826826
Fax: 44.1628.829730
Hakusan High-Tech Park
1-22-2 Hadusan, Midori-Ku,
Yokohama-City, 226-8505
Milton Keynes
Ingram Micro (UK) Ltd
Tel: 81.45.939.6140
Fax: 81.45.939.6141
The Netherlands
Eindhoven
Acal Nederland b.v.
Japan
Tokyo
Daito Electron
Tel: 49.89.4600980
Fax: 49.89.46009840
Munich
Avnet Emg GmbH
Global Electronics
Corporation
Stahlgruberring 12
81829 Munich
Nichibei Time24 Bldg. 35 Tansu-cho
Shinjuku-ku, Tokyo 162-0833
Tel: 49.89.45110102
Fax: 49.89.42.27.75
Tel: 81.3.3260.1411
Fax: 81.3.3260.7100
Technical Center
Tel: 81.471.43.8200
Tel: 81.3.5778.8662
Fax: 81.3.5778.8669
Shinki Electronics
Myuru Daikanyama 3F
3-7-3 Ebisu Minami
Shibuya-ku, Tokyo 150-0022
Tel: 81.3.3760.3110
Fax: 81.3.3760.3101
Tel: 44.1908.260422
Swindon
EBV Elektronik
Tel: 31.40.2.502602
Fax: 31.40.2.510255
12 Interface Business Park
Bincknoll Lane
Wootton Bassett,
Swindon, Wiltshire SN4 8SY
Switzerland
Brugg
LSI Logic Sulzer AG
Mattenstrasse 6a
CH 2555 Brugg
14F, No. 145,
Sec. 2, Chien Kuo N. Road
Taipei, Taiwan, R.O.C.
Tel: 886.2.2516.7303
Fax: 886.2.2505.7391
Lumax International
Corporation, Ltd
7th Fl., 52, Sec. 3
Nan-Kang Road
Taipei, Taiwan, R.O.C.
Tel: 886.2.2788.3656
Fax: 886.2.2788.3568
Prospect Technology
Corporation, Ltd
4Fl., No. 34, Chu Luen Street
Taipei, Taiwan, R.O.C.
Tel: 886.2.2721.9533
Fax: 886.2.2773.3756
Marubeni Solutions
1-26-20 Higashi
Shibuya-ku, Tokyo 150-0001
Garamonde Drive
Wymbush
Milton Keynes
Buckinghamshire MK8 8DF
Beatrix de Rijkweg 8
5657 EG Eindhoven
Taiwan
Taipei
Avnet-Mercuries
Corporation, Ltd
Tel: 81.3.3264.0326
Fax: 81.3.3261.3984
Tel: 49.2957.79.1692
Fax: 49.2957.79.9341
16 Grove Park Business Estate
Waltham Road
White Waltham
Maidenhead, Berkshire SL6 3LW
11 Rozanis Street
P.O. Box 39300
Tel Aviv 61392
Tel: 972.3.6458777
Fax: 972.3.6458666
United Kingdom
Maidenhead
Azzurri Technology Ltd
Tel: 81.45.474.9037
Fax: 81.45.474.9065
Tel: 41.32.3743232
Fax: 41.32.3743233
Sogo Kojimachi No.3 Bldg
1-6 Kojimachi
Chiyoda-ku, Tokyo 102-8730
Graf-Zepplin-Str 14
D-33181 Wuennenberg-Haaren
2-15-10 Shin Yokohama
Kohoku-ku
Yokohama-City, 222-8580
Israel
Tel Aviv
Eastronics Ltd
Hans-Pinsel Str. 4
D-85540 Haar
Wuennenberg-Haaren
Peacock AG
Yokohama-City
Innotech
Wintech Microeletronics
Co., Ltd
7F., No. 34, Sec. 3, Pateh Road
Taipei, Taiwan, R.O.C.
Tel: 886.2.2579.5858
Fax: 886.2.2570.3123
Tel: 44.1793.849933
Fax: 44.1793.859555
♦ Sales Offices with
Design Resource Centers