NB100ELT23L 3.3VDual Differential LVPECL to LVTTL Translator The NB100ELT23L is a dual differential LVPECL to LVTTL translator. Because LVPECL (Positive ECL) levels are used, only +3.3 V and ground are required. The small outline 8-lead package and the dual gate design of the ELT23L makes it ideal for applications which require the translation of a clock and a data signal. The ELT23L is available in only the ECL 100K standard. Since there are no LVPECL outputs or an external VBB reference, the ELT23L does not require both ECL standard versions. The LVPECL inputs are differential. Therefore, the NB100ELT23L can accept any standard differential LVPECL input referenced from a VCC of +3.3 V. • • • • • • http://onsemi.com MARKING DIAGRAMS* 8 8 1 2.1 ns Typical Propagation Delay KT23L ALYW SO−8 D SUFFIX CASE 751 1 8 Maximum Operating Frequency > 160 MHz 24 mA LVTTL Outputs TSSOP−8 DT SUFFIX CASE 948R 8 Operating Range: VCC = 3.0 V to 3.6 V with GND = 0 V 1 K23L ALYW 1 Open Input Default State Q Output Will Default LOW with Inputs Open or at GND A L Y W = Assembly Location = Wafer Lot = Year = Work Week *For additional information, see Application Note AND8002/D ORDERING INFORMATION Device Package Shipping† NB100ELT23LD SO−8 98 Units/Rail NB100ELT23LDR2 SO−8 2500 Tape & Reel TSSOP−8 100 Units/Rail NB100ELT23LDT NB100ELT23LDTR2 TSSOP−8 2500 Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Semiconductor Components Industries, LLC, 2003 October, 2003 − Rev. 2 1 Publication Order Number: NB100ELT23L/D NB100ELT23L D0 1 8 VCC PIN DESCRIPTION D0 2 7 LVPECL D1 D1 Q0 LVTTL 3 6 4 5 PIN FUNCTION Q0, Q1 LVTTL Outputs D0**, D1** D0**, D1** Differential LVPECL Inputs VCC Positive Supply GND Ground Q1 ** Pins will default to VCC/2 when left open. GND Figure 1. 8−Lead Pinout (Top View) and Logic Diagram ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 50 k Internal Input Pullup Resistor 50 k ESD Protection Human Body Model Machine Model Charged Device Model > 1.2 kV > 150 V > 2 kV Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Flammability Rating Level 1 Oxygen Index: 28 to 34 UL 94 V−0 @ 1.25 in Transistor Count 91 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. MAXIMUM RATINGS (Note 2) Parameter Symbol Condition 1 Condition 2 Rating Units 3.8 V 38 3.8 V 50 100 mA mA VCC Power Supply GND = 0 V VI Input Voltage GND = 0 V Iout Output Current Continuous Surge TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C JA Thermal Resistance (Junction−to−Ambient) 0 LFPM 500 LFPM 8 SOIC 8 SOIC 190 130 °C/W °C/W JC Thermal Resistance (Junction−to−Case) std bd 8 SOIC 41 to 44 °C/W JA Thermal Resistance (Junction−to−Ambient) 0 LFPM 500 LFPM 8 TSSOP 8 TSSOP 185 140 °C/W °C/W JC Thermal Resistance (Junction−to−Case) std bd 8 TSSOP 41 to 44 °C/W Tsol Wave Solder <2 to 3 sec @ 248°C 265 °C 2. Maximum Ratings are those values beyond which device damage may occur. http://onsemi.com 2 VI VCC NB100ELT23L PECL DC CHARACTERISTICS VCC = 3.3 V, GND = 0 V (Note 3) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit ICCH Power Supply Current (Outputs set to HIGH) 10 14 20 10 15 20 10 15 20 mA ICCL Power Supply Current (Outputs set to LOW) 15 19 25 15 19 25 15 20 25 mA VIH Input HIGH Voltage 2075 2420 2075 2420 2075 2420 mV VIL Input LOW Voltage 1355 1675 1355 1675 1355 1675 mV VIHCMR Input HIGH Voltage Common Mode Range (Note 4) 2.0 3.3 2.0 3.3 2.0 3.3 V IIH Input HIGH Current 150 A IIL Input LOW Current 150 0.5 150 0.5 A 0.5 NOTE: Circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 3. All values vary 1:1 with VCC. 4. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. TTL DC CHARACTERISTICS VCC = 3.3 V, GND = 0.0 V, TA = −40°C to 85°C Symbol Characteristic Condition VOH Output HIGH Voltage IOH = −3.0 mA VOL Output LOW Voltage IOL = 24 mA IOS Output Short Circuit Current Min Typ Max 2.4 Unit V −180 0.5 V −50 mA NOTE: Circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. AC CHARACTERISTICS VCC = 3.3 V 5%, GND = 0.0 V (Note 5) −40°C Symbol Min Characteristic fmax Maximum Frequency 160 tPLH, tPHL Propagation Delay to Output Differential (Note 6) CL = 20 pF 1.5 tSK+ + tSK− − tSKPP Output−to−Output Skew++ Output−to−Output Skew− − Part−to−Part Skew (Note 7) tJITTER Random Clock Jitter (RMS) VPP Input Voltage Swing (Differential Configuration) tr tf Output Rise/Fall Times (1.0 V − 2.0 V) Typ 25°C Max Min Typ Max 160 Min Typ Max 160 Unit MHz ns 2.1 2.75 1.5 2.1 60 25 500 150 CL = 20 pF Q 85°C 1.5 <1 800 1200 150 1300 1000 500 300 0.2 <1 800 1200 150 1300 1000 500 300 5. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 500 to GND, CL = 20 pF. 6. Reference (VCC = 3.3 V ± 5%; GND = 0 V) 7. Skews are measured between outputs under identical conditions. http://onsemi.com 3 2.1 60 25 500 0.2 500 300 2.75 2.75 60 25 500 ps 0.2 <1 ps 800 1200 mV 1300 1000 ps NB100ELT23L APPLICATION TTL RECEIVER CHARACTERISTIC TEST *CL includes fixture capacitance CL * RL AC TEST LOAD GND Figure 2. TTL Output Loading Used for Device Evaluation Resource Reference of Application Notes AN1404 − ECLinPS Circuit Performance at Non−Standard VIH Levels AN1405 − ECL Clock Distribution Techniques AN1406 − Designing with PECL (ECL at +5.0 V) AN1503 − ECLinPS I/O SPICE Modeling Kit AN1504 − Metastability and the ECLinPS Family AN1560 − Low Voltage ECLinPS SPICE Modeling Kit AN1568 − Interfacing Between LVDS and ECL AN1596 − ECLinPS Lite Translator ELT Family SPICE I/O Model Kit AN1650 − Using Wire−OR Ties in ECLinPS Designs AN1672 − The ECL Translator Guide AND8001 − Odd Number Counters Design AND8002 − Marking and Date Codes AND8020 − Termination of ECL Logic Devices For an updated list of Application Notes, please see our website at http://onsemi.com. http://onsemi.com 4 NB100ELT23L PACKAGE DIMENSIONS SO−8 D SUFFIX PLASTIC SOIC PACKAGE CASE 751−07 ISSUE AA −X− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDAARD IS 751−07 A 8 5 0.25 (0.010) S B 1 M Y M 4 K −Y− G C N X 45 SEATING PLANE −Z− 0.10 (0.004) H D 0.25 (0.010) M Z Y S X M S http://onsemi.com 5 J DIM A B C D G H J K M N S MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0 8 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 8 0.010 0.020 0.228 0.244 NB100ELT23L PACKAGE DIMENSIONS TSSOP−8 DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948R−02 ISSUE A 8x 0.15 (0.006) T U K REF 0.10 (0.004) S 2X L/2 8 1 PIN 1 IDENT S T U V S NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 6. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. S 5 0.25 (0.010) B −U− L 0.15 (0.006) T U M M 4 A −V− F DETAIL E C 0.10 (0.004) −T− SEATING PLANE D −W− G DETAIL E DIM A B C D F G K L M MILLIMETERS MIN MAX 2.90 3.10 2.90 3.10 0.80 1.10 0.05 0.15 0.40 0.70 0.65 BSC 0.25 0.40 4.90 BSC 0 6 INCHES MIN MAX 0.114 0.122 0.114 0.122 0.031 0.043 0.002 0.006 0.016 0.028 0.026 BSC 0.010 0.016 0.193 BSC 0 6 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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