Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET DESCRIPTION PIP3103-T QUICK REFERENCE DATA Monolithic temperature and overload protected logic level power MOSFET in TOPFET2 technology assembled in a 3 pin surface mount plastic package. SYMBOL PARAMETER MAX. UNIT VDS Continuous drain source voltage 50 V ID Continuous drain current 0.7 A APPLICATIONS PD Total power dissipation 1.8 W General purpose switch for driving lamps motors solenoids heaters Tj Continuous junction temperature 150 ˚C RDS(ON) Drain-source on-state resistance 200 mΩ FEATURES TrenchMOS output stage Current limiting Overload protection Overtemperature protection Protection latched reset by input 5 V logic compatible input level Control of output stage and supply of overload protection circuits derived from input Low operating input current permits direct drive by micro-controller ESD protection on all pins Overvoltage clamping for turn off of inductive loads FUNCTIONAL BLOCK DIAGRAM DRAIN O/V CLAMP POWER INPUT MOSFET RIG LOGIC AND PROTECTION SOURCE Fig.1. Elements of the TOPFET. PINNING - SOT223 PIN PIN CONFIGURATION DESCRIPTION 1 input 2 drain 3 source 4 drain (tab) June 2001 SYMBOL 4 D TOPFET I 2 1 1 3 P S Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET PIP3103-T LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL VDS ID II IIRM PD Tstg Tj PARAMETER CONDITIONS 1 Continuous drain source voltage Continuous drain current2 Continuous input current Non-repetitive peak input current Total power dissipation Storage temperature Continuous junction temperature clamping tp ≤ 1 ms Ta = 25˚C normal operation3 MIN. MAX. UNIT -55 - 50 self limiting 3 10 1.8 150 150 V A mA mA W ˚C ˚C ESD LIMITING VALUE SYMBOL PARAMETER CONDITIONS VC Electrostatic discharge capacitor voltage Human body model; C = 250 pF; R = 1.5 kΩ MIN. MAX. UNIT - 2 kV OVERVOLTAGE CLAMPING LIMITING VALUES At a drain source voltage above 50 V the power MOSFET is actively turned on to clamp overvoltage transients. SYMBOL PARAMETER CONDITIONS EDSM Non-repetitive clamping energy EDRM Repetitive clamping energy Ta ≤ 25˚C; IDM < ID(lim); inductive load Tsp ≤ 125˚C; IDM = 50 mA; f = 250 Hz MIN. MAX. UNIT - 100 mJ - 5 mJ OVERLOAD PROTECTION LIMITING VALUES With the protection supply provided via the input pin, TOPFET can protect itself from short circuit loads. Overload protection operates by means of drain current limiting and activating the overtemperature protection. SYMBOL PARAMETER REQUIRED CONDITION VDDP Protected drain source supply voltage VIS ≥ 4 V MIN. MAX. UNIT - 35 V THERMAL CHARACTERISTICS SYMBOL PARAMETER Rth j-sp Rth j-b Rth j-a Thermal resistance Junction to solder point Junction to board4 Junction to ambient CONDITIONS Mounted on any PCB Mounted on PCB of fig. 22 MIN. TYP. MAX. UNIT - 12 40 - 18 70 K/W K/W K/W 1 Prior to the onset of overvoltage clamping. For voltages above this value, safe operation is limited by the overvoltage clamping energy. 2 Refer to OVERLOAD PROTECTION CHARACTERISTICS. 3 Not in an overload condition with drain current limiting. 4 Temperature measured 1.3 mm from tab. June 2001 2 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET PIP3103-T OUTPUT CHARACTERISTICS Limits are for -40˚C ≤ Tmb ≤ 150˚C; typicals are for Tmb = 25 ˚C unless otherwise specified SYMBOL V(CL)DSS IDSS PARAMETER CONDITIONS Off-state VIS = 0 V Drain-source clamping voltage Drain source leakage current MIN. TYP. MAX. UNIT ID = 10 mA 50 - - V ID = 200 mA; tp ≤ 300 µs; δ ≤ 0.01 50 60 70 V - 0.1 100 10 µA µA - 150 380 200 mΩ mΩ MIN. TYP. MAX. UNIT Tmb = 25˚C 0.6 1.1 1.6 2.4 2.1 V V VDS = 40 V Tmb = 25 ˚C RDS(ON) On-state VIS ≥ 4 V; tp ≤ 300 µs; δ ≤ 0.01 Drain-source resistance ID = 100 mA Tmb = 25 ˚C INPUT CHARACTERISTICS The supply for the logic and overload protection is taken from the input. Limits are for -40˚C ≤ Tmb ≤ 150˚C; typicals are for Tmb = 25˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS VIS(TO) Input threshold voltage VDS = 5 V; ID = 1 mA IIS Input supply current normal operation; VIS = 5 V VIS = 4 V 100 80 220 195 400 330 µA µA IISL Input supply current protection latched; VIS = 5 V VIS = 3 V 200 130 400 250 650 430 µA µA VISR Protection reset voltage1 reset time tr ≥ 100 µs 1.5 2 2.9 V tlr Latch reset time VIS1 = 5 V, VIS2 < 1 V 10 40 100 µs V(CL)IS Input clamping voltage II = 1.5 mA 5.5 - 8.5 V RIG Input series resistance2 to gate of power MOSFET - 33 - kΩ Tmb = 25˚C 1 The input voltage below which the overload protection circuits will be reset. 2 Not directly measureable from device terminals. June 2001 3 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET PIP3103-T OVERLOAD PROTECTION CHARACTERISTICS TOPFET switches off to protect itself when one of the overload thresholds is exceeded. It remains latched off until reset by the input. SYMBOL PARAMETER CONDITIONS Overload protection -40˚C ≤ Tj ≤ 150˚C Drain current limiting VIS = 5 V VIS = 4.5 V VIS = 4 V to 5.5 V Short circuit load protection VIS = 5 V PD(TO) Overload power threshold TDSC ID Tj(TO) MIN. TYP. MAX. UNIT 0.8 0.7 0.6 1.3 - 1.7 1.8 A A A for protection to operate - 17 - W Characteristic time which determines trip time1 - 1.6 - ms Overtemperature protection from ID ≥ 280 mA or VDS ≥ 100 mV 150 165 - ˚C Threshold junction temperature VIS = 4 V to 5.5 V SWITCHING CHARACTERISTICS Ta = 25˚C; resistive load RL = 50 Ω; adjust VDD to obtain ID = 250 mA; refer to test circuit and waveforms SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT td on Turn-on delay time VIS: 0 V ⇒ 5 V - 5 12 µs tr Rise time - 11 30 µs td off Turn-off delay time - 25 65 µs tf Fall time - 14 35 µs VIS: 5 V ⇒ 0 V REVERSE DIODE LIMITING VALUE SYMBOL PARAMETER CONDITIONS IS Continuous forward current Tmb ≤ 25 ˚C; VIS = 0 V MIN. MAX. UNIT - 2 A REVERSE DIODE CHARACTERISTICS Limits are for -40˚C ≤ Tmb ≤ 150˚C; typicals are for Tmb = 25˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VSDO Forward voltage IS = 2 A; VIS = 0 V; tp = 300 µs - 0.83 1.1 V trr Reverse recovery time not applicable2 - - - - 1 Trip time td sc varies with overload dissipation PD according to the formula td sc ≈ TDSC / [ PD / PD(TO) - 1 ]. 2 The reverse diode of this type is not intended for applications requiring fast reverse recovery. June 2001 4 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET PIP3103-T Normalised Power Derating, PD (%) a 2 100 Normalised RDS(ON) = f(Tj) 90 80 1.5 70 60 50 1 40 30 20 0.5 10 0 0 25 50 75 100 125 Mounting Base temperature, Tmb (C) 150 0 -50 Fig.2. Normalised limiting power dissipation. PD% = 100⋅PD/PD(25˚C) = f(Tmb) 2.0 0 50 Tj / C 100 150 Fig.5. Normalised drain-source on-state resistance. a = RDS(ON)/RDS(ON)25˚C = f(Tj); ID = 100 mA; VIS = 4.4 V ID / A 350 CURRENT LIMITING OCCURS WITHIN SHADED REGION RDS(ON) / mOhm 300 1.5 TYP. 250 MAX. 200 1.0 150 TYP. 100 0.5 50 0 0 0 20 40 60 80 Tamb / ˚ C 100 120 140 Fig.3. Continuous drain current. ID = f(Tamb); condition: VIS = 5 V 2 1 2 3 4 VIS / V 5 6 7 8 Fig.6. Typical on-state resistance, Tj = 25˚C. RDS(ON) = f(VIS); conditions: ID = 100 mA, tp = 300 µs ID / A 2 ID / A VIS / V = 1.5 1.5 7 6 5 4 1 1 0.5 0 0 0.5 0 4 8 12 16 VDS / V 20 24 28 0 32 1 2 3 VIS / V 4 5 6 7 Fig.7. Typical transfer characteristics, Tj = 25˚C. ID = f(VIS); conditions: VDS = 10 V, tp = 300 µs Fig.4. Typical on-state characteristics, Tj = 25˚C. ID = f(VDS); parameter VIS; tp = 300 µs June 2001 0 5 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET PIP3103-T Tj(TO) / ˚C 200 4 VIS(TO) / V 195 DATA BELOW 4V IS FOR INFORMATION ONLY. 190 185 3 MAX. ALL SPEC. VALUES ARE FOR NORMAL OPERATION AT 4V AND ABOVE. 180 2 175 TYP. 1 170 MIN. 165 160 2 3 4 5 VIS / V 6 7 0 -50 8 50 Tj / ˚C 100 150 Fig.11. Input threshold voltage. VIS(TO) = f(Tj); conditions: ID = 1 mA; VDS = 5 V Fig.8. Typical overtemperature protection threshold. Tj(TO) = f(VIS) 1 0 Ii / mA 10 II / mA 9 8 7 6 0.5 Iisl 5 4 3 2 Iis 1 0 0 1 2 3 4 Vis / V 5 6 7 0 8 Fig.9. Typical DC input characteristics, Tj = 25˚C. IIS & IISL = f(VIS); normal operation & protection latched 500 1600 4 VIS / V 6 8 10 1s / tdsc 1400 5V 400 1200 VIS / V = 1000 300 3V 800 5V 200 600 4V 400 = IIS 100 200 = IISL 0 0 50 Tj / ˚C 100 150 0 5 10 15 20 25 30 35 40 45 50 Pd / W Fig.10. Typical DC input currents. IIS & IISL = f(Tj); parameter VIS; normal & latched June 2001 2 Fig.12. Typical input clamping characteristic. II = f(VIS); normal operation, Tj = 25˚C. IIS & IISL / uA 0 -50 0 Fig.13. Typical overload protection response time. 1 / tdsc = f(PD); VIS ≥ 4 V, Tj ≤ 125˚C. 6 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET 3 PIP3103-T VISR / V VIS & VDS / V 15 2.8 2.6 VDS 2.4 10 2.2 2 VIS 1.8 5 1.6 1.4 1.2 0 1 -50 -25 0 25 50 Tj / ˚C 75 100 125 Fig.14. Typical Protection reset voltage. VISR = f(Tj); tlr = 100 µs. 400 -20 -40 150 0 20 40 60 80 time / us 100 120 140 160 Fig.17. Typical switching waveforms, resistive load . RL = 50 Ω; adjust VDD to obtain ID = 250 mA; Tj = 25˚C ID / mA 10 uA IDSS 300 1 uA 200 TYP. 100 nA 100 0 56 58 60 62 VDS / V 64 66 10 nA 68 Fig.15. Overvoltage clamping characteristic, 25˚C. ID = f(VDS); conditions: VIS = 0 V; tp ≤ 300 µs -50 0 50 Tj / ˚C 100 150 Fig.18. Typical drain source leakage current IDSS = f(Tj); conditions: VDS = 40 V; VIS = 0 V. VDD RL VDS TOPFET D I D.U.T. P VIS measure S 0V Fig.16. Test circuit for resistive load switching times. VIS = 5 V June 2001 7 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET 1E+02 PIP3103-T Zth j-amb / (K / W) D= 0.5 1E+01 1 0.2 0.1 0.05 0.02 PD tp D= tp T 1E-01 T 0 1E-02 1E-07 1E-05 1E-03 t/s 1E-01 1E+01 t 1E+03 Fig.19. Transient thermal impedance, mounted on SOT223 PCB. Zth j-a = f(t); parameter D = tp / T June 2001 8 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET PIP3103-T MECHANICAL DATA Plastic surface mounted package; collector pad for good heat transfer; 4 leads D SOT223 E B A X c y HE v M A b1 4 Q A A1 1 2 3 Lp bp e1 w M B detail X e 0 2 4 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 bp b1 c D E e e1 HE Lp Q v w y mm 1.8 1.5 0.10 0.01 0.80 0.60 3.1 2.9 0.32 0.22 6.7 6.3 3.7 3.3 4.6 2.3 7.3 6.7 1.1 0.7 0.95 0.85 0.2 0.1 0.1 OUTLINE VERSION REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 96-11-11 97-02-28 SOT223 Fig.20. SOT223 surface mounting package3. 3 For further information, refer to surface mounting instructions for SOT223 envelope. Epoxy meets UL94 V0 at 1/8". Net Mass: 0.11 g June 2001 9 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET PIP3103-T MOUNTING INSTRUCTIONS PRINTED CIRCUIT BOARD Dimensions in mm. Dimensions in mm. 3.8 36 min 1.5 min 18 60 1.5 min 4.5 4.6 9 2.3 6.3 10 (3x) 1.5 min 7 4.6 15 50 Fig.22. PCB for thermal resistance and power rating. PCB: FR4 epoxy glass (1.6 mm thick), copper laminate (35 µm thick). Fig.21. Soldering pattern for surface mounting. June 2001 10 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET PIP3103-T DEFINITIONS DATA SHEET STATUS DATA SHEET STATUS4 PRODUCT STATUS5 DEFINITIONS Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in ordere to improve the design and supply the best possible product Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. Philips Electronics N.V. 2001 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 4 Please consult the most recently issued datasheet before initiating or completing a design. 5 The product status of the device(s) described in this datasheet may have changed since this datasheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. June 2001 11 Rev 1.000