Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET DESCRIPTION BUK110-50DL QUICK REFERENCE DATA Monolithic temperature and overload protected logic level power MOSFET in a 3 pin plastic surface mount envelope, intended as a general purpose switch for automotive systems and other applications. SYMBOL PARAMETER MAX. UNIT VDS ID PD Tj RDS(ON) Continuous drain source voltage Continuous drain current Total power dissipation Continuous junction temperature Drain-source on-state resistance 50 45 125 150 35 V A W ˚C mΩ APPLICATIONS IISL Input supply current 650 µA VIS = 5 V General controller for driving lamps motors solenoids heaters FEATURES Vertical power DMOS output stage Low on-state resistance Overload protection against over temperature Overload protection against short circuit load Latched overload protection reset by input 5 V logic compatible input level Control of power MOSFET and supply of overload protection circuits derived from input Lower operating input current permits direct drive by micro-controller ESD protection on input pin Overvoltage clamping for turn off of inductive loads FUNCTIONAL BLOCK DIAGRAM DRAIN O/V CLAMP POWER INPUT MOSFET RIG LOGIC AND PROTECTION SOURCE Fig.1. Elements of the TOPFET. PINNING - SOT404 PIN PIN CONFIGURATION DESCRIPTION mb 1 input 2 drain 3 source mb SYMBOL drain June 1996 D TOPFET I P 2 1 S 3 1 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET BUK110-50DL LIMITING VALUES Limiting values in accordance with the Absolute Maximum Rating System (IEC 134) SYMBOL PARAMETER CONDITIONS 1 VDS VIS ID ID IDRM PD Tstg Tj Continuous drain source voltage Continuous input voltage Continuous drain current Continuous drain current Repetitive peak on-state drain current Total power dissipation Storage temperature Continuous junction temperature2 Tmb ≤ 25 ˚C; VIS = 5 V Tmb ≤ 100 ˚C; VIS = 5 V Tmb ≤ 25 ˚C; VIS = 5 V Tmb ≤ 25 ˚C normal operation Tsold Lead temperature during soldering MIN. MAX. UNIT 0 -55 - 50 6 45 28 180 125 150 150 V V A A A W ˚C ˚C - 250 ˚C OVERLOAD PROTECTION LIMITING VALUES With the protection supply provided via the input pin, TOPFET can protect itself from two types of overload. SYMBOL VISP PARAMETER CONDITIONS 3 Protection supply voltage MIN. MAX. UNIT 4 - V - 50 V VIS = 5 V - 16 V Tmb = 25 ˚C - 2.1 kW for valid protection Over temperature protection VDDP(T) Protected drain source supply voltage VIS = 5 V 4 VDDP(P) PDSM Short circuit load protection Protected drain source supply voltage5 Instantaneous overload dissipation OVERVOLTAGE CLAMPING LIMITING VALUES At a drain source voltage above 50 V the power MOSFET is actively turned on to clamp overvoltage transients. SYMBOL PARAMETER CONDITIONS IDROM EDSM Repetitive peak clamping current Non-repetitive clamping energy EDRM Repetitive clamping energy VIS = 0 V Tmb ≤ 25 ˚C; IDM = 25 A; VDD ≤ 20 V; inductive load Tmb ≤ 85 ˚C; IDM = 16 A; VDD ≤ 20 V; f = 250 Hz MIN. MAX. UNIT - 45 1 A J - 80 mJ MIN. MAX. UNIT - 2 kV ESD LIMITING VALUE SYMBOL PARAMETER CONDITIONS VC Electrostatic discharge capacitor voltage Human body model; C = 250 pF; R = 1.5 kΩ 1 Prior to the onset of overvoltage clamping. For voltages above this value, safe operation is limited by the overvoltage clamping energy. 2 A higher Tj is allowed as an overload condition but at the threshold Tj(TO) the over temperature trip operates to protect the switch. 3 The input voltage for which the overload protection circuits are functional. 4 For further information, refer to OVERLOAD PROTECTION CHARACTERISTICS. 5 The short circuit load protection is able to save the device providing the instantaneous on-state dissipation is less than the limiting value for PDSM, which is always the case when VDS is less than VDDP(P) maximum. June 1996 2 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET BUK110-50DL THERMAL CHARACTERISTICS SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT - 0.8 1 K/W - 50 - K/W MIN. TYP. MAX. UNIT 50 - - V - - 70 V - 0.5 1 10 30 10 20 100 35 µA µA µA mΩ Thermal resistance Rth j-mb Junction to mounting base Rth j-a Junction to ambient minimum footprint FR4 PCB STATIC CHARACTERISTICS Tmb = 25 ˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS V(CL)DSS Drain-source clamping voltage VIS = 0 V; ID = 10 mA V(CL)DSS Drain-source clamping voltage IDSS IDSS IDSS RDS(ON) VIS = 0 V; IDM = 4 A; tp ≤ 300 µs; δ ≤ 0.01 Zero input voltage drain current VDS = 12 V; VIS = 0 V Zero input voltage drain current VDS = 50 V; VIS = 0 V Zero input voltage drain current VDS = 40 V; VIS = 0 V; Tj = 125 ˚C Drain-source on-state VIS = 5 V; IDM = 25 A; tp ≤ 300 µs; resistance1 δ ≤ 0.01 OVERLOAD PROTECTION CHARACTERISTICS TOPFET switches off when one of the overload thresholds is reached. It remains latched off until reset by the input. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT EDS(TO) td sc ID(SC) Short circuit load protection Overload threshold energy Response time Drain current3 Tmb = 25 ˚C; L ≤ 10 µH; RL = 10 mΩ VDD = 13 V; VIS = 5 V VDD = 13 V; VIS = 5 V VDD = 13 V; VIS = 5 V - 1.1 0.8 75 - J ms A IDM(SC) Peak drain current4 VIS = 5 V; VDD = 13 V - 200 - A Tj(TO) Over temperature protection Threshold junction temperature VIS = 5 V; from ID ≥ 2 A5 150 - - ˚C MIN. TYP. MAX. UNIT 17 28 - S 2 TRANSFER CHARACTERISTIC Tmb = 25 ˚C SYMBOL PARAMETER CONDITIONS gfs Forward transconductance VDS = 10 V; IDM = 25 A tp ≤ 300 µs; δ ≤ 0.01 1 Continuous input voltage. The specified pulse width is for the drain current. 2 Refer to OVERLOAD PROTECTION LIMITING VALUES. 3 Continuous drain-source supply voltage. Pulsed input voltage. 4 Continuous input voltage. Momentary short circuit load connection. (The higher peak current is due to the effect of capacitance Cgd). 5 The over temperature protection feature requires a minimum on-state drain source voltage for correct operation. The specified minimum ID ensures this condition. June 1996 3 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET BUK110-50DL INPUT CHARACTERISTICS Tmb = 25 ˚C unless otherwise specified. The supply for the logic and overload protection is taken from the input. SYMBOL PARAMETER CONDITIONS VIS(TO) IIS Input threshold voltage Input supply current VDS = 5 V; ID = 1 mA normal operation; VISR Protection reset voltage1 IISL Input supply current protection latched; V(BR)IS RIG Input breakdown voltage Input series resistance to gate of power MOSFET II = 10 mA VIS = 5 V VIS = 4 V Tj = 25 ˚C Tj = 150 ˚C VIS = 5 V VIS = 3.5 V Tj = 25 ˚C Tj = 150 ˚C MIN. TYP. MAX. UNIT 1.0 100 2.0 1.0 1.5 200 160 2.6 - 2.0 350 270 3.5 - V µA µA V 6 - 330 240 33 50 650 430 - µA µA V kΩ kΩ MIN. TYP. MAX. UNIT SWITCHING CHARACTERISTICS Tmb = 25 ˚C. RI = 50 Ω . Refer to waveform figure and test circuit. SYMBOL PARAMETER CONDITIONS td on Turn-on delay time VDD = 13 V; VIS = 5 V - 30 - µs tr Rise time resistive load RL = 2.1 Ω - 150 - µs td off Turn-off delay time VDD = 13 V; VIS = 0 V - 120 - µs tf Fall time resistive load RL = 2.1 Ω - 120 - µs REVERSE DIODE LIMITING VALUE SYMBOL PARAMETER CONDITIONS IS Continuous forward current Tmb ≤ 25 ˚C; VIS = 0 V MIN. MAX. UNIT - 45 A REVERSE DIODE CHARACTERISTICS Tmb = 25 ˚C SYMBOL PARAMETER CONDITIONS VSDO Forward voltage IS = 45 A; VIS = 0 V; tp = 300 µs trr Reverse recovery time MIN. TYP. MAX. UNIT - 1.0 1.5 V not applicable - - - - MIN. TYP. MAX. UNIT - 2.5 - nH - 7.5 - nH 2 ENVELOPE CHARACTERISTICS SYMBOL PARAMETER CONDITIONS Ld Internal drain inductance Ls Internal source inductance Measured from upper edge of tab to centre of die Measured from source lead soldering point to source bond pad 1 The input voltage below which the overload protection circuits will be reset. 2 The reverse diode of this type is not intended for applications requiring fast reverse recovery. June 1996 4 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET 120 BUK110-50DL Normalised Power Derating PD% 10 BUK110-50DL Zth / (K/W) 110 100 90 1 D= 80 0.5 70 60 50 0.2 0.1 0.05 0.1 0.02 40 30 0.01 20 10 0 0 20 40 60 80 100 Tmb / C 120 Fig.2. Normalised limiting power dissipation. PD% = 100⋅PD/PD(25 ˚C) = f(Tmb) 120 t 1E-03 t/s 1E-01 1E+01 ID / A 80 110 BUK110-50DL 6 VIS / V = 70 100 90 5.5 60 5 80 50 70 4.5 60 50 40 4 30 40 3.5 30 20 20 10 10 3 0 0 20 40 60 80 Tmb / C 100 120 0 140 0 ID & IDM / A BUK110-50DL 80 10 60 VD 4 4.5 5.5 5 6 O S( VIS / V = 3.5 D RD 5 BUK110-50DL RDS(ON) / mOhm 70 S/I 100 4 3 Fig.6. Typical on-state characteristics, Tj = 25 ˚C. ID = f(VDS); parameter VIS; tp = 2 ms Overload protection characteristics not shown = N) 2 1 VDS / V Fig.3. Normalised continuous drain current. ID% = 100⋅ID/ID(25 ˚C) = f(Tmb); conditions: VIS = 5 V 1000 1E-05 tp T Fig.5. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T Normalised Current Derating ID% D= T 0.001 1E-07 140 tp PD 0 50 tp = DC 100 us 40 1 ms 30 10 ms 20 100 ms 10 1 0 1 10 0 100 VDS / V 40 ID / A 60 80 Fig.7. Typical on-state resistance, Tj = 25 ˚C. RDS(ON) = f(ID); parameter VIS; tp = 2 ms Fig.4. Safe operating area. Tmb = 25 ˚C ID & IDM = f(VDS); IDM single pulse; parameter tp June 1996 20 5 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET a BUK110-50DL Normalised RDS(ON) = f(Tj) 1.5 Energy & Time BUK110-50DL Energy / J 1.5 1.0 1.0 Time / ms 0.5 0.5 Tj(TO) 0 0 -60 -40 -20 0 20 40 60 Tj / C 80 100 120 140 -60 td sc / ms 20 60 100 Tmb / C 140 180 220 Fig.11. Typical overload protection characteristics. Conditions: VDD = 13 V; VIS = 5 V; SC load = 30 mΩ Fig.8. Normalised drain-source on-state resistance. a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 25 A; VIS = 5 V 10 -20 BUK110-50DL 50 BUK110-50DL ID / A 40 PDSM 30 typ. 1 20 10 0.1 0 0.1 1 PDS / kW 50 10 60 VDS / V 70 Fig.12. Typical clamping characteristics, 25 ˚C. ID = f(VDS); conditions: VIS = 0 V; tp ≤ 50 µs Fig.9. Typical overload protection characteristics. td sc = f(PDS); conditions: VIS ≥ 4 V; Tj = 25 ˚C. VIS(TO) / V PDSM% 120 max. 2 100 typ. 80 60 min. 1 40 20 0 0 -60 -40 -20 0 20 40 60 Tmb / C 80 100 120 140 -60 Fig.10. Normalised limiting overload dissipation. PDSM% =100⋅PDSM/PDSM(25 ˚C) = f(Tmb) June 1996 -40 -20 0 20 40 60 Tj / C 80 100 120 140 Fig.13. Input threshold voltage. VIS(TO) = f(Tj); conditions: ID = 1 mA; VDS = 5 V 6 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET 600 BUK110-50DL IISL & IIS / uA BUK110-50DL VIS / V & VDS / V BUK110-50DL 15 PROTECTION LATCHED 500 VDS 10 400 IISL RESET 300 VIS 5 IIS 200 100 NORMAL 0 0 0 0 2 4 400 VIS / V IS / A 600 800 1000 time / us Fig.17. Typical switching waveforms, resistive load. VDD = 13 V; RL = 1.1 Ω; RI = 50 Ω, Tj = 25 ˚C. Fig.14. Typical DC input characteristics, Tj = 25 ˚C. IISL & IIS = f(VIS); protection latched & normal operation 200 200 6 EDSM% 120 BUK110-50DL 110 100 90 150 80 70 60 100 50 40 30 50 20 10 0 0 0 0 0.2 0.4 0.6 0.8 1 1.2 VSD / V 1.4 1.6 1.8 20 40 60 2 80 Tmb / C 100 120 140 Fig.18. Normalised limiting clamping energy. EDSM% = f(Tmb); conditions: ID = 25 A; VIS = 10 V Fig.15. Typical reverse diode current, Tj = 25 ˚C. IS = f(VSDS); conditions: VIS = 0 V; tp = 250 µs V(CL)DSS VDD VDS VDD + 0 RL L ID VDS 0 TOPFET I P D TOPFET 0 I RI VIS -ID/100 D.U.T. P Schottky RIS S ID measure - D VIS D.U.T. VDD S R 01 shunt 0V 0R1 Fig.19. Clamping energy test circuit, RIS = 50 Ω. EDSM = 0.5 ⋅ LID2 ⋅ V(CL)DSS /(V(CL)DSS − VDD ) Fig.16. Test circuit for resistive load switching times. June 1996 7 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET 1 mA BUK110-50DL Iiso & Iisl normalised to 25 C Idss 1.5 100 uA 10 uA typ. 1 1 uA 100 nA 0.5 0 20 40 60 80 Tj / C 100 120 140 -60 Fig.20. Typical off-state leakage current. IDSS = f(Tj); Conditions: VDS = 40 V; IIS = 0 V. June 1996 -20 20 60 Tj / C 100 140 180 Fig.21. Normalised input currents (normal & latched). IISO/IISO25˚C & IISL/IISL25˚C = f(Tj); VIS = 5 V 8 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET BUK110-50DL MECHANICAL DATA Dimensions in mm 4.5 max 1.4 max 10.3 max Net Mass: 1.4 g 11 max 15.4 2.5 0.85 max (x2) 0.5 2.54 (x2) Fig.22. SOT404 : centre pin connected to mounting base. Notes 1. Epoxy meets UL94 V0 at 1/8". MOUNTING INSTRUCTIONS Dimensions in mm 11.5 9.0 17.5 2.0 3.8 5.08 Fig.23. SOT404 : minimum pad sizes for surface mounting. Notes 1. Plastic meets UL94 V0 at 1/8". June 1996 9 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET BUK110-50DL DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. Philips Electronics N.V. 1996 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. June 1996 10 Rev 1.000