ETC PM4319-BI

Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
PM4319
OCTLIU-SH
Octal Short-Haul
E1/T1/J1 Line Interface Device
Data Sheet
Proprietary and Confidential
Released
Issue No. 3: May 2002
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2012568, Issue 3
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Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
Legal Information
Copyright
Copyright 2002 PMC-Sierra, Inc. All rights reserved.
The information in this document is proprietary and confidential to PMC-Sierra, Inc., and for its
customers’ internal use. In any event, no part of this document may be reproduced or
redistributed in any form without the express written consent of PMC-Sierra, Inc.
PMC-2012568 (R3), PMC-2020247, R2
Disclaimer
None of the information contained in this document constitutes an express or implied warranty
by PMC-Sierra, Inc. as to the sufficiency, fitness or suitability for a particular purpose of any
such information or the fitness, or suitability for a particular purpose, merchantability,
performance, compatibility with other parts or systems, of any of the products of PMC-Sierra,
Inc., or any portion thereof, referred to in this document. PMC-Sierra, Inc. expressly disclaims
all representations and warranties of any kind regarding the contents or use of the information,
including, but not limited to, express and implied warranties of accuracy, completeness,
merchantability, fitness for a particular use, or non-infringement.
In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or
consequential damages, including, but not limited to, lost profits, lost business or lost data
resulting from any use of or reliance upon the information, whether or not PMC-Sierra, Inc. has
been advised of the possibility of such damage.
Trademarks
AAL1gator-32, SBI, TE-32, TEMAP-84 and PMC-Sierra are trademarks of PMC-Sierra Inc.
Other product and company names mentioned herein may be the trademarks of their respective
owners.
Patents
Granted
The technology discussed in this document is protected by one or more of the following patent
grants:
U.S. Application No. US5973977. Canadian Application No. CA2242152.
Other relevant patent grants may also exist.
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Document No.: PMC-2012568, Issue 3
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Telecom Standard Product Data Sheet
Released
Contacting PMC-Sierra
PMC-Sierra
8555 Baxter Place
Burnaby, BC
Canada V5A 4V7
Tel: +1 (604) 415-6000
Fax: +1 (604) 415-6200
Document Information: [email protected]
Corporate Information: [email protected]
Technical Support: [email protected]
Web Site: http://www.pmc-sierra.com
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2012568, Issue 3
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Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
Revision History
Issue No.
Issue Date
Details of Change
3
May 2002
Changes for Production Release. Moved document to new template.
Change bars relative to issue 2.
2
April 2002
Preliminary version.
1
February 2002
Preview created from OCTLIU engineering document (PMC-2000964)
issue 6.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2012568, Issue 3
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Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
Table of Contents
Legal Information ...........................................................................................................................2
Copyright .................................................................................................................................2
Disclaimer................................................................................................................................2
Trademarks .............................................................................................................................2
Patents ....................................................................................................................................2
Contacting PMC-Sierra ..................................................................................................................3
Revision History .............................................................................................................................4
Table of Contents ...........................................................................................................................5
List of Registers .............................................................................................................................8
List of Figures ..............................................................................................................................12
List of Tables ................................................................................................................................14
1
Features ................................................................................................................................16
1.1
Each Receiver Section Features.................................................................................16
1.2
Each Transmitter Section Features .............................................................................17
2
Applications ...........................................................................................................................19
3
References ............................................................................................................................20
4
Application Examples ............................................................................................................22
5
Block Diagram .......................................................................................................................23
6
Description ............................................................................................................................24
7
Pin Diagram...........................................................................................................................25
8
Pin Description ......................................................................................................................27
9
Functional Description...........................................................................................................38
9.1
Octants ........................................................................................................................38
9.2
Receive Interface.........................................................................................................38
9.3
Clock and Data Recovery (CDRC) ..............................................................................38
9.4
Receive Jitter Attenuator (RJAT) .................................................................................40
9.5
T1 Inband Loopback Code Detector (IBCD) ...............................................................41
9.6
T1 Pulse Density Violation Detector (PDVD) ..............................................................41
9.7
Performance Monitor Counters (PMON) .....................................................................41
9.8
Pseudo Random Binary Sequence Generation and Detection (PRBS)......................41
9.9
T1 Inband Loopback Code Generator (XIBC) .............................................................42
9.10 Pulse Density Enforcer (XPDE)...................................................................................42
9.11 Transmit Jitter Attenuator (TJAT).................................................................................42
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
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Released
9.12 Line Transmitter...........................................................................................................47
9.13 Timing Options (TOPS) ...............................................................................................47
9.14 External Analogue Interface Circuits ...........................................................................48
9.15 Scaleable Bandwidth Interconnect (SBI) Interface......................................................49
9.16 SBI Extracter and PISO...............................................................................................49
9.17 SBI Inserter and SIPO .................................................................................................50
9.18 JTAG Test Access Port ................................................................................................50
9.19 Microprocessor Interface .............................................................................................50
10 Normal Mode Register Description .......................................................................................51
10.1 Normal Mode Register Memory Map ..........................................................................51
11 Test Features Description....................................................................................................164
11.1 JTAG Test Port...........................................................................................................164
12 Operation.............................................................................................................................168
12.1 Configuring the OCTLIU-SH from Reset ...................................................................168
12.2 Servicing Interrupts....................................................................................................168
12.3 Using the Performance Monitoring Features.............................................................169
12.4 Using the Transmit Line Pulse Generator .................................................................169
12.5 Using the Line Receiver ............................................................................................185
12.6 Using the PRBS Generator and Detector..................................................................192
12.7 Loopback Modes .......................................................................................................193
12.8 Initialization of the RJAT and TJAT............................................................................194
12.9 Configuring the SBI Bus ............................................................................................194
12.10 JTAG Support ............................................................................................................195
13 Functional Timing ................................................................................................................202
13.1 SBI BUS Interface Timing..........................................................................................202
13.2 Line Code Violation Insertion.....................................................................................203
13.3 Alarm Interface ..........................................................................................................206
14 Absolute Maximum Ratings.................................................................................................207
15 D.C. Characteristics ............................................................................................................208
16 Microprocessor Interface Timing Characteristics ................................................................ 211
17 OCTLIU-SH Timing Characteristics ....................................................................................215
17.1 RSTB Timing (Figure 28)...........................................................................................215
17.2 XCLK Input Timing (Figure 29) ..................................................................................215
17.3 SBI Interface (Figure 30 to Figure 32).......................................................................216
17.4 Alarm Interface (Figure 33)........................................................................................218
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2012568, Issue 3
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Telecom Standard Product Data Sheet
Released
17.5 JTAG Port Interface (Figure 34) ................................................................................218
18 Ordering and Thermal Information ......................................................................................221
19 Mechanical Information .......................................................................................................222
Notes..........................................................................................................................................223
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2012568, Issue 3
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Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
List of Registers
Register 000H: Reset / Revision ID / Device ID ..........................................................................58
Register 001H: Global Configuration / Clock Monitor..................................................................59
Register 002H: Master Interrupt Source #1.................................................................................61
Register 003H: Master Interrupt Source #2.................................................................................62
Register 004H: Master Test Control #1 .......................................................................................63
Register 005H: Master Test Control #2 .......................................................................................64
Register 006H: CSU Configuration..............................................................................................65
Register 008H, 088H, 108H, 188H, 208H, 288H, 308H, 388H: Receive Line
Interface Configuration #1..........................................................................................67
Register 009H, 089H, 109H, 189H, 209H, 289H, 309H, 389H: Receive Line
Interface Configuration #2..........................................................................................69
Register 00AH, 08AH, 10AH, 18AH, 20AH, 28AH, 30AH, 38AH: Transmit Line
Interface Configuration...............................................................................................71
Register 00BH, 08BH, 10BH, 18BH, 20BH, 28BH, 30BH, 38BH: Transmit
Timing Options / Clock Monitor / Pulse Template Selection......................................73
Register 00CH, 08CH, 10CH, 18CH, 20CH, 28CH, 30CH, 38CH: Line Interface
Interrupt Source #1 / PMON Update..........................................................................75
Register 00DH, 08DH, 10DH, 18DH, 20DH, 28DH, 30DH, 38DH: Line Interface
Interrupt Source #2 ....................................................................................................76
Register 00EH, 08EH, 10EH, 18EH, 20EH, 28EH, 30EH, 38EH: Line Interface
Diagnostics ................................................................................................................77
Register 00FH, 08FH, 10FH, 18FH, 20FH, 28FH, 30FH, 38FH: Line Interface
PRBS Position ...........................................................................................................79
Register 310H: INSBI Control......................................................................................................80
Register 311H: INSBI FIFO Underrun Interrupt Status ...............................................................82
Register 312H: INSBI FIFO Overrun Interrupt Status .................................................................83
Register 313H – 31AH: INSBI Page A Octant to Tributary Mapping #1 - #8 ..............................84
Register 31BH – 322H: INSBI Page B Octant to Tributary Mapping #1 - #8 ..............................85
Register 323H: INSBI Link Enable...............................................................................................86
Register 324H: INSBI Link Enable Busy......................................................................................87
Register 325H – 32CH: INSBI Tributary Control #1 – #8 ............................................................88
Register 32DH: INSBI Minimum Depth........................................................................................89
Register 32EH: INSBI FIFO Thresholds ......................................................................................90
Register 331H: INSBI Depth Check Interrupt Status...................................................................91
Register 332H: INSBI Master Interrupt Status.............................................................................92
Register 390H: EXSBI Control.....................................................................................................93
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2012568, Issue 3
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Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
Register 391H: EXSBI FIFO Underrun Interrupt Status ..............................................................95
Register 392H: EXSBI FIFO Overrun Interrupt Status ................................................................96
Register 393H: EXSBI Parity Error Interrupt Reason ..................................................................97
Register 394H: EXSBI Depth Check Interrupt Status..................................................................98
Register 395H: EXSBI Master Interrupt Status ...........................................................................99
Register 396H: EXSBI Minimum Depth .....................................................................................100
Register 397H: EXSBI FIFO Thresholds ...................................................................................101
Register 398H: EXSBI Link Enable ...........................................................................................102
Register 399H: EXSBI Link Enable Busy ..................................................................................103
Register 3A0H – 3A7H: EXSBI Tributary Control #1 – #8.........................................................104
Register 3A8H – 3AFH: EXSBI Page A Octant to Tributary Mapping #1 - #8...........................105
Register 3B0H to 3B7H: EXSBI Page B Octant to Tributary Mapping #1 - #8..........................106
Register 043H, 0C3H, 143H, 1C3H, 243H, 2C3H, 343H, 3C3H: T1 PDVD
Interrupt Enable/Status ............................................................................................107
Register 045H, 0C5H, 145H, 1C5H, 245H, 2C5H, 345H, 3C5H: T1 XPDE
Interrupt Enable/Status ............................................................................................108
Register 046H, 0C6H, 146H, 1C6H, 246H, 2C6H, 346H, 3C6H: T1 XIBC
Control......................................................................................................................110
Register 047H, 0C7H, 147H, 1C7H, 247H, 2C7H, 347H, 3C7H: T1 XIBC
Loopback Code........................................................................................................111
Register 048H, 0C8H, 148H, 1C8H, 248H, 2C8H, 348H, 3C8H: RJAT Interrupt
Status .......................................................................................................................112
Register 049H, 0C9H, 149H, 1C9H, 249H, 2C9H, 349H, 3C9H: RJAT
Reference Clock Divisor (N1) Control......................................................................113
Register 04AH, 0CAH, 14AH, 1CAH, 24AH, 2CAH, 34AH, 3CAH: RJAT Output
Clock Divisor (N2) Control .......................................................................................114
Register 04BH, 0CBH, 14BH, 1CBH, 24BH, 2CBH, 34BH, 3CBH: RJAT
Configuration............................................................................................................115
Register 04CH, 0CCH, 14CH, 1CCH, 24CH, 2CCH, 34CH, 3CCH: TJAT
Interrupt Status ........................................................................................................117
Register 04DH, 0CDH, 14DH, 1CDH, 24DH, 2CDH, 34DH, 3CDH: TJAT
Reference Clock Divisor (N1) Control......................................................................118
Register 04EH, 0CEH, 14EH, 1CEH, 24EH, 2CEH, 34EH, 3CEH: TJAT Output
Clock Divisor (N2) Control .......................................................................................119
Register 04FH, 0CFH, 14FH, 1CFH, 24FH, 2CFH, 34FH, 3CFH: TJAT
Configuration............................................................................................................120
Register 050H, 0D0H, 150H, 1D0H, 250H, 2D0H, 350H, 3D0H: IBCD
Configuration............................................................................................................122
Register 051H, 0D1H, 151H, 1D1H, 251H, 2D1H, 351H, 3D1H: IBCD Interrupt
Enable/Status...........................................................................................................123
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
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Released
Register 052H, 0D2H, 152H, 1D2H, 252H, 2D2H, 352H, 3D2H: IBCD Activate
Code.........................................................................................................................125
Register 053H, 0D3H, 153H, 1D3H, 253H, 2D3H, 353H, 3D3H: IBCD
Deactivate Code ......................................................................................................126
Register 054H, 0D4H, 154H, 1D4H, 254H, 2D4H, 354H, 3D4H: CDRC
Configuration............................................................................................................127
Register 055H, 0D5H, 155H, 1D5H, 255H, 2D5H, 355H, 3D5H: CDRC Interrupt
Control......................................................................................................................129
Register 056H, 0D6H, 156H, 1D6H, 256H, 2D6H, 356H, 3D6H: CDRC Interrupt
Status .......................................................................................................................130
Register 057H, 0D7H, 157H, 1D7H, 257H, 2D7H, 357H, 3D7H: CDRC
Alternate Loss of Signal Status................................................................................131
Register 058H, 0D8H, 158H, 1D8H, 258H, 2D8H, 358H, 3D8H: PMON Interrupt
Enable/Status...........................................................................................................132
Register 05EH, 0DEH, 15EH, 1DEH, 25EH, 2DEH, 35EH, 3DEH: PMON LCV
Count (LSB) .............................................................................................................133
Register 05FH, 0DFH, 15FH, 1DFH, 25FH, 2DFH, 35FH, 3DFH: PMON LCV
Count (MSB) ............................................................................................................134
Register 060H, 0E0H, 160H, 1E0H, 260H, 2E0H, 360H, 3E0H: PRBS
Generator/Checker Control......................................................................................135
Register 061H, 0E1H, 161H, 1E1H, 261H, 2E1H, 361H, 3E1H: PRBS Checker
Interrupt Enable/Status ............................................................................................137
Register 062H, 0E2H, 162H, 1E2H, 262H, 2E2H, 362H, 3E2H: PRBS Pattern
Select .......................................................................................................................139
Register 064H, 0E4H, 164H, 1E4H, 264H, 2E4H, 364H, 3E4H: PRBS Error
Count #1...................................................................................................................140
Register 065H, 0E5H, 165H, 1E5H, 265H, 2E5H, 365H, 3E5H: PRBS Error
Count #2...................................................................................................................141
Register 066H, 0E6H, 166H, 1E6H, 266H, 2E6H, 366H, 3E6H: PRBS Error
Count #3...................................................................................................................142
Register 068H, 0E8H, 168H, 1E8H, 268H, 2E8H, 368H, 3E8H: XLPG
Control/Status ..........................................................................................................143
Register 069H, 0E9H, 169H, 1E9H, 269H, 2E9H, 369H, 3E9H: XLPG Pulse
Waveform Scale.......................................................................................................144
Register 06AH, 0EAH, 16AH, 1EAH, 26AH, 2EAH, 36AH, 3EAH: XLPG Pulse
Waveform Storage Write Address #1 ......................................................................145
Register 06BH, 0EBH, 16BH, 1EBH, 26BH, 2EBH, 36BH, 3EBH: XLPG Pulse
Waveform Storage Write Address #2 ......................................................................146
Register 06CH, 0ECH, 16CH, 1ECH, 26CH, 2ECH, 36CH, 3ECH: XLPG Pulse
Waveform Storage Data ..........................................................................................147
Register 06DH, 0EDH, 16DH, 1EDH, 26DH, 2EDH, 36DH, 3EDH: XLPG Fuse
Control......................................................................................................................148
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Released
Register 070H, 0F0H, 170H, 1F0H, 270H, 2F0H, 370H, 3F0H: RLPS
Configuration and Status .........................................................................................149
Register 071H, 0F1H, 171H, 1F1H, 271H, 2F1H, 371H, 3F1H: RLPS ALOS
Detection/Clearance Threshold ...............................................................................151
Register 072H, 0F2H, 172H, 1F2H, 272H, 2F2H, 372H, 3F2H: RLPS ALOS
Detection Period ......................................................................................................152
Register 073H, 0F3H, 173H, 1F3H, 273H, 2F3H, 373H, 3F3H: RLPS ALOS
Clearance Period .....................................................................................................153
Register 074H, 0F4H, 174H, 1F4H, 274H, 2F4H, 374H, 3F4H: RLPS
Equalization Indirect Address ..................................................................................154
Register 075H, 0F5H, 175H, 1F5H, 275H, 2F5H, 375H, 3F5H: RLPS
Equalization Read/WriteB Select.............................................................................155
Register 076H, 0F6H, 176H, 1F6H, 276H, 2F6H, 376H, 3F6H: RLPS Equalizer
Loop Status and Control ..........................................................................................156
Register 077H, 0F7H, 177H, 1F7H, 277H, 2F7H, 377H, 3F7H: RLPS Equalizer
Configuration............................................................................................................157
Register 078H, 0F8H, 178H, 1F8H, 278H, 2F8H, 378H, 3F8H: RLPS
Equalization Indirect Data ........................................................................................158
Register 079H, 0F9H, 179H, 1F9H, 279H, 2F9H, 379H, 3F9H: RLPS
Equalization Indirect Data ........................................................................................159
Register 07AH, 0FAH, 17AH, 1FAH, 27AH, 2FAH, 37AH, 3FAH: RLPS
Equalization Indirect Data ........................................................................................160
Register 07BH, 0FBH, 17BH, 1FBH, 27BH, 2FBH, 37BH, 3FBH: RLPS
Equalization Indirect Data ........................................................................................161
Register 07CH, 0FCH, 17CH, 1FCH, 27CH, 2FCH, 37CH, 3FCH: RLPS
Equalizer Voltage Thresholds #1.............................................................................162
Register 07DH, 0FDH, 17DH, 1FDH, 27DH, 2FDH, 37DH, 3FDH: RLPS
Equalizer Voltage Thresholds #2.............................................................................163
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Document No.: PMC-2012568, Issue 3
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Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
List of Figures
Figure 1 High Density T1/E1 Framer/Transceiver Application ..................................................22
Figure 2 High Density Leased Line Circuit Emulation Application ............................................22
Figure 3 Metro Optical Access Equipment ................................................................................22
Figure 4 OCTLIU-SH Block Diagram.........................................................................................23
Figure 5 Pin Diagram (Bottom View) .........................................................................................25
Figure 6 T1 Jitter Tolerance.......................................................................................................39
Figure 7 Compliance with ITU-T Specification G.823 for E1 Input Jitter ...................................40
Figure 8 TJAT Jitter Tolerance ..................................................................................................44
Figure 9 TJAT Minimum Jitter Tolerance vs. XCLK Accuracy...................................................45
Figure 10 TJAT Jitter Transfer...................................................................................................46
Figure 11 External Analogue Interface Circuits .........................................................................48
Figure 12 Transmit Timing Options ...........................................................................................74
Figure 13 Line Loopback .........................................................................................................193
Figure 14 Diagnostic Digital Loopback ....................................................................................194
Figure 15 Boundary Scan Architecture....................................................................................195
Figure 16 TAP Controller Finite State Machine .......................................................................197
Figure 17 Input Observation Cell (IN_CELL)...........................................................................200
Figure 18 Output Cell (OUT_CELL) or Enable Cell (ENABLE) ...............................................200
Figure 19 Bidirectional Cell (IO_CELL)....................................................................................201
Figure 20 Layout of Output Enable and Bidirectional Cells.....................................................201
Figure 21 SBI BUS Functional Timing .....................................................................................202
Figure 22 B8ZS Line Code Violation Insertion ........................................................................203
Figure 23 HDB3 Line Code Violation Insertion........................................................................204
Figure 24 AMI Line Code Violation Insertion ...........................................................................205
Figure 25 LOS Alarm Serial Output .........................................................................................206
Figure 26 Microprocessor Interface Read Timing ...................................................................212
Figure 27 Microprocessor Interface Write Timing....................................................................213
Figure 28 RSTB Timing ...........................................................................................................215
Figure 29 XCLK Input Timing ..................................................................................................215
Figure 30 SBI Frame Pulse Timing..........................................................................................216
Figure 31 SBI ADD BUS Timing ..............................................................................................217
Figure 32 SBI DROP BUS Timing ...........................................................................................217
Figure 33 Alarm Interface Timing ............................................................................................218
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Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
Figure 34 JTAG Port Interface Timing .....................................................................................219
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Document No.: PMC-2012568, Issue 3
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Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
List of Tables
Table 1 External Component Descriptions ................................................................................48
Table 2 Normal Mode Register Memory Map............................................................................51
Table 3 Clock Synthesis Mode ..................................................................................................65
Table 4 TJAT FIFO Output Clock Source..................................................................................73
Table 5 TJAT PLL Source .........................................................................................................73
Table 6 EXSBI Clock Generation Options...............................................................................104
Table 7 Transmit In-band Code Length...................................................................................110
Table 8 Recommended N1/N2 values.....................................................................................114
Table 9 Recommended N1/N2 values.....................................................................................119
Table 10 Loopback Code Configurations ................................................................................122
Table 11 Loss of Signal Thresholds ........................................................................................128
Table 12 Transmit Output Amplitude .......................................................................................144
Table 13 ALOS Detection/Clearance Thresholds....................................................................151
Table 14 Boundary Scan Register...........................................................................................165
Table 15 Default Settings ........................................................................................................168
Table 16 T1.102 Transmit Waveform Values for T1 Short Haul (0 – 110 ft.) ..........................171
Table 17 T1.102 Transmit Waveform Values for T1 Short Haul (110 – 220 ft.) ......................172
Table 18 T1.102 Transmit Waveform Values for T1 Short Haul (220 – 330 ft.) ......................173
Table 19 T1.102 Transmit Waveform Values for T1 Short Haul (330 – 440 ft.) ......................174
Table 20 T1.102 Transmit Waveform Values for T1 Short Haul (440 – 550 ft.) ......................175
Table 21 T1.102 Transmit Waveform Values for T1 Short Haul (550 – 660 ft.) ......................176
Table 22 TR62411 Transmit Waveform Values for T1 Short Haul (0 – 110 ft.) ......................177
Table 23 TR62411 Transmit Waveform Values for T1 Short Haul (110 –
220 ft.) ......................................................................................................................178
Table 24 TR62411 Transmit Waveform Values for T1 Short Haul (220 –
330 ft.) ......................................................................................................................179
Table 25 TR62411 Transmit Waveform Values for T1 Short Haul (330 –
440 ft.) ......................................................................................................................180
Table 26 TR62411 Transmit Waveform Values for T1 Short Haul (440 –
550 ft.) ......................................................................................................................181
Table 27 TR62411 Transmit Waveform Values for T1 Short Haul (550 –
660 ft.) ......................................................................................................................182
Table 28 Transmit Waveform Values for E1 120 Ohm............................................................183
Table 29 Transmit Waveform Values for E1 75 Ohm..............................................................184
Table 30 RLPS Register Programming ...................................................................................185
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Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
Table 31 RLPS Equalizer RAM Table (T1 mode)....................................................................186
Table 32 RLPS Equalizer RAM Table (E1 mode) ...................................................................189
Table 33 Absolute Maximum Ratings ......................................................................................207
Table 34 D.C. Characteristics..................................................................................................208
Table 35 Microprocessor Interface Read Access....................................................................211
Table 36 Microprocessor Interface Write Access ....................................................................213
Table 37 RTSB Timing ............................................................................................................215
Table 38 XCLK Input Timing....................................................................................................215
Table 39 Clocks and SBI Frame Pulse....................................................................................216
Table 40 SBI ADD BUS ...........................................................................................................216
Table 41 SBI DROP BUS ........................................................................................................217
Table 42 Alarm Interface .........................................................................................................218
Table 43 JTAG Port Interface ..................................................................................................218
Table 44 Ordering Information.................................................................................................221
Table 45 OCTLIU-SH Theta Jc................................................................................................221
Table 46 OCTLIU-SH Junction Temperature ..........................................................................221
Table 47 OCTLIU-SH Theta Ja vs. Airflow..............................................................................221
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Document No.: PMC-2012568, Issue 3
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Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
1
1.1
Features
•
Monolithic device which integrates eight T1/J1 or E1 short haul line interface circuits.
•
Software switchable between T1/J1 and E1 operation on a per-device basis.
•
Meets or exceeds T1/J1 and E1 short haul network access specifications including ANSI
T1.102, T1.403, T1.408, AT&T TR 62411, ITU-T G.703, G.704 as well as ETSI 300-011,
CTR-4, CTR-12 and CTR-13.
•
Provides encoding and decoding of B8ZS, HDB3 and AMI line codes.
•
Provides receive equalization, clock recovery and line performance monitoring.
•
Provides transmit and receive jitter attenuation.
•
Provides digitally programmable short haul transmit templates.
•
Provides a selectable, per channel independent de-jittered T1 or E1 recovered clock for
system timing and redundancy.
•
Provides PRBS generators and detectors on each tributary for error testing at DS1 and E1
rates as recommended in ITU-T O.151.
•
Provides parallel Scaleable Bandwidth Interconnect (SBI) interfaces on the system side.
•
Provides an 8-bit microprocessor bus interface for configuration, control, and status
monitoring.
•
Uses line rate system clock.
•
Provides an IEEE 1149.1 (JTAG) compliant Test Access Port (TAP) and controller for
boundary scan test.
•
Implemented in a low power 3.3 V tolerant 1.8/3.3 V CMOS technology.
•
Available in a high density 288-pin Tape-SBGA (23 mm by 23 mm) package.
•
Provides a –40°C to +85°C Industrial temperature operating range.
Each Receiver Section Features
•
Supports T1 signal reception for distances with up to 12 dB of cable attenuation at nominal
conditions using PIC 22 gauge cable emulation.
•
Supports E1 signal reception for distances with up to 12 dB of cable attenuation at nominal
conditions using PIC 22 gauge cable emulation.
•
Supports G.772 compliant non-intrusive protected monitoring points.
•
Recovers clock and data using a digital phase locked loop for high jitter tolerance.
•
Tolerates more than 0.4 UI peak-to-peak; high frequency jitter as required by AT&T TR
62411 and Bellcore TR-TSY-000170.
•
Outputs parallel data in SBI bus format.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2012568, Issue 3
16
Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
1.2
•
Performs B8ZS or AMI decoding when processing a bipolar DS-1 signal and HDB3 or AMI
decoding when processing a bipolar E1 signal.
•
Detects line code violations (LCVs), B8ZS/HDB3 line code signatures, and 4 (E1), 8
(T1+B8ZS) or 16 (T1 AMI) successive zeros.
•
Accumulates up to 8191 line code violations (LCVs), for performance monitoring purposes,
over accumulation intervals defined by the period between software write accesses to the
LCV register.
•
Detects loss of signal (LOS), which is defined as 10, 15, 31, 63, or 175 successive zeros.
•
Detects programmable inband loopback activate and deactivate code sequences received in
the DS-1 data stream when they are present for 5.1 seconds. Optionally, enters loopback
mode automatically on detection of an inband loopback code.
•
Detects violations of the ANSI T1.403 12.5% pulse density rule over a moving 192-bit
window.
•
A pseudo-random sequence user selectable from 211 –1, 215 –1 or 220 –1, may be detected in
the T1/E1 stream in either the receive or transmit directions. The detector counts pattern
errors using a 24-bit saturating PRBS error counter.
Each Transmitter Section Features
•
Supports transfer of transmitted single rail PCM and signaling data from 1.544 Mbit/s and
2.048 Mbit/s backplane buses.
•
Generates DSX-1 shorthaul pulses with programmable pulse shape compatible with AT&T,
ANSI and ITU requirements.
•
Generates E1 pulses compliant to G.703 recommendations.
•
Provides a digitally programmable pulse shape extending up to 5 transmitted bit periods for
custom short haul pulse shaping applications.
•
Provides line outputs that are current limited and may be tristated for protection or in
redundant applications.
•
Provides a digital phase locked loop for generation of a low jitter transmit clock complying
with all jitter attenuation, jitter transfer and residual jitter specifications of AT&T TR 62411
and ETSI TBR 12 and TBR 13.
•
Provides a FIFO buffer for jitter attenuation and rate conversion in the transmit path.
•
Allows bipolar violation (BPV) transparent operation for error restoring regenerator
applications.
•
Allows bipolar violation (BPV) insertion for diagnostic testing purposes.
•
Supports all ones transmission for alarm indication signal (AIS) generation.
•
Accepts parallel data from the SBI interface.
•
Performs B8ZS or AMI encoding when processing an SBI-sourced DS-1 signal and HDB3
or AMI encoding when processing an SBI-sourced E1 signal.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2012568, Issue 3
17
Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
•
A pseudo-random sequence user selectable from 211 –1, 215 –1 or 220 –1, may be inserted
into or detected from the T1 or E1 stream in either the receive or transmit directions.
•
Detects violations of the ANSI T1.403 12.5% pulse density rule over a moving 192-bit
window and optionally stuffs ones to maintain minimum ones density.
•
Supports transmission of a programmable unframed inband loopback code sequence.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2012568, Issue 3
18
Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
2
Applications
•
Metro Optical Access Equipment.
•
Edge Router Linecards.
•
Multiservice ATM Switch Linecards.
•
3G Base Station Controllers (BSC).
•
3G Base Transceiver Stations (BTS).
•
Digital Private Branch Exchanges (PBX).
•
Digital Access Cross-Connect Systems (DACS) and Electronic DSX Cross-Connect
Systems (EDSX).
•
Test Equipment.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2012568, Issue 3
19
Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
3
References
1. ANSI – T1.102-1993 – American National Standard for Telecommunications – Digital
Hierarchy – Electrical Interfaces.
2. ANSI – T1.107-1995 – American National Standard for Telecommunications – Digital
Hierarchy – Formats Specification.
3. ANSI – T1.403-1999 – American National Standard for Telecommunications – Carrier to
Customer Installation – DS-1 Metallic Interface Specification.
4. ANSI – T1.408-1990 – American National Standard for Telecommunications – Integrated
Services Digital Network (ISDN) Primary Rate – Customer Installation Metallic Interfaces
Layer 1 Specification.
5. AT&T – TR 62411 – Accunet T1.5 – Service Description and Interface Specification,
December 1990.
6. AT&T – TR 62411 – Accunet T1.5 – Service Description and Interface Specification,
Addendum 1, March 1991.
7. AT&T – TR 62411 – Accunet T1.5 – Service Description and Interface Specification,
Addendum 2, October 1992.
8. TR-TSY-000170 – Bellcore – Digital Cross-Connect System Requirements and Objectives,
Issue 1, November 1985.
9. TR-N1WT-000233 – Bell Communications Research – Wideband and Broadband Digital
Cross-Connect Systems Generic Criteria, Issue 3, November 1993.
10. TR-NWT-000303 – Bell Communications Research – Integrated Digital Loop Carrier
Generic Requirements, Objectives, and Interface, Issue 2, December, 1992.
11. TR-TSY-000499 – Bell Communications Research – Transport Systems Generic
Requirements (TSGR): Common Requirement, Issue 5, December, 1993.
12. ETSI – ETS 300 011 – ISDN Primary Rate User-Network Interface Specification and Test
Principles, 1992.
13. ETSI – ETS 300 233 – Access Digital Section for ISDN Primary Rates.
14. ETSI – CTR 4 – Integrated Services Digital Network (ISDN); Attachment requirements for
terminal equipment to connect to an ISDN using ISDN primary rate access, November
1995.
15. ETSI – CTR 12 – Business Telecommunications (BT); Open Network Provision (ONP)
technical requirements; 2 048 kbit/s digital unstructured leased lines (D2048U) Attachment
requirements for terminal equipment interface, December 1993.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2012568, Issue 3
20
Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
16. ETSI – CTR 13 – Business Telecommunications (BTC); 2 048 kbit/s digital structured
leased lines (D2048S); Attachment requirements for terminal equipment interface,
January 1996.
17. FCC Rules – Part 68.308 – Signal Power Limitations.
18. ITU-T – Recommendation G.703 – Physical/Electrical Characteristics of Hierarchical
Digital Interface, Geneva, 1998.
19. ITU-T – Recommendation G.704 – Synchronous Frame Structures Used at Primary
Hierarchical Levels, July 1998.
20. ITU-T Recommendation G.772 – Protected Monitoring Points Provided on Digital
Transmission Systems, 1992.
21. ITU-T – Recommendation G.775 – Loss of Signal (LOS), November 1998.
22. ITU-T Recommendation G.823, - The Control of Jitter and Wander Within Digital Networks
Which are Based on the 2048 kbit/s Hierarchy, 1993.
23. ITU-T – Recommendation I.431 – Primary Rate User-Network Interface – Layer 1
Specification, 1993.
24. ITU-T Recommendation O.151, - Error Performance Measuring Equipment For Digital
Systems at the Primary Bit Rate and Above, 1992.
25. TTC Standard JT-G703 – Physical/Electrical Characteristics of Hierarchical Digital
Interfaces, 1995.
26. TTC Standard JT-G704 – Frame Structures on Primary and Secondary Hierarchical Digital
Interfaces, 1995.
27. TTC Standard JT-I431 – ISDN Primary Rate User-Network Interface Layer 1 –
Specification, 1995.
28. Nippon Telegraph and Telephone Corporation – Technical Reference for High-Speed
Digital Leased Circuit Services, Third Edition, 1990.
29. ITU-T Recommendation G.824, The Control of Jitter and Wander within Digital Networks
which are based on the 1544 kbit/s Hierarchy (March 1993).
30. PMC-Sierra Application Note: "Configuring SBI Compatible Devices", PMC-2020180.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2012568, Issue 3
21
Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
4
Application Examples
Figure 1 High Density T1/E1 Framer/Transceiver Application
SBI
32 T1/J1
or E1 lines
H-MVIP or SBI
OCTLIU
OCTLIU
OCTLIU
OCTLIU-SH
PM4318
PM4318
PM4318
PM4319
TE-32
PM4332
T1/J1/E1 Framer
4 x OCTLIU-SH
Figure 2 High Density Leased Line Circuit Emulation Application
SBI
SBI
32 T1/J1
or E1 lines
Utopia L2
O CTLIU
OCTLIU
OCTLIU
OCTLIU-SH
AAL1gator-32
PM4318
PM4318
PM4318
PM4319
ATM
Backbone
PM73122
4 x OCTLIU-SH
AAL1 SAR
Figure 3 Metro Optical Access Equipment
Telecom Bus
SBI
84 T1/J1 or
63 E1 lines
OCTLIU
OCTLIU
OCTLIU
OCTLIU
OCTLIU
OCTLIU
OCTLIU
OCTLIU
OCTLIU
OCTLIU
OCTLIUSH
PM4318
PM4318
PM4318
PM4318
PM4318
PM4318
PM4318
PM4318
PM4318
PM4318
PM4319
11 or 8 x OCTLIU-SH
TEMAP-84
PM5366
T1/E1 VT/TU Mapper
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2012568, Issue 3
Cross Connect
22
RSYNC
XCLK
RXRING[8:1]
RXTIP[8:1]
CSD
Clock
Synthesis /
Distribution
RLPS
Receive LIU
XLPG
Transmit LIU
TOPS
Timing
Options
(Line
Loopback)
LOS
Serial
Output
CDRC
Clk/Data
Recovery
(Diagnostic
Digital
Loopback)
TJAT
Digital Jitter
Attenuator
PDVD
Pulse Density
Viol. Detector
PMON
Performance
Monitor
LCODE
AMI / B8ZS /
HDB3 Line
Encoder
JTAG
IBCD
Inband Loop back Code
Detector
XPDE
Pulse Density
Enforcer
uP Interface
RJAT
Digital Jitter
Attenuator
PRBS
Pattern
Generator /
Detector
XIBC
Inband Loopback Code
Generator
LIU Octant x 8
Rx Clock
Rx Data
Tx Clock
Tx Data
SBI Insert
INSBI-8
SBI Extract
EXSBI-8
RSTB
TXHIZ/LLB
DACTIVE
DV5
DPL
DDP
DDATA[7:0]
C1FPOUT
REFCLK
AC1FP
DC1FP
AV5
APL
ADP
ADATA[7:0]
5
TXRING1[8:1]
TXRING2[8:1]
TXTIP1[8:1]
TXTIP2[8:1]
Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
Block Diagram
Figure 4 OCTLIU-SH Block Diagram
PO
PI
INTB
RDB
WRB
CSB
ALE
A[10:0]
D[7:0]
TRSTB
TDO
TDI
TMS
TCK
LOS
LOS_L1
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2012568, Issue 3
23
Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
6
Description
The PM4319 Octal Short Haul E1/T1/J1 Line Interface Device (OCTLIU-SH) is a monolithic
integrated circuit suitable for use in short haul T1, J1 and E1 systems with a minimum of
external circuitry. The OCTLIU-SH is configurable via microprocessor control, allowing
feature selection without changes to external wiring.
Analogue circuitry is provided to allow direct reception of short haul E1 and T1 compatible
signals with up to 12 dB cable loss (at 1.024 MHz) in E1 mode or up to 12 dB cable loss (at
772 kHz) in T1 mode using a minimum of external components. Typically, only line protection,
a transformer and a line termination resistor are required.
The OCTLIU-SH recovers clock and data from the line. Decoding of AMI, HDB3 and B8ZS
line codes is supported. In T1 mode, the OCTLIU-SH also detects the presence of in-band loop
back codes.
The OCTLIU-SH supports detection of loss of signal, pulse density violation and line code
violation alarm conditions. Line code violations are accumulated for performance monitoring
purposes.
Internal analogue circuitry allows direct transmission of short haul T1 and E1 compatible
signals using a minimum of external components. Typically, only line protection, a transformer
and an optional line termination resistor are required. Digitally programmable pulse shaping
allows transmission of DSX-1 compatible signals up to 655 feet from the cross-connect, E1
short haul pulses into 120 ohm twisted pair or 75 ohm coaxial cable. In addition, the
programmable pulse shape extending over 5-bit periods allows customization of short haul line
interface circuits to application requirements.
Each channel of the OCTLIU-SH can generate a low jitter transmit clock from the input clock
source and also provide jitter attenuation in the receive path. A low jitter recovered T1 clock
can be routed outside the OCTLIU-SH for network timing applications.
The OCTLIU-SH supports an 8-bit parallel SBI interface for interfacing to high-density
framers.
The OCTLIU-SH may be configured, controlled and monitored via a generic 8-bit
microprocessor bus through which all internal registers are accessed.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2012568, Issue 3
24
Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
7
Pin Diagram
The OCTLIU-SH is packaged in a 288-pin Tape-SBGA package having a body size of 23mm by
23mm.
Figure 5 Pin Diagram (Bottom View)
22
21
20
19
18
17
16
15
14
13
12
11
A
ALE
VSS
D[1]
D[2]
D[4]
VSS
VDD1V8
TAVS2[1]
B
VDD3V3
VDD3V3
CSB
D[0]
D[3]
D[6]
RES_1
QAVS[4]
RES_0
TAVD3[1] TAVS3[8] TAVD2[8]
C
A[8]
A[9]
A[10]
RDB
VDD3V3
VDD3V3
VSS
D[7]
CAVD
D
A[4]
A[5]
A[6]
VSS
WRB
INTB
VSS
D[5]
CAVS
E
A[0]
A[1]
A[2]
10
9
8
7
TXRING2 TXRING1
TXRING1 TXRING2
TXTIP1[1] TXTIP2[1] TXTIP2[8] TXTIP1[8]
[1]
[1]
[8]
[8]
QAVD[4]
6
5
4
3
2
1
RSTB
LOS
RES_NC
RES_NC
VDD3V3
TDI
A
VDD1V8
VDD3V3
RES_0
RES_0
RES_NC
PI
RES_0
TDO
RES_0
B
TAVD2[1] TAVS3[1] TAVD3[8] TAVS2[8]
VSS
VSS
LOS_L1
RES_0
RES_NC
RES_NC
VSS
TCK
TXHIZ/LLB
C
TAVS1[1] TAVD1[1] TAVD1[8] TAVS1[8]
XCLK
RSYNC
VDD3V3
PO
VSS
NC
TMS
VDD3V3
RAVS1[8]
D
A[7]
TRSTB
VSS
RAVD2[8] RAVD2[7]
E
F
RAVS1[1] RAVD2[1]
QAVD[1]
A[3]
QAVS[3]
RES_0
RAVS2[7]
TXRING2
[7]
F
G
RAVD1[1]
RAVS2[1]
VDD3V3
RAVS2[8]
RXTIP[8]
RAVS1[7]
TXRING1
[7]
G
H
TXRING2
RXRING[1
RAVD2[2] RAVS2[2]
[2]
]
RXRING[8
RAVD1[8] RAVD1[7] TXTIP1[7]
]
H
J
TXRING1
[2]
RXRING[7
RXTIP[7]
]
TAVS2[7] TXTIP2[7]
J
K
TXTIP1[2] RAVD1[2] TAVS2[2] TAVS1[2]
TAVS1[7] TAVD2[7] TAVD3[7] TXTIP2[6]
K
L
TXTIP2[2] TAVD2[2] TAVD3[2] TAVD1[2]
TAVD1[7] TAVS3[7] TAVS3[6] TXTIP1[6]
L
M
TXTIP2[3] TAVS3[2] TAVS3[3] TAVD1[3]
TAVD1[6] TAVD3[6] TAVD2[6]
TXRING1
[6]
M
N
TXTIP1[3] TAVD3[3] TAVD2[3] TAVS1[3]
TAVS1[6] TAVS2[6] RAVD1[6]
TXRING2
[6]
N
P
TXRING1
RXRING[3
TAVS2[3] RAVD1[3]
[3]
]
RXRING[6
RAVS1[6] RAVD2[6]
]
RXTIP[6]
P
R
TXRING2
[3]
RXTIP[4]
RXTIP[5]
RXRING[5
RAVD1[5] RAVS2[6]
]
R
T
RAVS1[3] RAVS2[3] RAVD1[4] RAVS2[4]
QAVD[3]
RAVS2[5] RAVD2[5] RAVS1[5]
T
U
RXRING[4
RAVS1[4] RAVD2[4]
]
RXTIP[1]
RXTIP[2]
RXTIP[3]
RXRING[2
RAVS1[2]
]
RAVD2[3]
RES_0
RES_0
RES_0
ADATA[7]
VSS
U
AV5
RES_0
RES_0
RES_0
V
NC
VDD3V3
RES_0
ADATA[6]
W
ADATA[4] ADATA[5]
Y
V
RES_0
QAVS[1]
VSS
ADATA[1]
W
ADATA[0]
REFCLK
RES_0
VDD3V3
ADP
VDD3V3
Y
AC1FP
ADATA[2]
VDD3V3
ADATA[3]
VSS
AA
RES_0
DC1FP
VSS
RES_NC
RES_NC
AB
VSS
VSS
VSS
DDATA[0]
RES_NC
22
21
20
19
18
VDD3V3 C1FPOUT
VSS
TAVS1[4] TAVD1[4] TAVD1[5] TAVS1[5]
VDD1V8
DDATA[4]
RES_NC
DDATA[1]
RES_NC
VDD3V3
DDP
TAVS2[4] TAVD3[4] TAVS3[5] TAVD2[5]
RES_0
DPL
VDD3V3
VSS
DDATA[6] DACTIVE
VSS
VSS
RES_NC
VDD1V8
QAVS[2]
VSS
VSS
DDATA[5]
RES_NC
VDD3V3
VSS
APL
AA
RES_NC
DV5
VDD3V3
VSS
RES_NC
VDD3V3
AB
6
5
4
3
2
1
RES_NC DDATA[2] DDATA[3]
17
16
15
QAVD[2]
TAVD2[4] TAVS3[4] TAVD3[5] TAVS2[5]
TXRING2 TXRING1
TXRING1 TXRING2
TXTIP1[4] TXTIP2[4] TXTIP2[5] TXTIP1[5]
[4]
[4]
[5]
[5]
14
13
12
11
10
9
8
7
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2012568, Issue 3
RES_NC DDATA[7]
VSS
25
Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2012568, Issue 3
26
Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
8
Pin Description
By convention, where a bus of eight pins indexed [8:1] is present, the index indicates to which
octant the pin applies. With RXTIP[8:1], for example, RXTIP[1] applies to octant #1, RXTIP[2]
applies to octant #2, etc.
Pin Name
Type
Pin No. Function
SBI System Side Interface
REFCLK
Input
W21
The SBI reference clock signal (REFCLK) provides
reference timing for the SBI ADD and DROP busses.
REFCLK is nominally a 50% duty cycle clock of frequency
19.44 MHz ±50ppm.
AC1FP
Input
Y22
The SBI ADD bus C1 octet frame pulse signal (AC1FP)
provides frame synchronisation for devices connected via
an SBI interface. AC1FP must be asserted for 1 REFCLK
cycle every 500 µs or multiples thereof (i.e. every 9720 n
REFCLK cycles, where n is a positive integer). All devices
connected to the SBI ADD bus must be synchronised to a
AC1FP signal from a single source.
AC1FP is sampled on the rising edge of REFCLK.
DC1FP
Input
AA21
The SBI DROP bus C1 octet frame pulse signal (DC1FP)
provides frame synchronisation for devices connected via
an SBI interface. DC1FP must be asserted for 1 REFCLK
cycle every 500 µs or multiples thereof (i.e. every 9720 n
REFCLK cycles, where n is a positive integer). All devices
connected to the SBI DROP bus must be synchronised to
a DC1FP signal from a single source.
DC1FP is sampled on the rising edge of REFCLK.
C1FPOUT
Output
W15
The C1 octet frame pulse output signal (C1FPOUT) may
be used to provide frame synchronisation for devices
interconnected via an SBI interface. C1FPOUT is
asserted for 1 REFCLK cycle every 500 µs (i.e. every
9720 REFCLK cycles). If C1FPOUT is used for
synchronisation, it must be connected to the A/DC1FP
inputs of all the devices connected to the SBI ADD or
DROP bus.
C1FPOUT is updated on the rising edge of REFCLK.
ADATA[0]
ADATA[1]
ADATA[2]
ADATA[3]
ADATA[4]
ADATA[5]
ADATA[6]
ADATA[7]
Input
W22
V19
Y21
Y19
Y2
Y1
W1
U2
The SBI ADD bus data signals (ADATA[7:0]) contain time
division multiplexed transmit data from up to 84
independently timed links. Link data is transported as T1
or E1 tributaries within the SBI TDM bus structure. The
OCTLIU-SH may be configured to extract data from up to
8 tributaries within the structure.
ADATA[7:0] are sampled on the rising edge of REFCLK.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2012568, Issue 3
27
Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
Pin Name
Type
Pin No. Function
ADP
Input
W18
The SBI ADD bus parity signal (ADP) carries the even or
odd parity for the ADD bus signals. The parity calculation
encompasses the ADATA[7:0], APL and AV5 signals.
Multiple devices can drive the SBI ADD bus at uniquely
assigned tributary column positions. This parity signal is
intended to detect accidental driver clashes in the column
assignment.
ADP is sampled on the rising edge of REFCLK.
APL
Input
AA1
The SBI ADD bus payload signal (APL) indicates valid
data within the SBI TDM bus structure. This signal is
asserted during all octets making up a tributary. This
signal may be asserted during the V3 octet within a
tributary to accommodate negative timing adjustments
between the tributary rate and the fixed TDM bus
structure. This signal may be deasserted during the octet
following the V3 octet within a tributary to accommodate
positive timing adjustments between the tributary rate and
the fixed TDM bus structure.
APL is sampled on the rising edge of REFCLK.
AV5
Input
V4
The SBI ADD bus payload indicator signal (AV5) locates
the position of the floating payloads for each tributary
within the SBI TDM bus structure. Timing differences
between the port timing and the TDM bus timing are
indicated by adjustments of this payload indicator relative
to the fixed TDM bus structure. All movements indicated
by this signal must be accompanied by appropriate
adjustments in the APL signal.
AV5 is sampled on the rising edge of REFCLK.
DDATA[0]
DDATA[1]
DDATA[2]
DDATA[3]
DDATA[4]
DDATA[5]
DDATA[6]
DDATA[7]
Tristate
Output
AB19
Y17
AB16
AB15
W8
AA5
Y5
W5
The SBI DROP bus data signals (DDATA[7:0]) contain
time division multiplexed receive data from up to 84
independently timed links. Link data is transported as T1
or E1 tributaries within the SBI TDM bus structure. The
OCTLIU-SH may be configured to insert data into up to 8
tributaries within the structure. Multiple LIU devices can
drive the SBI DROP bus at uniquely assigned tributary
column positions. DDATA[7:0] are tristated when the
OCTLIU-SH is not outputting data on a particular tributary
column.
DDATA[7:0] are updated on the rising edge of REFCLK.
DDP
Tristate
Output
Y14
The SBI DROP bus parity signal (DDP) carries the even or
odd parity for the DROP bus signals. The parity
calculation encompasses the DDATA[7:0], DPL and DV5
signals.
Multiple LIU devices can drive this signal at uniquely
assigned tributary column positions. DDP is tristated
when the OCTLIU-SH is not outputting data on a particular
tributary column. This parity signal is intended to detect
accidental source clashes in the column assignment.
DDP is updated on the rising edge of REFCLK.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2012568, Issue 3
28
Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
Pin Name
Type
Pin No. Function
DPL
Tristate
Output
Y8
The SBI DROP bus payload signal (DPL) indicates valid
data within the SBI TDM bus structure. This signal is
asserted during all octets making up a tributary. This
signal may be asserted during the V3 octet within a
tributary to accommodate negative timing adjustments
between the tributary rate and the fixed TDM bus
structure. This signal may be deasserted during the octet
following the V3 octet within a tributary to accommodate
positive timing adjustments between the tributary rate and
the fixed TDM bus structure.
Multiple LIU devices can drive this signal at uniquely
assigned tributary column positions. DPL is tristated when
the OCTLIU-SH is not outputting data on a particular
tributary column.
DPL is updated on the rising edge of REFCLK.
DV5
Tristate
output
AB5
The SBI DROP bus payload indicator signal (DV5) locates
the position of the floating payloads for each tributary
within the SBI TDM bus structure. Timing differences
between the port timing and the TDM bus timing are
indicated by adjustments of this payload indicator relative
to the fixed TDM bus structure.
Multiple LIU devices can drive this signal at uniquely
assigned tributary column positions. DV5 is tristated when
the OCTLIU-SH is not outputting data on a particular
tributary column.
DV5 is updated on the rising edge of REFCLK.
DACTIVE
Output
Y4
The SBI DROP bus active indicator signal (DACTIVE) is
asserted whenever the OCTLIU-SH is driving the SBI
DROP bus signals, DDATA[7:0], DDP, DPL and DV5.
DACTIVE is updated on the rising edge of REFCLK.
Transmit Line Interface
TXTIP1[1]
TXTIP1[2]
TXTIP1[3]
TXTIP1[4]
TXTIP1[5]
TXTIP1[6]
TXTIP1[7]
TXTIP1[8]
TXTIP2[1]
TXTIP2[2]
TXTIP2[3]
TXTIP2[4]
TXTIP2[5]
TXTIP2[6]
TXTIP2[7]
TXTIP2[8]
Analogue
Output
A12
K22
N22
AB12
AB9
L1
H1
A9
Transmit Analogue Positive Pulse (TXTIP1[8:1] and
TXTIP2[8:1]). When the transmit analogue line interface
is enabled, the TXTIP1[x] and TXTIP2[x] analogue outputs
drive the transmit line pulse signal through an external
matching transformer. Both TXTIP1[x] and TXTIP2[x] are
normally connected to the positive lead of the transformer
primary. Two outputs are provided for better signal
integrity and must be shorted together on the board.
A11
L22
M22
AB11
AB10
K1
J1
A10
After a reset, TXTIP1[x] and TXTIP2[x] are high
impedance. The HIGHZ bit of the octant’s XLPG Line
Driver Configuration register must be programmed to logic
0 to remove the high impedance state.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2012568, Issue 3
29
Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
Pin Name
Type
Pin No. Function
TXRING1[1]
TXRING1[2]
TXRING1[3]
TXRING1[4]
TXRING1[5]
TXRING1[6]
TXRING1[7]
TXRING1[8]
Analogue
Output
A13
J22
P22
AB13
AB8
M1
G1
A8
A14
H22
R22
AB14
AB7
N1
F1
A7
TXRING2[1]
TXRING2[2]
TXRING2[3]
TXRING2[4]
TXRING2[5]
TXRING2[6]
TXRING2[7]
TXRING2[8]
Transmit Analogue Negative Pulse (TXRING1[8:1] and
TXRING2[8:1]). When the transmit analogue line interface
is enabled, the TXRING1[x] and TXRING2[x] analogue
outputs drive the transmit line pulse signal through an
external matching transformer. Both TXRING1[x] and
TXRING2[x] are normally connected to the negative lead
of the transformer primary. Two outputs are provided for
better signal integrity and must be shorted together on the
board.
After a reset, TXRING1[x] and TXRING2[x] are high
impedance. The HIGHZ bit of the octant’s XLPG Line
Driver Configuration register must be programmed to logic
0 to remove the high impedance state.
Receive Line Interface
RXTIP[1]
RXTIP[2]
RXTIP[3]
RXTIP[4]
RXTIP[5]
RXTIP[6]
RXTIP[7]
RXTIP[8]
Analogue
Input
G21
J21
R21
R19
R4
P1
J3
G3
Receive Analogue Positive Pulse (RXTIP[8:1]). When the
analogue receive line interface is enabled, RXTIP[x]
samples the received line pulse signal from an external
isolation transformer. RXTIP[x] is normally connected
directly to the positive lead of the receive transformer
secondary.
RXRING[1]
RXRING[2]
RXRING[3]
RXRING[4]
RXRING[5]
RXRING[6]
RXRING[7]
RXRING[8]
Analogue
Input
H19
J19
P19
U22
R3
P4
J4
H4
Receive Analogue Negative Pulse (RXRING[8:1]). When
the analogue receive line interface is enabled, RXRING[x]
samples the received line pulse signal from an external
isolation transformer. RXRING[x] is normally connected
directly to the negative lead of the receive transformer
secondary.
Input
D9
Crystal Clock Input (XCLK). This signal provides a stable,
global timing reference for the OCTLIU-SH internal
circuitry via an internal clock synthesizer. XCLK is a
nominally jitter free clock at 1.544 MHz in T1 mode and
2.048 MHz in E1 mode.
Timing Options Control
XCLK
In T1 mode, a 2.048 MHz clock may be used as a
reference. When used in this way, however, the jitter
transfer specifications in AT&T TR62411 may not be met.
RSYNC
Output
D8
Recovered Clock Synchronization Signal (RSYNC). This
output signal is the recovered, jitter attenuated, receiver
line rate clock (1.544 or 2.048 MHz) of one of the eight T1
or E1 channels or, optionally, the recovered, jitter
attenuated clock synchronously divided by 193 (T1 mode)
or 256 (E1 mode) to create a 8 kHz timing reference
signal. The default is to source RSYNC from octant #1.
When the OCTLIU-SH is in a loss of signal state, RSYNC
is derived from the XCLK input or, optionally, is held high.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2012568, Issue 3
30
Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
Pin Name
Type
Pin No. Function
Output
A5
Alarm Interface
LOS
Loss of Signal Alarm (LOS). This signal outputs the LOS
status of the 8 LIU octants in a serial format which repeats
every 8 XCLK cycles. The presence of the LOS status for
LIU #1 on this output is indicated by the LOS_L1 output
pulsing high. On the following XCLK cycle, the LOS
status for LIU #2 is output, then LIU #3, and so on.
When the microprocessor interface is enabled, the status
of the LOS alarm can also be determined by reading the
LOSV bit in the CDRC Interrupt Status register.
LOS is updated on the falling edge of XCLK.
LOS_L1
Output
C7
Loss of Signal LIU #1 indicator (LOS_L1). This signal is
pulsed high for one XCLK cycle every 8 XCLK cycles and
indicates that the LOS status for LIU #1 is being output on
LOS.
LOS_L1 is updated on the falling edge of XCLK.
Misc. Control Signals
RSTB
Input
A6
Active Low Reset (RSTB). This signal provides an
asynchronous OCTLIU-SH reset. RSTB is a Schmidt
triggered input with an internal pull up resistor.
TXHIZ/LLB
Input
C1
Transmitter tri-state enable (TXHIZ) or Line Loopback
enable (LLB). The mode of TXHIZ/LLB is controlled by
register 005H, bit 3 (TXHIZ_LLB_EN).
If this bit (TXHIZ_LLB_EN) is set to logic 0, setting
TXHIZ/LLB=1 forces each of the transmitters into a high
impedance state (i.e. TXTIP1[8:1], TXTIP2[8:1],
TXRING1[8:1] and TXRING2[8:1]).
Optionally, if TXHIZ_LLB_EN is set to logic 1, setting
TXHIZ/LLB=1 forces each of the LIU’s into line loopback.
When line loopback is enabled the recovered data is
internally directed to the digital inputs of the transmit jitter
attenuator.
E22
E21
E20
F19
D22
D21
D20
E19
C22
C21
C20
Address Bus (A[10:0]). This bus selects specific registers
during OCTLIU-SH register accesses.
A22
Address Latch Enable (ALE). This signal is active high
and latches the address bus contents, A[10:0], when low.
When ALE is high, the internal address latches are
transparent. ALE allows the OCTLIU-SH to interface to a
multiplexed address/data bus. The ALE input has an
internal pull up resistor.
Microprocessor Interface
A[0]
A[1]
A[2]
A[3]
A[4]
A[5]
A[6]
A[7]
A[8]
A[9]
A[10]
Input
ALE
Input
Signal A[10] selects between normal mode and test mode
register access. A[10] has an internal pull down resistor.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2012568, Issue 3
31
Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
Pin Name
Type
Pin No. Function
WRB
Input
D18
Active Low Write Strobe (WRB). This signal is low during
a OCTLIU-SH register write access. The D[7:0] bus
contents are clocked into the addressed register on the
rising WRB edge while CSB is low. Alternatively, the
D[7:0] bus contents are clocked into the addressed
register on the rising CSB edge while WRB is low.
RDB
Input
C19
Active Low Read Enable (RDB). This signal is low during
OCTLIU-SH register read accesses. The OCTLIU-SH
drives the D[7:0] bus with the contents of the addressed
register while RDB and CSB are low.
CSB
Input
B20
Active Low Chip Select (CSB). CSB must be low to
enable OCTLIU-SH register accesses. CSB must go high
at least once after power up to clear internal test modes.
If CSB is not used, it should be tied to an inverted version
of RSTB, in which case, RDB and WRB determine register
accesses.
INTB
Open-drain D17
Output
Active low Open-Drain Interrupt (INTB). This signal goes
low when an unmasked interrupt event is detected on any
of the internal interrupt sources. Note that INTB will
remain low until all active, unmasked interrupt sources are
acknowledged at their source at which time, INTB will
tristate.
D[0]
D[1]
D[2]
D[3]
D[4]
D[5]
D[6]
D[7]
I/O
B19
A20
A19
B18
A18
D15
B17
C15
BidirectionalBi-directional Data Bus (D[7:0]). This bus
provides OCTLIU-SH register read and write accesses.
PO
Output
D6
Programmable Output pin (PO). The programmable output
pin is controlled by register 00EH, bit 7 (PO_EN). When
PO_EN is set to logic 1, PO is set to logic 1. Otherwise
when PO_EN is set to logic 0 PO is set to logic 0.
PI
Input
B4
Programmable Input pin (PI). The status programmable
input pin is observed via register 00EH, bit 6 (PI_S).
Reading the PI_S register latches the state of the PI input.
RES_0[1]
Input
B7
This pin must be tied low for normal operation.
RES_0[2]
RES_0[3]
RES_0[4]
RES_0[5]
Analogue
I/O
V22
Y9
F3
B14
These pins must be connected to an analogue ground for
normal operation.
RES_0[6]
Input
B6
This pin must be tied to ground for normal operation.
Reserved Pins
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2012568, Issue 3
32
Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
Pin Name
Type
Pin No. Function
RES_0[7]
RES_0[8]
RES_0[9]
RES_0[10]
RES_0[11]
RES_0[12]
RES_0[13]
RES_0[14]
RES_0[15]
RES_0[16]
RES_0[17]
RES_0[18]
RES_0[19]
Input
B1
B3
C6
U3
U4
U19
V1
V2
V3
W2
W20
AA20
AA22
These pins must be tied low for normal operation.
RES_1[1]
Input
B16
This pin must be tied high for normal operation.
RES_NC[1]
RES_NC[2]
RES_NC[3]
RES_NC[4]
RES_NC[5]
RES_NC[6]
RES_NC[7]
RES_NC[8]
RES_NC[9]
RES_NC[10]
RES_NC[11]
RES_NC[12]
RES_NC[13]
RES_NC[14]
RES_NC[15]
RES_NC[16]
Output
A3
A4
B5
C4
C5
W6
W7
Y16
AA4
AA15
AA18
AA19
AB2
AB6
AB17
AB18
These pins must be left unconnected for normal operation.
TDO
Tristate
Output
B2
Test Data Output (TDO). This signal carries test data out
of the OCTLIU-SH via the IEEE 1149.1 test access port.
TDO is updated on the falling edge of TCK. TDO is a tristate output that is tri-stated except when scanning of data
is in progress.
TDI
Input
A1
Test Data Input (TDI). This signal carries test data into the
OCTLIU-SH via the IEEE 1149.1 test access port. TDI is
sampled on the rising edge of TCK. TDI has an internal
pull up resistor.
TCK
Input
C2
Test Clock (TCK). This signal provides timing for test
operations that can be carried out using the IEEE 1149.1
test access port.
TMS
Input
D3
Test Mode Select (TMS). This signal controls the test
operations that can be carried out using the IEEE 1149.1
test access port. TMS is sampled on the rising edge of
TCK. TMS has an internal pull up resistor.
JTAG Interface
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2012568, Issue 3
33
Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
Pin Name
Type
Pin No. Function
TRSTB
Input
E4
Active low Test Reset (TRSTB). This signal provides an
asynchronous OCTLIU-SH test access port reset via the
IEEE 1149.1 test access port. TRSTB is a Schmidt
triggered input with an internal pull up resistor. TRSTB
must be asserted during the power up sequence.
Note that if not used, TRSTB should be connected to the
RSTB input.
Analogue Power and Ground Pins
TAVD1[1]
TAVD1[2]
TAVD1[3]
TAVD1[4]
TAVD1[5]
TAVD1[6]
TAVD1[7]
TAVD1[8]
Analogue
Power
D12
L19
M19
W12
W11
M4
L4
D11
Transmit Analogue Power (TAVD1[8:1]). TAVD1[8:1]
provide power for the transmit LIU analogue circuitry.
TAVD1[8:1] should be connected to analogue +3.3 V.
TAVD2[1]
TAVD2[2]
TAVD2[3]
TAVD2[4]
TAVD2[5]
TAVD2[6]
TAVD2[7]
TAVD2[8]
Analogue
Power
C13
L21
N20
AA12
Y10
M2
K3
B11
Transmit Analogue Power (TAVD2[8:1], TAVD3[8:1]).
TAVD2[8:1] and TAVD3[8:1] supply power for the transmit
LIU current DACs. They should be connected to analogue
+3.3 V.
TAVD3[1]
TAVD3[2]
TAVD3[3]
TAVD3[4]
TAVD3[5]
TAVD3[6]
TAVD3[7]
TAVD3[8]
B13
L20
N21
Y12
AA10
M3
K2
C11
CAVD
Analogue
Power
C14
Clock Synthesis Unit Analogue Power (CAVD). CAVD
supplies power for the transmit clock synthesis unit.
CAVD should be connected to analogue +3.3 V.
TAVS1[1]
TAVS1[2]
TAVS1[3]
TAVS1[4]
TAVS1[5]
TAVS1[6]
TAVS1[7]
TAVS1[8]
Analogue
Ground
D13
K19
N19
W13
W10
N4
K4
D10
Transmit Analogue Ground (TAVS1[8:1]). TAVS1[8:1]
provide ground for the transmit LIU analogue circuitry.
TAVS1[8:1] should be connected to analogue GND.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2012568, Issue 3
34
Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
Pin Name
Type
Pin No. Function
TAVS2[1]
TAVS2[2]
TAVS2[3]
TAVS2[4]
TAVS2[5]
TAVS2[6]
TAVS2[7]
TAVS2[8]
Analogue
Ground
A15
K20
P21
Y13
AA9
N3
J2
C10
TAVS3[1]
TAVS3[2]
TAVS3[3]
TAVS3[4]
TAVS3[5]
TAVS3[6]
TAVS3[7]
TAVS3[8]
Transmit Analogue Ground (TAVS2[8:1], TAVS3[8:1]).
TAVS2[8:1] and TAVS3[8:1] supply ground for the
transmit LIU current DACs. They should be connected to
analogue GND.
C12
M21
M20
AA11
Y11
L2
L3
B12
CAVS
Analogue
Ground
D14
Clock Synthesis Unit Analogue Ground (CAVS). CAVS
supplies ground for the transmit clock synthesis unit.
CAVS should be connected to analogue GND.
RAVD1[1]
RAVD1[2]
RAVD1[3]
RAVD1[4]
RAVD1[5]
RAVD1[6]
RAVD1[7]
RAVD1[8]
Analogue
Power
G22
K21
P20
T20
R2
N2
H2
H3
Receive Analogue Power (RAVD1[8:1]). RAVD1[8:1]
supplies power for the receive LIU input equalizer.
RAVD1[8:1] should be connected to analogue +3.3 V.
RAVD2[1]
RAVD2[2]
RAVD2[3]
RAVD2[4]
RAVD2[5]
RAVD2[6]
RAVD2[7]
RAVD2[8]
Analogue
Power
F21
H21
R20
U20
T2
P2
E1
E2
Receive Analogue Power (RAVD2[8:1]). RAVD2[8:1]
supplies power for the receive LIU peak detect and slicer.
RAVD2[8:1] should be connected to analogue +3.3 V.
RAVS1[1]
RAVS1[2]
RAVS1[3]
RAVS1[4]
RAVS1[5]
RAVS1[6]
RAVS1[7]
RAVS1[8]
Analogue
Ground
F22
J20
T22
U21
T1
P3
G2
D1
Receive Analogue Ground (RAVS1[8:1]). RAVS1[8:1]
supplies ground for the receive LIU input equalizer.
RAVS1[8:1] should be connected to analogue GND.
RAVS2[1]
RAVS2[2]
RAVS2[3]
RAVS2[4]
RAVS2[5]
RAVS2[6]
RAVS2[7]
RAVS2[8]
Analogue
Ground
G20
H20
T21
T19
T3
R1
F2
G4
Receive Analogue Ground (RAVS2[8:1]). RAVS2[8:1]
supplies ground for the receive LIU peak detect and slicer.
RAVS2[8:1] should be connected to analogue GND.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2012568, Issue 3
35
Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
Pin Name
Type
Pin No. Function
QAVD[1]
QAVD[2]
QAVD[3]
QAVD[4]
Analogue
Power
F20
AA13
T4
B10
Quiet Analogue Power (QAVD[4:1]). QAVD[4:1] supplies
power for the core analogue circuitry. QAVD[4:1] should
be connected to analogue +3.3 V.
QAVS[1]
QAVS[2]
QAVS[3]
QAVS[4]
Analogue
Ground
V21
AA8
F4
B15
Quiet Analogue Ground (QAVS[4:1]). QAVS[4:1] supplies
ground for the core analogue circuitry. QAVS[4:1] should
be connected to analogue GND.
Digital Power and Ground Pins
VDD1V8[1]
VDD1V8[2]
VDD1V8[3]
VDD1V8[4]
Power
A16
B9
W9
AA14
Core Power (VDD1V8[4:1]). The VDD1V8[4:1] pins
should be connected to a well decoupled +1.8V DC power
supply.
VDD3V3[1]
VDD3V3[2]
VDD3V3[3]
VDD3V3[4]
VDD3V3[5]
VDD3V3[6]
VDD3V3[7]
VDD3V3[8]
VDD3V3[9]
VDD3V3[10]
VDD3V3[11]
VDD3V3[12]
VDD3V3[13]
VDD3V3[14]
VDD3V3[15]
VDD3V3[16]
VDD3V3[17]
VDD3V3[18]
VDD3V3[19]
Power
A2
B8
B21
B22
C17
C18
D2
D7
G19
W3
W16
W17
W19
Y7
Y15
Y20
AA3
AB1
AB4
I/O Power (VDD3V3[19:1]). The VDD3V3[19:1] pins
should be connected to a well decoupled +3.3V DC power
supply.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2012568, Issue 3
36
Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
Pin Name
Type
Pin No. Function
VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
Ground
A17
A21
C3
C8
C9
C16
D5
D16
D19
E3
U1
V20
W14
Y3
Y6
Y18
AA2
AA6
AA7
AA16
AA17
AB3
AB20
AB21
AB22
Ground (VSS [25:1]). The VSS[25:1] pins should be
connected to Ground.
NC1
NC2
Open
D4
W4
These pins must be left unconnected.
Notes on Pin Descriptions:
1.
All OCTLIU-SH inputs and bi-directionals present minimum capacitive loading.
2.
All OCTLIU-SH inputs and bi-directionals, when configured as inputs, tolerate TTL logic levels.
3.
All OCTLIU-SH outputs and bi-directionals have at least 8 mA drive capability, except the LOS,
LOS_L1, TDO, which have at least 6 mA drive capability. The transmit analogue outputs (TXTIP and
TXRING) have built-in short circuit current limiting.
4.
Inputs RSTB, ALE, TMS, TDI and TRSTB have internal pull-up resistors.
5.
Inputs A[10], RES_0[1], and RES_0[6] have internal pull-down resistors.
6.
All unused inputs should be connected to GROUND.
7.
The 3.3 Volt power pins (i.e., TAVD1, TAVD2, TAVD3, CAVD, RAVD1, RAVD2, QAVD, and VDD3V3)
will be collectively referred to as VDDall33 in this document.
8.
Power to VDDall33 should be applied before power to the VDD1V8 pins is applied. Similarly, power
to the VDD1V8 pins should be removed before power to VDDall33 is removed.
9.
The VDDall33 voltage level should not be allowed to drop below the VDD1V8 voltage level except
when VDD1V8 is not powered.
10. All analogue and digital ground pins (i.e. TAVS1, TAVS2, TAVS3, CAVS, QAVS, RAVS1, RAVS2 and
VSS) must be connected to a common low impedance ground plane.
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9
Functional Description
9.1
Octants
The OCTLIU-SH’s eight E1/T1 line interface units operate independently and can be
configured to operate uniquely. The octants do share a common XCLK clock input and internal
clock synthesizer; hence only a single CSU Configuration register is present. Additionally, all
octants share a common E1/T1B mode register bit to select between T1 and E1 operation.
9.2
Receive Interface
The analogue receive interface is configurable to operate in both E1 and T1 short-haul
applications. Short-haul T1 is defined as transmission over less than 655 ft of cable. Short-haul
E1 is defined as transmission on any cable that attenuates the signal by less than 6 dB, while
short-haul T1 cable attenuation is less than 3dB.
For short-haul, the slicing threshold is set to a fraction of the input signal’s peak amplitude, and
adapts to changes in this amplitude. The slicing threshold is programmable, but is typically
50% for DSX-1 and E1 applications. Abnormally low input signals are detected when the input
level is below a programmable threshold, which is typically 140 mV for E1 and 105 mV for T1.
9.3
Clock and Data Recovery (CDRC)
The Clock and Data Recovery function is provided by the Clock and Data Recovery (CDRC)
block. The CDRC provides clock and PCM data recovery, B8ZS and HDB3 decoding, line
code violation detection, and loss of signal detection. It recovers the clock from the incoming
RZ data pulses using a digital phase-locked-loop and reconstructs the NRZ data. Loss of signal
is indicated after a programmable threshold of consecutive bit periods of the absence of pulses
on both the positive and negative line pulse inputs and is cleared after the occurrence of a single
line pulse. An alternate loss of signal indication is provided which is cleared upon meeting ana
1-in-8 pulse density criteria for T1 and a 1-in-4 pulse density criteria for E1. If enabled, a
microprocessor interrupt is generated when a loss of signal is detected and when the signal
returns. A line code violation is defined as a bipolar violation (BPV) for AMI-coded signals, is
defined as a BPV that is not part of a zero substitution code for B8ZS-coded signals, and is
defined as a bipolar violation of the same polarity as the last bipolar violation for HDB3-coded
signals.
In T1 mode, the input jitter tolerance of the OCTLIU-SH complies with the Bellcore Document
TA-TSY-000170 and with the AT&T specification TR62411, as shown in Figure 6. The
tolerance is measured with a QRSS sequence (220-1 with 14 zero restriction).
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Octal Short-Haul E1/T1/J1 Line Interface Device
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Released
Figure 6 T1 Jitter Tolerance
10
Acceptable Range
Sine W ave
Jitter
Am plitude
P. to P. (UI)
Log Scale
1.0
Bellcore Spec.
0.3
AT&T Spec.
0.2
0.1
0.1
0.30 0.31
1.0
10
100
Sine W ave Jitter Frequency (kHz) Log Scale
For E1 applications, the input jitter tolerance complies with the ITU-T Recommendation G.823
“The Control of Jitter and Wander Within Digital Networks Which are Based on the 2048 kbit/s
Hierarchy.” Figure 7 illustrates this specification and the performance of the phase-locked loop.
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Figure 7 Compliance with ITU-T Specification G.823 for E1 Input Jitter
DPLL TOLERANCE
WITH AMI ENCODED
15
2 -1 PRBS
10
SINEWAVE
JITTER
AMPLITUDE
P. TO P. (UI)
LOG SCALE
DPLL TOLERANCE
WITH HDB3 ENCODED
15
2 -1 PRBS
IN SPEC
REGION
1.5
1
REC. G823
JITTER
TOLERANCE
SPECIFICATION
0.2
0.1
10
3
2.4
10
4
1.8
10
5
SINEWAVE JITTER FREQUENCY, Hz - LOG SCALE
9.4
Receive Jitter Attenuator (RJAT)
The Receive Jitter Attenuator (RJAT) digital PLL attenuates the jitter present on the
RXTIP/RXRING inputs. The attenuation is only performed when the RJATBYP register bit is a
logic 0.
The jitter characteristics of the Receive Jitter Attenuator (RJAT) are the same as the Transmit
Jitter Attenuator (TJAT).
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9.5
T1 Inband Loopback Code Detector (IBCD)
The T1 Inband Loopback Code Detection function is provided by the IBCD block. This block
detects the presence of either of two programmable INBAND LOOPBACK ACTIVATE and
DEACTIVATE code sequences in the receive data stream. Each INBAND LOOPBACK code
sequence is defined as the repetition of the programmed code in the PCM stream for at least 5.1
seconds. The detection algorithm tolerates more than the minimum number of discrepancy bits
in order to detect framed PCM data in the presence of a 10-2 bit error rate. The code sequence
detection and timing is compatible with the specifications defined in T1.403-1993, TA-TSY000312, and TR-TSY-000303. LOOPBACK ACTIVATE and DEACTIVATE code indication is
provided through internal register bits. An interrupt is generated to indicate when either code
status has changed.
9.6
T1 Pulse Density Violation Detector (PDVD)
The Pulse Density Violation Detection function is provided by the PDVD block. The block
detects pulse density violations of the requirement that there be N ones in each and every time
window of 8(N+1) data bits (where N can equal 1 through 23). The PDVD also detects periods
of 16 consecutive zeros in the incoming data. Pulse density violation detection is provided
through an internal register bit. An interrupt is generated to signal a 16 consecutive zero event,
and/or a change of state on the pulse density violation indication.
9.7
Performance Monitor Counters (PMON)
The Performance Monitor block accumulates line code violation events with a saturating
counter over consecutive intervals as defined by the period between writes to trigger registers
(typically 1 second). When the trigger is applied, the PMON transfers the counter value into
holding registers and resets the counter to begin accumulating events for the interval. The
counter is reset in such a manner that error events occurring during the reset are not missed.
Triggering a counter transfer within an octant is performed by writing to any counter register
location within the octant or by writing to the “Line Interface Interrupt Source #1 / PMON
Update” register.
9.8
Pseudo Random Binary Sequence Generation and Detection
(PRBS)
The Pseudo Random Binary Sequence Generator/Detector (PRBS) block is a software
selectable PRBS generator and checker for 211-1, 215-1 or 220-1 PRBS polynomials for use in the
T1 and E1 links. PRBS patterns may be generated and detected in either the transmit or receive
directions.
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The PRBS block can perform an auto synchronization to the expected PRBS pattern and
accumulates the total number of bit errors in two 24-bit counters. The error count accumulates
over the interval defined by successive writes to the Line Interface Interrupt Source #1 / PMON
Update register. When an accumulation is forced, the holding register is updated, and the
counter reset to begin accumulating for the next interval. The counter is reset in such a way that
no events are missed. The data is then available in the Error Count registers until the next
accumulation.
9.9
T1 Inband Loopback Code Generator (XIBC)
The T1 Inband Loopback Code Generator (XIBC) block generates a stream of inband loopback
codes (IBC) to be inserted into a T1 data stream. The IBC stream consists of continuous
repetitions of a specific code. The contents of the code and its length are programmable from 3
to 8 bits.
9.10 Pulse Density Enforcer (XPDE)
The Pulse Density Enforcer function is provided by the XPDE block. Pulse density
enforcement is enabled by a register bit within the XPDE.
This block monitors the digital output of the transmitter and detects when the stream is about to
violate the ANSI T1.403 12.5% pulse density rule over a moving 192-bit window. If a density
violation is detected, the block can be enabled to insert a logic 1 into the digital stream to ensure
the resultant output no longer violates the pulse density requirement. When the XPDE is
disabled from inserting logic 1s, the digital stream from the transmitter is passed through
unaltered.
9.11 Transmit Jitter Attenuator (TJAT)
The Transmit Jitter Attenuation function is provided by a digital phase lock loop and 80-bit deep
FIFO. The TJAT receives jittery, dual-rail data in NRZ format on two separate inputs, which
allows bipolar violations to pass through the block uncorrected. The incoming data streams are
stored in a FIFO timed to the transmit clock. The respective input data emerges from the FIFO
timed to the jitter attenuated clock.
The jitter attenuator generates the jitter-free 1.544 MHz or 2.048 MHz Transmit clock output by
adjusting the Transmit clock’s phase in 1/96 UI increments to minimize the phase difference
between the generated Transmit clock and input data clock to TJAT. Jitter fluctuations in the
phase of the input data clock are attenuated by the phase-locked loop within TJAT so that the
frequency of Transmit clock is equal to the average frequency of the input data clock. For T1
applications, to best fit the jitter attenuation transfer function recommended by TR 62411, phase
fluctuations with a jitter frequency above 5.7 Hz are attenuated by 6 dB per octave of jitter
frequency. Wandering phase fluctuations with frequencies below 5.7 Hz are tracked by the
generated Transmit clock. In E1 applications, the corner frequency is 7.6 Hz. To provide a
smooth flow of data out of TJAT, the Transmit clock is used to read data out of the FIFO.
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If the FIFO read pointer (timed to the Transmit clock) comes within one bit of the write pointer
(timed to the input data clock), TJAT will track the jitter of the input clock. This permits the
phase jitter to pass through unattenuated, inhibiting the loss of data.
Jitter Characteristics
The TJAT Block provides excellent jitter tolerance and jitter attenuation while generating
minimal residual jitter. It can accommodate up to 61 Uipp of input jitter at jitter frequencies
above 5.7 Hz (7.6 Hz for E1). For jitter frequencies below 5.7 Hz (7.6 Hz for E1), more
correctly called wander, the tolerance increases 20 dB per decade. In most applications the
TJAT Block will limit jitter tolerance at lower jitter frequencies only. For high frequency jitter,
above 10 kHz for example, other factors such as clock and data recovery circuitry may limit
jitter tolerance and must be considered. For low frequency wander, below 10 Hz for example,
other factors such as slip buffer hysteresis may limit wander tolerance and must be considered.
The TJAT block meets the stringent low frequency jitter tolerance requirements of AT&T
TR 62411 and thus allows compliance with this standard and the other less stringent jitter
tolerance standards cited in the references.
TJAT exhibits negligible jitter gain for jitter frequencies below 5.7 Hz (7.6 Hz for E1), and
attenuates jitter at frequencies above 5.7 Hz (7.6 Hz for E1) by 20 dB per decade. In most
applications, the TJAT block will determine jitter attenuation for higher jitter frequencies only.
Wander, below 10 Hz for example, will essentially be passed unattenuated through TJAT. Jitter,
above 10 Hz for example, will be attenuated as specified, however, outgoing jitter may be
dominated by the generated residual jitter in cases where incoming jitter is insignificant. This
generated residual jitter is directly related to the use of a 1/96 UI phase adjustment quantum.
TJAT meets the jitter attenuation requirements of AT&T TR 62411. The block allows the
implied jitter attenuation requirements for a TE or NT1 given in ANSI Standard T1.408, and the
implied jitter attenuation requirements for a type II customer interface given in ANSI T1.403 to
be met.
Jitter Tolerance
Jitter tolerance is the maximum input phase jitter at a given jitter frequency that a device can
accept without exceeding its linear operating range, or corrupting data. For TJAT, the input
jitter tolerance is 61 Unit Intervals peak-to-peak (Uipp) with a worst case frequency offset of
354 Hz. It is 80 Uipp with no frequency offset. The frequency offset is the difference between
the frequency of XCLK and that of the input data clock.
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Released
Figure 8 TJAT Jitter Tolerance
100
JAT
MIN.TOLER
ANCE
28
JITTER
AMPLITUDE,
UI pp
10
61
1.0
acceptable
0.4
unacceptable
0.1
0.01
1
10
100
1k
10k
100k
JITTER FREQUENCY, Hz
The accuracy of the XCLK frequency and that of the TJAT PLL reference input clock used to
generate the jitter-free Transmit clock output have an effect on the minimum jitter tolerance.
Given that the TJAT PLL reference clock accuracy can be ±200 Hz and that the XCLK input
accuracy can be ±50 ppm, the minimum jitter tolerance for various differences between the
frequency of PLL reference clock and XCLK are shown in Figure 9.
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Figure 9 TJAT Minimum Jitter Tolerance vs. XCLK Accuracy
70
68
66
65
JAT MIN.
JITTER
TOLERANCE, 60
UI pp
61
55
MAX. FREQUENCY
100
OFFSET
XCLK ACCURACY
200
250
0
32
300
354
100
Hz
,± ppm
Jitter Transfer
For T1 applications, the output jitter for jitter frequencies from 0 to 1.075.7 Hz (1.427.6 Hz for
E1) is no more than 0.1 dB greater than the input jitter, excluding residual jitter. Jitter
frequencies above 1.075.7 Hz (1.427.6 Hz for E1) are attenuated at a level of 6 dB per octave,
as shown in Figure 10. The figure is valid for the case where the N1 = F2FH in the TJAT Jitter
Attenuator Divider N1 Control register and N2 = F2FH in the TJAT Divider N2 Control
register.
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Released
Figure 10 TJAT Jitter Transfer
0
-10
JAT
JITTER
GAIN
dB
-20
62411
max
resp onse
62411
m in
43802
max
-30
-40
-50
1
1.07
10
100
1k
10k
JITTER FREQUENCY
Hz
T1
In the non-attenuating mode, when the FIFO is within one UI of overrunning or underrunning,
the tracking range is 1.48 MHz to 1.608 MHz.
The guaranteed linear operating range for the jittered input clock is 1.544 MHz ± 200 Hz with
worst case jitter (61 Uipp), and maximum system clock frequency offset (± 50 ppm). The
nominal range is 1.544 MHz ± 963 Hz with no jitter or system clock frequency offset.
E1
In the non-attenuating mode, when the FIFO is within one UI of overrunning or underrunning,
the tracking range is 2.13 MHz to 1.97 MHz.
The guaranteed linear operating range for the jittered input clock is 2.048 MHz ± 300 Hz with
worst case jitter (61 Uipp), and maximum system clock frequency offset (± 50 ppm). The
nominal range is 2.048 MHz ± 1277 Hz with no jitter or system clock frequency offset.
Jitter Generation
In the absence of input jitter, the output jitter shall be less than 0.025 Uipp. This complies with
the AT&T TR 62411 requirement of less than 0.025 Uipp of jitter generation.
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9.12 Line Transmitter
The line transmitter generates Alternate Mark Inversion (AMI) transmit pulses suitable for use
in the DSX-1 (short haul T1), short haul E1 environments. The voltage pulses are produced by
applying a current to a known termination (termination resistor plus line impedance). The use
of current (instead of a voltage driver) simplifies transmit Input Return Loss (IRL), transmit
short circuit protection (none needed) and transmit tri-stating.
The output pulse shape is synthesized digitally with current digital-to-analogue (DAC)
converters, which produce 24 samples per symbol. The current DAC’s produce differential
bipolar outputs that directly drive the TXTIP1[x], TXTIP2[x], TXRING1[x] and TXRING2[x]
pins. The current output is applied to a terminating resistor and line-coupling transformer in a
differential manner, which when viewed from the line side of the transformer produce the
output pulses at the required levels and ensures a small positive to negative pulse imbalance.
The pulse shape is user programmable. For T1 short haul, the cable length between the
OCTLIU-SH and the cross-connect (where the pulse template specifications are given) greatly
affects the resulting pulse shapes. Hence, the data applied to the converter must account for
different cable lengths. For CEPT E1 applications the pulse template is specified at the
transmitter, thus only one setting is required.
Refer to the Operation section for details on creating the synthesized pulse shape.
9.13 Timing Options (TOPS)
The Timing Options block provides a means of selecting the source of the internal input clock to
the TJAT block, and the reference clock for the TJAT digital PLL.
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9.14 External Analogue Interface Circuits
Figure 11 External Analogue Interface Circuits
VDD
D1
F1
TTip
TXTIP
1:n
inA
outB
R1
Z5
inB
TXRING
T1
outA
TRing
gnd
VDD
F3
RTip
RXTIP
inA
1:n
outB
Z6
R2
inB
RXRING
T2
outA
RRing
One of Eight
T1 or E1 LIUs
gnd
Figure 11 gives the recommended external protection circuitry for designs required to meet the
intra-building line protection standards including Telcordia Intrabuilding Protection
Requirements under GR-1089-CORE.
See Table 1 for the descriptions of components for Figure 11.
Table 1 External Component Descriptions
Component
Description
Part #
Source
R1
36.0Ω ±1%, 0.25W Resistor
ERJ-14NF36R0U
Panasonic
R2
27.0Ω ±1%, 0.25W Resistor
ERJ-14NF27R0U
Panasonic
D1
Surge Protector Diode Array
SRDA3.3-4
Semtech
T1 & T2
1:2 CT Transformers
T9023
Pulse
Z5 – Z6
Bi-directional Transient Surge Suppressors
P0720SC
Teccor
F1 & F3
Telecom/Time Lag Fuses
F1250T
Teccor
When operating in E1 mode with 75Ω cable, a 1:1.58 turns ratio transformer is specified in the
above table. It is in fact also possible to use a 1:2 turns ratio transformer, in which case the
value of R1 must be changed to 22.0Ω ±1% and the value of R2 must be changed to
18.0Ω ±1%.
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9.15 Scaleable Bandwidth Interconnect (SBI) Interface
The Scaleable Bandwidth Interconnect is a synchronous, time-division multiplexed bus
designed to transfer, in a pin-efficient manner, data belonging to a number of independently
timed links of varying bandwidth. The bus is timed to a reference 19.44MHz clock and a 2 kHz
(or fraction thereof) frame pulse. All sources and sinks of data on the bus are timed to the
reference clock and frame pulse.
Timing is communicated across the Scaleable Bandwidth Interconnect by floating data
structures. Payload indicator signals in the SBI control the position of the floating data structure
and therefore the timing. When sources are running faster than the SBI the floating payload
structure is advanced by an octet by passing an extra octet in the V3 octet locations (H3 octet
for DS3 mappings which are not used by the OCTLIU-SH). When the source is slower than the
SBI the floating payload is retarded by leaving the octet after the V3 or H3 octet unused. Both
these rate adjustments are indicated by the SBI control signals.
The SBI multiplexing structure is modeled on the SONET/SDH standards. The SONET/SDH
virtual tributary structure is used to carry T1/J1 and E1 links. Unchannelized DS3 payloads (not
used by OCTLIU-SH) follow a byte synchronous structure modeled on the SONET/SDH
format.
The SBI structure uses a locked SONET/SDH structure fixing the position of the TUG-3/TU-3
relative to the STS-3/STM-1 transport frame. The SBI is also of fixed frequency and alignment
as determined by the reference clock (REFCLK) and frame indicator signal (C1FP). Frequency
deviations are compensated by adjusting the location of the T1/J1/E1/DS3 channels using
floating tributaries as determined by the V5 indicator and payload signals (DV5, AV5, DPL and
APL). Note that the OCTLIU-SH always operates as a clock slave on the SBI ADD bus and as
a clock master on the SBI DROP bus, i.e. it does not support the AJUST_REQ and
DJUST_REQ timing adjustment request signals defined in the SBI bus specification.
The multiplexed links are separated into three Synchronous Payload Envelopes (SPE). Each
envelope may be configured independently to carry up to 28 T1/J1s, 21 E1s or a DS3. The
OCTLIU-SH may be configured to use any eight T1/J1 tributaries or any eight E1 tributaries
from any of the three SPE’s. The eight tributaries need not all be selected from the same SPE.
A single OCTLIU-SH device cannot, however, use T1/J1 and E1 tributaries simultaneously.
If the AC1FP signal is not generated the downstream transmit path blocks are disabled, since no
clock will be generated.
9.16 SBI Extracter and PISO
The SBI Extract block receives data from the SBI ADD BUS and converts it to serial bit
streams for transmission. The SBI Extract block may be configured to enable or disable
extraction of individual tributaries within the SBI ADD bus. It may also be configured to
generate an all-1s output to the transmit LIU when an alarm indication is signalled for a
particular tributary via the SBI bus.
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9.17 SBI Inserter and SIPO
The SBI Insert block receives serial data from the LIU octants and inserts it on the SBI DROP
BUS. The SBI Insert block may be configured to enable or disable transmission of individual
tributaries on to the SBI DROP bus.
9.18 JTAG Test Access Port
The JTAG Test Access Port block provides JTAG support for boundary scan. The standard
JTAG EXTEST, SAMPLE, BYPASS, IDCODE and STCTEST instructions are supported.
9.19 Microprocessor Interface
The Microprocessor Interface Block provides normal and test mode registers, the interrupt
logic, and the logic required to connect to the Microprocessor Interface. The normal mode
registers are required for normal operation, and test mode registers are used to enhance the
testability of the OCTLIU-SH.
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10
Normal Mode Register Description
Normal mode registers are used to configure and monitor the operation of the OCTLIU-SH.
Normal mode registers (as opposed to test mode registers) are selected when A[10] is low.
The Register Memory Map in Table 2 below shows where the normal mode registers are
accessed. The OCTLIU-SH contains 1 set of master configuration, SBI, and CSU registers and
8 sets of T1/E1 LIU registers. Where only 1 set is present, the registers apply to the entire
device. Where 8 sets are present, each set of registers apply to a single octant of the OCTLIUSH. By convention, where 8 sets of registers are present, address space 000H – 07FH applies to
octant #1, 080H – 0FFH applies to octant #2, etc, up to 380H – 3FFH for octant #8.
On reset the OCTLIU-SH defaults to T1 mode. For proper operation some register
configuration is expected. By default interrupts will not be enabled, and automatic alarm
generation is disabled.
Notes on Normal Mode Register Bits:
1.
Writing values into unused register bits has no effect. Reading back unused bits can produce either a
logic 1 or a logic 0; hence, unused register bits should be masked off by software when read.
2.
All configuration bits that can be written into can also be read back. This allows the processor
controlling the OCTLIU-SH to determine the programming state of the chip.
3.
Writeable normal mode register bits are cleared to zero upon reset unless otherwise noted.
4.
Writing into read-only normal mode register bit locations does not affect OCTLIU-SH operation unless
otherwise noted.
5.
Certain register bits are reserved. These bits are associated with functions that are unused in this
application. To ensure that the OCTLIU-SH operates as intended, reserved register bits must only be
written with their default values unless otherwise stated. Similarly, writing to reserved registers should
be avoided unless otherwise stated.
10.1 Normal Mode Register Memory Map
Table 2 Normal Mode Register Memory Map
Addr
Register
000H
Reset / Revision ID / Device ID
080H, 100H, 180H, 200H, 280H, 300H,
380H
Reserved
001H
Global Configuration / Clock Monitor
081H, 101H, 181H, 201H, 281H, 301H,
381H
Reserved
002H
Master Interrupt Source #1
082H, 102H, 182H, 202H, 282H, 302H,
382H
Reserved
003H
Master Interrupt Source #2
083H, 103H, 183H, 203H, 283H, 303H,
383H
Reserved
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
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Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
Addr
Register
004H
Master Test Control #1
084H, 104H, 184H, 204H, 284H, 304H,
384H
Reserved
005H
Master Test Control #2
085H, 105H, 185H, 205H, 285H, 305H,
385H
Reserved
006H
CSU Configuration
086H, 106H, 186H, 206H, 286H, 306H,
386H
Reserved
007H
CSU Reserved
087H, 107H, 187H, 207H, 287H, 307H,
387H
Reserved
008H, 088H, 108H, 188H, 208H, 288H,
308H, 388H
Receive Line Interface Configuration #1
009H, 089H, 109H, 189H, 209H, 289H,
309H, 389H
Receive Line Interface Configuration #2
00AH, 08AH, 10AH, 18AH, 20AH,
28AH, 30AH, 38AH
Transmit Line Interface Configuration
00BH, 08BH, 10BH, 18BH, 20BH,
28BH, 30BH, 38BH
Transmit Line Interface Timing Options / Clock Monitor / Pulse
Template Selection
00CH, 08CH, 10CH, 18CH, 20CH,
28CH, 30CH, 38CH
Line Interface Interrupt Source #1 / PMON Update
00DH, 08DH, 10DH, 18DH, 20DH,
28DH, 30DH, 38DH
Line Interface Interrupt Source #2
00EH, 08EH, 10EH, 18EH, 20EH,
28EH, 30EH, 38EH
Line Interface Diagnostics
00FH, 08FH, 10FH, 18FH, 20FH,
28FH, 30FH, 38FH
Line Interface PRBS Position
010H – 03FH
Reserved
090H – 0BFH
Reserved
110H – 13FH
Reserved
190H – 1BFH
Reserved
210H – 23FH
Reserved
290H – 2BFH
Reserved
310H
INSBI Control
311H
INSBI FIFO Underrun Interrupt Status
312H
INSBI FIFO Overrun Interrupt Status
313H
INSBI Page A Octant to Tributary Mapping #1
314H
INSBI Page A Octant to Tributary Mapping #2
315H
INSBI Page A Octant to Tributary Mapping #3
316H
INSBI Page A Octant to Tributary Mapping #4
317H
INSBI Page A Octant to Tributary Mapping #5
318H
INSBI Page A Octant to Tributary Mapping #6
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2012568, Issue 3
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Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
Addr
Register
319H
INSBI Page A Octant to Tributary Mapping #7
31AH
INSBI Page A Octant to Tributary Mapping #8
31BH
INSBI Page B Octant to Tributary Mapping #1
31CH
INSBI Page B Octant to Tributary Mapping #2
31DH
INSBI Page B Octant to Tributary Mapping #3
31EH
INSBI Page B Octant to Tributary Mapping #4
31FH
INSBI Page B Octant to Tributary Mapping #5
320H
INSBI Page B Octant to Tributary Mapping #6
321H
INSBI Page B Octant to Tributary Mapping #7
322H
INSBI Page B Octant to Tributary Mapping #8
323H
INSBI Link Enable
324H
INSBI Link Enable Busy
325H
INSBI Tributary Control #1
326H
INSBI Tributary Control #2
327H
INSBI Tributary Control #3
328H
INSBI Tributary Control #4
329H
INSBI Tributary Control #5
32AH
INSBI Tributary Control #6
32BH
INSBI Tributary Control #7
32CH
INSBI Tributary Control #8
32DH
INSBI Minimum Depth
32EH
INSBI FIFO Thresholds
32FH – 330H
INSBI Reserved
331H
INSBI Depth Check Interrupt Status
332H
INSBI Master Interrupt Status
333H – 33FH
INSBI Reserved
390H
EXSBI Control
391H
EXSBI FIFO Underrun Interrupt Status
392H
EXSBI FIFO Overrun Interrupt Status
393H
EXSBI Parity Error Interrupt Reason
394H
EXSBI Depth Check Interrupt Status
395H
EXSBI Master Interrupt Status
396H
EXSBI Minimum Depth
397H
EXSBI FIFO Thresholds
398H
EXSBI Link Enable
399H
EXSBI Link Enable Busy
39AH – 39FH
EXSBI Reserved
3A0H
EXSBI Tributary Control #1
3A1H
EXSBI Tributary Control #2
3A2H
EXSBI Tributary Control #3
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
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Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
Addr
Register
3A3H
EXSBI Tributary Control #4
3A4H
EXSBI Tributary Control #5
3A5H
EXSBI Tributary Control #6
3A6H
EXSBI Tributary Control #7
3A7H
EXSBI Tributary Control #8
3A8H
EXSBI Page A Octant to Tributary Mapping #1
3A9H
EXSBI Page A Octant to Tributary Mapping #2
3AAH
EXSBI Page A Octant to Tributary Mapping #3
3ABH
EXSBI Page A Octant to Tributary Mapping #4
3ACH
EXSBI Page A Octant to Tributary Mapping #5
3ADH
EXSBI Page A Octant to Tributary Mapping #6
3AEH
EXSBI Page A Octant to Tributary Mapping #7
3AFH
EXSBI Page A Octant to Tributary Mapping #8
3B0H
EXSBI Page B Octant to Tributary Mapping #1
3B1H
EXSBI Page B Octant to Tributary Mapping #2
3B2H
EXSBI Page B Octant to Tributary Mapping #3
3B3H
EXSBI Page B Octant to Tributary Mapping #4
3B4H
EXSBI Page B Octant to Tributary Mapping #5
3B5H
EXSBI Page B Octant to Tributary Mapping #6
3B6H
EXSBI Page B Octant to Tributary Mapping #7
3B7H
EXSBI Page B Octant to Tributary Mapping #8
3B8H – 3BFH
EXSBI Reserved
040H, 0C0H, 140H, 1C0H, 240H,
2C0H, 340H, 3C0H
Reserved
041H, 0C1H, 141H, 1C1H, 241H,
2C1H, 341H, 3C1H
Reserved
042H, 0C2H, 142H, 1C2H, 242H,
2C2H, 342H, 3C2H
T1 PDVD Reserved
043H, 0C3H, 143H, 1C3H, 243H,
2C3H, 343H, 3C3H
T1 PDVD Interrupt Enable/Status
044H, 0C4H, 144H, 1C4H, 244H,
2C4H, 344H, 3C4H
T1 XPDE Reserved
045H, 0C5H, 145H, 1C5H, 245H,
2C5H, 345H, 3C5H
T1 XPDE Interrupt Enable/Status
046H, 0C6H, 146H, 1C6H, 246H,
2C6H, 346H, 3C6H
T1 XIBC Control
047H, 0C7H, 147H, 1C7H, 247H,
2C7H, 347H, 3C7H
T1 XIBC Loopback Code
048H, 0C8H, 148H, 1C8H, 248H,
2C8H, 348H, 3C8H
RJAT Interrupt Status
049H, 0C9H, 149H, 1C9H, 249H,
2C9H, 349H, 3C9H
RJAT Reference Clock Divisor (N1) Control
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2012568, Issue 3
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Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
Addr
Register
04AH, 0CAH, 14AH, 1CAH, 24AH,
2CAH, 34AH, 3CAH
RJAT Output Clock Divisor (N2) Control
04BH, 0CBH, 14BH, 1CBH, 24BH,
2CBH, 34BH, 3CBH
RJAT Configuration
04CH, 0CCH, 14CH, 1CCH, 24CH,
2CCH, 34CH, 3CCH
TJAT Interrupt Status
04DH, 0CDH, 14DH, 1CDH, 24DH,
2CDH, 34DH, 3CDH
TJAT Reference Clock Divisor (N1) Control
04EH, 0CEH, 14EH, 1CEH, 24EH,
2CEH, 34EH, 3CEH
TJAT Output Clock Divisor (N2) Control
04FH, 0CFH, 14FH, 1CFH, 24FH,
2CFH, 34FH, 3CFH
TJAT Configuration
050H, 0D0H, 150H, 1D0H, 250H,
2D0H, 350H, 3D0H
IBCD Configuration
051H, 0D1H, 151H, 1D1H, 251H,
2D1H, 351H, 3D1H
IBCD Interrupt Enable/Status
052H, 0D2H, 152H, 1D2H, 252H,
2D2H, 352H, 3D2H
IBCD Activate Code
053H, 0D3H, 153H, 1D3H, 253H,
2D3H, 353H, 3D3H
IBCD Deactivate Code
054H, 0D4H, 154H, 1D4H, 254H,
2D4H, 354H, 3D4H
CDRC Configuration
055H, 0D5H, 155H, 1D5H, 255H,
2D5H, 355H, 3D5H
CDRC Interrupt Control
056H, 0D6H, 156H, 1D6H, 256H,
2D6H, 356H, 3D6H
CDRC Interrupt Status
057H, 0D7H, 157H, 1D7H, 257H,
2D7H, 357H, 3D7H
CDRC Alternate Loss of Signal
058H, 0D8H, 158H, 1D8H, 258H,
2D8H, 358H, 3D8H
PMON Interrupt Enable/Status
059H, 0D9H, 159H, 1D9H, 259H,
2D9H, 359H, 3D9H
PMON Reserved
05AH, 0DAH, 15AH, 1DAH, 25AH,
2DAH, 35AH, 3DAH
PMON Reserved
05BH, 0DBH, 15BH, 1DBH, 25BH,
2DBH, 35BH, 3DBH
PMON Reserved
05CH, 0DCH, 15CH, 1DCH, 25CH,
2DCH, 35CH, 3DCH
PMON Reserved
05DH, 0DDH, 15DH, 1DDH, 25DH,
2DDH, 35DH, 3DDH
PMON Reserved
05EH, 0DEH, 15EH, 1DEH, 25EH,
2DEH, 35EH, 3DEH
PMON LCV Count (LSB)
05FH, 0DFH, 15FH, 1DFH, 25FH,
2DFH, 35FH, 3DFH
PMON LCV Count (MSB)
060H, 0E0H, 160H, 1E0H, 260H,
2E0H, 360H, 3E0H
PRBS Generator/Checker Control
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
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Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
Addr
Register
061H, 0E1H, 161H, 1E1H, 261H,
2E1H, 361H, 3E1H
PRBS Checker Interrupt Enable/Status
062H, 0E2H, 162H, 1E2H, 262H,
2E2H, 362H, 3E2H
PRBS Pattern Select
063H, 0E3H, 163H, 1E3H, 263H,
2E3H, 363H, 3E3H
PRBS Reserved
064H, 0E4H, 164H, 1E4H, 264H,
2E4H, 364H, 3E4H
PRBS Error Count #1
065H, 0E5H, 165H, 1E5H, 265H,
2E5H, 365H, 3E5H
PRBS Error Count #2
066H, 0E6H, 166H, 1E6H, 266H,
2E6H, 366H, 3E6H
PRBS Error Count #3
067H, 0E7H, 167H, 1E7H, 267H,
2E7H, 367H, 3E7H
PRBS Reserved
068H, 0E8H, 168H, 1E8H, 268H,
2E8H, 368H, 3E8H
XLPG Control/Status
069H, 0E9H, 169H, 1E9H, 269H,
2E9H, 369H, 3E9H
XLPG Pulse Waveform Scale
06AH, 0EAH, 16AH, 1EAH, 26AH,
2EAH, 36AH, 3EAH
XLPG Pulse Waveform Storage Write Address #1
06BH, 0EBH, 16BH, 1EBH, 26BH,
2EBH, 36BH, 3EBH
XLPG Pulse Waveform Storage Write Address #2
06CH, 0ECH, 16CH, 1ECH, 26CH,
2ECH, 36CH, 3ECH
XLPG Pulse Waveform Storage Data
06DH, 0EDH, 16DH, 1EDH, 26DH,
2EDH, 36DH, 3EDH
XLPG Fuse Control
06EH, 0EEH, 16EH, 1EEH, 26EH,
2EEH, 36EH, 3EEH
XLPG Reserved
06FH, 0EFH, 16FH, 1EFH, 26FH,
2EFH, 36FH, 3EFH
XLPG Reserved
070H, 0F0H, 170H, 1F0H, 270H,
2F0H, 370H, 3F0H
RLPS Configuration and Status
071H, 0F1H, 171H, 1F1H, 271H,
2F1H, 371H, 3F1H
RLPS ALOS Detection/Clearance Threshold
072H, 0F2H, 172H, 1F2H, 272H,
2F2H, 372H, 3F2H
RLPS ALOS Detection Period
073H, 0F3H, 173H, 1F3H, 273H,
2F3H, 373H, 3F3H
RLPS ALOS Clearance Period
074H, 0F4H, 174H, 1F4H, 274H,
2F4H, 374H, 3F4H
RLPS Equalization Indirect Address
075H, 0F5H, 175H, 1F5H, 275H,
2F5H, 375H, 3F5H
RLPS Equalization Read/WriteB Select
076H, 0F6H, 176H, 1F6H, 276H,
2F6H, 376H, 3F6H
RLPS Equalizer Loop Status and Control
077H, 0F7H, 177H, 1F7H, 277H,
2F7H, 377H, 3F7H
RLPS Equalizer Configuration
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2012568, Issue 3
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Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
Addr
Register
078H, 0F8H, 178H, 1F8H, 278H,
2F8H, 378H, 3F8H
RLPS Equalization Indirect Data Register
079H, 0F9H, 179H, 1F9H, 279H,
2F9H, 379H, 3F9H
RLPS Equalization Indirect Data Register
07AH, 0FAH, 17AH, 1FAH, 27AH,
2FAH, 37AH, 3FAH
RLPS Indirect Data Register
07BH, 0FBH, 17BH, 1FBH, 27BH,
2FBH, 37BH, 3FBH
RLPS Indirect Data Register
07CH, 0FCH, 17CH, 1FCH, 27CH,
2FCH, 37CH, 3FCH
RLPS Voltage Thresholds #1
07DH, 0FDH, 17DH, 1FDH, 27DH,
2FDH, 37DH, 3FDH
RLPS Voltage Thresholds #2
07EH, 0FEH, 17EH, 1FEH, 27EH,
2FEH, 37EH, 3FEH
RLPS Reserved
07FH, 0FFH, 17FH, 1FFH, 27FH,
2FFH, 37FH, 3FFH
RLPS Reserved
400H – 7FFH
Reserved for Test
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2012568, Issue 3
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Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
Register 000H: Reset / Revision ID / Device ID
Bit
Type
Function
Default
Bit 7
R/W
RESET
0
Bit 6
R
TYPE[2]
1
Bit 5
R
TYPE[1]
0
Bit 4
R
TYPE[0]
0
Bit 3
R
ID[3]
0
Bit 2
R
ID[2]
0
Bit 1
R
ID[1]
0
Bit 0
R
ID[0]
1
RESET
The RESET bit implements a software reset. If the RESET bit is a logic 1, the OCTLIU-SH
is held in reset. This bit is not self-clearing; therefore, a logic 0 must be written to bring the
OCTLIU-SH out of reset. Holding the OCTLIU-SH in a reset state effectively puts it into a
low-power, stand-by mode. A hardware reset clears the RESET bit, thus deasserting the
software reset. The RESET bit must be set for at least 100ns.
TYPE
The device identification bits, TYPE[2:0], are set to a fixed value of “100” representing the
OCTLIU-SH.
ID
The version identification bits, ID[3:0], are set to a fixed value representing the version
number of the OCTLIU-SH.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2012568, Issue 3
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Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
Register 001H: Global Configuration / Clock Monitor
Bit
Type
Function
Default
Bit 7
R
XCLKA
X
Bit 6
R
REFCLKA
X
Bit 5
R/W
SIMUL_REGWR
0
Bit 4
R/W
Reserved
0
Bit 3
R/W
RSYNC_SEL[2]
0
Bit 2
R/W
RSYNC_SEL[1]
0
Bit 1
R/W
RSYNC_SEL[0]
0
Bit 0
R/W
E1/T1B
0
XCLKA
The XCLK active (XCLKA) bit detects low to high transitions on the XCLK input.
XCLKA is set high on a rising edge of XCLK, and is set low when this register is read. A
lack of transitions is indicated by the register bit reading low. This register bit may be read
at periodic intervals to detect clock failures.
REFCLKA
The REFCLK active (REFCLKA) bit detects low to high transitions on the REFCLK input.
REFCLKA is set high on a rising edge of REFCLK, and is set low when this register is
read. A lack of transitions is indicated by the register bit reading low. This register bit may
be read at periodic intervals to detect clock failures.
SIMUL_REGWR
The Simultaneous Register Write (SIMUL_REGWR) bit enables registers for all 8 octants
to be written simultaneously. When SIMUL_REGWR is set high, a write to an octant
register will result in the same data also being written simultaneously to the corresponding
registers belonging to the other 7 octants. When SIMUL_REGWR is set low, a write to a
register will result in the addressed register, and that register only, being written.
Note:
•
SIMUL_REGWR must be set low prior to reading any OCTLIU-SH register.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2012568, Issue 3
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Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
RSYNC_SEL[2:0]
The RSYNC Select register bits, RSYNC_SEL[2:0], select the source of the RSYNC
OCTLIU-SH output.
When RSYNC_SEL[2:0] = “000”, octant #1 is selected as the source.
When RSYNC_SEL[2:0] = “001”, octant #2 is selected as the source.
When RSYNC_SEL[2:0] = “010”, octant #3 is selected as the source.
When RSYNC_SEL[2:0] = “011”, octant #4 is selected as the source.
When RSYNC_SEL[2:0] = “100”, octant #5 is selected as the source.
When RSYNC_SEL[2:0] = “101”, octant #6 is selected as the source.
When RSYNC_SEL[2:0] = “110”, octant #7 is selected as the source.
When RSYNC_SEL[2:0] = “111”, octant #8 is selected as the source.
E1/T1B
The global E1/T1B bit selects the operating mode of all eight of the OCTLIU-SH octants.
If E1/T1B is logic 1, the 2.048 Mbit/s E1 mode is selected for all eight octants. If E1/T1B
is logic 0, the 1.544 Mbit/s T1 mode is selected for all eight octants.
RESERVED
The reserved bit must be set to the default value for normal operation.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2012568, Issue 3
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Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
Register 002H: Master Interrupt Source #1
Bit
Type
Function
Default
Bit 7
R
LIU[8]
X
Bit 6
R
LIU[7]
X
Bit 5
R
LIU[6]
X
Bit 4
R
LIU[5]
X
Bit 3
R
LIU[4]
X
Bit 2
R
LIU[3]
X
Bit 1
R
LIU[2]
X
Bit 0
R
LIU[1]
X
LIU[8:1]
The LIU[8:1] register bits allow software to determine which octant’s LIU(s) is/are
producing an interrupt on the INTB output pin. A logic 1 indicates an interrupt is being
produced from the corresponding octant.
Reading this register does not remove the interrupt indication; within the corresponding
octant, the corresponding block’s interrupt status register must be read to remove the
interrupt indication.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2012568, Issue 3
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Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
Register 003H: Master Interrupt Source #2
Bit
Type
Function
Default
Bit 7
Unused
X
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
Unused
X
Bit 3
Unused
X
Bit 2
Unused
X
Bit 1
R
EXSBI
X
Bit 0
R
INSBI
X
INSBI, EXSBI
The INSBI and EXSBI register bits allow software to determine whether the INSBI and/or
EXSBI blocks are producing an interrupt on the INTB output pin. A logic 1 indicates an
interrupt is being produced from the corresponding block.
Reading this register does not remove the interrupt indication; the corresponding block’s
interrupt status register must be read to remove the interrupt indication.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2012568, Issue 3
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Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
Register 004H: Master Test Control #1
Bit
Type
Function
Default
Bit 7
W
Reserved
X
Bit 6
W
Reserved
X
Bit 5
W
Reserved
X
Bit 4
W
Reserved
X
Bit 3
W
Reserved
0
Bit 2
R/W
Reserved
0
Bit 1
W
HIZDATA
0
Bit 0
R/W
HIZIO
0
This register is used to select OCTLIU-SH test features. All bits, except for 7,6,5 and 4 are
reset to zero by a hardware reset of the OCTLIU, a software reset of the OCTLIU does not
affect the state of the bits in this register.
HIZIO, HIZDATA
The HIZIO and HIZDATA bits control the tri-state modes of the OCTLIU-SH. While the
HIZIO bit is a logic 1, all digital output pins of the OCTLIU-SH except TDO and the data
bus are held in a high-impedance state. The microprocessor interface is still active. While
the HIZDATA bit is a logic 1, the data bus is held in a high-impedance state which inhibits
microprocessor read cycles. Note that the HIZIO and HIZDATA have no affect on the
analog transmit outputs (TXTIP1[1:8], TXTIP2[1:8], TXRING1[1:8] and TXRING2[1:8]).
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2012568, Issue 3
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Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
Register 005H: Master Test Control #2
Bit
Type
Function
Default
Bit 7
R/W
Reserved
0
Bit 6
R/W
Reserved
0
Bit 5
R/W
Reserved
0
Bit 4
R/W
Reserved
0
Bit 3
R/W
TXHIZ_LLB_EN
0
Bit 2
R/W
Unused
X
Bit 1
R/W
Unused
X
Bit 0
R/W
Unused
X
TXHIZ_LLB_EN
Transmitter tri-state or line loopback pin enable. This register bit is used to control the
functionality of the TXHIZ/LLB pin. If TXHIZ_LLB_EN set to logic 0, the TXHIZ/LLB
pin can be used to force the analogue transmitter outputs (TXTIP1[1:8], TXTIP2[1:8],
TXRING1[1:8] and TXRING2[1:8]) into a high impedance state. Otherwise, if set to logic
1 the TXHIZ/LLB pin may be used to force all 8 octants into line loopback mode.
RESERVED
These bits must be 0 for correct operation.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2012568, Issue 3
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Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
Register 006H: CSU Configuration
Bit
Type
Function
Default
Bit 7
R/W
CSU_RESET
0
Bit 6
R/W
IDDQ_EN
0
Bit 5
Unused
X
Bit 4
Unused
X
Bit 3
R
CSU_LOCK
X
Bit 2
R/W
MODE[2]
0
Bit 1
R/W
MODE[1]
0
Bit 0
R/W
MODE[0]
0
MODE[2:0]
The MODE[2:0] selects the mode of the CSU. Table 3 indicates the required XCLK
frequency, and output frequencies for each mode.
Table 3 Clock Synthesis Mode
MODE[2:0]
XCLK frequency
Transmit clock frequency
000
2.048 MHz
2.048 MHz
001
1.544 MHz
1.544 MHz
01X
Reserved
Reserved
10X
Reserved
Reserved
110
Reserved
Reserved
111
2.048 MHz
1.544 MHz
CSU_LOCK
The CSU_LOCK bit can be used to determine whether or not the embedded clock synthesis
unit (CSU) has achieved phase and frequency lock to XCLK. If the CSU_LOCK bit is
polled repetitively and is persistently a logic 1, then the divided down synthesized clock
frequency is within 244 ppm of the XCLK frequency. A persistent logic 0 may indicate a
mismatch between the actual and expected XCLK frequency or a problem with the
analogue supplies (CAVS and CAVD).
IDDQ_EN
The IDDQ enable bit (IDDQ_EN) is used to configure the embedded CSU for IDDQ tests.
When IDDQ_EN is a logic 1, or the IDDQEN bit in the Master Test Control #1 register is a
logic 1, the digital outputs of the CSU are pulled to ground. When either the IDDQ_EN bit
or IDDQEN bit is set to logic 1, the HIGHZ bit in the XLPG Line Driver Configuration
register must also be set to logic 1.
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Telecom Standard Product Data Sheet
Released
CSU_RESET
Setting the CSU_RESET bit to logic 1 causes the embedded CSU to be forced to a
frequency much lower than normal operation.
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Telecom Standard Product Data Sheet
Released
Register 008H, 088H, 108H, 188H, 208H, 288H, 308H, 388H:
Receive Line Interface Configuration #1
Bit
Type
Function
Default
Bit 7
R/W
LLB_AIS
0
Bit 6
R/W
AUTO_LLB
0
Bit 5
R/W
LOS_SBI
0
Bit 4
R/W
LOS_AIS
0
Bit 3
R/W
Reserved
0
Bit 2
R/W
BPV
0
Bit 1
R/W
Reserved
0
Bit 0
R/W
RX_PRBS_ENB
1
LLB_AIS
When the LLB_AIS bit is set to logic 1, the LIU will generate AIS on the receive data
output whenever line loopback is active. When the LLB_AIS bit is set to logic 0, the LIU
receive path will operate normally, regardless of whether or not line loopback is active. If
LLB_AIS is logic 0, AIS may be inserted manually via the RAIS register bit.
AUTO_LLB
When the AUTO_LLB bit is set to logic 1, the LIU will activate and deactivate line
loopback automatically upon detection of the line loopback activate/deactivate codes by the
IBCD. The AUTO_LLB bit is only valid in T1 mode and must be set to logic 0 in E1 mode.
If line loopback is entered using the activate code (AUTO_LLB), the LINELB bit (in the
Line Interface Diagnostics Register) cannot be used to exit the loopback state. Likewise, if
the loopback state is entered via the LINELB bit, the deactivate code cannot be used to exit
the loopback state.
LOS_SBI
The LOS_SBI bit enables the indication of loss of signal over the SBI interface. When
LOS_SBI is set to logic 1, loss of signal will result in the ALM (alarm) bit of the affected
tributary being asserted on the SBI interface. When LOS_SBI is set to logic 0, the
tributary’s ALM bit will be set to 0.
LOS_AIS
If the LOS_AIS bit is logic 1, AIS is inserted in the receive path for the duration of a loss of
signal condition. The AIS condition will be de-asserted once a pulse is detected by the
CDRC. If LOS_AIS is logic 0, AIS may be inserted manually via the RAIS register bit.
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Telecom Standard Product Data Sheet
Released
BPV
In T1 mode, the BPV bit enables only bipolar violations to indicate line code violations and
be accumulated in the PMON LCV Count Registers. When BPV is set to logic 1, BPVs
(provided they are not part of a valid B8ZS signature if B8ZS line coding is used) generate
an LCV indication and increment the PMON LCV counter. When BPV is set to logic 0,
both BPVs (provided they are not part of a valid B8ZS signature if B8ZS line coding is
used) and excessive zeros (EXZ) generate an LCV indication and increment the PMON
LCV counter. Excessive zeros is a sequence of zeros greater than fifteen bits long for an
AMI-coded signal and greater than seven bits long for a B8ZS-coded signal.
In E1 mode, the BPV bit enables only bipolar violations to indicate line code violations and
be accumulated in the PMON LCV Count Registers. (The O162 bit in the CDRC
Configuration register provides two E1 LCV definitions.) When BPV is set to logic 1,
BPVs (provided they are not part of a valid HDB3 signature if HDB3 line coding is used)
generate an LCV indication and increment the PMON LCV counter. When BPV is set to
logic 0, both BPVs (provided they are not part of a valid HDB3 signature if HDB3 line
coding is used) and excessive zeros (EXZ) generate an LCV indication and increment the
PMON LCV counter. Excessive zeros is a sequence of zeros greater than four bits long for
an HDB3-coded signal. When HDB3 decoding is disabled in E1 mode (AMI bit in CDRC
Configuration Register = 1), excessive zeros do not generate an LCV indication regardless
of the setting of the BPV bit.
RX_PRBS_ENB
The Receive Pseudo Random Generator Enable (RX_PRBS_ENB) register bit must be set
to logic 0 (active low) when the corresponding RX_GEN register bit in the Line Interface
PRBS Position register is set to logic 1. Otherwise RX_PRBS_GEN must be set to logic 1.
RESERVED
These bits must set to logic 0 for correct operation.
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Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
Register 009H, 089H, 109H, 189H, 209H, 289H, 309H, 389H:
Receive Line Interface Configuration #2
Bit
Type
Function
Default
Bit 7
R/W
RJATBYP
1
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
Unused
X
Bit 3
Unused
X
Bit 2
R/W
RSYNC_ALOSB
0
Bit 1
R/W
RSYNC_MEM
0
Bit 0
R/W
RSYNCSEL
0
RJATBYP
The RJATBYP bit disables jitter attenuation in the receive direction. When receive jitter
attenuation is not being used, setting RJATBYP to logic 1 will reduce the latency through
the receiver section by typically 40 bits. When RJATBYP is set to logic 0, the LIU’s
RSYNC output is jitter attenuated. When the RJAT is bypassed, the octant’s RSYNC is not
jitter attenuated.
RSYNC_ALOSB
The RSYNC_ALOSB bit controls the source of the loss of signal condition used to control
the behaviour of the receive reference presented on the RSYNC output. If
RSYNC_ALOSB is a logic 0, analogue loss of signal is used. If RSYNC_ALOSB is a
logic 1, digital loss of signal is used. When the LIU is in a loss of signal state, the RSYNC
output is derived from XCLK or held high, as determined by the RSYNC_MEM bit. When
the LIU is not in a loss of signal state, the RSYNC output is derived from the receive
recovered clock of the selected octant.
The octant to be used as the source of RSYNC is determined by the RSYNC_SEL[2:0] bits.
RSYNC_MEM
The RSYNC_MEM bit controls the octant’s RSYNC output under a loss of signal condition
(as determined by the RSYNC_ALOSB register bit). When RSYNC_MEM is a logic 1, the
octant’s RSYNC output is held high during a loss of signal condition. When
RSYNC_MEM is a logic 0, the octant’s RSYNC output is derived from the CSU 1x line
rate clock during a loss of signal condition.
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Telecom Standard Product Data Sheet
Released
RSYNCSEL
The RSYNCSEL bit selects the frequency of the receive reference presented on the octant’s
RSYNC output. If RSYNCSEL is a logic 1, the octant’s RSYNC will be an 8 kHz clock. If
RSYNCSEL is a logic 0, the octant’s RSYNC will be an 1.544 MHz (T1) or 2.048 MHz
(E1) clock.
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Document No.: PMC-2012568, Issue 3
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Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
Register 00AH, 08AH, 10AH, 18AH, 20AH, 28AH, 30AH, 38AH:
Transmit Line Interface Configuration
Bit
Type
Function
Default
Bit 7
R/W
TJATBYP
0
Bit 6
R/W
TAISEN
0
Bit 5
R/W
TAUXP
0
Bit 4
R/W
SBI_AIS
1
Bit 3
R/W
Reserved
0
Bit 2
R/W
AMI
0
Bit 1
R/W
Reserved
0
Bit 0
R/W
Reserved
1
TJATBYP
The TJATBYP bit enables the transmit jitter attenuator to be removed from the transmit data
path. When the transmit jitter attenuator is bypassed, the latency through the transmitter
section is reduced by typically 40 bits.
TAISEN
The TAISEN bit enables the interface to generate an unframed all-ones AIS alarm on the
TXTIP[n] and TXRING[n]. When TAISEN is set to logic 1, the bipolar TXTIP[n] and
TXRING[n] outputs are forced to pulse alternately, creating an all-ones signal. The
transition to transmitting AIS on the TXTIP[n] and TXRING[n] outputs is done in such a
way as to avoid introducing any bipolar violations.
The diagnostic digital loopback point is prior to the AIS insertion point.
TAUXP
The TAUXP bit enables the interface to generate an unframed alternating zeros and ones
(i.e. 010101…) auxiliary pattern (AUXP) on the TXTIP[n] and TXRING[n]. When
TAUXP is set to logic 1, the bipolar TXTIP[n] and TXRING[n] outputs are forced to pulse
alternately every other cycle. The transition to transmitting AUXP on the TXTIP[n] and
TXRING[n] outputs is done in such a way as to avoid introducing any bipolar violations.
The diagnostic digital loopback point is prior to the AUXP insertion point.
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Telecom Standard Product Data Sheet
Released
SBI_AIS
The SBI_AIS bit enables the insertion of AIS in the transmit path in response to an alarm
indication from the SBI interface. When SBI_AIS is set to logic 1, setting the ALM (alarm)
bit of a tributary on the SBI interface causes the bipolar TXTIP[n] and TXRING[n] outputs
to be forced to pulse alternately, creating an all-ones signal. The transition to transmitting
AIS on the TXTIP[n] and TXRING[n] outputs is done in such a way as to avoid introducing
any bipolar violations.
The diagnostic digital loopback point is prior to the AIS insertion point.
AMI
The AMI bit enables AMI line coding. If AMI is set to a logic 1, the LIU will perform AMI
line encoding on the input data stream. If AMI is set to a logic 0, the LIU will perform
B8ZS (if operating in T1 mode) or HDB3 (if operating in E1 mode) line encoding on the
input data stream.
RESERVED:
These bits must be set to their default value for correct operation.
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Document No.: PMC-2012568, Issue 3
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Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
Register 00BH, 08BH, 10BH, 18BH, 20BH, 28BH, 30BH, 38BH:
Transmit Timing Options / Clock Monitor / Pulse Template Selection
Bit
Type
Function
Default
Bit 7
R/W
PT_SEL[3]
0
Bit 6
R/W
PT_SEL[2]
0
Bit 5
R/W
PT_SEL[1]
0
Bit 4
R/W
PT_SEL[0]
0
Bit 3
R
UnusedReserved
X
Bit 2
R/W
OCLKSEL
0
Bit 1
R/W
PLLREF[1]
0
Bit 0
R/W
PLLREF[0]
0
PT_SEL[3:0]
The Pulse Template Selection (PT_SEL[3:0]) bits determine which of the twelve pulse
template waveforms stored in the XLPG is used to generate transmit data pulses on the
TXTIP[n] and TXRING[n] outputs. PT_SEL[3:0] must be set to a value between 0 and 11.
OCLKSEL
The OCLKSEL bit selects the source of the Transmit Jitter Attenuator FIFO output clock
signal.
Table 4 TJAT FIFO Output Clock Source
OCLKSEL
Source of FIFO Output Clock
0
The TJAT FIFO output clock is connected to the internal jitterattenuated 1.544 MHz or 2.048 MHz clock.
1
The TJAT FIFO output clock is connected to the FIFO input clock.
In this mode the jitter attenuation is disabled and the input clock
must be jitter-free. PLLREF[1:0] must be set to “00” in this mode.
PLLREF
The PLLREF bit selects the source of the Transmit Jitter Attenuator phase locked loop
reference signal as follows:
Table 5 TJAT PLL Source
PLLREF[1:0]
Source of PLL Reference
00
TJAT FIFO input clock (either the transmit clock or the receive recovered clock, as
selected by LINELB)
01
Receive recovered clock
1X
CSU transmit clock (see Table 3)
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Document No.: PMC-2012568, Issue 3
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Telecom Standard Product Data Sheet
Released
Upon reset of the OCTLIU-SH, the OCLKSEL and PLLREF bits are cleared to zero, selecting
jitter attenuation with transmit line clock referenced to the transmit clock (the SBI tributary
clock). Figure 12 illustrates the various bit setting options, with the reset condition highlighted.
Note:
•
The recommended mode of operation is:
OCLKSEL = 0,
PLLREF[1:0] = 00 for intrinsically timed applications, or
PLLREF[1:0] = 01 for loop-timed applications.
Figure 12 Transmit Timing Options
1
Transmit data in
0
TJAT
FIFO
SBI transmit clock
0
1
FIFO input
data clock
TJATBYP
Transmit line clock
OCLKSEL or TJATBYP
0
LINELB
FIFO output
data clock
00
Receive recovered clock
01
CSU transmit clock
Transmit data out
TJAT
PLL
1
"Jitter-free" line rate clock
(1.544MHz or 2.048MHz)
24x line rate clock
for pulse generation
1X
PLLREF
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Document No.: PMC-2012568, Issue 3
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Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
Register 00CH, 08CH, 10CH, 18CH, 20CH, 28CH, 30CH, 38CH:
Line Interface Interrupt Source #1 / PMON Update
Bit
Type
Function
Default
Bit 7
R
PMON
X
Bit 6
R
PRBS
X
Bit 5
R
IBCD
X
Bit 4
R
PDVD
X
Bit 3
R
XPDE
X
Bit 2
R
TJAT
X
Bit 1
R
RJAT
X
Bit 0
R
CDRC
X
This register allows software to determine the block which produced the interrupt on the INTB
output pin. A logic 1 indicates an interrupt was produced from the block.
Reading this register does not remove the interrupt indication; the corresponding block’s
interrupt status register must be read to remove the interrupt indication.
Writing any value to this register causes the octant’s performance monitor LCV counter and
PRBS error counter to be updated.
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Document No.: PMC-2012568, Issue 3
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Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
Register 00DH, 08DH, 10DH, 18DH, 20DH, 28DH, 30DH, 38DH:
Line Interface Interrupt Source #2
Bit
Type
Function
Default
Bit 7
R
Reserved
X
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
Unused
X
Bit 3
Unused
X
Bit 2
Unused
X
Bit 1
Unused
X
RLPS
X
Bit 0
R
This register allows software to determine the block that produced the interrupt on the INTB
output pin. A logic 1 indicates an interrupt was produced from the block.
Reading this register does not remove the interrupt indication; the corresponding block’s
interrupt status register must be read to remove the interrupt indication.
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Document No.: PMC-2012568, Issue 3
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Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
Register 00EH, 08EH, 10EH, 18EH, 20EH, 28EH, 30EH, 38EH:
Line Interface Diagnostics
Bit
Type
Function
Default
Bit 7
R/W
PO_EN
0
Bit 6
R
PI_S
X
Bit 5
R/W
LCVINS
0
Bit 4
R/W
LINELB
0
Bit 3
R/W
RAIS
0
Bit 2
R/W
DDLB
0
Bit 1
R/W
Reserved
0
Bit 0
R/W
Reserved
0
PO_EN
The programmable output enable (PO_EN) register bit is used to control the state of the PO
output pin. When PO_EN is set to logic 1 the PO output is set to logic 1. Otherwise when
PO_EN is set to logic 0 the PO output is set to logic 0.
Note:
•
This register bit is only available in register 00EH.
PI_S
The programmable input status (PI_S) register bit is used to read the status of the PI input.
Reading this register latches the state of the PI input.
Note:
•
This register bit is only available in register 00EH.
LCVINS
The LCVINS bit introduces a single line code violation on the transmitted data stream. In
B8ZS, the violation is generated by masking the first violation pulse of a B8ZS signature.
In AMI, one pulse is sent with the same polarity as the previous pulse. In HDB3, the
violation is generated by causing the next HDB3-code generated bipolar violation pulse to
be of the same polarity as the previous bipolar violation. To generate another violation, this
bit must first be written to 0 and then to logic 1 again. At least one bit period should elapse
between writing LCVINS 0 and writing it 1 again, or vice versa, if an error is to be
successfully inserted.
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Document No.: PMC-2012568, Issue 3
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Telecom Standard Product Data Sheet
Released
LINELB
The LINELB bit selects the line loopback mode, where the recovered data are internally
directed to the digital inputs of the transmit jitter attenuator. The data sent to the TJAT is
the recovered data from the output of the CDRC block. When LINELB is set to logic 1, the
line loopback mode is enabled. When LINELB is set to logic 0, the line loopback mode is
disabled. Note that when line loopback is enabled, to correctly attenuate the jitter on the
receive clock, the contents of the TJAT Reference Clock Divisor and Output Clock Divisor
registers should be programmed to 2FFH in both T1 and E1 mode / FFH in E1 mode and
the Transmit Timing Options register should be cleared to all zeros. Only one of LINELB
and DDLB can be enabled at any one time.
If line loopback is entered using the activate code (AUTO_LLB in Receive Line Interface
Configuration #1 register), the LINELB bit cannot be used to exit the loopback state.
Likewise, if the loopback state is entered via the LINELB bit, the deactivate code cannot be
used to exit the loopback state.
RAIS
When the RAIS bit is set to logic 1, the receive output data stream of the octant is forced to
all ones.
DDLB
The DDLB bit selects the diagnostic digital loopback mode, where the octant is configured
to internally direct the output of the TJAT to the inputs of the receiver section. The dual-rail
RZ outputs of the TJAT are directed to the dual-rail inputs of the CDRC. When DDLB is
set to logic 1, the diagnostic digital loopback mode is enabled. When DDLB is set to
logic 0, the diagnostic digital loopback mode is disabled. Only one of LINELB and DDLB
can be enabled at any one time.
RESERVED
These bits must be a logic 0 for correct operation.
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Document No.: PMC-2012568, Issue 3
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Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
Register 00FH, 08FH, 10FH, 18FH, 20FH, 28FH, 30FH, 38FH: Line Interface PRBS Position
Bit
Type
Function
Default
Bit 7
Unused
X
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
Unused
X
Bit 3
Unused
X
Bit 2
R/W
TX_GEN
0
Bit 1
R/W
RX_GEN
0
Bit 0
R/W
TX_DET
0
TX_GEN
The Transmit Path Generate, TX_GEN, bit controls the output of the PRBS generator.
When TX_GEN is set to logic 1, the PRBS generator output is inserted into the transmit
path. When TX_GEN is set to logic 0, the transmit path functions normally.
Note:
•
TX_GEN and RX_GEN PRBS generation cannot be enabled at the same time. The transmit
PRBS data has priority over the inband code data stream generated by the XIBC.
RX_GEN
The Receive Path Generate, RX_GEN, bit controls the output of the PRBS generator.
When RX_GEN is set to logic 1, the PRBS generator output is inserted into the receive
path. When RX_GEN is set to logic 0, the receive path functions normally. The
corresponding RX_PRBS_ENB register bit in the Receive Line Interface Configuration #1
register must be set logic 0 when RX_GEN is set to logic 1.
Note:
•
TX_GEN and RX_GEN PRBS generation cannot be enabled at the same time.
TX_DET
The Transmit Path Detect, TX_DET, bit controls the input of the PRBS checker. When
TX_DET is set to logic 1, the PRBS checker monitors the transmit path. When TX_DET is
set to logic 0, the PRBS detector monitors the receive path.
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Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
Register 310H: INSBI Control
Bit
Type
Function
Default
Bit 7
R/W
APAGE
0
Bit 6
R/W
DC_ENBL
1
Bit 5
R/W
DC_INT_EN
0
Bit 4
R/W
FIFO_OVRE
0
Bit 3
R/W
FIFO_UDRE
0
Bit 2
R/W
Bit 1
Bit 0
R/W
TS_EN
0
Unused
X
SBI_PAR_CTL
1
SBI_PAR_CTL
The SBI_PAR_CTL bit is used to configure the Parity mode for generation of the SBI data
parity signal, DDP as follows:
o
o
When SBI_PAR_CTL is a ‘0’ parity will be even.
When SBI_PAR_CTL is a ‘1’ parity will be odd.
TS_EN
The TS_EN bit is used to enable the LIU octant data stream to SBI tributary mapping
capability.
o
o
When TS_EN is a ‘0’, the mapping is fixed to a one to one mapping and is not
programmable. The 8 LIU data streams are mapped to tributaries 1 to 8 of SPE #1
within the SBI structure.
When TS_EN is a ‘1’, LIU octant data stream to SBI tributary mapping is enabled and
is specified by the contents of the INSBI Tributary Mapping registers.
FIFO_UDRE
The FIFO_UDRE bit is used to enable/disable the generation of an interrupt when a FIFO
underrun is detected.
o
o
When FIFO_UDRE is a ‘0’ underrun interrupt generation is disabled.
When FIFO_UDRE is a ‘1’ underrun interrupt generation is enabled.
FIFO_OVRE
The FIFO_OVRE bit is used to enable/disable the generation of an interrupt when a FIFO
overrun is detected.
o
o
When FIFO_OVRE is a ‘0’ overrun interrupt generation is disabled.
When FIFO_OVRE is a ‘1’ overrun interrupt generation is enabled.
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Telecom Standard Product Data Sheet
Released
DC_INT_EN
This bit is set to enable the generation of an interrupt when either of the following events
occurs:
o
o
A Depth Check error
An external resynchronization event occurs on the DC1FP signal
DC_ENBL
This bit enables depth check resets. The depth checker periodically monitors the link FIFO
depths and compares them against the read and write pointers. Discrepancies are reported in
the Depth Checker Interrupt Status Register. If DC_ENBL is ‘1’, the affected link is
automatically reset. If DC_ENBL is ‘0’, the link is not reset.
APAGE
The tributary mapping register active page select bit (APAGE) controls the selection of one
of two pages of tributary mapping registers. When APAGE is set low, the configuration in
page A of the tributary mapping registers is used to associate SBI tributaries to LIU octant
data streams. When APAGE is set high, the configuration in page B of the tributary
mapping registers is used to associate SBI tributaries to LIU octant data streams. When
APAGE changes state, any data streams where the mapping registers do not match are
automatically reset.
Note:
•
The APAGE bit should not be changed when TS_EN is logic 0.
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Telecom Standard Product Data Sheet
Released
Register 311H: INSBI FIFO Underrun Interrupt Status
Bit
Type
Function
Default
Bit 7
Unused
X
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
R
LINK[3]
0
Bit 3
R
LINK[2]
0
Bit 2
R
LINK[1]
0
Bit 1
R
LINK[0]
0
Bit 0
R
FIFO_UDRI
0
Back to back reads of this register must be at least 250 ns apart.
This Underrun interrupt register is the output of a priority encoder of the underrun history of all
links. The most significant links have the highest priority and will be reported first if underruns
simultaneously occur on multiple links.
If bit 0 is zero, no links have entered underrun since the last read, and all pending underrun
notifications have been reported. Bits 1-4 should be ignored.
If bit 0 is one, the register contents are valid, and indicate a link has entered underrun since the
last read, or a prior notification was still pending. Continue reading this register, recording all
entries, until bit 0 is zero, indicating that no more pending entries are present.
Note: If a tributary is misbehaving so that it frequently enters underrun, the reporting of the
multiple underruns can prevent the reporting of underrun on lower priority links. Such
misbehaving links should be disabled (ENBLx=0, Register 323H) to obtain the complete
underrun history.
FIFO_UDRI
This bit is set when a FIFO underrun is detected. It is cleared when the register is read (but
may be set again immediately thereafter if a further underrun report is pending).
LINK[3:0]
The LINK[3:0] field is used to specify the LIU octant data stream associated with the FIFO
buffer in which the underrun was detected. LINK[3:0] should only be looked at when
FIFO_UDRI is a ‘1’. Valid values of LINK[3:0] are from 1 to 8.
This register will contain the interrupt status even if the corresponding interrupt enable is
not set. Interrupts are reported such that link 1 has highest priority.
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Document No.: PMC-2012568, Issue 3
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Telecom Standard Product Data Sheet
Released
Register 312H: INSBI FIFO Overrun Interrupt Status
Bit
Type
Function
Default
Bit 7
Unused
X
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
R
LINK[3]
0
Bit 3
R
LINK[2]
0
Bit 2
R
LINK[1]
0
Bit 1
R
LINK[0]
0
Bit 0
R
FIFO_OVRI
0
Back to back reads of this register must be at least 250 ns apart.
This Overrun interrupt register is the output of a priority encoder of the overrun history of all
links. The most significant links have the highest priority and will be reported first if overruns
simultaneously occur on multiple links.
If bit 0 is zero, no links have overrun since the last read, and all pending overrun notifications
have been reported. Bits 1-4 should be ignored.
If bit 0 is one, the register contents are valid, and indicate a link has overrun since the last read,
or a prior notification was still pending. Continue reading this register, recording all entries,
until bit 0 is zero, indicating that no more pending entries are present.
Note: If a tributary is misbehaving so that it frequently overruns, the reporting of the multiple
overruns can prevent the reporting of overruns on lower priority links. Such misbehaving links
should be disabled (ENBLx=0, Register 323H) to obtain the complete overrun history.
FIFO_OVRI
This bit is set when a FIFO overrun is detected. It is cleared when the register is read (but
may be set again immediately thereafter if a further overrun report is pending).
LINK[3:0]
The LINK[3:0] field is used to specify the LIU octant data stream associated with the FIFO
buffer in which the overrun was detected. LINK[3:0] should only be looked at when
FIFO_OVRI is a ‘1’. Valid values of LINK[3:0] are from 1 to 8.
This register will contain the interrupt status even if the corresponding interrupt enable is
not set. Interrupts are reported such that link 1 has highest priority.
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Document No.: PMC-2012568, Issue 3
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Telecom Standard Product Data Sheet
Released
Register 313H – 31AH: INSBI Page A Octant to Tributary Mapping #1 - #8
Bit
Type
Bit 7
Function
Default
Unused
X
Bit 6
R/W
SPE[1]
0
Bit 5
R/W
SPE[0]
0
Bit 4
R/W
TRIB[4]
0
Bit 3
R/W
TRIB[3]
0
Bit 2
R/W
TRIB[2]
0
Bit 1
R/W
TRIB[1]
0
Bit 0
R/W
TRIB[0]
0
SPE[1:0] and TRIB[4:0]
The SPE[1:0] and TRIB[4:0] fields are used to specify the LIU octant data stream to SBI
tributary mapping when APAGE is set to 0. The output of the octant corresponding to the
register (1-8) is mapped to the SPE and tributary specified by the value of SPE[1:0] and
TRIB[4:0]. Valid values of SPE[1:0] are from 1 to 3. Valid values of TRIB[4:0] are from 1
to 28 in T1 mode and from 1 to 21 in E1 mode.
Note:
•
The mapping of more than one tributary to the same LIU octant data stream or more than one LIU
octant data stream to the same tributary is not allowed. Special care must be taken to ensure that all
LIU octants and tributaries are uniquely mapped when using multiple OCTLIU-SH’s on the same SBI
bus. Failure to do so will result in bus contention.
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Document No.: PMC-2012568, Issue 3
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Telecom Standard Product Data Sheet
Released
Register 31BH – 322H: INSBI Page B Octant to Tributary Mapping #1 - #8
Bit
Type
Bit 7
Function
Default
Unused
X
Bit 6
R/W
SPE[1]
0
Bit 5
R/W
SPE[0]
0
Bit 4
R/W
TRIB[4]
0
Bit 3
R/W
TRIB[3]
0
Bit 2
R/W
TRIB[2]
0
Bit 1
R/W
TRIB[1]
0
Bit 0
R/W
TRIB[0]
0
SPE[1:0] and TRIB[4:0]
The SPE[1:0] and TRIB[4:0] fields are used to specify the LIU octant data stream to SBI
tributary mapping when APAGE is set to 1. The output of the octant corresponding to the
register (1-8) is mapped to the SPE and tributary specified by the value of SPE[1:0] and
TRIB[4:0]. Valid values of SPE[1:0] are from 1 to 3. Valid values of TRIB[4:0] are from 1
to 28 in T1 mode and from 1 to 21 in E1 mode.
Note:
•
The mapping of more than one tributary to the same LIU octant data stream or more than one LIU
octant data stream to the same tributary is not allowed. Special care must be taken to ensure that all
LIU octants and tributaries are uniquely mapped when using multiple OCTLIU-SH’s on the same SBI
bus. Failure to do so will result in bus contention.
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Document No.: PMC-2012568, Issue 3
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Telecom Standard Product Data Sheet
Released
Register 323H: INSBI Link Enable
Bit
Type
Function
Default
Bit 7
R/W
ENBL8
0
Bit 6
R/W
ENBL7
0
Bit 5
R/W
ENBL6
0
Bit 4
R/W
ENBL5
0
Bit 3
R/W
ENBL4
0
Bit 2
R/W
ENBL3
0
Bit 1
R/W
ENBL2
0
Bit 0
R/W
ENBL1
0
ENBL1 – ENBL8
The ENBLx bits are used to enable the LIU octant data streams. Setting the ENBL bit for a
particular LIU octant data stream enables the INSBI8 to take data from the octant and
transmit that data to the SBI tributary mapped to that stream.
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Document No.: PMC-2012568, Issue 3
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Telecom Standard Product Data Sheet
Released
Register 324H: INSBI Link Enable Busy
Bit
Function
Default
Bit 7
Unused
X
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
Unused
X
Bit 3
Unused
X
Bit 2
Unused
X
Bit 1
Unused
X
BUSY
0
Bit 0
Type
R
BUSY
A write to the INSBI Link Enable Register sets BUSY to ‘1’. BUSY is cleared to ‘0’
approximately three REFCLK cycles later after the register contents have been
synchronized to REFCLK.
The user must check that BUSY is ‘0’ before writing to the INSBI Link Enable Register.
Following a reset, BUSY will be ‘1’ until startup circuitry has finished automatically
initializing certain RAMs within INSBI.
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Document No.: PMC-2012568, Issue 3
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Telecom Standard Product Data Sheet
Released
Register 325H – 32CH: INSBI Tributary Control #1 – #8
Bit
Type
Function
Default
Bit 7
Unused
X
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
R/W
Reserved
0
Bit 3
R/W
Reserved
0
Bit 2
R/W
Reserved
1
Bit 1
R/W
Reserved
0
Bit 0
R/W
Reserved
0
A tributary control register should only be written when the associated ENBLx bit is ‘0’.
RESERVED:
The reserved bits must be set to their default value for correct operation of the OCTLIU-SH
device.
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Document No.: PMC-2012568, Issue 3
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Telecom Standard Product Data Sheet
Released
Register 32DH: INSBI Minimum Depth
Bit
Type
Function
Default
Bit 7
Unused
X
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
Unused
X
Bit 3
R/W
MIN_DEP[3]
0
Bit 2
R/W
MIN_DEP[2]
1
Bit 1
R/W
MIN_DEP[1]
1
Bit 0
R/W
MIN_DEP[0]
1
MIN_DEP [3:0]
The MIN_DEPTH[3:0] bits specify the tributary FIFO Minimum Depth, i.e. the depth that
must be reached before the FIFO reader starts to take data from the FIFO.
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Document No.: PMC-2012568, Issue 3
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Telecom Standard Product Data Sheet
Released
Register 32EH: INSBI FIFO Thresholds
Bit
Type
Function
Default
Bit 7
R/W
MIN_THR[3]
0
Bit 6
R/W
MIN_THR[2]
1
Bit 5
R/W
MIN_THR[1]
1
Bit 4
R/W
MIN_THR[0]
0
Bit 3
R/W
MAX_THR[3]
1
Bit 2
R/W
MAX_THR[2]
1
Bit 1
R/W
MAX_THR[1]
1
Bit 0
R/W
MAX_THR[0]
0
MIN_THR[3:0]
The MIN_THR[3:0] bits specify the tributary FIFO minimum threshold, i.e. the FIFO depth
below which a positive justification is performed.
Note:
•
The recommended value for MIN_THR[3:0] is “0010”, which is not the default value following
device reset.
MAX_THR[3:0]
The MAX_THR[3:0] bits specify the tributary FIFO maximum threshold, i.e. the FIFO
depth which when exceeded will cause a negative justification.
Note:
•
The recommended value for MAX_THR[3:0] is “1010”, which is not the default value following
device reset.
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Document No.: PMC-2012568, Issue 3
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Telecom Standard Product Data Sheet
Released
Register 331H: INSBI Depth Check Interrupt Status
Bit
Type
Function
Default
Bit 7
Unused
X
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
R
LINK[3]
0
Bit 3
R
LINK[2]
0
Bit 2
R
LINK[1]
0
Bit 1
R
LINK[0]
0
Bit 0
R
DCR_INTI
0
DCR_INTI
This bit is set when a depth check error is detected. It is cleared when the register is read
(but may be set again immediately thereafter if a further depth check error report is
pending).
LINK[3:0]
The LINK[3:0] field is used to specify the LIU octant data stream associated with the FIFO
buffer in which the depth check error was detected. LINK[3:0] should only be looked at
when DCR_INTI is a ‘1’. Valid values for LINK[3:0] are from 1 to 8.
This register will contain the interrupt status even if the corresponding interrupt enable is
not set. Link 1 has the highest priority.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2012568, Issue 3
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Telecom Standard Product Data Sheet
Released
Register 332H: INSBI Master Interrupt Status
Bit
Function
Default
Bit 7
Unused
X
Bit 6
Unused
X
Bit 5
Type
R
Bit 4
Bit 3
R
Bit 2
R
Bit 1
Bit 0
R
DCR_INTI_SHDW
0
Unused
X
FIFO_UDRI_SHDW
0
FIFO_OVRI_SHDW
0
Unused
X
C1FP_SYNC_INTI
0
C1FP_SYNC_INTI
This bit is set when a DC1FP realignment has been detected. It is cleared when the register
is read.
FIFO_OVRI_SHDW
This bit is a shadow of the FIFO_OVRI bit in the INSBI FIFO Over Run Interrupt Status
Register. It is set when the FIFO_OVRI bit is set and the interrupt enable FIFO_OVRE is
set. Reading this register has no affect on the interrupt status.
FIFO_UDRI_SHDW
This bit is a shadow of the FIFO_UDRI bit in the INSBI FIFO Under Run Interrupt Status
Register. It is set when the FIFO_UDRI bit is set and the interrupt enable FIFO_UDRE is
set. Reading this register has no affect on the interrupt status.
DCR_INTI_SHDW
This bit is a shadow of the DCR_INTI bit in the INSBI Depth Check Interrupt Status
Register. It is set when the DCR_INTI bit is set and the interrupt enable DCR_INT_EN is
set. Reading this register has no affect on the interrupt status.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2012568, Issue 3
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Telecom Standard Product Data Sheet
Released
Register 390H: EXSBI Control
Bit
Type
Function
Default
Bit 7
R/W
APAGE
0
Bit 6
R/W
DC_ENBL
1
Bit 5
R/W
DC_INT_EN
0
Bit 4
R/W
FIFO_OVRE
0
Bit 3
R/W
FIFO_UDRE
0
Bit 2
R/W
TS_EN
0
Bit 1
R/W
SBI_PERR_EN
0
Bit 0
R/W
SBI_PAR_CTL
1
SBI_PAR_CTL
The SBI_PAR_CTL bit is used to configure the Parity mode for checking of the SBI data
parity signal, ADP as follows:
o
o
When SBI_PAR_CTL is a ‘0’ parity will be even.
When SBI_PAR_CTL is a ‘1’ parity will be odd.
SBI_PERR_EN
The SBI_PERR_EN bit is used to enable the SBI Parity Error interrupt generation
o
o
When SBI_PERR_EN is ‘0’ SBI Parity Error Interrupts will be disabled
When SBI_PERR_EN is ‘1’ SBI Parity Error Interrupts will be enabled
In both cases the SBI Parity checker logic will update the SBI Parity Error Interrupt Reason
Register.
TS_EN
The TS_EN bit is used to enable the SBI tributary to LIU octant data stream mapping
capability.
o
o
When TS_EN is a ‘0’, the mapping is fixed to a one to one mapping and is not
programmable. Tributaries 1 to 8 of SPE #1 within the SBI structure are mapped to the
8 LIU data streams.
When TS_EN is a ‘1’, SBI tributary to LIU octant data stream mapping is enabled and
is specified by the contents of the EXSBI Tributary Mapping registers.
FIFO_UDRE
The FIFO_UDRE bit is used to enable/disable the generation of an interrupt when a FIFO
underrun is detected.
o
When FIFO_UDRE is a ‘0’ underrun interrupt generation is disabled.
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Telecom Standard Product Data Sheet
Released
o
When FIFO_UDRE is a ‘1’ underrun interrupt generation is enabled.
FIFO_OVRE
The FIFO_OVRE bit is used to enable/disable the generation of an interrupt when a FIFO
overrun is detected.
o
o
When FIFO_OVRE is a ‘0’ overrun interrupt generation is disabled.
When FIFO_OVRE is a ‘1’ overrun interrupt generation is enabled.
DC_INT_EN
This bit is set to enable the generation of an interrupt when either of the following events
occurs:
o
o
A Depth Check error
An external resynchronization event occurs on the AC1FP signal
DC_ENBL
This bit enables depth check resets. The depth checker periodically monitors the link FIFO
depths and compares them against the read and write pointers. Discrepancies are reported in
the Depth Checker Interrupt Status Register. If DC_ENBL is ‘1’, the affected link is
automatically reset. If DC_ENBL is ‘0’, the link is not reset.
APAGE
The tributary mapping active page select bit (APAGE) controls the group of mapping
registers used to associate SBI tributaries and LIU octant data streams. When mapping is
enabled and APAGE is low, the A set of mapping registers (0x3A8 to 0x3AF) is used.
When mapping is enabled and APAGE is high, the B set of mapping registers (0x3B0 to
0x3B7) is used. When APAGE changes state, any data streams where the mapping registers
do not match are automatically reset.
Note:
•
The APAGE should not be changed when TS_EN is logic 0.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2012568, Issue 3
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Telecom Standard Product Data Sheet
Released
Register 391H: EXSBI FIFO Underrun Interrupt Status
Bit
Type
Function
Default
Bit 7
Unused
X
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
R
LINK[3]
0
Bit 3
R
LINK[2]
0
Bit 2
R
LINK[1]
0
Bit 1
R
LINK[0]
0
Bit 0
R
FIFO_UDRI
0
Back to back reads of this register must be at least 250 ns apart.
This Underrun interrupt register is the output of a priority encoder of the underrun history of all
links. The most significant links have the highest priority and will be reported first if underruns
simultaneously occur on multiple links.
If bit 0 is zero, no links have entered underrun since the last read, and all pending underrun
notifications have been reported. Bits 1-4 should be ignored.
If bit 0 is one, the register contents are valid, and indicate a link has entered underrun since the
last read, or a prior notification was still pending. Continue reading this register, recording all
entries, until bit 0 is zero, indicating that no more pending entries are present.
Note: If a tributary is misbehaving so that it frequently enters underrun, the reporting of the
multiple underruns can prevent the reporting of underrun on lower priority links. Such
misbehaving links should be disabled (LINK_ENBL[x]=0, Register 398H) to obtain the
complete underrun history.
FIFO_UDRI
This bit is set when a FIFO underrun is detected. It is cleared when the register is read.
LINK[3:0]
The LINK[3:0] field is used to specify the LIU octant data stream associated with the FIFO
buffer in which the underrun was detected. LINK[3:0] should only be looked at when
FIFO_UDRI is a ‘1’. Valid values of LINK[3:0] are from 1 to 8.
This register will contain the interrupt status even if the corresponding interrupt enable is
not set. Link 1 has the highest priority.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2012568, Issue 3
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Telecom Standard Product Data Sheet
Released
Register 392H: EXSBI FIFO Overrun Interrupt Status
Bit
Type
Function
Default
Bit 7
Unused
X
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
R
LINK[3]
0
Bit 3
R
LINK[2]
0
Bit 2
R
LINK[1]
0
Bit 1
R
LINK[0]
0
Bit 0
R
FIFO_OVRI
0
Back to back reads of this register must be at least 250 ns apart.
This Overrun interrupt register is the output of a priority encoder of the overrun history of all
links. The most significant links have the highest priority and will be reported first if overruns
simultaneously occur on multiple links.
If bit 0 is zero, no links have overrun since the last read, and all pending overrun notifications
have been reported. Bits 1-4 should be ignored.
If bit 0 is one, the register contents are valid, and indicate a link has overrun since the last read,
or a prior notification was still pending. Continue reading this register, recording all entries,
until bit 0 is zero, indicating that no more pending entries are present.
Note: If a tributary is misbehaving so that it frequently overruns, the reporting of the multiple
overruns can prevent the reporting of overruns on lower priority links. Such misbehaving links
should be disabled (LINK_ENBL[x]=0, Register 398H) to obtain the complete overrun history.
FIFO_OVRI
This bit is set when a FIFO overrun is detected. It is cleared when the register is read.
LINK[3:0]
The LINK[3:0] field is used to specify the LIU octant data stream associated with the FIFO
buffer in which the over-run was detected. LINK[3:0] should only be looked at when
FIFO_OVRI is a ‘1’. Valid values of LINK[3:0] are from 1 to 8.
This register will contain the interrupt status even if the corresponding interrupt enable is
not set. Link 1 has the highest priority.
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Document No.: PMC-2012568, Issue 3
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Telecom Standard Product Data Sheet
Released
Register 393H: EXSBI Parity Error Interrupt Reason
Bit
Type
Function
Default
Bit 7
R
SPE[1]
0
Bit 6
R
SPE[0]
0
Bit 5
R
TRIB[4]
0
Bit 4
R
TRIB[3]
0
Bit 3
R
TRIB[2]
0
Bit 2
R
TRIB[1]
0
Bit 1
R
TRIB[0]
0
Bit 0
R
PERRI
0
PERRI
When set PERRI indicates that an SBI parity error has been detected. It is cleared when the
register is read.
TRIB[4:0] and SPE[1:0]
The TRIB[4:0] and SPE[1:0] field are used to specify the SBI tributary for which a parity
error was detected. These fields are only valid only when PERRI is set. When a parity
error has not been detected the TRIB[4:0] field may contain an out of range tributary value.
If the type of the SPE where the parity error occurred does not correspond to the operating
mode of the OCTLIU-SH (e.g. a parity error in a SPE containing E1s when the OCTLIUSH is operating in T1 mode), SPE[1:0] will be valid but TRIB[4:0] will be invalid.
Values in these fields should only be looked at when PERRI is a ‘1’.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2012568, Issue 3
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Telecom Standard Product Data Sheet
Released
Register 394H: EXSBI Depth Check Interrupt Status
Bit
Type
Function
Default
Bit 7
Unused
X
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
R
LINK[3]
0
Bit 3
R
LINK[2]
0
Bit 2
R
LINK[1]
0
Bit 1
R
LINK[0]
0
Bit 0
R
DCRI
0
DCRI
This bit is set when a Depth Check error is detected. It is cleared when the register is read.
LINK[3:0]
The LINK[3:0] field is used to specify the LIU octant data stream associated with the FIFO
buffer in which the depth check error was detected. LINK[3:0] should only be looked at
when DCRI is a ‘1’. Valid values for LINK[3:0] are from 1 to 8.
This register will contain the interrupt status even if the corresponding interrupt enable is
not set. Link 1 has the highest priority.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2012568, Issue 3
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Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
Register 395H: EXSBI Master Interrupt Status
Bit
Type
Function
Default
Bit 7
R/W
Reserved
0
Unused
X
Bit 6
Bit 5
R
DCRI_SHDW
0
Bit 4
R
PERRI_SHDW
0
Bit 3
R
FIFO_UDRI_SHDW
0
Bit 2
R
Bit 1
Bit 0
R
FIFO_OVRI_SHDW
0
Unused
X
C1FP_SYNCI
0
C1FP_SYNCI
This bit is set when a AC1FP realignment has been detected. Reading this register clears
this interrupt source.
FIFO_OVRI_SHDW
This bit is a shadow of the FIFO_OVRI bit in the EXSBI FIFO Overrun Interrupt Status
Register. It is set when the FIFO_OVRI bit is set and the interrupt enable FIFO_OVRE is
set. Reading this register has no affect on this interrupt source.
FIFO_UDRI_SHDW
This bit is a shadow of the FIFO_UDRI bit in the EXSBI FIFO Underrun Interrupt Status
Register. It is set when the FIFO_UDRI bit is set and the interrupt enable FIFO_UDRE is
set. Reading this register has no affect on this interrupt source.
PERRI_SHDW
This bit is a shadow of the PERRI bit in the EXSBI Parity Error Interrupt Reason Register.
It is set when the PERRI bit is set and the interrupt enable SBI_PERR_EN is set. Reading
this register has no affect on this interrupt source.
DCRI_SHDW
This bit is a shadow of the DCRI bit in the EXSBI Depth Check Interrupt Status Register. It
is set when the DCRI bit is set and the interrupt enable DCR_INT_EN is set. Reading this
register has no affect on this interrupt source.
RESERVED
The reserved bit must be set to 0 for correct operation of the OCTLIU-SH device.
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Telecom Standard Product Data Sheet
Released
Register 396H: EXSBI Minimum Depth
Bit
Type
Function
Default
Bit 7
Unused
X
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
Unused
X
Bit 3
R/W
MIN_DEP[3]
0
Bit 2
R/W
MIN_DEP[2]
1
Bit 1
R/W
MIN_DEP[1]
1
Bit 0
R/W
MIN_DEP[0]
1
MIN_DEP[3:0]
The MIN_DEPTH[3:0] bits specify the tributary FIFO Minimum Depth, i.e. the depth that
must be reached before the FIFO reader starts to take data from the FIFO.
Note:
•
The recommended value for MIN_DEP[3:0] is “1001”, which is not the default value following
reset.
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Document No.: PMC-2012568, Issue 3
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Telecom Standard Product Data Sheet
Released
Register 397H: EXSBI FIFO Thresholds
Bit
Type
Function
Default
Bit 7
R/W
MIN_THR[3]
0
Bit 6
R/W
MIN_THR[2]
0
Bit 5
R/W
MIN_THR[1]
1
Bit 4
R/W
MIN_THR[0]
0
Bit 3
R/W
MAX_THR[3]
1
Bit 2
R/W
MAX_THR[2]
1
Bit 1
R/W
MAX_THR[1]
0
Bit 0
R/W
MAX_THR[0]
1
MIN_THR[3:0]
The MIN_THR[3:0] bits specify the tributary FIFO minimum threshold, i.e. the FIFO depth
below which the serial data stream to the LIU octant is slowed down (when
CLK_MODE[1:0] = “00” in the EXSBI Tributary Control Register for the octant).
MAX_THR[3:0]
The MAX_THR[3:0] bits specify the tributary FIFO maximum threshold, i.e. the FIFO
depth above which the serial data stream to the LIU octant is sped up (when
CLK_MODE[1:0] = “00” in the EXSBI Tributary Control Register for the octant).
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Telecom Standard Product Data Sheet
Released
Register 398H: EXSBI Link Enable
Bit
Type
Function
Default
Bit 7
R/W
LINK_ENBL[8]
0
Bit 6
R/W
LINK_ENBL[7]
0
Bit 5
R/W
LINK_ENBL[6]
0
Bit 4
R/W
LINK_ENBL[5]
0
Bit 3
R/W
LINK_ENBL[4]
0
Bit 2
R/W
LINK_ENBL[3]
0
Bit 1
R/W
LINK_ENBL[2]
0
Bit 0
R/W
LINK_ENBL[1]
0
LINK_ENBL[8:1]
The LINK_ENBL[8:1] bits enable the operation of the corresponding LIU octant data
streams. When LINK_ENBL is ‘1’ for a stream, the EXSBI8 will take data from an SBI
tributary and transmit that data to the LIU octant. The tributary to octant mapping is
determined by the Octant to Tributary Mapping Registers and APAGE.
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Telecom Standard Product Data Sheet
Released
Register 399H: EXSBI Link Enable Busy
Bit
Function
Default
Bit 7
Unused
X
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
Unused
X
Bit 3
Unused
X
Bit 2
Unused
X
Bit 1
Unused
X
BUSY
0
Bit 0
Type
R
BUS:
A write to the EXSBI Link Enable Register sets BUSY to ‘1’. BUSY is cleared to ‘0’
approximately three REFCLK cycles later after the register contents have been
synchronized to REFCLK.
The user must check that BUSY is ‘0’ before writing to the EXSBI Link Enable Register.
Following a reset, BUSY will be ‘1’ until startup circuitry has finished automatically
initializing certain RAMs within EXSBI.
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Telecom Standard Product Data Sheet
Released
Register 3A0H – 3A7H: EXSBI Tributary Control #1 – #8
Bit
Type
Bit 7
Bit 6
R/W
Function
Default
Unused
X
CLK_MODE[1]
0
Bit 5
R/W
CLK_MODE[0]
0
Bit 4
R/W
Reserved
0
Bit 3
R/W
Reserved
1
Bit 2
R/W
Reserved
0
Bit 1
R/W
Reserved
0
Unused
X
Bit 0
A tributary control register should only be written when the associated LINK_ENBL bit is ‘0’.
RESERVED:
The reserved bits must be set to their default value for correct operation of the OCTLIU-SH
device.
CLK_MODE[1:0]:
The CLK_MODE[1:0] field selects one of three different methods whereby the frequency
of the serial data stream output to the LIU octant is determined, as shown in Table 6.
Table 6 EXSBI Clock Generation Options
CLK_MODE[1:0]
Description
00
Speed up and slow down the output serial clock depending on the FIFO fill
level and the thresholds specified in the EXSBI Thresholds Register.
01
Speed up and slow down the output serial clock depending on the ‘ClkRate’
field of the tributary’s Link Rate Octet on the SBI bus.
10
Speed up and slow down the output serial clock depending on the ‘Phase’
field of the tributary’s Link Rate Octet on the SBI bus.
11
Reserved.
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Telecom Standard Product Data Sheet
Released
Register 3A8H – 3AFH: EXSBI Page A Octant to Tributary Mapping #1 - #8
Bit
Type
Bit 7
Function
Default
Unused
X
Bit 6
R/W
SPE[1]
0
Bit 5
R/W
SPE[0]
0
Bit 4
R/W
TRIB[4]
0
Bit 3
R/W
TRIB[3]
0
Bit 2
R/W
TRIB[2]
0
Bit 1
R/W
TRIB[1]
0
Bit 0
R/W
TRIB[0]
0
SPE[1:0] and TRIB[4:0]
The SPE[1:0] and TRIB[4:0] fields are used to specify the LIU octant data stream to SBI
tributary mapping when APAGE is set to 0. The input of the octant corresponding to the
register (1-8) is sourced from the SPE and tributary specified by the value of SPE[1:0] and
TRIB[4:0]. Valid values of SPE[1:0] are from 1 to 3. Valid values of TRIB[4:0] are from 1
to 28 in T1 mode and from 1 to 21 in E1 mode.
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Telecom Standard Product Data Sheet
Released
Register 3B0H to 3B7H: EXSBI Page B Octant to Tributary Mapping #1 - #8
Bit
Type
Bit 7
Function
Default
Unused
X
Bit 6
R/W
SPE[1]
0
Bit 5
R/W
SPE[0]
0
Bit 4
R/W
TRIB[4]
0
Bit 3
R/W
TRIB[3]
0
Bit 2
R/W
TRIB[2]
0
Bit 1
R/W
TRIB[1]
0
Bit 0
R/W
TRIB[0]
0
SPE[1:0] and TRIB[4:0]
The SPE[1:0] and TRIB[4:0] fields are used to specify the LIU octant data stream to SBI
tributary mapping when APAGE is set to 1. The input of the octant corresponding to the
register (1-8) is sourced from the SPE and tributary specified by the value of SPE[1:0] and
TRIB[4:0]. Valid values of SPE[1:0] are from 1 to 3. Valid values of TRIB[4:0] are from 1
to 28 in T1 mode and from 1 to 21 in E1 mode.
Note:
•
The mapping of more than one tributary to the same LIU octant data stream or more than one LIU
octant data stream to the same tributary is not allowed. Special care must be taken to ensure that all
LIU octants and tributaries are uniquely mapped when using multiple OCTLIU-SH’s on the same SBI
bus. Failure to do so will result in bus contention.
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Document No.: PMC-2012568, Issue 3
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Telecom Standard Product Data Sheet
Released
Register 043H, 0C3H, 143H, 1C3H, 243H, 2C3H, 343H, 3C3H:
T1 PDVD Interrupt Enable/Status
Bit
Type
Function
Default
Bit 7
Unused
X
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
R
PDV
X
Bit 3
R
Z16DI
X
Bit 2
R
PDVI
X
Bit 1
R/W
Z16DE
0
Bit 0
R/W
PDVE
0
When the E1/T1B bit of the Global Configuration register is a logic 1, this register is held reset.
PDV
The PDV bit indicates the current state of the pulse density violation indication. When PDV
is a logic 1, a violation of the pulse density rule exists. When PDV is a logic 0, no violation
of the pulse density rule exists. Note: the PDV indication persists for the duration of the
pulse density violation. At its minimum, PDV may be asserted for only 1 bit time,
therefore, reading this bit may not return a logic 1 even though a pulse density violation has
occurred.
PDVI, Z16DI
The PDVI and Z16DI bits identify the source of a generated interrupt. PDVI is a logic 1
whenever a change in the pulse density violation indication generated an interrupt. PDVI is
cleared to 0 when this register is read. Z16DI is a logic 1 whenever 16 consecutive zeros
are detected. Z16DI is cleared to 0 when this register is read. Note that the PDVI and
Z16DI interrupt indications operate regardless of whether interrupts are enabled or disabled.
Z16DE
The Z16DE bit enables an interrupt to be generated on the microprocessor INTB pin when
16 consecutive zeros are detected. When Z16DE is set to logic 1, interrupt generation is
enabled. When Z16DE is set to logic 0, interrupt generation is disabled.
PDVE
The PDVE bit enables an interrupt to be generated on the microprocessor INTB pin when a
change in the pulse density is detected. When PDVE is set to logic 1, an interrupt is
generated whenever a pulse density violation occurs or when the pulse density ceases to
exist. When PDVE is set to logic 0, interrupt generation by pulse density violations is
disabled.
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Telecom Standard Product Data Sheet
Released
Register 045H, 0C5H, 145H, 1C5H, 245H, 2C5H, 345H, 3C5H:
T1 XPDE Interrupt Enable/Status
Bit
Type
Function
Default
Bit 7
R/W
STUFE
0
Bit 6
R/W
STUFF
0
Bit 5
R
STUFI
X
Bit 4
R
PDV
X
Bit 3
R
Z16DI
X
Bit 2
R
PDVI
X
Bit 1
R/W
Z16DE
0
Bit 0
R/W
PDVE
0
When the E1/T1B bit of the Global Configuration register is a logic 1, this register is held reset.
STUFE
The STUFE bit enables the occurrence of pulse stuffing to generate an interrupt on INTB.
When STUFE is set to logic 1, an interrupt is generated on the occurrence of a bit stuff.
When STUFE is a logic 0, bit stuffing occurrences do not generate an interrupt on INTB.
STUFF
The STUFF bit enables pulse stuffing to occur upon detection of a violation of the pulse
density rule. Bit stuffing is performed in such a way that the resulting data stream no longer
violates the pulse density rule. When STUFF is set to logic 1, bit stuffing is enabled and the
STUFI bit indicates the occurrence of bit stuffs. When STUFF is a logic 0, bit stuffing is
disabled and the PDVI bit indicates occurrences of pulse density violation. Also, when
STUFF is a logic 0, PCM data passes through XPDE unaltered.
STUFI
The STUFI bit is valid when pulse stuffing is active. This bit indicates when a bit stuff
occurred to eliminate a pulse density violation and that an interrupt was generated due to the
bit stuff (if STUFE is logic 1). When pulse stuffing is active, PDVI remains logic 0,
indicating that the stuffing has removed the density violation. The STUFI bit is reset to
logic 0 once this register is read. If the STUFE bit is also logic 1, the interrupt is also
cleared once this register is read.
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Telecom Standard Product Data Sheet
Released
PDV
The PDV bit indicates the current state of the pulse density violation indication. When PDV
is a logic 1, a violation of the pulse density rule exists. When PDV is a logic 0, no violation
of the pulse density rule exists. Note: the PDV indication persists for the duration of the
pulse density violation. At its minimum, PDV may be asserted for only 1 bit time,
therefore, reading this bit may not return a logic 1 even though a pulse density violation has
occurred. When the XPDE is enabled for pulse stuffing, PDV remains logic 0.
PDVI, Z16DI
The PDVI and Z16DI bits identify the source of a generated interrupt. PDVI is a logic 1
whenever a change in the pulse density violation indication generated an interrupt. PDVI is
cleared to 0 when this register is read. Z16DI is a logic 1 whenever 16 consecutive zeros
are detected. Z16DI is cleared to 0 when this register is read. Note that the PDVI and
Z16DI interrupt indications operate regardless of whether the corresponding interrupt
enables are enabled or disabled. When STUFF is set to logic 1, the PDVI and Z16DI bits
are forced to logic 0.
Z16DE
The Z16DE bit enables an interrupt to be generated on the microprocessor INTB pin when
16 consecutive zeros are detected. When Z16DE is set to logic 1, interrupt is generation is
enabled. When Z16DE is set to logic 0, interrupt generation is disabled.
PDVE
The PDVE bit enables an interrupt to be generated on the microprocessor INTB pin when a
change in the pulse density is detected. When PDVE is set to logic 1, an interrupt is
generated whenever a pulse density violation occurs or when the pulse density ceases to
exist (if STUFE is logic 0). When PDVE is set to logic 0, interrupt generation by pulse
density violations is disabled.
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Document No.: PMC-2012568, Issue 3
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Telecom Standard Product Data Sheet
Released
Register 046H, 0C6H, 146H, 1C6H, 246H, 2C6H, 346H, 3C6H: T1 XIBC Control
Bit
Type
Function
Default
Bit 7
R/W
EN
0
Bit 6
R/W
Reserved
0
Bit 5
Unused
X
Bit 4
Unused
X
Bit 3
Unused
X
Bit 2
Unused
X
Bit 1
R/W
CL1
0
Bit 0
R/W
CL0
0
When the E1/T1B bit of the Global Configuration register is a logic 1, this register is held reset.
EN
The EN bit controls whether the Inband Code is transmitted or not. A logic 1 in the EN bit
position enables transmission of inband codes; a logic 0 in the EN bit position disables
inband code transmission.
Note:
•
The PRBS transmit data (TX_GEN=1) has priority over the XIBC data stream.
RESERVED
The reserved bit must be set to 0 for correct operation of the OCTLIU-SH device.
CL1, CL0
The bit positions CL1 and CL0 of this register indicate the length of the inband loopback
code sequence, as follows:
Table 7 Transmit In-band Code Length
CL1
CL0
Code Length
0
0
5
0
1
6
1
0
7
1
1
8
Codes of 3 or 4 bits in length may be accommodated by treating them as half of a double-sized
code (i.e., a 3-bit code would use the 6-bit code length setting).
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Document No.: PMC-2012568, Issue 3
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Telecom Standard Product Data Sheet
Released
Register 047H, 0C7H, 147H, 1C7H, 247H, 2C7H, 347H, 3C7H: T1 XIBC Loopback Code
Bit
Type
Function
Default
Bit 7
R/W
IBC7
X
Bit 6
R/W
IBC6
X
Bit 5
R/W
IBC5
X
Bit 4
R/W
IBC4
X
Bit 3
R/W
IBC3
X
Bit 2
R/W
IBC2
X
Bit 1
R/W
IBC1
X
Bit 0
R/W
IBC0
X
When the E1/T1B bit of the Global Configuration register is a logic 1, this register is held reset.
This register contains the inband loopback code pattern to be transmitted. The code is
transmitted most significant bit (IBC7) first, followed by IBC6 and so on. The code, regardless
of the length, must be aligned with the MSB always in the IBC7 position (e.g., a 5-bit code
would occupy the IBC7 through IBC2 bit positions). To transmit a 3-bit or a 4-bit code pattern,
the pattern must be paired to form a double-sized code (i.e., the 3-bit code ‘011’ would be
written as the 6-bit code ‘011011’).
When the OCTLIU-SH is reset, the contents of this register are not affected.
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Telecom Standard Product Data Sheet
Released
Register 048H, 0C8H, 148H, 1C8H, 248H, 2C8H, 348H, 3C8H: RJAT Interrupt Status
Bit
Type
Function
Default
Bit 7
Unused
X
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
Unused
X
Bit 3
Unused
X
Bit 2
Unused
X
Bit 1
R
OVRI
X
Bit 0
R
UNDI
X
UNDI
The UNDI bit is asserted when an attempt is made to read data from the receive FIFO when
the FIFO is already empty. When UNDI is a logic 1, an underrun event has occurred.
Reading this register will clear the UNDI bit to logic 0.
OVRI
The OVRI bit is asserted when an attempt is made to write data into the receive FIFO when
the FIFO is already full. When OVRI is a logic 1, an overrun event has occurred. Reading
this register will clear the OVRI bit to logic 0.
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Document No.: PMC-2012568, Issue 3
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Telecom Standard Product Data Sheet
Released
Register 049H, 0C9H, 149H, 1C9H, 249H, 2C9H, 349H, 3C9H:
RJAT Reference Clock Divisor (N1) Control
Bit
Type
Function
Default
Bit 7
R/W
N1[7]
0
Bit 6
R/W
N1[6]
0
Bit 5
R/W
N1[5]
1
Bit 4
R/W
N1[4]
0
Bit 3
R/W
N1[3]
1
Bit 2
R/W
N1[2]
1
Bit 1
R/W
N1[1]
1
Bit 0
R/W
N1[0]
1
This register contains an 8-bit binary number, N1, which is one less than the magnitude of the
reference clock divisor. The reference divisor magnitude, (N1+1), is the ratio between the
frequency of the recovered clock (or the transmit clock if a diagnostic loopback is enabled) and
the frequency at the phase discriminator input.
Writing to this register will reset the PLL.
The default value of N1 after a device reset is 47 = 2FH.
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Document No.: PMC-2012568, Issue 3
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Telecom Standard Product Data Sheet
Released
Register 04AH, 0CAH, 14AH, 1CAH, 24AH, 2CAH, 34AH, 3CAH:
RJAT Output Clock Divisor (N2) Control
Bit
Type
Function
Default
Bit 7
R/W
N2[7]
0
Bit 6
R/W
N2[6]
0
Bit 5
R/W
N2[5]
1
Bit 4
R/W
N2[4]
0
Bit 3
R/W
N2[3]
1
Bit 2
R/W
N2[2]
1
Bit 1
R/W
N2[1]
1
Bit 0
R/W
N2[0]
1
This register contains an 8-bit binary number, N2, which is one less than the magnitude of the
output clock divisor. The output clock divisor magnitude, (N2+1), is the ratio between the
frequency of the smooth output clock, and the frequency applied to the phase discriminator
input.
Writing to this register will reset the PLL.
The default value of N2 after a device reset is 47 = 2FH.
Recommendations
In general, the relationship N1 = N2 must always be true in order for the PLL to operate
correctly.
In order to meet jitter transfer specifications for some modes, such as basic E1 operation, N1
and N2 must be large in order to reduce the PLL transfer cutoff frequency. The recommended
N1/N2 values for the various operating modes are shown in Table 8.
Table 8 Recommended N1/N2 values
Mode
N1
N2
T1 SBI (1.544 MHz)
FFH
FFH
E1 SBI (2.048 MHz)
FFH
FFH
T1 SBI (2.048 MHz)
FFH
FFH
Note:
•
The frequencies quoted in parentheses refer to the XCLK frequency being used.
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Document No.: PMC-2012568, Issue 3
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Telecom Standard Product Data Sheet
Released
Register 04BH, 0CBH, 14BH, 1CBH, 24BH, 2CBH, 34BH, 3CBH: RJAT Configuration
Bit
Type
Function
Default
Bit 7
Unused
X
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
R/W
CENT
0
Bit 3
R/W
UNDE
0
Bit 2
R/W
OVRE
0
Bit 1
R/W
FIFORST
0
Bit 0
R/W
LIMIT
1
CENT
Setting the CENT option to logic 1 will enable the FIFO self-centering option for the next
384 OCLK cycles, and for the first 384 OCLK cycles following an overrun or underrun
event. If an EMPTY or FULL alarm occurs during this 384 UI period, then the period will
be extended by the number of UI that the EMPTY or FULL alarm persists.
Setting both LIMIT and CENT to logic 1 will cause the FIFO to self-center only once
(when CENT transitions from low to high) and then default to LIMIT functionality. The
reason is that the FIFO must overrun or underrun in order for centering to trigger, but
LIMIT prevents this from occurring.
The recommended value of CENT is logic 1.
UNDE
Setting the UNDE bit to logic 1 enables an underrun event to assert the INTB output low.
OVRE
Setting the OVRE bit to logic 1 enables an overrun event to assert the INTB output low.
FIFORST
Setting the FIFORST bit allows the FIFO to be reset. When FIFORST is logic 1, the FIFO
will reset. When FIFORST is logic 0, the FIFO operates normally.
LIMIT
Setting the LIMIT bit to logic 1 will limit the PLL jitter attenuation by enabling the FIFO to
increase or decrease the frequency of the smooth output clock whenever the FIFO is within
one UI of overflowing or underflowing.
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Telecom Standard Product Data Sheet
Released
Setting both LIMIT and CENT to logic 1 will cause the FIFO to self-center only once
(when CENT transitions from low to high) and then default to LIMIT functionality. The
reason is that the FIFO must overrun or underrun in order for centering to trigger, but
LIMIT prevents this from occurring.
The recommended value of LIMIT is logic 0.
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Telecom Standard Product Data Sheet
Released
Register 04CH, 0CCH, 14CH, 1CCH, 24CH, 2CCH, 34CH, 3CCH: TJAT Interrupt Status
Bit
Type
Function
Default
Bit 7
Unused
X
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
Unused
X
Bit 3
Unused
X
Bit 2
Unused
X
Bit 1
R
OVRI
X
Bit 0
R
UNDI
X
UNDI
The UNDI bit is asserted when an attempt is made to read data from the transmit FIFO
when the FIFO is already empty. When UNDI is a logic 1, an underrun event has occurred.
Reading this register will clear the UNDI bit to logic 0.
OVRI
The OVRI bit is asserted when an attempt is made to write data into the transmit FIFO
when the FIFO is already full. When OVRI is a logic 1, an overrun event has occurred.
Reading this register will clear the OVRI bit to logic 0.
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Telecom Standard Product Data Sheet
Released
Register 04DH, 0CDH, 14DH, 1CDH, 24DH, 2CDH, 34DH, 3CDH:
TJAT Reference Clock Divisor (N1) Control
Bit
Type
Function
Default
Bit 7
R/W
N1[7]
0
Bit 6
R/W
N1[6]
0
Bit 5
R/W
N1[5]
1
Bit 4
R/W
N1[4]
0
Bit 3
R/W
N1[3]
1
Bit 2
R/W
N1[2]
1
Bit 1
R/W
N1[1]
1
Bit 0
R/W
N1[0]
1
This register contains an 8-bit binary number, N1, which is one less than the magnitude of the
reference clock divisor. The reference divisor magnitude, (N1+1), is the ratio between the
frequency of the reference clock (as selected by the PLLREF1 and PLLREF0 bits of the
Transmit Line Interface Timing Options register) and the frequency at the phase discriminator
input.
Writing to this register will reset the PLL.
The default value of N1 after a device reset is 47 = 2FH.
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Telecom Standard Product Data Sheet
Released
Register 04EH, 0CEH, 14EH, 1CEH, 24EH, 2CEH, 34EH, 3CEH:
TJAT Output Clock Divisor (N2) Control
Bit
Type
Function
Default
Bit 7
R/W
N2[7]
0
Bit 6
R/W
N2[6]
0
Bit 5
R/W
N2[5]
1
Bit 4
R/W
N2[4]
0
Bit 3
R/W
N2[3]
1
Bit 2
R/W
N2[2]
1
Bit 1
R/W
N2[1]
1
Bit 0
R/W
N2[0]
1
This register contains an 8-bit binary number, N2, which is one less than the magnitude of the
output clock divisor. The output clock divisor magnitude, (N2+1), is the ratio between the
frequency of the smooth output clock and the frequency applied to the phase discriminator
input.
Writing to this register will reset the PLL.
The default value of N2 after a device reset is 47 = 2FH.
Recommendations
In general, the relationship N1 = N2 must always be true in order for the PLL to operate
correctly.
In order to meet jitter transfer specifications for some modes, such as basic E1 operation, N1
and N2 must be large in order to reduce the PLL transfer cutoff frequency. The recommended
N1/N2 values for the various operating modes are shown in Table 9.
Table 9 Recommended N1/N2 values
Mode
N1
N2
T1 SBI (1.544 MHz)
FFH
FFH
E1 SBI (2.048 MHz)
FFH
FFH
T1 SBI (2.048 MHz)
FFH
FFH
Note:
•
The frequencies quoted in parentheses refer to the XCLK frequency being used.
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Document No.: PMC-2012568, Issue 3
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Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
Register 04FH, 0CFH, 14FH, 1CFH, 24FH, 2CFH, 34FH, 3CFH: TJAT Configuration
Bit
Type
Function
Default
Bit 7
Unused
X
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
R/W
CENT
0
Bit 3
R/W
UNDE
0
Bit 2
R/W
OVRE
0
Bit 1
R/W
FIFORST
0
Bit 0
R/W
LIMIT
1
CENT
Setting the CENT option to logic 1 will enable the FIFO self-centering option for the next
384 OCLK cycles, and for the first 384 OCLK cycles following an overrun or underrun
event. If an EMPTY or FULL alarm occurs during this 384 UI period, then the period will
be extended by the number of UI that the EMPTY or FULL alarm persists.
Setting both LIMIT and CENT to logic 1 will cause the FIFO to self-center only once
(when CENT transitions from low to high) and then default to LIMIT functionality. The
reason is that the FIFO must overrun or underrun in order for centering to trigger, but
LIMIT prevents this from occurring.
The recommended value of CENT is logic 1.
UNDE
Setting the UNDE bit to logic 1 enables an underrun event to assert the INTB output low.
OVRE
Setting the OVRE bit to logic 1 enables an overrun event to assert the INTB output low.
FIFORST
Setting the FIFORST bit allows the FIFO to be reset. When FIFORST is logic 1, the FIFO
will reset. When FIFORST is logic 0, the FIFO operates normally.
LIMIT
Setting the LIMIT bit to logic 1 will limit the PLL jitter attenuation by enabling the FIFO to
increase or decrease the frequency of the smooth output clock whenever the FIFO is within
one UI of overflowing or underflowing.
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Telecom Standard Product Data Sheet
Released
Setting both LIMIT and CENT to logic 1 will cause the FIFO to self-center only once
(when CENT transitions from low to high) and then default to LIMIT functionality. The
reason is that the FIFO must overrun or underrun in order for centering to trigger, but
LIMIT prevents this from occurring.
The recommended value of LIMIT is logic 0.
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Telecom Standard Product Data Sheet
Released
Register 050H, 0D0H, 150H, 1D0H, 250H, 2D0H, 350H, 3D0H: IBCD Configuration
Bit
Type
Function
Default
Bit 7
R/W
Reserved
0
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
Unused
X
DSEL1
0
Bit 3
R/W
Bit 2
R/W
DSEL0
0
Bit 1
R/W
ASEL1
0
Bit 0
R/W
ASEL0
0
When the E1/T1B bit of the Global Configuration register is a logic 1, this register is held reset.
This register provides the selection of the Activate and De-activate loopback code lengths (from
3 bits to 8 bits) as follows:
Table 10 Loopback Code Configurations
DEACTIVATE Code
ACTIVATE Code
DSEL1
DSEL0
ASEL1
ASEL0
CODE LENGTH
0
0
0
0
5 bits
0
1
0
1
6 (or 3*) bits
1
0
1
0
7 bits
1
1
1
1
8 (or 4*) bits
Note:
•
3-bit and 4-bit code sequences can be accommodated by configuring the IBCD for 6 or 8 bits and
by programming two repetitions of the code sequence.
•
The Reserved bit is used for production test purposes only. The Reserved bit must be logic 0 for
normal operation.
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Telecom Standard Product Data Sheet
Released
Register 051H, 0D1H, 151H, 1D1H, 251H, 2D1H, 351H, 3D1H: IBCD Interrupt Enable/Status
Bit
Type
Function
Default
Bit 7
R
LBACP
X
Bit 6
R
LBDCP
X
Bit 5
R/W
LBAE
0
Bit 4
R/W
LBDE
0
Bit 3
R
LBAI
X
Bit 2
R
LBDI
X
Bit 1
R
LBA
X
Bit 0
R
LBD
X
When the E1/T1B bit of the Global Configuration register is a logic 1, this register is held reset.
LBACP, LBDCP
The LBACP and LBDCP bits indicate when the corresponding loopback code is present
during a 39.8 ms interval.
LBAE
The LBAE bit enables the assertion or deassertion of the inband Loopback Activate (LBA)
detect indication to generate an interrupt on the microprocessor INTB pin. When LBAE is
set to logic 1, any change in the state of the LBA detect indication generates an interrupt.
When LBAE is set to logic 0, no interrupt is generated by changes in the LBA detect state.
LBDE
The LBDE bit enables the assertion or deassertion of the inband Loopback Deactivate
(LBD) detect indication to generate an interrupt on the microprocessor INTB pin. When
LBDE is set to logic 1, any change in the state of the LBD detect indication generates an
interrupt. When LBDE is set to logic 0, no interrupt is generated by changes in the LBD
detect state.
LBAI, LBDI
The LBAI and LBDI bits indicate which of the two expected loopback codes generated the
interrupt when their state changed. A logic 1 in these bit positions indicates that a state
change in that code has generated an interrupt; a logic 0 in these bit positions indicates that
no state change has occurred. After the Enable/Status Register has been read, the LBAI and
LBDI bits are set to logic 0.
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Telecom Standard Product Data Sheet
Released
LBA, LBD
The LBA and LBD bits indicate the current state of the corresponding loopback code detect
indication. A logic 1 in these bit positions indicates the presence of that code has been
detected; a logic 0 in these bit positions indicates the absence of that code. Each INBAND
LOOPBACK code sequence is defined as the repetition of the programmed code in the
PCM stream for at least 5.1 seconds. The detection algorithm tolerates more than the
minimum number of discrepancy bits in order to detect framed PCM data in the presence of
a 10-2 bit error rate.
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Telecom Standard Product Data Sheet
Released
Register 052H, 0D2H, 152H, 1D2H, 252H, 2D2H, 352H, 3D2H: IBCD Activate Code
Bit
Type
Function
Default
Bit 7
R/W
ACT7
0
Bit 6
R/W
ACT6
0
Bit 5
R/W
ACT5
0
Bit 4
R/W
ACT4
0
Bit 3
R/W
ACT3
0
Bit 2
R/W
ACT2
0
Bit 1
R/W
ACT1
0
Bit 0
R/W
ACT0
0
When the E1/T1B bit of the Global Configuration register is a logic 1, this register is held reset.
This 8-bit register selects the Activate code sequence that is to be detected. If the code sequence
length is less than 8 bits, the first 8 bits of several repetitions of the code sequence must be used
to fill the 8-bit register. For example, if code sequence is a repeating 00001, the first 8 bits of
two repetitions (0000100001) is programmed into the register, i.e.00001000. Note that bit ACT7
corresponds to the first code bit received.
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Telecom Standard Product Data Sheet
Released
Register 053H, 0D3H, 153H, 1D3H, 253H, 2D3H, 353H, 3D3H: IBCD Deactivate Code
Bit
Type
Function
Default
Bit 7
R/W
DACT7
0
Bit 6
R/W
DACT6
0
Bit 5
R/W
DACT5
0
Bit 4
R/W
DACT4
0
Bit 3
R/W
DACT3
0
Bit 2
R/W
DACT2
0
Bit 1
R/W
DACT1
0
Bit 0
R/W
DACT0
0
When the E1/T1B bit of the Global Configuration register is a logic 1, this register is held reset.
This 8-bit register selects the Deactivate code sequence that is to be detected. If the code
sequence length is less than 8 bits, the first 8 bits of several repetitions of the code sequence
must be used to fill the 8-bit register. For example, if code sequence is a repeating 001, the first
8 bits of three repetitions (001001001) is programmed into the register, i.e.00100100. Note that
bit DACT7 corresponds to the first code bit received.
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Telecom Standard Product Data Sheet
Released
Register 054H, 0D4H, 154H, 1D4H, 254H, 2D4H, 354H, 3D4H: CDRC Configuration
Bit
Type
Function
Default
Bit 7
R/W
AMI
0
Bit 6
R/W
LOS[1]
0
Bit 5
R/W
LOS[0]
0
Bit 4
R/W
Reserved
0
Bit 3
R/W
Reserved
0
Bit 2
R/W
Reserved
0
Bit 1
R/W
O162
0
Bit 0
R/W
Reserved
0
RESERVED
Reserved bit 2 must be set to logic 1 for correct operation. All other reserved bits must be a
logic 0 for correct operation.
O162
If the AMI bit is logic 0 in E1 mode, the Recommendation O.162 compatibility select bit
(O162) allows selection between two line code violation definitions:
If O162 is a logic 0, a line code violation is indicated if the serial stream does not match the
verbatim HDB3 definition given in Recommendation G.703. A bipolar violation that is not
part of an HDB3 signature or a bipolar violation in an HDB3 signature that is the same
polarity as the last bipolar violation results in a line code violation indication.
If O162 is a logic 1, a line code violation is indicated if a bipolar violation is of the same
polarity as the last bipolar violation, as per Recommendation O.162.
The O162 bit has no effect in T1 mode.
AMI
The alternate mark inversion (AMI) bit specifies the line coding of the incoming signal. A
logic 1 selects AMI line coding by disabling HDB3 decoding in E1 mode and B8ZS in T1
mode. In E1 mode, a logic 0 selects HDB3 line decoding which entails substituting an
HDB3 signature with four zeros. In T1 mode, a logic 0 selects B8ZS line decoding which
entails substituting an B8ZS signature with eight zeros.
LOS[1:0]
The loss of signal threshold is set by the operating mode and the state of the AMI, LOS[1]
and LOS[0] bits:
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Telecom Standard Product Data Sheet
Released
Table 11 Loss of Signal Thresholds
Mode
AMI
LOS[1]
LOS[0]
Threshold (PCM periods)
E1
0
0
0
10
T1
0
0
0
15
X
1
0
0
15
X
X
0
1
31
X
X
1
0
63
X
X
1
1
175
When the number of consecutive zeros on the incoming PCM line exceeds the programmed
threshold, the LOSV status bit is set. For example, if the threshold is set to 10, the 11th zero
causes the LOSV bit to be set.
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Telecom Standard Product Data Sheet
Released
Register 055H, 0D5H, 155H, 1D5H, 255H, 2D5H, 355H, 3D5H: CDRC Interrupt Control
Bit
Type
Function
Default
Bit 7
R/W
LCVE
0
Bit 6
R/W
LOSE
0
Bit 5
R/W
LCSDE
0
Bit 4
R/W
ZNDE
0
Bit 3
Unused
X
Bit 2
Unused
X
Bit 1
Unused
X
Bit 0
Unused
X
The bit positions LCVE, LOSE, LCSDE and ZNDE (bits 7 to 4) of this register are interrupt
enables to select which of the status events (Line Code Violation , Loss Of Signal, HDB3
signature, B8ZS signature or N Zeros), either singly or in combination, are enabled to generate
an interrupt on the microprocessor INTB pin when they are detected. A logic 1 bit in the
corresponding bit position enables the detection of these signals to generate an interrupt; a
logic 0 bit in the corresponding bit position disables that signal from generating an interrupt.
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Document No.: PMC-2012568, Issue 3
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Telecom Standard Product Data Sheet
Released
Register 056H, 0D6H, 156H, 1D6H, 256H, 2D6H, 356H, 3D6H: CDRC Interrupt Status
Bit
Type
Function
Default
Bit 7
R
LCVI
X
Bit 6
R
LOSI
X
Bit 5
R
LCSDI
X
Bit 4
R
ZNDI
X
Bit 3
Unused
X
Bit 2
Unused
X
Bit 1
Unused
X
LOSV
X
Bit 0
R
The ZNDI, LCSDI, LOSI and LCVI (bits 4 to 7) of this register indicate which of the status
events have occurred since the last time this register was read. A logic 1 in any of these bit
positions indicates that the corresponding event was detected.
Bits ZNDI, LCSDI, LOSI and LCVI are cleared to logic 0 by reading this register.
LOSV
The LOSV bit reflects the status of the LOS alarm.
ZNDI
The consecutive zeros detection interrupt (ZNDI) indicates that N consecutive spaces have
occurred, where N is four for E1 and eight for T1. This bit can be used to detect an AMI
coded signal.
LCSDI
The line code signature detection interrupt (LCSDI) indicates that a valid line code
signature has occurred. In T1 mode, the B8ZS signature is defined as 000+-0-+ if the
previous impulse is positive, or 000-+0+- if it is negative. In E1 mode, a valid HDB3
signature is defined as a bipolar violation preceded by two zeros. This bit can be used to
detect an HDB3 coded signal in E1 mode and B8ZS coded signal in T1.
LOSI
The LOSI bit is set to a logic 1 when the LOSV bit changes state.
LCVI
The line code violation interrupt (LCVI) indicates a series of marks and spaces has occurred
in contradiction to the defined line code (AMI, B8ZS or HDB3).
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Telecom Standard Product Data Sheet
Released
Register 057H, 0D7H, 157H, 1D7H, 257H, 2D7H, 357H, 3D7H:
CDRC Alternate Loss of Signal Status
Bit
Type
Function
Default
Bit 7
R/W
ALTLOSE
0
Bit 6
R
ALTLOSI
X
Bit 5
Unused
X
Bit 4
Unused
X
Bit 3
Unused
X
Bit 2
Unused
X
Bit 1
Unused
X
ALTLOSV
X
Bit 0
R
The alternate loss of signal status provides a more stringent criteria for the deassertion of the
alarm than the LOS indication in the CDRC Interrupt Status register.
ALTLOSE
If the ALTLOSE bit is a logic 1, the INTB output is asserted low when the ALTLOSV status
bit changes state.
ALTLOSI
The ALTLOSI bit is set high when the ALTLOSV status bit changes state. It is cleared
when this register is read.
ALTLOSV
The ALTLOSV bit is asserted upon the absence of marks for the threshold of bit periods
specified by the LOS[1:0] register bits. The ALTLOSV bit is deasserted only after pulse
density requirements have been met. In T1 mode, there must be N ones in each and every
time window of 8(N+1) data bits (where N can equal 1 through 23). In E1 mode, ALTLOSV
is deasserted only after 255 bit periods during which no sequence of four zeros has been
received.
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Document No.: PMC-2012568, Issue 3
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Telecom Standard Product Data Sheet
Released
Register 058H, 0D8H, 158H, 1D8H, 258H, 2D8H, 358H, 3D8H: PMON Interrupt
Enable/Status
Bit
Type
Function
Default
Bit 7
Unused
X
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
Unused
X
Bit 3
Unused
X
Bit 2
R/W
INTE
0
Bit 1
R
XFER
0
Unused
X
Bit 0
This register contains status information indicating when counter data has been transferred into
the holding registers and indicating whether the holding registers have been overrun.
INTE
The INTE bit controls the generation of a microprocessor interrupt when the transfer clock
has caused the counter values to be stored in the holding registers. A logic 1 bit in the INTE
position enables the generation of an interrupt via the INTB output; a logic 0 bit in the
INTE position disables the generation of an interrupt.
XFER
The XFER bit indicates that a transfer of counter data has occurred. A logic 1 in this bit
position indicates that a latch request, initiated by writing to one of the counter register
locations or the Octant PMON Update register, was received and a transfer of the counter
values has occurred. A logic 0 indicates that no transfer has occurred. The XFER bit is
cleared (acknowledged) by reading this register.
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Document No.: PMC-2012568, Issue 3
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Telecom Standard Product Data Sheet
Released
Register 05EH, 0DEH, 15EH, 1DEH, 25EH, 2DEH, 35EH, 3DEH: PMON LCV Count (LSB)
Bit
Type
Function
Default
Bit 7
R
LCV[7]
X
Bit 6
R
LCV[6]
X
Bit 5
R
LCV[5]
X
Bit 4
R
LCV[4]
X
Bit 3
R
LCV[3]
X
Bit 2
R
LCV[2]
X
Bit 1
R
LCV[1]
X
Bit 0
R
LCV[0]
X
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Telecom Standard Product Data Sheet
Released
Register 05FH, 0DFH, 15FH, 1DFH, 25FH, 2DFH, 35FH, 3DFH: PMON LCV Count (MSB)
Bit
Type
Function
Default
Bit 7
Unused
X
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
R
LCV[12]
X
Bit 3
R
LCV[11]
X
Bit 2
R
LCV[10]
X
Bit 1
R
LCV[9]
X
Bit 0
R
LCV[8]
X
LCV[12:0]
The LCV[12:0] bits indicate the number of LCV error events that occurred during the
previous accumulation interval. An LCV event is defined as the occurrence of a Bipolar
Violation or Excessive Zeros. The counting of Excessive Zeros can be disabled by the BPV
bit of the Receive Line Interface Configuration #1 register.
The LCV count registers for a octant are updated by writing to the PMON LCV Count
(LSB) register. A write to this location loads count data located in the PMON into the
internal holding registers. Alternatively, the LCV count registers for the octant are updated
by writing to the Line Interface Interrupt Source #1 / PMON Update register. The data
contained in the holding registers can then be subsequently read by microprocessor accesses
into the PMON count register address space. The latching of count data, and subsequent
resetting of the counters, is synchronized to the internal event timing so that no events are
missed.
The PMON is loaded with new count data within 3.5 recovered clock periods of the
triggering register write. With nominal line rates, the PMON registers should not be polled
until 2.3 µsec have elapsed from the triggering register write.
When the OCTLIU-SH is reset, the contents of the PMON count registers are unknown
until the first latching of performance data is performed.
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Telecom Standard Product Data Sheet
Released
Register 060H, 0E0H, 160H, 1E0H, 260H, 2E0H, 360H, 3E0H:
PRBS Generator/Checker Control
Bit
Type
Bit 7
Bit 6
Bit 5
R/W
Bit 4
Bit 3
R/W
Function
Default
Unused
X
Unused
X
QRSS
0
Unused
X
TINV
0
Bit 2
R/W
RINV
0
Bit 1
R/W
AUTOSYNC
1
Bit 0
R/W
MANSYNC
0
QRSS
The quasi-random signal source (QRSS) bit enables the zero suppression feature required
when generating a QRSS sequence. When QRSS is a logic 1, a one is forced in the
generated PRBS stream when the following 14 bit positions are all zeros. When QRSS is a
logic 0, the zero suppression feature is disabled.
In order to generate the AT&T TR 62411 QRSS sequence, or the 220-1 sequence as specified
in ITU-T O.151, the PATSEL[1:0] field in the PRBS Pattern Select Register must be set to
“01” and QRSS set to 1.
TINV
The TINV bit controls the logical inversion of the generated data stream. When TINV is a
logic 1, the data is inverted. When TINV is a logic 0, the data is not inverted.
RINV
The RINV bit controls the logical inversion of the received stream before processing. When
RINV is a logic 1, the received data is inverted before being processed by the pattern
detector. When RINV is a logic 0, the data is not inverted
AUTOSYNC
The AUTOSYNC bit enables the automatic resynchronization of the pattern detector. The
automatic resynchronization is activated when 10 or more bit errors are detected in a fixed
48-bit window. When AUTOSYNC is a logic 1, the auto resync feature is enabled. When
AUTOSYNC is a logic 0, the auto sync feature is disabled, and pattern resynchronization is
accomplished using the MANSYNC bit.
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Telecom Standard Product Data Sheet
Released
MANSYNC
The MANSYNC bit is used to initiate a manual resynchronization of the pattern detector. A
low to high transition on MANSYNC initiates the resynchronization.
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Telecom Standard Product Data Sheet
Released
Register 061H, 0E1H, 161H, 1E1H, 261H, 2E1H, 361H, 3E1H:
PRBS Checker Interrupt Enable/Status
Bit
Type
Function
Default
Bit 7
R/W
SYNCE
0
Bit 6
R/W
BEE
0
Bit 5
R/W
XFERE
0
Bit 4
R
SYNCV
X
Bit 3
R
SYNCI
X
Bit 2
R
BEI
X
Bit 1
R
XFERI
X
Unused
X
Bit 0
SYNCE
The SYNCE bit enables the generation of an interrupt when the PRBS checker changes
synchronization state. When SYNCE is set to logic 1, the interrupt is enabled.
BEE
The BEE bit enables the generation of an interrupt when a bit error is detected in the receive
data. Bit errors are not flagged unless the pattern detector is synchronized. When BEE
is set to logic 1, the interrupt is enabled.
XFERE
The XFERE bit enables the generation of an interrupt when an accumulation interval is
completed and new values are stored in the error counter holding registers. When XFERE
is set to logic 1, the interrupt is enabled.
SYNCV
The SYNCV bit indicates the synchronization state of the PRBS checker. When SYNCV is
a logic 1 the PRBS checker is synchronized (the PRBS checker has observed at least 32
consecutive error free bit periods). When SYNCV is a logic 0, the PRBS checker is out of
sync (the PRBS checker has detected 6 or more bit errors in a 64 bit period window).
SYNCI
The SYNCI bit indicates that the detector has changed synchronization state since the last
time this register was read. If SYNCI is logic 1, the pattern detector has gained or lost
synchronization at least once. SYNCI is set to logic 0 when this register is read.
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Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
BEI
The BEI bit indicates that one or more bit errors have been detected since the last time this
register was read. When BEI is set to logic 1, at least one bit error has been detected. BEI
is set to logic 0 when this register is read.
XFERI
The XFERI bit indicates that a transfer of the error count has occurred. A logic 1 in this bit
position indicates that the error counter holding registers has been updated. This update is
initiated by writing to one of the PRBS Error Count register locations, or by writing to the
Line Interface Interrupt Source #1 / PMON Update register. XFERI is set to logic 0 when
this register is read.
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Document No.: PMC-2012568, Issue 3
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Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
Register 062H, 0E2H, 162H, 1E2H, 262H, 2E2H, 362H, 3E2H: PRBS Pattern Select
Bit
Type
Function
Default
Bit 7
Unused
X
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
Unused
X
Bit 3
Unused
X
Bit 2
Unused
X
Bit 1
R/W
PATSEL[1]
0
Bit 0
R/W
PATSEL[0]
0
PATSEL[1:0]
PATSEL[1:0] determines which of the three PRBS patterns are generated and checked for
errors.
PATSEL[1:0]
Pattern
00
215-1
01
220-1
10
2 -1
11
Reserved
11
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Document No.: PMC-2012568, Issue 3
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Telecom Standard Product Data Sheet
Released
Register 064H, 0E4H, 164H, 1E4H, 264H, 2E4H, 364H, 3E4H: PRBS Error Count #1
Bit
Type
Function
Default
Bit 7
R
ERRCNT[7]
X
Bit 6
R
ERRCNT[6]
X
Bit 5
R
ERRCNT[5]
X
Bit 4
R
ERRCNT[4]
X
Bit 3
R
ERRCNT[3]
X
Bit 2
R
ERRCNT[2]
X
Bit 1
R
ERRCNT[1]
X
Bit 0
R
ERRCNT[0]
X
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Document No.: PMC-2012568, Issue 3
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Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
Register 065H, 0E5H, 165H, 1E5H, 265H, 2E5H, 365H, 3E5H: PRBS Error Count #2
Bit
Type
Function
Default
Bit 7
R
ERRCNT[15]
X
Bit 6
R
ERRCNT[14]
X
Bit 5
R
ERRCNT[13]
X
Bit 4
R
ERRCNT[12]
X
Bit 3
R
ERRCNT[11]
X
Bit 2
R
ERRCNT[10]
X
Bit 1
R
ERRCNT[9]
X
Bit 0
R
ERRCNT[8]
X
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Document No.: PMC-2012568, Issue 3
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Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
Register 066H, 0E6H, 166H, 1E6H, 266H, 2E6H, 366H, 3E6H: PRBS Error Count #3
Bit
Type
Function
Default
Bit 7
R
ERRCNT[23]
X
Bit 6
R
ERRCNT[22]
X
Bit 5
R
ERRCNT[21]
X
Bit 4
R
ERRCNT[20]
X
Bit 3
R
ERRCNT[19]
X
Bit 2
R
ERRCNT[18]
X
Bit 1
R
ERRCNT[17]
X
Bit 0
R
ERRCNT[16]
X
ERRCNT[23:0]
ERRCNT[23:0] contain the error counter holding register. The value in this register
represents the number of bit errors that have been accumulated since the last accumulation
interval, up to a maximum (saturation) value of 224-1. Note that bit errors are not
accumulated while the pattern detector is out of sync.
The Error Count registers for each individual PRBS generator/checker are updated by
writing to any one of the Error count registers. Alternatively, the Error Count registers are
updated with all other octant counter registers by writing to the Line Interface Interrupt
Source #1 / PMON Update register. The data contained in the holding registers can then be
subsequently read by microprocessor accesses into the PRBS error count register address
space. The latching of error count data, and subsequent resetting of the counters, is
synchronized to the internal event timing so that no events are missed.
The PRBS is loaded with new count data within 6 recovered clock periods of the triggering
register write. In T1 mode, the PRBS registers should not be read until 4 µsec have elapsed
from the triggering register write. In E1 mode, the PRBS registers should not be read until
3 µsec have elapsed from the triggering register write. The XFERI bit the PRBS Checker
Interrupt Enable/Status Register may be polled to determine whether the required interval
has elapsed.
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Document No.: PMC-2012568, Issue 3
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Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
Register 068H, 0E8H, 168H, 1E8H, 268H, 2E8H, 368H, 3E8H: XLPG Control/Status
Bit
Type
Function
Default
Bit 7
R/W
HIGHZ
1
Bit 6
R/W
ARST
0
Bit 5
Unused
X
Bit 4
R/W
Reserved
0
Bit 3
R
Reserved
X
Bit 2
R/W
Reserved
0
Bit 1
R/W
Reserved
0
Bit 0
R/W
Reserved
1
HIGHZ
The HIGHZ bit controls tristating of the TXTIP[x] and TXRING[x] outputs. When the
HIGHZ bit is set to a logic 0, the outputs are enabled. When the HIGHZ bit is set to a
logic 1, the outputs are put into high impedance. Setting HIGHZ to logic 1 has the same
effect as setting SCALE[4:0] to 00H.
ARST
The Analogue Reset bit (ARST) resets the analogue portion of the XLPG (without affecting
the digital portion) when set to logic 1.
RESERVED
The Reserved bits must remain in their default state for correct operation.
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Document No.: PMC-2012568, Issue 3
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Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
Register 069H, 0E9H, 169H, 1E9H, 269H, 2E9H, 369H, 3E9H: XLPG Pulse Waveform Scale
Bit
Type
Function
Default
Bit 7
Unused
X
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
R/W
SCALE[4]
0
Bit 3
R/W
SCALE[3]
0
Bit 2
R/W
SCALE[2]
0
Bit 1
R/W
SCALE[1]
0
Bit 0
R/W
SCALE[0]
0
SCALE[4:0]
The SCALE[4:0] bits specify a scaling factor to be applied to the amplitude of the D/A
output waveform. Each of the 12 waveforms stored in the XLPG’s pulse template RAM
may have a different scaling factor. When a particular waveform is selected for use (by the
PT_SEL[3:0] register bits or LENx[2:0] inputs), the scaling factor corresponding to that
waveform is chosen automatically.
When this register is written to, the value of SCALE[4:0] is stored in one of 12 storage
locations indexed by the WAVEFORM[3:0] bits of the Pulse Waveform Storage Write
Address #2 register. Thus to set up scaling factors for more than one waveform, this
register should be written to a number of times, with WAVEFORM[3:0] set to the different
waveform numbers, as appropriate.
The SCALE[4:0] bits scale the maximum output amplitude by increments of 11.14 mA. A
value of 0 (00H) tristates the output while the maximum value of 21 (15H) sets the full
scale current to 234 mA.
Table 12 Transmit Output Amplitude
SCALE[4:0]
Decimal Equiv.
Output Amplitude
00000
0
0 mA (tristate)
00001-10100
1-20
Increments of 11.14 mA for each scale step
10101
21
234 mA total
10110-11111
>21
Reserved
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Document No.: PMC-2012568, Issue 3
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Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
Register 06AH, 0EAH, 16AH, 1EAH, 26AH, 2EAH, 36AH, 3EAH:
XLPG Pulse Waveform Storage Write Address #1
Bit
Type
Function
Default
Bit 7
R/W
SAMPLE[4]
0
Bit 6
R/W
SAMPLE[3]
0
Bit 5
R/W
SAMPLE[2]
0
Bit 4
R/W
SAMPLE[1]
0
Bit 3
R/W
SAMPLE[0]
0
Bit 2
R/W
UI[2]
0
Bit 1
R/W
UI[1]
0
Bit 0
R/W
UI[0]
0
UI[2:0]
The pulse waveform write address is composed of a unit interval selector, a sample selector
and a waveform number. The unit interval selector (UI[2:0]) specifies the unit interval
portion of the address. There are 5 unit intervals, numbered from 0 to 4. UI[2:0] can take
the values 0H, 1H, 2H, 3H and 4H. The values 5H, 6H and 7H are undefined.
SAMPLE[4:0]
The pulse waveform write address is composed of a unit interval selector, a sample selector
and a waveform number. The sample selector (SAMPLE[4:0]) specifies the sample portion
of the address. There are 24 samples, numbered from 0 to 23. SAMPLE[4:0] can thus have
any value from 00H to 17H. The values from 18H to 1FH are undefined.
Note:
•
The Pulse Waveform Storage Write Indirect Address Registers #1 and #2 must be written to
before the Pulse Waveform Storage Data register. In addition, waveform samples must be written in
groups of 5. Within each group of 5 writes, the waveform number and sample selector must remain
constant and the unit interval selector must be set to 0x0, 0x1, 0x2, 0x3 and 0x4 in sequence. See
the Operation section for more details on setting up waveform templates.
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Document No.: PMC-2012568, Issue 3
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Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
Register 06BH, 0EBH, 16BH, 1EBH, 26BH, 2EBH, 36BH, 3EBH:
XLPG Pulse Waveform Storage Write Address #2
Bit
Type
Function
Default
Bit 7
Unused
X
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
Unused
X
Bit 3
R/W
WAVEFORM[3]
0
Bit 2
R/W
WAVEFORM[2]
0
Bit 1
R/W
WAVEFORM[1]
0
Bit 0
R/W
WAVEFORM[0]
0
WAVEFORM[3:0]
The pulse waveform write address is composed of a unit interval selector, a sample selector
and a waveform number. The waveform number (WAVEFORM[3:0]) specifies the
waveform portion of the address. There are 12 waveforms, numbered from 0 to 11.
WAVEFORM[3:0] can thus have any value from 0H to BH. The values from CH to FH are
undefined.
Note:
•
The Pulse Waveform Storage Write Indirect Address Registers #1 and #2 must be written to
before the Pulse Waveform Storage Data register. In addition, waveform samples must be written in
groups of 5. Within each group of 5 writes, the waveform number and sample selector must remain
constant and the unit interval selector must be set to 0x0, 0x1, 0x2, 0x3 and 0x4 in sequence. See
the Operation section for more details on setting up waveform templates.
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Document No.: PMC-2012568, Issue 3
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Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
Register 06CH, 0ECH, 16CH, 1ECH, 26CH, 2ECH, 36CH, 3ECH:
XLPG Pulse Waveform Storage Data
Bit
Type
Bit 7
Function
Default
Unused
X
Bit 6
W
WDAT[6]
X
Bit 5
W
WDAT[5]
X
Bit 4
W
WDAT[4]
X
Bit 3
W
WDAT[3]
X
Bit 2
W
WDAT[2]
X
Bit 1
W
WDAT[1]
X
Bit 0
W
WDAT[0]
X
WDAT[6:0]
The WDAT[6:0] bits contain the write data to be stored in the pulse template RAM, as
addressed by the UI[2:0], SAMPLE[4:0] and WAVEFORM[3:0] bits in the Pulse Waveform
Storage Write Address registers. When writing to the RAM, the address must first be written
to the Pulse Waveform Storage Write Address registers. Writing to the Pulse Waveform
Storage Data register triggers the transfer of data. If the UI portion of the address is 0, 1, 2
or 3, WDAT[6:0] are transferred to internal holding registers. If the UI portion of the
address is 4, WDAT[6:0] are combined with the contents of the holding registers to form a
35-bit long word which is then stored in the pulse template RAM. Waveform samples must
therefore be written in groups of 5 and within each group of 5 writes, the waveform number
and sample selector must remain constant and the unit interval selector must be set to 0x0,
0x1, 0x2, 0x3 and 0x4 in sequence.
WDAT[6:0] are coded in signed magnitude representation. WDAT[6] is the sign bit,
WDAT[5] is the most significant data bit and WDAT[0] is the least significant data bit. The
data values thus can range from –63 to +63.
See the Operation section for more details on setting up custom waveform templates.
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Document No.: PMC-2012568, Issue 3
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Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
Register 06DH, 0EDH, 16DH, 1EDH, 26DH, 2EDH, 36DH, 3EDH: XLPG Fuse Control
Bit
Type
Function
Default
Bit 7
R/W
Reserved
0
Bit 6
R/W
FSTR
0
Bit 5
R/W
Reserved
1
Bit 4
R/W
FSEL
0
Bit 3
R/W
Reserved
0
Bit 2
R/W
Reserved
0
Bit 1
R/W
Reserved
0
Bit 0
R/W
Reserved
0
FSEL
The Fuse Bank Selector (FSEL) bit determines which half of the fuse bus is to be accessed.
When FSEL is logic 0, bits [3:0] of the fuse bus are selected. When FSEL is logic 1, bits
[7:4] of the fuse bus are selected.
FSTR
Fuse latch enable. When FSTR = ‘1’, the latches which drive either the upper or lower 4
bits of the fuse bus (depending on FSEL) are updated with their input data as defined by the
fuse values. When FSTR = ‘0’, the latches retain their previously stored values.
RESERVED
These bits must be set their default for correct operation.
Note:
1.
The four MSB’s of the poly-silicon fuse’s state will be loaded each time the OCTLIU-SH is powered up
or reset. The four LSB poly-silicon fuses are loaded under software control. The following sequence
must be used to load the four LSB fuse registers, each time the OCTLIU-SH is powered up or reset;
Step 1:
Step 2:
Step 3:
Step 4:
Write “00000000” to the XLPG Fuse Control register. This presents the actual fuse
values (LSB only) to the fuse register.
Write “01000000” to load the fuse values into register.
Write “00000000” to latch the register values.
Write “00100000” to power down the poly-silicon fuse analogue circuitry.
These steps can be performed in broadcast mode (SIMUL_REGWR=1, in the Global
Configuration/Clock Monitor register 0x001), so they need not be repeated per channel.
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Document No.: PMC-2012568, Issue 3
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Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
Register 070H, 0F0H, 170H, 1F0H, 270H, 2F0H, 370H, 3F0H: RLPS Configuration and
Status
Bit
Type
Function
Default
Bit 7
R
ALOSI
X
Bit 6
R
ALOSV
X
Bit 5
R/W
ALOSE
0
Bit 4
R/W
SQUELCHE
0
Bit 3
R/W
IDDQ_EN
0
Bit 2
R
Bit 1
Bit 0
R/W
DB_VALID
X
Unused
X
Reserved
1
RESERVED
The Reserved bit must be logic 1 for correct operation.
DB_VALID
The DB_VALID bit indicates if the adaptive equalizer has stabilized. This bit is set if the
equalisation has not changed by more than 2dB (or +/-8 steps in the RAM table) in more
than a selectable count of sampling periods.
IDDQ_EN
The IDDQ enable bit (IDDQ_EN) is used to configure the analogue receiver for IDDQ
tests. When IDDQ_EN is a logic 1, or the IDDQEN bit in the Master Test Control #1
register (004H) is a logic 1, the digital outputs of the analogue receiver are pulled to ground.
SQUELCHE
The output data squelch enable (SQUELCHE) allows control of data squelching in response
to an analogue loss of signal (ALOS) condition. When SQUELCHE is set to logic 1, the
recovered data are forced to all-zeros if the ALOSV register bit is asserted. When
SQUELCHE is set to logic 0, squelching is disabled.
ALOSE
The loss of signal interrupt enable bit (ALOSE) enables the generation of device level
interrupt on a change of Loss of Signal status. When ALOSE is a logic 1, an interrupt is
generated by asserting INTB low when there is a change of the ALOSV status. When
ALOSE is set to logic 0, interrupts are disabled.
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Document No.: PMC-2012568, Issue 3
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Telecom Standard Product Data Sheet
Released
ALOSV
The loss of signal value bit (ALOSV) indicates the loss of signal alarm state.
ALOSI
The loss of signal interrupt bit (ALOSI) is a logic 1 whenever the Loss of Signal indicator
state (ALOSV) changes. This bit is cleared when this register is read.
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Document No.: PMC-2012568, Issue 3
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Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
Register 071H, 0F1H, 171H, 1F1H, 271H, 2F1H, 371H, 3F1H:
RLPS ALOS Detection/Clearance Threshold
Bit
Type
Function
Default
Bit 7
R/W
CLR_THR[3]Reserved
0
Bit 6
R/W
CLR_THR[2]
0
Bit 5
R/W
CLR_THR[1]
0
Bit 4
R/W
CLR_THR[0]
0
Bit 3
R/W
DET_THR[3]Reserved
0
Bit 2
R/W
DET_THR[2]
0
Bit 1
R/W
DET_THR[1]
0
Bit 0
R/W
DET_THR[0]
0
Table 13 ALOS Detection/Clearance Thresholds
THR
Signal level (dB)
0000
8
0001
9
0010
10
0011
11
0100
> 1220
Applicable
Standard
Detection/Clearance
G.775(E1)
Clearance (if <= 9dB)
Note:
•
Cable loss uncertainty for T1 is +/-2dB with 0.2dB margin.
•
Cable loss uncertainty for E1 is +/-1.5dB with 0.3dB margin.
DET_THR[23:0]
DET_THR[23:0] references one of the threshold settings in Table 13 as the ALOS detection
criteria. If the equalised cable loss is greater than or equal to the threshold for N consecutive
pulse periods, where N = 16 * DET_PER stored in the RLPS ALOS Detection Period
Register, ALOS is declared and interrupt set.
CLR_THR[23:0]
CLR_THR[23:0] references one of the threshold settings listed in Table 13 as the ALOS
clearance criteria. ALOS is cleared when the equalised cable loss is less than the threshold
for N consecutive pulse intervals, where N = 16 * CLR_PER stored in the RLPS ALOS
Clearance Period Register.
Reserved
The reserved bits must be set to logic 0 for correct operation.
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Document No.: PMC-2012568, Issue 3
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Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
Register 072H, 0F2H, 172H, 1F2H, 272H, 2F2H, 372H, 3F2H: RLPS ALOS Detection Period
Bit
Type
Function
Default
Bit 7
R/W
DET_PER[7]
0
Bit 6
R/W
DET_PER[6]
0
Bit 5
R/W
DET_PER[5]
0
Bit 4
R/W
DET_PER[4]
0
Bit 3
R/W
DET_PER[3]
0
Bit 2
R/W
DET_PER[2]
0
Bit 1
R/W
DET_PER[1]
0
Bit 0
R/W
DET_PER[0]
1
DET_PER[7:0]
This register specifies the time duration that the equalised cable loss has to remain above
the detection threshold in order for the ALOS to be issued. This duration is equal to
DET_PER * 16 number of pulse intervals, the resulting range is from 16 to 4080 and thus
compliant with all the presently available E1/T1 ALOS detection
standards/recommendations.
Note:
•
In T1 mode the recommended value for the DET_PER[7:0] is 0x20h, which is not the default value.
•
In E1 mode the recommended value for the DET_PER[7:0] is 0x2Dh, which is not the default value.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2012568, Issue 3
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Telecom Standard Product Data Sheet
Released
Register 073H, 0F3H, 173H, 1F3H, 273H, 2F3H, 373H, 3F3H: RLPS ALOS Clearance Period
Bit
Type
Function
Default
Bit 7
R/W
CLR_PER[7]
0
Bit 6
R/W
CLR_PER[6]
0
Bit 5
R/W
CLR_PER[5]
0
Bit 4
R/W
CLR_PER[4]
0
Bit 3
R/W
CLR_PER[3]
0
Bit 2
R/W
CLR_PER[2]
0
Bit 1
R/W
CLR_PER[1]
0
Bit 0
R/W
CLR_PER[0]
1
CLR_PER[7:0]
This register specifies the time duration that the equalised cable loss has to remain below
the clearance threshold in order for the ALOS to be cleared. This duration is equal to
CLR_PER * 16 number of pulse intervals resulting in a range from 16 to 4080 and thus
compliant with all the presently available E1/T1 ALOS clearance standards/
recommendations.
Note:
•
In T1 mode the recommended value for the CLR_PER[7:0] is 0x20h, which is not the default value.
•
In E1 mode the recommended value for the CLR_PER[7:0] is 0x2Dh, which is not the default value.
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Document No.: PMC-2012568, Issue 3
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Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
Register 074H, 0F4H, 174H, 1F4H, 274H, 2F4H, 374H, 3F4H:
RLPS Equalization Indirect Address
Bit
Type
Function
Default
Bit 7
R/W
EQ_ADDR[7]
0
Bit 6
R/W
EQ_ADDR[6]
0
Bit 5
R/W
EQ_ADDR[5]
0
Bit 4
R/W
EQ_ADDR[4]
0
Bit 3
R/W
EQ_ADDR[3]
0
Bit 2
R/W
EQ_ADDR[2]
0
Bit 1
R/W
EQ_ADDR[1]
0
Bit 0
R/W
EQ_ADDR[0]
0
EQ_ADDR [7:0]
Writing to this register initiates an internal uP access request cycle to the RAM. Depending
on the setting of the RWB bit inside the RLPS Equalization Read/WriteB Select, a read or a
write will be performed. During a write cycle, the indirect data bits located in the RLPS
Equalization Indirect Data registers are written into the RAM. For a read request, the
content of the addressed RAM location is written into the RLPS Equalization Indirect Data
registers. This register should be the last register to be written for a uP access.
A waiting period of at least three line rate cycles is needed from when this register is written
until the next indirect data bits are written into any of the respective octant’s RLPS
Equalization Indirect Data registers.
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Register 075H, 0F5H, 175H, 1F5H, 275H, 2F5H, 375H, 3F5H:
RLPS Equalization Read/WriteB Select
Bit
Type
Function
Default
Bit 7
R/W
RWB
1
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
Unused
X
Bit 3
Unused
X
Bit 2
Unused
X
Bit 1
Unused
X
Bit 0
Unused
X
RWB
This bit selects the operation to be performed on the RAM: when RWB is ‘1’, a read from
the equalization RAM is requested; when RWB is set to ‘0’, a write to the RAM is desired.
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Register 076H, 0F6H, 176H, 1F6H, 276H, 2F6H, 376H, 3F6H:
RLPS Equalizer Loop Status and Control
Bit
Type
Function
Default
Bit 7
R/W
Unused
0
Bit 6
R/W
Unused
0
Bit 5
R/W
LOCATION[5]
0
Bit 4
R/W
LOCATION[4]
0
Bit 3
R/W
LOCATION[3]
0
Bit 2
R/W
LOCATION[2]
0
Bit 1
R/W
LOCATION[1]
0
Bit 0
R/W
LOCATION[0]
0
LOCATION[5:0]
Writing to this register overwrites a counter which serves as the read address to the
equalization RAM. Reading this register returns the current value of the counter and thus
an indication of the cable loss as estimated by the equaliser.
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Register 077H, 0F7H, 177H, 1F7H, 277H, 2F7H, 377H, 3F7H: RLPS Equalizer Configuration
Bit
Type
Function
Default
Bit 7
R/W
Reserved
0
Bit 6
R/W
Reserved
0
Bit 5
Unused
X
Bit 4
R/W
Reserved
0
Bit 3
R/W
EQ_EN
0
Bit 2
R/W
Reserved
0
Bit 1
R/W
Reserved
1
Bit 0
R/W
Reserved
1
EQ_EN
The EQ_EN bit enables operation of the equaliser when set to logic 1. This bit defaults to
logic 0 after reset and must be set to logic 1, but only after the equalisation RAM has been
initialised.
Reserved
This bit must be set to its default value for normal operation.
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Register 078H, 0F8H, 178H, 1F8H, 278H, 2F8H, 378H, 3F8H:
RLPS Equalization Indirect Data
Bit
Type
Function
Default
7
R/W
EQ_DATA[31]
0
6
R/W
EQ_DATA[30]
0
5
R/W
EQ_DATA[29]
0
4
R/W
EQ_DATA[28]
0
3
R/W
EQ_DATA[27]
0
2
R/W
EQ_DATA[26]
0
1
R/W
EQ_DATA[25]
0
0
R/W
EQ_DATA[24]
0
EQ_DATA[31:24]
This register consists of 2-parts: read-only and write-only. Writing this register affects the
most significant byte of the input-data to the equalization RAM. Reading it returns the
MSB of the RAM location indexed by the RLPS Equalization Indirect Address register.
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Register 079H, 0F9H, 179H, 1F9H, 279H, 2F9H, 379H, 3F9H:
RLPS Equalization Indirect Data
Bit
Type
Function
Default
7
R/W
EQ_DATA[23]
0
6
R/W
EQ_DATA[22]
0
5
R/W
EQ_DATA[21]
0
4
R/W
EQ_DATA[20]
0
3
R/W
EQ_DATA[19]
0
2
R/W
EQ_DATA[18]
0
1
R/W
EQ_DATA[17]
0
0
R/W
EQ_DATA[16]
0
EQ_DATA[23:16]
This register consists of 2-parts: read-only and write-only. Writing this register affects the
second most significant byte of the input-data to the equalization RAM. Reading it returns
the second MSB of the RAM location indexed by the RLPS Equalization Indirect Address
register.
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Register 07AH, 0FAH, 17AH, 1FAH, 27AH, 2FAH, 37AH, 3FAH:
RLPS Equalization Indirect Data
Bit
Type
Function
Default
7
R/W
EQ_DATA[15]
0
6
R/W
EQ_DATA[14]
0
5
R/W
EQ_DATA[13]
0
4
R/W
EQ_DATA[12]
0
3
R/W
EQ_DATA[11]
0
2
R/W
EQ_DATA[10]
0
1
R/W
EQ_DATA[9]
0
0
R/W
EQ_DATA[8]
0
EQ_DATA[15:8]
This register consists of 2-parts: read-only and write-only. Writing this register affects the
second least significant byte of the input-data to the equalization RAM. Reading it returns
the corresponding bits of the RAM location indexed by the RLPS Equalization Indirect
Address register.
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Register 07BH, 0FBH, 17BH, 1FBH, 27BH, 2FBH, 37BH, 3FBH:
RLPS Equalization Indirect Data
Bit
Type
Function
Default
7
R/W
EQ_DATA[7]
0
6
R/W
EQ_DATA[6]
0
5
R/W
EQ_DATA[5]
0
4
R/W
EQ_DATA[4]
0
3
R/W
EQ_DATA[3]
0
2
R/W
EQ_DATA[2]
0
1
R/W
EQ_DATA[1]
0
0
R/W
EQ_DATA[0]
0
EQ_DATA[7:0]
This register consists of 2-parts: read-only and write-only. Writing this register affects the
least significant byte of the input-data to the equalization RAM. Reading it returns the LSB
of the RAM location indexed by the RLPS Equalization Indirect Address register.
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Register 07CH, 0FCH, 17CH, 1FCH, 27CH, 2FCH, 37CH, 3FCH:
RLPS Equalizer Voltage Thresholds #1
Bit
Type
7
6
Function
Default
unused
X
unused
X
5
R/W
VREF[5]
1
4
R/W
VREF[4]
1
3
R/W
VREF[3]
0
2
R/W
VREF[2]
1
1
R/W
VREF[1]
0
0
R/W
VREF[0]
1
VREF[5:0]
The VREF[5:0] bits set the voltage thresholds of amplitude comparators within the RLPS.
For T1 mode, the VREF[5:0] bits must be programmed to 26H (‘b100110). For E1 mode,
the VREF[5:0] bits must be programmed to 26H (‘b100110).
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Register 07DH, 0FDH, 17DH, 1FDH, 27DH, 2FDH, 37DH, 3FDH:
RLPS Equalizer Voltage Thresholds #2
Bit
Type
Function
Default
7
R/W
CUTOFF[1]
0
6
R/W
CUTOFF[0]
0
5
Unused
X
4
Unused
X
3
Unused
X
2
R/W
VREF[8]
0
1
R/W
VREF[7]
1
0
R/W
VREF[6]
1
CUTOFF[1:0]
The CUTOFF[1:0] bits control cutoff frequencies of the bandlimiter and equaliser within
the RLPS. For T1 mode, the CUTOFF[1:0] bits must be programmed to 3H (‘b11). For E1
mode, the CUTOFF[1:0] bits must be programmed to 0H (‘b00).
VREF[8:6]
The VREF[8:6] bits set the voltage thresholds of amplitude comparators within the RLPS.
For T1 mode, the VREF[8:6] bits must be programmed to 3H (‘b011). For E1 mode, the
VREF[8:6] bits must be programmed to 3H (‘b011).
Note:
•
This register defaults to E1 mode.
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11
Test Features Description
11.1 JTAG Test Port
The OCTLIU-SH JTAG Test Access Port (TAP) allows access to the TAP controller and the 4
TAP registers: instruction, bypass, device identification and boundary scan. Using the TAP,
device input logic levels can be read, device outputs can be forced, the device can be identified
and the device scan path can be bypassed. For more details on the JTAG port, please refer to
the Operations section.
Instruction Register
Length: 3 bits
Selected Register
Instruction Codes,
IR[2:0]
EXTEST
Boundary Scan
000
IDCODE
Identification
001
SAMPLE
Boundary Scan
010
BYPASS
Bypass
011
BYPASS
Bypass
100
STCTEST
Boundary Scan
101
BYPASS
Bypass
110
BYPASS
Bypass
111
Instructions
Identification Register
Length – 32 bits
Version number – 1H for Rev A.
Part Number – 4318H
Manufacturer’s identification code – 0CDH
Device identification – 143180CDH for Rev. A
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Boundary Scan Register
Length: 131
Table 14 Boundary Scan Register
Scan
Cell Type Device
Register
ID
Bit
Pin/Enable
Scan
Cell Type
Register
Bit
A[10]
130
IN_CELL
0
DACTIVE
64
OUT_CELL -
A[9]
129
IN_CELL
0
OEB_DDATA[7] 63
OUT_CELL -
A[8]
128
IN_CELL
0
DDATA[7]
62
OUT_CELL -
A[7]
127
IN_CELL
1
Unused
61
OUT_CELL -
A[6]
126
IN_CELL
0
Unused
60
OUT_CELL -
A[5]
125
IN_CELL
1
APL
59
IN_CELL
-
A[4]
124
IN_CELL
0
ADATA[4]
58
IN_CELL
-
A[3]
123
IN_CELL
0
Logic 0
57
IN_CELL
-
A[2]
122
IN_CELL
0
AV5
56
IN_CELL
-
A[1]
121
IN_CELL
0
ADATA[5]
55
IN_CELL
-
A[0]
120
IN_CELL
1
Logic 0
54
IN_CELL
-
Pin/Enable
Logic 0
119
IN_CELL
1
Logic 0
53
IN_CELL
-
ADATA[0]
118
IN_CELL
0
ADATA[6]
52
IN_CELL
-
REFCLK
117
IN_CELL
0
Logic 0
51
IN_CELL
-
Logic 0
116
IN_CELL
0
Logic 0
50
IN_CELL
-
ADATA[1]
115
IN_CELL
1
ADATA[7]
49
IN_CELL
-
AC1FP
114
IN_CELL
1
Logic 0
48
IN_CELL
-
Logic 0
113
IN_CELL
0
Logic 0
47
IN_CELL
-
ADATA[2]
112
IN_CELL
0
Logic 0
46
IN_CELL
-
DC1FP
111
IN_CELL
0
Unused
45
OUT_CELL -
Logic 0
110
IN_CELL
0
Unused
44
IO_CELL
ADATA[3]
109
IN_CELL
0
Unused
43
OUT_CELL -
ADP
108
IN_CELL
0
Unused
42
IO_CELL
Unused
107
OUT_CELL 0
OEB_PO
41
OUT_CELL -
Unused
106
OUT_CELL 1
PO
40
OUT_CELL -
OEB_DDATA[0] 105
OUT_CELL 1
PI
39
IN_CELL
DDATA[0]
104
OUT_CELL 0
OEB_PI
38
OUT_CELL -
Unused
103
OUT_CELL 0
Unused
37
OUT_CELL -
Unused
102
OUT_CELL 1
Unused
36
OUT_CELL -
Unused
101
OUT_CELL 1
Unused
35
OUT_CELL -
Unused
100
OUT_CELL 0
Unused
34
OUT_CELL -
OEB_DDATA[1] 99
OUT_CELL 1
Unused
33
OUT_CELL -
DDATA[1]
OUT_CELL -
Logic 0
32
IN_CELL
98
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Pin/Enable
Scan
Cell Type Device
Register
ID
Bit
Pin/Enable
Scan
Cell Type
Register
Bit
Unused
97
OUT_CELL -
OEB_LOS_L1
31
Unused
96
OUT_CELL -
LOS_L1
30
OUT_CELL -
Unused
95
OUT_CELL -
OEB_LOS
29
OUT_CELL -
Unused
94
OUT_CELL -
LOS
28
OUT_CELL -
OEB_DDATA[2] 93
OUT_CELL -
OEB_RSYNC
27
OUT_CELL -
DDATA[2]
OUT_CELL -
92
OUT_CELL -
RSYNC
26
OUT_CELL -
OEB_C1FPOUT 91
OUT_CELL -
RES[1]
25
IN_CELL
-
C1FPOUT
90
OUT_CELL -
RSTB
24
IN_CELL
-
Unused
89
OUT_CELL -
XCLK
23
IN_CELL
-
Unused
88
OUT_CELL -
Logic 1
22
IN_CELL
-
OEB_DDATA[3] 87
OUT_CELL -
OEB_D[7]
21
OUT_CELL -
DDATA[3]
86
OUT_CELL -
D[7]
20
IO_CELL
OEB_DDP
85
OUT_CELL -
OEB_D[6]
19
OUT_CELL -
DDP
84
OUT_CELL -
D[6]
18
IO_CELL
OEB_DPL
83
OUT_CELL -
OEB_D[5]
17
OUT_CELL -
DPL
-
82
OUT_CELL -
D[5]
16
IO_CELL
OEB_DDATA[4] 81
OUT_CELL -
OEB_D[4]
15
OUT_CELL -
-
DDATA[4]
80
OUT_CELL -
D[4]
14
IO_CELL
Unused
79
OUT_CELL -
OEB_D[3]
13
OUT_CELL -
-
Unused
78
OUT_CELL -
D[3]
12
IO_CELL
OEB_DV5
77
OUT_CELL -
OEB_D[2]
11
OUT_CELL -
-
DV5
76
OUT_CELL -
D[2]
10
IO_CELL
OEB_DDATA[5] 75
OUT_CELL -
OEB_D[1]
9
OUT_CELL -
DDATA[5]
74
OUT_CELL -
D[1]
8
IO_CELL
Unused
73
OUT_CELL -
OEB_D[0]
7
OUT_CELL -
Unused
72
OUT_CELL -
D[0]
6
IO_CELL
-
Unused
71
OUT_CELL -
OEB_INTB
5
OUT_CELL -
Unused
70
OUT_CELL -
INTB
4
IO_CELL
-
OEB_DDATA[6] 69
OUT_CELL -
CSB
3
IN_CELL
-
DDATA[6]
68
OUT_CELL -
RDB
2
IN_CELL
-
Unused
67
OUT_CELL -
WRB
1
IN_CELL
-
Unused
66
OUT_CELL -
ALE
0
IN_CELL
-
OEB_DACTIVE 65
OUT_CELL -
Notes:
1.
OEB signals, when set low, will set the corresponding bi-directional signal to an output.
2.
OEB signals, when set high, will set the corresponding output to high impedance.
3.
ALE is the first bit in the boundary scan chain scanned in and out. It is closest to TDO in the scan
chain.
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4.
IN_CELL‘s labelled “Logic 0” will always capture 0, since they are permanently tied to VSS.
5.
IN_CELL‘s labelled “Logic 1” will always capture 1, since they are permanently tied to VDD.
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12
Operation
12.1 Configuring the OCTLIU-SH from Reset
After a system reset (either via the RSTB pin or via the RESET register bit), the OCTLIU-SH
will default to the following settings:
Table 15 Default Settings
Setting
Receiver Section
Transmitter Section
T1/E1 mode
T1
T1
Line Code
B8ZS
B8ZS
Line interface
Pins RXTIP[x] and RXRING[x]
active short haul analogue inputs
TXTIP1[x], TXTIP2[x],
TXRING1[x], TXRING2[x]
tristated
Timing Options
Not applicable
Jitter attenuation enabled, with
output clock frequency
referenced to the serial SBI
transmit clock.
Diagnostics
All diagnostic modes disabled
All diagnostic modes disabled
12.2 Servicing Interrupts
The OCTLIU-SH will assert INTB to logic 0 when a condition that is configured to produce an
interrupt occurs. To find which condition caused this interrupt to occur, the procedure outlined
below should be followed:
1. Read the bits of the Master Interrupt Source registers (002H and 003H) to identify which
octants and/or SBI interface blocks generated the interrupt. For example, a logic one read
in the LIU[2] bit of the Master Interrupt Source #1 register indicates that octant #2 produced
the interrupt.
2. Read the bits of the second level Line Interface Interrupt Source registers to identify the
block within the octant generating the interrupt.
The Interrupt Source registers for octant #1 are at addresses 00CH and 00DH.
The Interrupt Source registers for octant #2 are at addresses 08CH and 08DH.
The Interrupt Source registers for octant #3 are at addresses 10CH and 10DH.
The Interrupt Source registers for octant #4 are at addresses 18CH and 18DH.
The Interrupt Source registers for octant #5 are at addresses 20CH and 20DH.
The Interrupt Source registers for octant #6 are at addresses 28CH and 28DH.
The Interrupt Source registers for octant #7 are at addresses 30CH and 30DH.
The Interrupt Source registers for octant #8 are at addresses 38CH and 38DH.
3. Read the third level Interrupt Source bits to identify the interrupt source. (These bits are
contained within the registers for the various functional blocks.)
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4. Service the interrupt.
5. If the INTB pin is still logic 0, then there are still interrupts to be serviced. Otherwise, all
interrupts have been serviced. Wait for the next assertion of INTB
12.3 Using the Performance Monitoring Features
The PMON blocks are provided for performance monitoring purposes. The PMON blocks
within each LIU are used to monitor LCV events. An accumulation interval is initiated by
writing to one of the PMON event counter register addresses or by writing to the Line Interface
Interrupt Source / PMON Update register. After initiating an accumulation interval, 3.5
recovered clock periods must be allowed to elapse to permit the PMON counter values to be
properly transferred before the PMON registers may be read.
12.4 Using the Transmit Line Pulse Generator
The internal D/A pulse waveform template RAM, accessible via the microprocessor bus, can be
used to create up to 12 custom waveforms. The RAM is accessed indirectly through the XLPG
Pulse Waveform Storage Write Address and XLPG Pulse Waveform Storage Data registers. The
values written into the pulse waveform storage registers correspond to one of 127 quantized
levels. 24 samples are output during every transmit clock cycle.
The waveform being programmed is completely arbitrary and programming must be done
properly in order to meet the various T1 and E1 template specifications. The SCALE[4:0] bits
of Line Driver Configuration Register bits are used to obtain a proper output amplitude. It must
also be noted that since samples from the 5 UI are added before driving the DAC, it is possible
to create arithmetic overflows.
The following tables contain the waveform values to be programmed for different situations.
Table 16 to Table 21 specify waveform values typically used for short haul transmission. Table
22 to Table 27 specify waveform values for compliance to the AT&T TR62411 ACCUNET T1.5
pulse template. Table 28 and Table 29 specify waveform values for E1 transmission.
The programming of template values must observe the following sequencing rule: Samples
must be written in groups of 5 at a time, each group consisting of the 5 UI values corresponding
to a particular waveform and sample number. For example, the following programming
sequence fragment is legal:
:
Write
Write
Write
Write
Write
Write
Write
Write
Write
data
data
data
data
data
data
data
data
data
for
for
for
for
for
for
for
for
for
WAVEFORM=0,
WAVEFORM=0,
WAVEFORM=0,
WAVEFORM=0,
WAVEFORM=0,
WAVEFORM=1,
WAVEFORM=1,
WAVEFORM=1,
WAVEFORM=1,
SAMPLE=0, UI=0
SAMPLE=0, UI=1
SAMPLE=0, UI=2
SAMPLE=0, UI=3
SAMPLE=0, UI=4
SAMPLE=12, UI=0
SAMPLE=12, UI=1
SAMPLE=12, UI=2
SAMPLE=12, UI=3
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Write data for WAVEFORM=1, SAMPLE=12, UI=4
:
Whereas the following sequence fragment is illegal:
:
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
:
data
data
data
data
data
data
data
data
data
data
for
for
for
for
for
for
for
for
for
for
WAVEFORM=0,
WAVEFORM=0,
WAVEFORM=0,
WAVEFORM=0,
WAVEFORM=0,
WAVEFORM=0,
WAVEFORM=0,
WAVEFORM=0,
WAVEFORM=0,
WAVEFORM=0,
SAMPLE=0,
SAMPLE=1,
SAMPLE=2,
SAMPLE=3,
SAMPLE=4,
SAMPLE=5,
SAMPLE=6,
SAMPLE=7,
SAMPLE=8,
SAMPLE=9,
UI=0
UI=0
UI=0
UI=0
UI=0
UI=0
UI=0
UI=0
UI=0
UI=0
This restriction is necessary because each group of five 7-bit samples is stored in a temporary
holding register as it is written. The 5 samples are then transferred to the pulse template RAM
as a single 35-bit word when the 5th sample (i.e. the sample whose UI[2:0] address field is set to
4) is written.
Prior to commencing normal operation, the HIGHZ bit of the octant’s XLPG Line Driver
Configuration register must be programmed to logic 0 to remove the high impedance state from
the TXTIP1[x], TXTIP2[x], TXRING1[x] and TXRING2[x] Transmit outputs.
The Pulse Template Selection (PT_SEL[3:0]) bits in registers 00BH, 08BH, 10BH, 18BH,
20BH, 30BH and 38BH select the waveforms to be used by each octant.
When PT_SEL[3:0] = “0000”, Pulse Template RAM table 1 is selected.
When PT_SEL[3:0] = “0001”, Pulse Template RAM table 2 is selected.
When PT_SEL[3:0] = “0010”, Pulse Template RAM table 3 is selected.
When PT_SEL[3:0] = “0011”, Pulse Template RAM table 4 is selected.
When PT_SEL[3:0] = “0100”, Pulse Template RAM table 5 is selected.
When PT_SEL[3:0] = “0101”, Pulse Template RAM table 6 is selected.
When PT_SEL[3:0] = “0110”, Pulse Template RAM table 7 is selected.
When PT_SEL[3:0] = “0111”, Pulse Template RAM table 8 is selected.
When PT_SEL[3:0] = “1000”, Pulse Template RAM table 9 is selected.
When PT_SEL[3:0] = “1001”, Pulse Template RAM table 10 is selected.
When PT_SEL[3:0] = “1010”, Pulse Template RAM table 11 is selected.
When PT_SEL[3:0] = “1011”, Pulse Template RAM table 12 is selected.
Note:
•
The internal pulse template RAM tables 1-12 which are indexed by PT_SEL[3:0] must be initialized via
the microprocessor interface. Recommended values for the various short-haul standards are shown in
tables Table 16 through Table 29.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2012568, Issue 3
170
Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
Table 16 T1.102 Transmit Waveform Values for T1 Short Haul (0 – 110 ft.)
Sample number
UI #0
UI #1
UI #2
UI #3
UI #4
1
00
44
00
00
00
2
00
43
00
00
00
3
0F
42
00
00
00
4
27
42
00
00
00
5
3A
41
00
00
00
6
39
41
00
00
00
7
37
00
00
00
00
8
35
00
00
00
00
9
34
00
00
00
00
10
34
00
00
00
00
11
34
00
00
00
00
12
34
00
00
00
00
13
34
00
00
00
00
14
33
00
00
00
00
15
2B
00
00
00
00
16
21
00
00
00
00
17
55
00
00
00
00
18
54
00
00
00
00
19
50
00
00
00
00
20
4E
00
00
00
00
21
4B
00
00
00
00
22
49
00
00
00
00
23
47
00
00
00
00
24
44
00
00
00
00
Note: SCALE[4:0] programmed to 0BH.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2012568, Issue 3
171
Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
Table 17 T1.102 Transmit Waveform Values for T1 Short Haul (110 – 220 ft.)
Sample number
UI #0
UI #1
UI #2
UI #3
UI #4
1
00
45
00
00
00
2
00
44
00
00
00
3
1E
43
00
00
00
4
30
42
00
00
00
5
3C
41
00
00
00
6
39
00
00
00
00
7
34
00
00
00
00
8
31
00
00
00
00
9
31
00
00
00
00
10
30
00
00
00
00
11
30
00
00
00
00
12
30
00
00
00
00
13
30
00
00
00
00
14
30
00
00
00
00
15
25
00
00
00
00
16
0D
00
00
00
00
17
65
00
00
00
00
18
5A
00
00
00
00
19
54
00
00
00
00
20
50
00
00
00
00
21
4B
00
00
00
00
22
49
00
00
00
00
23
48
00
00
00
00
24
44
00
00
00
00
Note:
•
SCALE[4:0] programmed to 0DH.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2012568, Issue 3
172
Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
Table 18 T1.102 Transmit Waveform Values for T1 Short Haul (220 – 330 ft.)
Sample number
UI #0
UI #1
UI #2
UI #3
UI #4
1
00
45
00
00
00
2
19
43
00
00
00
3
2D
43
00
00
00
4
3C
42
00
00
00
5
3A
00
00
00
00
6
37
00
00
00
00
7
32
00
00
00
00
8
31
00
00
00
00
9
2F
00
00
00
00
10
2E
00
00
00
00
11
2D
00
00
00
00
12
2D
00
00
00
00
13
2C
00
00
00
00
14
2B
00
00
00
00
15
14
00
00
00
00
16
6C
00
00
00
00
17
5D
00
00
00
00
18
54
00
00
00
00
19
52
00
00
00
00
20
4E
00
00
00
00
21
4C
00
00
00
00
22
4B
00
00
00
00
23
47
00
00
00
00
24
46
00
00
00
00
Note:
•
SCALE[4:0] programmed to 0EH.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2012568, Issue 3
173
Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
Table 19 T1.102 Transmit Waveform Values for T1 Short Haul (330 – 440 ft.)
Sample number
UI #0
UI #1
UI #2
UI #3
UI #4
1
00
44
00
00
00
2
21
43
00
00
00
3
36
42
00
00
00
4
3E
41
00
00
00
5
39
00
00
00
00
6
34
00
00
00
00
7
2F
00
00
00
00
8
2E
00
00
00
00
9
2E
00
00
00
00
10
2D
00
00
00
00
11
2D
00
00
00
00
12
2C
00
00
00
00
13
2C
00
00
00
00
14
28
00
00
00
00
15
01
00
00
00
00
16
75
00
00
00
00
17
5D
00
00
00
00
18
54
00
00
00
00
19
4F
00
00
00
00
20
4C
00
00
00
00
21
49
00
00
00
00
22
47
00
00
00
00
23
46
00
00
00
00
24
45
00
00
00
00
Note:
•
SCALE[4:0] programmed to 0FH.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2012568, Issue 3
174
Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
Table 20 T1.102 Transmit Waveform Values for T1 Short Haul (440 – 550 ft.)
Sample number
UI #0
UI #1
UI #2
UI #3
UI #4
1
00
44
00
00
00
2
1D
43
00
00
00
3
39
43
00
00
00
4
3E
42
00
00
00
5
3B
42
00
00
00
6
31
02
00
00
00
7
2E
02
00
00
00
8
2D
00
00
00
00
9
2C
00
00
00
00
10
2C
00
00
00
00
11
2B
00
00
00
00
12
2B
00
00
00
00
13
29
00
00
00
00
14
21
00
00
00
00
15
08
00
00
00
00
16
7E
00
00
00
00
17
68
00
00
00
00
18
5A
00
00
00
00
19
52
00
00
00
00
20
4C
00
00
00
00
21
49
00
00
00
00
22
47
00
00
00
00
23
46
00
00
00
00
24
45
00
00
00
00
Note:
•
SCALE[4:0] programmed to 10H.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2012568, Issue 3
175
Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
Table 21 T1.102 Transmit Waveform Values for T1 Short Haul (550 – 660 ft.)
Sample number
UI #0
UI #1
UI #2
UI #3
UI #4
1
00
44
00
00
00
2
03
44
00
00
00
3
37
43
00
00
00
4
3E
42
00
00
00
5
37
41
00
00
00
6
31
00
00
00
00
7
26
00
00
00
00
8
27
00
00
00
00
9
26
00
00
00
00
10
26
00
00
00
00
11
25
00
00
00
00
12
24
00
00
00
00
13
24
00
00
00
00
14
26
00
00
00
00
15
17
00
00
00
00
16
7E
00
00
00
00
17
71
00
00
00
00
18
59
00
00
00
00
19
55
00
00
00
00
20
4A
00
00
00
00
21
49
00
00
00
00
22
47
00
00
00
00
23
46
00
00
00
00
24
45
00
00
00
00
Note:
•
SCALE[4:0] programmed to 12H.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2012568, Issue 3
176
Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
Table 22 TR62411 Transmit Waveform Values for T1 Short Haul (0 – 110 ft.)
Sample number
UI #0
UI #1
UI #2
UI #3
UI #4
1
00
41
00
00
00
2
00
41
00
00
00
3
0F
41
00
00
00
4
27
41
00
00
00
5
3A
41
00
00
00
6
39
00
00
00
00
7
37
00
00
00
00
8
35
00
00
00
00
9
34
00
00
00
00
10
34
00
00
00
00
11
34
00
00
00
00
12
34
00
00
00
00
13
34
00
00
00
00
14
33
00
00
00
00
15
2B
00
00
00
00
16
21
00
00
00
00
17
57
00
00
00
00
18
56
00
00
00
00
19
51
00
00
00
00
20
4D
00
00
00
00
21
49
00
00
00
00
22
45
00
00
00
00
23
43
00
00
00
00
24
41
00
00
00
00
Note:
•
SCALE[4:0] programmed to 0BH.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2012568, Issue 3
177
Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
Table 23 TR62411 Transmit Waveform Values for T1 Short Haul (110 – 220 ft.)
Sample number
UI #0
UI #1
UI #2
UI #3
UI #4
1
00
41
00
00
00
2
00
41
00
00
00
3
1E
41
00
00
00
4
30
41
00
00
00
5
3C
00
00
00
00
6
39
00
00
00
00
7
34
00
00
00
00
8
31
00
00
00
00
9
31
00
00
00
00
10
30
00
00
00
00
11
30
00
00
00
00
12
30
00
00
00
00
13
30
00
00
00
00
14
30
00
00
00
00
15
25
00
00
00
00
16
0D
00
00
00
00
17
65
00
00
00
00
18
5A
00
00
00
00
19
54
00
00
00
00
20
50
00
00
00
00
21
4C
00
00
00
00
22
46
00
00
00
00
23
43
00
00
00
00
24
41
00
00
00
00
Note:
•
SCALE[4:0] programmed to 0DH.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2012568, Issue 3
178
Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
Table 24 TR62411 Transmit Waveform Values for T1 Short Haul (220 – 330 ft.)
Sample number
UI #0
UI #1
UI #2
UI #3
UI #4
1
00
41
00
00
00
2
19
41
00
00
00
3
2D
41
00
00
00
4
3C
41
00
00
00
5
3A
00
00
00
00
6
37
00
00
00
00
7
32
00
00
00
00
8
31
00
00
00
00
9
2F
00
00
00
00
10
2E
00
00
00
00
11
2D
00
00
00
00
12
2D
00
00
00
00
13
2C
00
00
00
00
14
2B
00
00
00
00
15
14
00
00
00
00
16
6C
00
00
00
00
17
5E
00
00
00
00
18
55
00
00
00
00
19
52
00
00
00
00
20
4E
00
00
00
00
21
46
00
00
00
00
22
45
00
00
00
00
23
41
00
00
00
00
24
41
00
00
00
00
Note:
•
SCALE[4:0] programmed to 0EH.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2012568, Issue 3
179
Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
Table 25 TR62411 Transmit Waveform Values for T1 Short Haul (330 – 440 ft.)
Sample number
UI #0
UI #1
UI #2
UI #3
UI #4
1
00
41
00
00
00
2
21
41
00
00
00
3
36
41
00
00
00
4
3E
41
00
00
00
5
39
00
00
00
00
6
34
00
00
00
00
7
2F
00
00
00
00
8
2E
00
00
00
00
9
2E
00
00
00
00
10
2D
00
00
00
00
11
2D
00
00
00
00
12
2C
00
00
00
00
13
2C
00
00
00
00
14
28
00
00
00
00
15
01
00
00
00
00
16
75
00
00
00
00
17
5D
00
00
00
00
18
54
00
00
00
00
19
4F
00
00
00
00
20
4A
00
00
00
00
21
46
00
00
00
00
22
44
00
00
00
00
23
41
00
00
00
00
24
41
00
00
00
00
Note:
•
SCALE[4:0] programmed to 0FH.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2012568, Issue 3
180
Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
Table 26 TR62411 Transmit Waveform Values for T1 Short Haul (440 – 550 ft.)
Sample number
UI #0
UI #1
UI #2
UI #3
UI #4
1
00
41
00
00
00
2
1D
41
00
00
00
3
39
41
00
00
00
4
3E
41
00
00
00
5
3B
00
00
00
00
6
31
00
00
00
00
7
2E
00
00
00
00
8
2D
00
00
00
00
9
2C
00
00
00
00
10
2C
00
00
00
00
11
2B
00
00
00
00
12
2B
00
00
00
00
13
29
00
00
00
00
14
21
00
00
00
00
15
08
00
00
00
00
16
7E
00
00
00
00
17
68
00
00
00
00
18
5A
00
00
00
00
19
52
00
00
00
00
20
4B
00
00
00
00
21
41
00
00
00
00
22
41
00
00
00
00
23
41
00
00
00
00
24
41
00
00
00
00
Note:
•
SCALE[4:0] programmed to 10H.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2012568, Issue 3
181
Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
Table 27 TR62411 Transmit Waveform Values for T1 Short Haul (550 – 660 ft.)
Sample number
UI #0
UI #1
UI #2
UI #3
UI #4
1
00
41
00
00
00
2
03
41
00
00
00
3
37
41
00
00
00
4
3E
41
00
00
00
5
37
00
00
00
00
6
31
00
00
00
00
7
26
00
00
00
00
8
27
00
00
00
00
9
26
00
00
00
00
10
26
00
00
00
00
11
25
00
00
00
00
12
24
00
00
00
00
13
24
00
00
00
00
14
26
00
00
00
00
15
17
00
00
00
00
16
7E
00
00
00
41
17
70
00
00
00
41
18
59
00
00
00
01
19
51
00
00
00
01
20
4B
00
00
00
01
21
42
00
00
00
00
22
41
00
00
00
00
23
41
00
00
00
00
24
41
00
00
00
00
Note:
•
SCALE[4:0] programmed to 12H.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2012568, Issue 3
182
Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
Table 28 Transmit Waveform Values for E1 120 Ohm
Sample number
UI #0
UI #1
UI #2
UI #3
UI #4
1
00
00
00
00
00
2
00
00
00
00
00
3
0A
00
00
00
00
4
3C
00
00
00
00
5
3C
00
00
00
00
6
37
00
00
00
00
7
35
00
00
00
00
8
34
00
00
00
00
9
34
00
00
00
00
10
34
00
00
00
00
11
34
00
00
00
00
12
34
00
00
00
00
13
34
00
00
00
00
14
34
00
00
00
00
15
27
00
00
00
00
16
00
00
00
00
00
17
47
00
00
00
00
18
41
00
00
00
00
19
00
00
00
00
00
20
00
00
00
00
00
21
00
00
00
00
00
22
00
00
00
00
00
23
00
00
00
00
00
24
00
00
00
00
00
Note:
•
SCALE[4:0] programmed to 0AH.
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Released
Table 29 Transmit Waveform Values for E1 75 Ohm
Sample number
UI #0
UI #1
UI #2
UI #3
UI #4
1
00
00
00
00
00
2
00
00
00
00
00
3
00
00
00
00
00
4
3A
00
00
00
00
5
37
00
00
00
00
6
38
00
00
00
00
7
38
00
00
00
00
8
37
00
00
00
00
9
36
00
00
00
00
10
36
00
00
00
00
11
35
00
00
00
00
12
35
00
00
00
00
13
35
00
00
00
00
14
35
00
00
00
00
15
36
00
00
00
00
16
0A
00
00
00
00
17
00
00
00
00
00
18
00
00
00
00
00
19
00
00
00
00
00
20
00
00
00
00
00
21
00
00
00
00
00
22
00
00
00
00
00
23
00
00
00
00
00
24
00
00
00
00
00
Note:
•
SCALE[4:0] programmed to 0DH.
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Released
12.5 Using the Line Receiver
The line receiver must be properly initialized for correct operation. Several register bits must be
programmed and the equalizer RAM table must be initialized according to the appropriate table
below.
The RLPS equalizer RAM content is programmed by the RLPS Equalization Indirect Data
registers for each address location. The address location is given by the octant’s RLPS
Equalization Indirect Address register. A read or write request is done by setting the RWB bit in
the octant’s RLPS Equalization Read/WriteB Select register.
Note that several registers are not their default values. The EQ_EN bit of the RLPS Equalizer
Configuration register must be set to logic 1. The CUTOFF[1:0] bits of the RLPS Voltage
Thresholds #2 register must be programmed to 3H (11B) for T1 mode or 0H (00B) for E1 mode.
Table 30 summarizes the values the RLPS registers are to contain.
Table 30 RLPS Register Programming
Register
Data Value
Bin
Hex
RLPS Configuration and Status
XX000XX1
01H
RLPS ALOS Detection/ Clearance Threshold
X000X000
00H
RLPS ALOS Detection Period
00000001
01H
RLPS ALOS Clearance Period
00000001
01H
RLPS Equalization Indirect Address
00000000
00H
RLPS Equalization RAM Read/WriteB Select
1XXXXXXX
80H
RLPS Equalizer Loop Status and Control
00000000
00H
RLPS Equalizer Configuration
00X01011
0BH
RLPS Equalization Indirect Data[31:24]
*
*
RLPS Equalization Indirect Data[23:16]
*
*
RLPS Equalization Indirect Data[15:8]
*
*
RLPS Equalization Indirect Data[7:0]
*
*
RLPS Voltage Thresholds #1
XX100110
26H
(T1 mode)
11XXX011
C3H
(E1 mode)
00XXX011
03H
RLPS Voltage Thresholds #2
Since the line receiver supports both E1 and T1 standards over short haul cables, the line
receiver has two normal modes of operation, as selected by the E1/T1B bit of the Global
Configuration register.
Access to the Equalizer RAM is provided by means of Indirect Access Registers A typical
programming sequence follows. This programming sequence is repeated for each of the 256
Equalizer RAM Addresses.
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Telecom Standard Product Data Sheet
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WRITE RLPS Indirect Data Register
<31 – 24 Bits of Data>
WRITE RLPS Indirect Data Register
<23 – 16 Bits of Data>
WRITE RLPS Indirect Data Register
<15 – 8 Bits of Data>
WRITE RLPS Indirect Data Register
<7 – 0 Bits of Data>
ACTION RLPS Equalisation Read/WriteB Select Register
<A=80H for “read”; A=00H for “write” action>
WRITE RLPS Equalisation Indirect Address Register
<address from 0 to 255>
PAUSE
<wait 3 line rate clock cycles>
Table 31 RLPS Equalizer RAM Table (T1 mode)
RAM Address
Content (MSB..LSB)
RAM Address
Content (MSB..LSB)
00D
0x03061C3F
128D
0x424E0F3D
01D
0x03061C3D
129D
0x424E0F3D
02D
0x03061C3A
130D
0x424E0F3D
03D
0x03062C3D
131D
0x424E0F3D
04D
0x03062C3B
132D
0x424E0F3D
05D
0x03062C38
133D
0x424E0F3D
06D
0x030E2C3F
134D
0x424E0F3D
07D
0x030E2C3C
135D
0x424E0F3D
08D
0x030E2C38
136D
0x424E0F3D
09D
0x03162C3F
137D
0x424E0F3D
10D
0x03162C3D
138D
0x424E0F3D
11D
0x03162C3A
139D
0x424E0F3D
12D
0x03163C3F
140D
0x424E0F3D
13D
0x03163C38
141D
0x424E0F3D
14D
0x0316283B
142D
0x424E0F3D
15D
0x0316383B
143D
0x424E0F3D
16D
0x03163CBB
144D
0x424E0F3D
17D
0x031E3CBF
145D
0x424E0F3D
18D
0x031E3CBD
146D
0x424E0F3D
19D
0x031E3CBA
147D
0x424E0F3D
20D
0x031E3CB8
148D
0x424E0F3D
21D
0x03263CBC
149D
0x424E0F3D
22D
0x032628BA
150D
0x424E0F3D
23D
0x032638BB
151D
0x424E0F3D
24D
0x0B263D3F
152D
0x424E0F3D
25D
0x0B263D3E
153D
0x424E0F3D
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Telecom Standard Product Data Sheet
Released
RAM Address
Content (MSB..LSB)
RAM Address
Content (MSB..LSB)
26D
0x0B263D3D
154D
0x424E0F3D
27D
0x0B263D3C
155D
0x424E0F3D
28D
0x0B26293A
156D
0x424E0F3D
29D
0x0B26393F
157D
0x424E0F3D
30D
0x13262DB8
158D
0x424E0F3D
31D
0x132E2DBF
159D
0x424E0F3D
32D
0x132E2DBF
160D
0x424E0F3D
33D
0x132E2DBE
161D
0x424E0F3D
34D
0x132E2DBD
162D
0x424E0F3D
35D
0x132E2DBC
163D
0x424E0F3D
36D
0x132E2DBB
164D
0x424E0F3D
37D
0x132E19B8
165D
0x424E0F3D
38D
0x132E29BF
166D
0x424E0F3D
39D
0x1B2E1E38
167D
0x424E0F3D
40D
0x1B361E3F
168D
0x424E0F3D
41D
0x1B361E3C
169D
0x424E0F3D
42D
0x1B361E3B
170D
0x424E0F3D
43D
0x1B360A3B
171D
0x424E0F3D
44D
0x1B361A3B
172D
0x424E0F3D
45D
0x23361EBF
173D
0x424E0F3D
46D
0x23361EB8
174D
0x424E0F3D
47D
0x23361EBF
175D
0x424E0F3D
48D
0x233E1EBD
176D
0x424E0F3D
49D
0x2B3E1EBB
177D
0x424E0F3D
50D
0x2B3E1EB8
178D
0x424E0F3D
51D
0x2B461EBF
179D
0x424E0F3D
52D
0x33461EBD
180D
0x424E0F3D
53D
0x33461EBA
181D
0x424E0F3D
54D
0x33461EB8
182D
0x424E0F3D
55D
0x334E1EBA
183D
0x424E0F3D
56D
0x32461EBC
184D
0x424E0F3D
57D
0x3A4E1EBF
185D
0x424E0F3D
58D
0x3A4E1EBC
186D
0x424E0F3D
59D
0x3A4E0ABA
187D
0x424E0F3D
60D
0x3A4E1AB8
188D
0x424E0F3D
61D
0x424E1F3F
189D
0x424E0F3D
62D
0x424E0F3E
190D
0x424E0F3D
63D
0x424E0F3D
191D
0x424E0F3D
64D
0x424E0F3D
192D
0x424E0F3D
65D
0x424E0F3D
193D
0x424E0F3D
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Telecom Standard Product Data Sheet
Released
RAM Address
Content (MSB..LSB)
RAM Address
Content (MSB..LSB)
66D
0x424E0F3D
194D
0x424E0F3D
67D
0x424E0F3D
195D
0x424E0F3D
68D
0x424E0F3D
196D
0x424E0F3D
69D
0x424E0F3D
197D
0x424E0F3D
70D
0x424E0F3D
198D
0x424E0F3D
71D
0x424E0F3D
199D
0x424E0F3D
72D
0x424E0F3D
200D
0x424E0F3D
73D
0x424E0F3D
201D
0x424E0F3D
74D
0x424E0F3D
202D
0x424E0F3D
75D
0x424E0F3D
203D
0x424E0F3D
76D
0x424E0F3D
204D
0x424E0F3D
77D
0x424E0F3D
205D
0x424E0F3D
78D
0x424E0F3D
206D
0x424E0F3D
79D
0x424E0F3D
207D
0x424E0F3D
80D
0x424E0F3D
208D
0x424E0F3D
81D
0x424E0F3D
209D
0x424E0F3D
82D
0x424E0F3D
210D
0x424E0F3D
83D
0x424E0F3D
211D
0x424E0F3D
84D
0x424E0F3D
212D
0x424E0F3D
85D
0x424E0F3D
213D
0x424E0F3D
86D
0x424E0F3D
214D
0x424E0F3D
87D
0x424E0F3D
215D
0x424E0F3D
88D
0x424E0F3D
216D
0x424E0F3D
89D
0x424E0F3D
217D
0x424E0F3D
90D
0x424E0F3D
218D
0x424E0F3D
91D
0x424E0F3D
219D
0x424E0F3D
92D
0x424E0F3D
220D
0x424E0F3D
93D
0x424E0F3D
221D
0x424E0F3D
94D
0x424E0F3D
222D
0x424E0F3D
95D
0x424E0F3D
223D
0x424E0F3D
96D
0x424E0F3D
224D
0x424E0F3D
97D
0x424E0F3D
225D
0x424E0F3D
98D
0x424E0F3D
226D
0x424E0F3D
99D
0x424E0F3D
227D
0x424E0F3D
100D
0x424E0F3D
228D
0x424E0F3D
101D
0x424E0F3D
229D
0x424E0F3D
102D
0x424E0F3D
230D
0x424E0F3D
103D
0x424E0F3D
231D
0x424E0F3D
104D
0x424E0F3D
232D
0x424E0F3D
105D
0x424E0F3D
233D
0x424E0F3D
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Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
RAM Address
Content (MSB..LSB)
RAM Address
Content (MSB..LSB)
106D
0x424E0F3D
234D
0x424E0F3D
107D
0x424E0F3D
235D
0x424E0F3D
108D
0x424E0F3D
236D
0x424E0F3D
109D
0x424E0F3D
237D
0x424E0F3D
110D
0x424E0F3D
238D
0x424E0F3D
111D
0x424E0F3D
239D
0x424E0F3D
112D
0x424E0F3D
240D
0x424E0F3D
113D
0x424E0F3D
241D
0x424E0F3D
114D
0x424E0F3D
242D
0x424E0F3D
115D
0x424E0F3D
243D
0x424E0F3D
116D
0x424E0F3D
244D
0x424E0F3D
117D
0x424E0F3D
245D
0x424E0F3D
118D
0x424E0F3D
246D
0x424E0F3D
119D
0x424E0F3D
247D
0x424E0F3D
120D
0x424E0F3D
248D
0x424E0F3D
121D
0x424E0F3D
249D
0x424E0F3D
122D
0x424E0F3D
250D
0x424E0F3D
123D
0x424E0F3D
251D
0x424E0F3D
124D
0x424E0F3D
252D
0x424E0F3D
125D
0x424E0F3D
253D
0x424E0F3D
126D
0x424E0F3D
254D
0x424E0F3D
127D
0x424E0F3D
255D
0x424E0F3D
Table 32 RLPS Equalizer RAM Table (E1 mode)
RAM Address
Content (MSB..LSB)
RAM Address
Content (MSB..LSB)
00D
0x03062C3E
128D
0x3A5E6E3F
01D
0x03062C3C
129D
0x3A5E6E3F
02D
0x03062C3A
130D
0x3A5E6E3F
03D
0x03062C38
131D
0x3A5E6E3F
04D
0x030E2C3F
132D
0x3A5E6E3F
05D
0x030E2C38
133D
0x3A5E6E3F
06D
0x03162C3F
134D
0x3A5E6E3F
07D
0x03162C3B
135D
0x3A5E6E3F
08D
0x03162C38
136D
0x3A5E6E3F
09D
0x03163C3F
137D
0x3A5E6E3F
10D
0x03163C38
138D
0x3A5E6E3F
11D
0x031E3C3F
139D
0x3A5E6E3F
12D
0x031E3C3C
140D
0x3A5E6E3F
13D
0x031E3C3A
141D
0x3A5E6E3F
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
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Telecom Standard Product Data Sheet
Released
RAM Address
Content (MSB..LSB)
RAM Address
Content (MSB..LSB)
14D
0x031E3C39
142D
0x3A5E6E3F
15D
0x031E3C38
143D
0x3A5E6E3F
16D
0x031E4C3F
144D
0x3A5E6E3F
17D
0x031E4C3C
145D
0x3A5E6E3F
18D
0x031E4C3A
146D
0x3A5E6E3F
19D
0x031E4C38
147D
0x3A5E6E3F
20D
0x03264C3F
148D
0x3A5E6E3F
21D
0x03264C3B
149D
0x3A5E6E3F
22D
0x03264C38
150D
0x3A5E6E3F
23D
0x032E4C3F
151D
0x3A5E6E3F
24D
0x032E4C3B
152D
0x3A5E6E3F
25D
0x032E4C39
153D
0x3A5E6E3F
26D
0x032E4C38
154D
0x3A5E6E3F
27D
0x032E5C3F
155D
0x3A5E6E3F
28D
0x032E5C3D
156D
0x3A5E6E3F
29D
0x032E5C3B
157D
0x3A5E6E3F
30D
0x032E5C38
158D
0x3A5E6E3F
31D
0x032E6C3F
159D
0x3A5E6E3F
32D
0x032E6C38
160D
0x3A5E6E3F
33D
0x03366C3F
161D
0x3A5E6E3F
34D
0x03366C3C
162D
0x3A5E6E3F
35D
0x03366C3A
163D
0x3A5E6E3F
36D
0x03366C38
164D
0x3A5E6E3F
37D
0x03367C3F
165D
0x3A5E6E3F
38D
0x03367C3D
166D
0x3A5E6E3F
39D
0x03367C3C
167D
0x3A5E6E3F
40D
0x03367C3A
168D
0x3A5E6E3F
41D
0x03367C39
169D
0x3A5E6E3F
42D
0x03367C38
170D
0x3A5E6E3F
43D
0x0B3E7C3F
171D
0x3A5E6E3F
44D
0x0B3E683F
172D
0x3A5E6E3F
45D
0x0B3E683B
173D
0x3A5E6E3F
46D
0x0B3E683A
174D
0x3A5E6E3F
47D
0x0B3E6838
175D
0x3A5E6E3F
48D
0x0B3E6CBF
176D
0x3A5E6E3F
49D
0x133E6CBD
177D
0x3A5E6E3F
50D
0x133E6CBC
178D
0x3A5E6E3F
51D
0x133E6CBA
179D
0x3A5E6E3F
52D
0x133E58B8
180D
0x3A5E6E3F
53D
0x133E68BD
181D
0x3A5E6E3F
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Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
RAM Address
Content (MSB..LSB)
RAM Address
Content (MSB..LSB)
54D
0x1B3E6D3F
182D
0x3A5E6E3F
55D
0x1B3E6D3D
183D
0x3A5E6E3F
56D
0x1B3E6D3B
184D
0x3A5E6E3F
57D
0x1B3E6D3A
185D
0x3A5E6E3F
58D
0x1B3E6D38
186D
0x3A5E6E3F
59D
0x1B466D3F
187D
0x3A5E6E3F
60D
0x1B466D3D
188D
0x3A5E6E3F
61D
0x23466D3C
189D
0x3A5E6E3F
62D
0x23466D3A
190D
0x3A5E6E3F
63D
0x23465938
191D
0x3A5E6E3F
64D
0x23466938
192D
0x3A5E6E3F
65D
0x23466DBF
193D
0x3A5E6E3F
66D
0x23466DBC
194D
0x3A5E6E3F
67D
0x2B466DBA
195D
0x3A5E6E3F
68D
0x2B466DB8
196D
0x3A5E6E3F
69D
0x2B4E6DBF
197D
0x3A5E6E3F
70D
0x2A465DB8
198D
0x3A5E6E3F
71D
0x2A466DBD
199D
0x3A5E6E3F
72D
0x2A466DBB
200D
0x3A5E6E3F
73D
0x324E6DBD
201D
0x3A5E6E3F
74D
0x324E6DBB
202D
0x3A5E6E3F
75D
0x3A4E59B8
203D
0x3A5E6E3F
76D
0x3A4E69B8
204D
0x3A5E6E3F
77D
0x3A4E6E3F
205D
0x3A5E6E3F
78D
0x3A4E6E3C
206D
0x3A5E6E3F
79D
0x3A4E6E3A
207D
0x3A5E6E3F
80D
0x3A4E6E38
208D
0x3A5E6E3F
81D
0x3A566E3E
209D
0x3A5E6E3F
82D
0x3A566E38
210D
0x3A5E6E3F
83D
0x3A5E6E3F
211D
0x3A5E6E3F
84D
0x3A5E6E3F
212D
0x3A5E6E3F
85D
0x3A5E6E3F
213D
0x3A5E6E3F
86D
0x3A5E6E3F
214D
0x3A5E6E3F
87D
0x3A5E6E3F
215D
0x3A5E6E3F
88D
0x3A5E6E3F
216D
0x3A5E6E3F
89D
0x3A5E6E3F
217D
0x3A5E6E3F
90D
0x3A5E6E3F
218D
0x3A5E6E3F
91D
0x3A5E6E3F
219D
0x3A5E6E3F
92D
0x3A5E6E3F
220D
0x3A5E6E3F
93D
0x3A5E6E3F
221D
0x3A5E6E3F
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RAM Address
Content (MSB..LSB)
RAM Address
Content (MSB..LSB)
94D
0x3A5E6E3F
222D
0x3A5E6E3F
95D
0x3A5E6E3F
223D
0x3A5E6E3F
96D
0x3A5E6E3F
224D
0x3A5E6E3F
97D
0x3A5E6E3F
225D
0x3A5E6E3F
98D
0x3A5E6E3F
226D
0x3A5E6E3F
99D
0x3A5E6E3F
227D
0x3A5E6E3F
100D
0x3A5E6E3F
228D
0x3A5E6E3F
101D
0x3A5E6E3F
229D
0x3A5E6E3F
102D
0x3A5E6E3F
230D
0x3A5E6E3F
103D
0x3A5E6E3F
231D
0x3A5E6E3F
104D
0x3A5E6E3F
232D
0x3A5E6E3F
105D
0x3A5E6E3F
233D
0x3A5E6E3F
106D
0x3A5E6E3F
234D
0x3A5E6E3F
107D
0x3A5E6E3F
235D
0x3A5E6E3F
108D
0x3A5E6E3F
236D
0x3A5E6E3F
109D
0x3A5E6E3F
237D
0x3A5E6E3F
110D
0x3A5E6E3F
238D
0x3A5E6E3F
111D
0x3A5E6E3F
239D
0x3A5E6E3F
112D
0x3A5E6E3F
240D
0x3A5E6E3F
113D
0x3A5E6E3F
241D
0x3A5E6E3F
114D
0x3A5E6E3F
242D
0x3A5E6E3F
115D
0x3A5E6E3F
243D
0x3A5E6E3F
116D
0x3A5E6E3F
244D
0x3A5E6E3F
117D
0x3A5E6E3F
245D
0x3A5E6E3F
118D
0x3A5E6E3F
246D
0x3A5E6E3F
119D
0x3A5E6E3F
247D
0x3A5E6E3F
120D
0x3A5E6E3F
248D
0x3A5E6E3F
121D
0x3A5E6E3F
249D
0x3A5E6E3F
122D
0x3A5E6E3F
250D
0x3A5E6E3F
123D
0x3A5E6E3F
251D
0x3A5E6E3F
124D
0x3A5E6E3F
252D
0x3A5E6E3F
125D
0x3A5E6E3F
253D
0x3A5E6E3F
126D
0x3A5E6E3F
254D
0x3A5E6E3F
127D
0x3A5E6E3F
255D
0x3A5E6E3F
RLPS Equalizer RAM Table (T1 Monitor Mode)
TBD
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LPS Equalizer RAM Table (E1 Monitor Mode)
TBD
12.6 Using the PRBS Generator and Detector
PRBS patterns may be generated and detected in either the transmit or receive directions, as
configured by the TX_GEN, RX_GEN and TX_DET bits of the Line Interface PRBS Position
registers.
12.7 Loopback Modes
The OCTLIU-SH provides two loopback modes to aid in network and system diagnostics. The
network (line) loopback can be initiated at any time via the µP interface, but is usually initiated
once an inband loopback activate code is detected. The system Diagnostic Digital loopback can
be initiated at any time by the system via the µP interface to check the path of system data
through the LIU.
12.7.1
Line Loopback
When LINE loopback (LINELB) is initiated by setting the LINELB bit in the Line Interface
Diagnostics Register to logic 1, the LIU is configured to internally connect the recovered data to
the transmit jitter attenuator, TJAT. The data sent to the TJAT is the recovered data from the
output of the CDRC block. Note that when line loopback is enabled, the contents of the TJAT
Reference Clock Divisor and Output Clock Divisor registers should be programmed to FFH to
correctly attenuate the jitter on the receive clock. Conceptually, the data flow through a single
octant of the OCTLIU-SH in this loopback mode is illustrated in Figure 13.
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Figure 13 Line Loopback
TXTIP1[8:1]
TXTIP2[8:1]
TXRING1[8:1]
TXRING2[8:1]
TJAT
Digital Jitter
Attenuator
XLPG
Transmit LIU
LCODE
AMI / B8ZS /
HDB3 Line
Encoder
XIBC
Inband Loopback Code
Generator
XPDE
Pulse Density
Enforcer
ADATA[7:0]
Tx Data
Tx Clock
EXSBI-8
ADP
SBI Extract
APL
AV5
LINE
LOOPBACK
REFCLK
AC1FP
DC1FP
C1FPOUT
Rx Data
RXTIP[8:1]
RXRING[8:1]
CDRC
Clk/Data
Recovery
RLPS
Receive LIU
IBCD
Inband Loop back Code
Detector
PDVD
Pulse Density
Viol. Detector
RJAT
Digital Jitter
Attenuator
DDATA[7:0]
INSBI-8
SBI Insert
Rx Clock
DDP
DPL
DV5
DACTIVE
LIU Octant x 8
TXHIZ/LLB
RSTB
XCLK
RSYNC
CSD
Clock
Synthesis /
Distribution
TOPS
Timing
Options
LOS
Serial
Output
uP Interface
PO
PI
INTB
RDB
WRB
CSB
ALE
A[10:0]
D[7:0]
TRSTB
TDO
TDI
TMS
TCK
LOS
LOS_L1
12.7.2
JTAG
Diagnostic Digital Loopback
When Diagnostic Digital loopback (DDLB) mode is initiated by setting the DDLB bit in the
Line Interface Diagnostics Register to logic 1, the OCTLIU-SH octant is configured to
internally direct the output of the TJAT to the inputs of the receiver section. The dual-rail RZ
outputs of the TJAT are directed to the dual-rail inputs of the CDRC. Conceptually, the data
flow through a single octant of the OCTLIU-SH in this loopback condition is illustrated in
Figure 14.
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Figure 14 Diagnostic Digital Loopback
TXTIP1[8:1]
TXTIP2[8:1]
TXRING1[8:1]
TXRING2[8:1]
TJAT
Digital Jitter
Attenuator
XLPG
Transmit LIU
LCODE
AMI / B8ZS /
HDB3 Line
Encoder
XIBC
Inband Loopback Code
Generator
XPDE
Pulse Density
Enforcer
ADATA[7:0]
Tx Data
Tx Clock
EXSBI-8
ADP
SBI Extract
APL
AV5
DIAGNOSTIC
LOOPBACK
REFCLK
AC1FP
DC1FP
C1FPOUT
DDATA[7:0]
RXTIP[8:1]
RXRING[8:1]
CDRC
Clk/Data
Recovery
RLPS
Receive LIU
Rx Data
IBCD
Inband Loop back Code
Detector
PDVD
Pulse Density
Viol. Detector
RJAT
Digital Jitter
Attenuator
INSBI-8
SBI Insert
Rx Clock
DDP
DPL
DV5
DACTIVE
LIU Octant x 8
TXHIZ/LLB
RSTB
XCLK
RSYNC
CSD
Clock
Synthesis /
Distribution
TOPS
Timing
Options
LOS
Serial
Output
JTAG
uP Interface
PO
PI
INTB
RDB
WRB
CSB
ALE
A[10:0]
TRSTB
D[7:0]
TDO
TDI
TMS
TCK
LOS
LOS_L1
12.8 Initialization of the RJAT and TJAT
The recommended procedure to initialize the TJAT and RJAT is as follows:
1. Set the N1 and N2 values (this will reset the JAT PLL).
2. Wait 15ms for the JAT PLL to lock.
3. Toggle the FIFORST bit (this will reset and centre the JAT).
12.9 Configuring the SBI Bus
For more information about configuring the SBI bus and using this device with other SBI
devices, please see the PMC-Sierra document titled "Configuring SBI Compatible Devices"
(PMC-2020180).
12.912.10
JTAG Support
The OCTLIU-SH supports the IEEE Boundary Scan Specification as described in the IEEE
1149.1 standards. The Test Access Port (TAP) consists of the five standard pins, TRSTB, TCK,
TMS, TDI and TDO used to control the TAP controller and the boundary scan registers. The
TRSTB input is the active-low reset signal used to reset the TAP controller. TCK is the test
clock used to sample data on the TDI primary input and to output data on the TDO primary
output. The TMS primary input is used to direct the TAP controller through its states. The
basic boundary scan architecture is shown below.
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Figure 15 Boundary Scan Architecture
Boundary Scan
Register
TDI
Device Identification
Register
Bypass
Register
Instruction
Register
and
Decode
Mux
DFF
TDO
Control
TMS
Test
Access
Port
Controller
Select
Tri-state Enable
TRSTB
TCK
The boundary scan architecture consists of a TAP controller, an instruction register with
instruction decode, a bypass register, a device identification register and a boundary scan
register. The TAP controller interprets the TMS input and generates control signals to load the
instruction and data registers. The instruction register with instruction decode block is used to
select the test to be executed and/or the register to be accessed. The bypass register offers a
single-bit delay from primary input, TDI to primary output, TDO. The device identification
register contains the device identification code.
The boundary scan register allows testing of board inter-connectivity. The boundary scan
register consists of a shift register placed in series with device inputs and outputs. Using the
boundary scan register, all digital inputs can be sampled and shifted out on primary output,
TDO. In addition, patterns can be shifted in on primary input, TDI, and forced onto all digital
outputs.
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12.9.112.10.1
TAP Controller
The TAP controller is a synchronous finite state machine clocked by the rising edge of primary
input, TCK. All state transitions are controlled using primary input, TMS. The finite state
machine is described below.
Figure 16 TAP Controller Finite State Machine
TRSTB=0
Test-Logic-Reset
1
0
1
1
Run-Test-Idle
1
Select-IR-Scan
Select-DR-Scan
0
0
0
1
1
Capture-IR
Capture-DR
0
0
Shift-IR
Shift-DR
0
1
0
1
1
1
Exit1-IR
Exit1-DR
0
0
Pause-IR
Pause-DR
0
1
0
0
1
0
Exit2-IR
Exit2-DR
1
1
Update-IR
Update-DR
1
0
1
0
All transitions dependent on input TMS
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Test-Logic-Reset
The test logic reset state is used to disable the TAP logic when the device is in normal mode
operation. The state is entered asynchronously by asserting input, TRSTB. The state is entered
synchronously regardless of the current TAP controller state by forcing input, TMS high for 5
TCK clock cycles. While in this state, the instruction register is set to the IDCODE instruction.
Run-Test-Idle
The run/test/idle state is used to execute tests.
Capture-DR
The capture data register state is used to load parallel data into the test data registers selected by
the current instruction. If the selected register does not allow parallel loads or no loading is
required by the current instruction, the test register maintains its value. Loading occurs on the
rising edge of TCK.
Shift-DR
The shift data register state is used to shift the selected test data registers by one stage. Shifting
is from MSB to LSB and occurs on the rising edge of TCK.
Update-DR
The update data register state is used to load a test register’s parallel output latch. In general,
the output latches are used to control the device. For example, for the EXTEST instruction, the
boundary scan test register’s parallel output latches are used to control the device’s outputs.
The parallel output latches are updated on the falling edge of TCK.
Capture-IR
The capture instruction register state is used to load the instruction register with a fixed
instruction. The load occurs on the rising edge of TCK.
Shift-IR
The shift instruction register state is used to shift both the instruction register and the selected
test data registers by one stage. Shifting is from MSB to LSB and occurs on the rising edge of
TCK.
Update-IR
The update instruction register state is used to load a new instruction into the instruction
register. The new instruction must be scanned in using the Shift-IR state. The load occurs on
the falling edge of TCK.
The Pause-DR and Pause-IR states are provided to allow shifting through the test data and/or
instruction registers to be momentarily paused.
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Boundary Scan Instructions
The following is a description of the standard instructions. Each instruction selects a serial test
data register path between input, TDI and output, TDO.
BYPASS
The bypass instruction shifts data from input, TDI to output, TDO with one TCK clock period
delay. The instruction is used to bypass the device.
EXTEST
The external test instruction allows testing of the interconnection to other devices. When the
current instruction is the EXTEST instruction, the boundary scan register is placed between
input, TDI and output, TDO. Primary device inputs can be sampled by loading the boundary
scan register using the Capture-DR state. The sampled values can then be viewed by shifting
the boundary scan register using the Shift-DR state. Primary device outputs can be controlled
by loading patterns shifted in through input TDI into the boundary scan register using the
Update-DR state.
SAMPLE
The sample instruction samples all the device inputs and outputs. For this instruction, the
boundary scan register is placed between TDI and TDO. Primary device inputs and outputs can
be sampled by loading the boundary scan register using the Capture-DR state. The sampled
values can then be viewed by shifting the boundary scan register using the Shift-DR state.
IDCODE
The identification instruction is used to connect the identification register between TDI and
TDO. The device’s identification code can then be shifted out using the Shift-DR state.
STCTEST
The single transport chain instruction is used to test out the TAP controller and the boundary
scan register during production test. When this instruction is the current instruction, the
boundary scan register is connected between TDI and TDO. During the Capture-DR state, the
device identification code is loaded into the boundary scan register. The code can then be
shifted out of the output, TDO, using the Shift-DR state.
Boundary Scan Cells
In the following diagrams, CLOCK-DR is equal to TCK when the current controller state is
SHIFT-DR or CAPTURE-DR, and unchanging otherwise. The multiplexer in the center of the
diagram selects one of four inputs, depending on the status of select lines G1 and G2. The ID
Code bit is as listed in the Boundary Scan Register table in the JTAG Test Port section 11.2.
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Figure 17 Input Observation Cell (IN_CELL)
IDCODE
Scan Chain Out
INPUT
to internal
logic
Input
Pad
G1
G2
SHIFT-DR
12
1 2 MUX
12
I.D. Code bit
D
C
12
CLOCK-DR
Scan Chain In
Figure 18 Output Cell (OUT_CELL) or Enable Cell (ENABLE)
Scan Chain Out
G1
EXTEST
Output or Enable
from system logic
IDOODE
SHIFT-DR
I.D. code bit
1
G1
G2
1 2
1 2 MUX
1 2
1 2
1
OUTPUT
or Enable
MUX
D
C
D
C
CLOCK-DR
UPDATE-DR
Scan Chain In
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Figure 19 Bidirectional Cell (IO_CELL)
Scan Chain Out
G1
EXTEST
OUTPUT from
internal logic
IDCODE
1
1
G1
G2
SHIFT-DR
INPUT
from pin
I.D. code bit
MUX
12
1 2 MUX
12
12
D
INPUT
to internal
logic
OUTPUT
to pin
D
C
C
CLOCK-DR
UPDATE-DR
Scan Chain In
Figure 20 Layout of Output Enable and Bidirectional Cells
Scan Chain Out
OUTPUT ENABLE
from internal
logic (0 = drive)
INPUT to
internal logic
OUTPUT from
internal logic
OUT_CELL
IO_CELL
I/O
PAD
Scan Chain In
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13
Functional Timing
13.1 SBI BUS Interface Timing
Figure 21 SBI BUS Functional Timing
REFCLK
•••
C1FP
•••
DATA[7:0]
C1
•••
PL
•••
V5
•••
DP
•••
V3
V3
V3 DS0#4. V5 DS0#9.
Figure 21 illustrates the operation of the SBI Bus, using a negative justification on the second to
last V3 octet as an example. The justification is indicated by asserting PL high during the V3
octet. The timing diagram also shows the location of one of the tributaries by asserting V5 high
during the V5 octet.
Note – the SBI ADD and DROP busses operate in an identical manner. Signal names on the
ADD bus have an A prepended to the names shown in Figure 21 (e.g, AC1FP, ADATA[7:0],
etc.) and those on the DROP bus have an D prepended to them (e.g, DC1FP, DDATA[7:0], etc.)
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13.2 Line Code Violation Insertion
Figure 22 B8ZS Line Code Violation Insertion
B8ZS Signature Pattern
0 0 0 V B 0 V B
TCLK
continuous zeros
TDP
0 0 0 V
TXTIP
TXRING
B
B 0 V
B8ZS Signature Pattern
0 0 0 V B 0 V B
TCLK
TDP
TXTIP
continuous zeros
0 0 0 0
B
B 0 V
TXRING
LCVINS = 1 causes
omission of first bipolar
violation pulse.
The effect of setting the LCVINS bit of the Line Interface Diagnostics register is shown in
Figure 22. TXTIP[X] and TXRING[X] have been shown as square NRZ pulses for illustrative
purposes. Setting LCVINS to a logic 1 generates one line code violation and 3 bit errors by
causing the omission of the first line code violation pulse when a string of 8 consecutive zeros
occurs in the unipolar serial transmit data stream. To generate another line code violation, the
LCVINS bit must be reset to logic 0 and then set to logic 1 again. Note the Serial Tx Clock and
Data signals are internally generated from the SBI.
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Figure 23 HDB3 Line Code Violation Insertion
TCLK
continuous zeros
TDP
TXTIP
0 0 0 V
1 0 0 V
1 0 0 V
TXRING
1
TCLK
TDP
TXTIP
TXRING
continuous zeros
0 0 0 V
1
1 0 0 V 0 0 0 V
LCVINS = 1 causes omission
of bipolar pulse and violation
of same polarity as previous
violation.
The effect of setting the LCVINS bit of the Line Interface Diagnostics register is shown in
Figure 23. TXTIP[X] and TXRING[X] have been shown as square NRZ pulses for illustrative
purposes. Setting LCVINS to a logic 1 generates one line code violation by causing the
omission of a bipolar pulse and hence a bipolar violation pulse of the same polarity as the
previous bipolar violation pulse when a string of 4 consecutive zeros occurs in the unipolar
serial transmit data stream. To generate another line code violation, the LCVINS bit must be
reset to logic 0 and then set to logic 1 again. Note the Serial Tx Clock and Data signals are
internally generated from the SBI.
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Figure 24 AMI Line Code Violation Insertion
TCLK
TDP
TXTIP
TXRING
TCLK
TDP
TXTIP
V
TXRING
LCVINS = 1 causes
a bipolar violation
The effect of setting the LCVINS bit of the Line Interface Diagnostics register is shown in
Figure 24. TXTIP[X] and TXRING[X] have been shown as square NRZ pulses for illustrative
purposes. Setting LCVINS to a logic 1 generates one line code violation by causing the next
pulse to be of the same polarity as the previous pulse. Subsequent pulses will be of alternate
polarity. To generate another line code violation, the LCVINS bit must be reset to logic 0 and
then set to logic 1 again. Note the Serial Tx Clock and Data signals are internally generated
from the SBI.
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13.3 Alarm Interface
Figure 25 LOS Alarm Serial Output
XCLK
LOS_L1
LOS
LOS8
LOS1
LOS2
LOS3
LOS4
LOS5
LOS6
LOS7
LOS8
LOS1
Figure 25 shows the operation of the Alarm Interface. The LOS status of the 8 LIU octants is
output continuously in a serial format with a marker signal LOS_L1 to indicate the presence of
the LOS status for LIU #1.
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14
Absolute Maximum Ratings
Maximum ratings are the worst case limits that the device can withstand without sustaining
permanent damage. They are not indicative of normal mode operation conditions.
Table 33 Absolute Maximum Ratings
AmbientCase Temperature under
Bias
-40°C to +85°C
Storage Temperature
-40°C to +125°C
1
Supply Voltage VDDall33
-0.3V to +4.6V
Supply Voltage VDD1V8
-0.3V to +3.6V
Voltage on Any Pin
-0.3V to VDDall33 + 0.3V
Static Discharge Voltage
±1000V
Latch-Up Current
±100mA
DC Input Current
±20mA
Lead Temperature
+230°C
Junction Temperature
+150°C
Not Withstanding the values in the above table 3.3V power supplies must always be at a voltage
greater than or equal to the 1.8V power supplies.
1
The OCTLIU-SH 3.3 Volt digital and analogue power pins are collectively referred to as
VDDall33.
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15
D.C. Characteristics
TA = -40°C to +85°C, VDDall33 = 3.3V ±5%, VDD1V8 = 1.8V ±5%
(Typical Conditions: TA = 25°C, VDDall33 = 3.3V, VDD1V8 = 1.8V)
Table 34 D.C. Characteristics
Symbol
Parameter
Min
Typ
Max
Units
Conditions
VDD3V3,
TAVD1,
TAVD2,
TAVD3,
Power Supply
3.135
3.3
3.465
Volts
Note 5.
VDD1V8
Power Supply
1.71
1.8
1.89
Volts
Note 5.
VIL
Input Low
Voltage
0.8
Volts
Guaranteed Input LOW Voltage
VIH
Input High
Voltage
Volts
Guaranteed Input HIGH Voltage
VOL
Output or
Bidirectional
Low Voltage
Volts
VDD = min, IOL = -6mA for LOS,
LOS_L1, TDO; -8mA for others.
Notes 3, 5
VOH
Output or
Bidirectional
High Voltage
2.4
2.7
Volts
VDD = min, IOH = 6mA for LOS,
LOS_L1, TDO; 8mA for others.
Notes 3,5
VT+
Reset Input High
Voltage
2.20
1.6
Volts
Applies to TTL Schmidt-triggered
inputs (RSTB, TRSTB) only.
Note 5.
VT-
Reset Input Low
Voltage
1.1
Volts
Applies to TTL Schmidt-triggered
inputs (RSTB, TRSTB) only.
Note 5.
VTH
Reset Input
Hysteresis
Voltage
0.5
Volts
Applies to TTL Schmidt-triggered
inputs (RSTB, TRSTB) only.
Note 5.
IILPU
Input Low
Current
+20
+99
+200
µA
VIL = GND. Notes 1, 3, 5
IIHPU
Input High
Current
-10
0
+10
µA
VIH = VDD. Notes 1, 3, 5
IILPD
Input Low
Current
-10
0
+10
µA
VIL = GND. Notes 4, 3, 5
IIHPD
Input High
Current
271.50
0
155.5
-20
µA
VIH = VDD. Notes 4, 3, 5
IIL
Input Low
Current
-210
0
+210
µA
VIL = GND. Notes 2, 3, 5
IIH
Input High
Current
-210
0
+210
µA
VIH = VDD. Notes 2, 3, 5
CAVD,
RAVD1,
RAVD2,
QAVD
2.0
0.1
0.4
0.8
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Telecom Standard Product Data Sheet
Released
Symbol
Parameter
Units
Conditions
CIN
Input
Capacitance
Min
5
Typ
Max
pF
Excluding Package, Package
Typically 2 pF. Note 5.
COUT
Output
Capacitance
5
pF
Excluding Package, Package
Typically 2 pF. Note 5.
CIO
Bidirectional
Capacitance
5
pF
Excluding Package, Package
Typically 2 pF. Note 5.
IDDOP
3V3
3.3V Operating
Current
mA
Digital output pads loaded with
max capacitance. Transmission
of pattern containing 50% ones in
T1 (550-660ft).
463
Digital output pads loaded with
max capacitance. Transmission
of pattern containing 100% ones
in T1 (550-660ft).
775
430
Digital output pads loaded with
max capacitance. Transmission
of pattern containing 50% ones in
E1 (120Ω).
529
Digital output pads loaded with
max capacitance. Transmission
of pattern containing 100% ones
in E1 (120Ω).
Note 5.
IDDOP
1V8
1.8V Operating
Current
54
mA
56
73
74
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Digital output pads loaded with
max capacitance. Transmission
of pattern containing 50% ones in
T1 (550-660ft).
Digital output pads loaded with
max capacitance. Transmission
of pattern containing 100% ones
in T1 (550-660ft).
Digital output pads loaded with
max capacitance. Transmission
of pattern containing 50% ones in
E1 (120Ω).
Digital output pads loaded with
max capacitance. Transmission
of pattern containing 100% ones
in E1 (120Ω).
209
Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
Symbol
Parameter
Min
Net power
(power
dissipated by
OCTLIU-SH)
Typ
Max
Units
Conditions
1.21
1.32
W
Digital output pads loaded with
max capacitance. Transmission
of pattern containing 50% ones in
T1 (330-440ft).
1.79
1.99
1.30
1.47
1.52
1.68
Digital output pads loaded with
max capacitance. Transmission
of pattern containing 100% ones
in T1 (330-440ft).
Digital output pads loaded with
max capacitance. Transmission
of pattern containing 50% ones in
E1 (120Ω).
Digital output pads loaded with
max capacitance. Transmission
of pattern containing 100% ones
in E1 (120Ω).
Note 5.
Notes on D.C. Characteristics:
1.
Input pin or bi-directional pin with internal pull-up resistor.
2.
Input pin or bi-directional pin without internal pull-up or pull-down resistor
3.
Negative currents flow into the device (sinking), positive currents flow out of the device (sourcing).
4.
Input pin or bi-directional pin with internal pull-down resistor.
5.
IDDOP3V3 includes the operating current of both the OCTLIU-SH device and the transmit line driver.
Whereas, the "Net Power" is the power dissipated by the OCTLIU-SH device only.
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Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
16
Microprocessor Interface Timing Characteristics
(TA = -40°C to +85°C, VDDall33 = 3.3V ±5%, VDD1V8 = 1.8V ±5%)
Table 35 Microprocessor Interface Read Access
Symbol
Parameter
Min
tSAR
Address to Valid Read Set-up Time
10
ns
tHAR
Address to Valid Read Hold Time
5
ns
tSALR
Address to Latch Set-up Time
10
ns
tHALR
Address to Latch Hold Time
10
ns
tVL
Valid Latch Pulse Width
20
ns
tSLR
Latch to Read Set-up
0
ns
tHLR
Latch to Read Hold
5
ns
tPRD
Valid Read to Valid Data Propagation Delay
70
ns
tZRD
Valid Read Negated to Output Tri-state
20
ns
tZINTH
Valid Read Negated to Output Tri-state
50
ns
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Max
Units
211
Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
Figure 26 Microprocessor Interface Read Timing
tSAR
A[10:0]
Valid
Address
tHAR
tS ALR
tV L
tHALR
ALE
tHLR
tS LR
(CSB+RDB)
tZ INTH
INTB
tZ RD
tPRD
D[7:0]
Valid Data
Notes on Microprocessor Interface Read Timing:
1.
Output propagation delay time is the time in nanoseconds from the 1.4 Volt point of the reference
signal to the 1.4 Volt point of the output.
2.
Maximum output propagation delays are measured with a 100 pF load on the Microprocessor
Interface data bus, (D[7:0]).
3.
A valid read cycle is defined as a logical OR of the CSB and the RDB signals.
4.
In non-multiplexed address/data bus architectures, ALE should be held high so parameters tSALR,
tHALR, tVL, and tSLR are not applicable.
5.
Parameter tHAR is not applicable if address latching is used.
6.
When a set-up time is specified between an input and a clock, the set-up time is the time in
nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock.
7.
When a hold time is specified between an input and a clock, the hold time is the time in nanoseconds
from the 1.4 Volt point of the input to the 1.4 Volt point of the clock.
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Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
Table 36 Microprocessor Interface Write Access
Symbol
Parameter
Min
Max
Units
tSAW
Address to Valid Write Set-up Time
10
ns
tSDW
Data to Valid Write Set-up Time
20
ns
tSALW
Address to Latch Set-up Time
10
ns
tHALW
Address to Latch Hold Time
10
ns
tVL
Valid Latch Pulse Width
5
ns
tSLW
Latch to Write Set-up
0
ns
tHLW
Latch to Write Hold
5
ns
tHDW
Data to Valid Write Hold Time
5
ns
tHAW
Address to Valid Write Hold Time
5
ns
TVWR
Valid Write Pulse Width
40
ns
Figure 27 Microprocessor Interface Write Timing
A[9:0]
Valid Address
tS ALW
tV L
tH ALW
tS LW
tHLW
ALE
tSAW
tVWR
tH AW
(CSB+WRB)
tS DW
D[7:0]
tH DW
Valid Data
Notes on Microprocessor Interface Write Timing:
1.
A valid write cycle is defined as a logical OR of the CSB and the WRB signals.
2.
In non-multiplexed address/data bus architectures, ALE should be held high so parameters tSALW,
tHALW, tVL, tSLW and tHLW are not applicable.
3.
Parameter tHAW is not applicable if address latching is used.
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Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
4.
When a set-up time is specified between an input and a clock, the set-up time is the time in
nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock.
5.
When a hold time is specified between an input and a clock, the hold time is the time in nanoseconds
from the 1.4 Volt point of the input to the 1.4 Volt point of the clock.
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Octal Short-Haul E1/T1/J1 Line Interface Device
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Released
17
OCTLIU-SH Timing Characteristics
17.1 RSTB Timing (Figure 28)
(TA = -40°C to +85°C VDDall33 = 3.3V ±5%, VDD1V8 = 1.8V ±5%)
Table 37 RTSB Timing
Symbol
Description
Min
tVRSTB
RSTB Pulse Width
100
Max
Units
ns
Figure 28 RSTB Timing
tV RSTB
RSTB
17.2 XCLK Input Timing (Figure 29)
Table 38 XCLK Input Timing
Symbol
Description
Min
Max
Units
tXCLK
XCLK Frequency (1.544 MHz or 2.048 MHz
± 50ppm)
1.544
-50ppm
2.048
+50ppm
MHz
tLXCLK
XCLK Low Pulse Width (Note 1)
160
ns
tHXCLK
XCLK High Pulse Width (Note 1)
160
ns
Figure 29 XCLK Input Timing
t H XCLK
XCLK
t L XCLK
t
XCLK
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Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
17.3 SBI Interface (Figure 30 to Figure 32)
(TA = -40°C to +85°C VDDall33 = 3.3V ±5%, VDD1V8 = 1.8V ±5%)
Table 39 Clocks and SBI Frame Pulse
Symbol
Description
Min
Max
Units
REFCLK Frequency
19.44
-50ppm
19.44
+50ppm
MHz
REFCLK Duty Cycle
40
60
%
TSC1FP
AC1FP, DC1FP Set-Up Time to REFCLK
4
ns
THC1FP
AC1FP, DC1FP Hold Time to REFCLK
0
ns
TPC1FPOUT
REFCLK to C1FPOUT Valid
1
20
ns
Figure 30 SBI Frame Pulse Timing
REFCLK
tHC1FP
tSC1FP
AC1FP
DC1FP
tPC1FPOUT
C1FPOUT
Table 40 SBI ADD BUS
Symbol
Description
Min
tSSBIADD
All SBI ADD BUS Inputs Set-Up Time to
REFCLK
4
ns
tHSBIADD
All SBI ADD BUS Inputs Hold Time to REFCLK
0
ns
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Document No.: PMC-2012568, Issue 3
Max
Units
216
Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
Figure 31 SBI ADD BUS Timing
REFCLK
tSSBIADD
tHSBIADD
ADATA[7:0]
ADP, APL
AV5
Table 41 SBI DROP BUS
Symbol
Description
Min
Max
Units
tPDACTIVE
REFCLK to DACTIVE Valid
2
15
ns
tPSBIDROP
REFCLK to All SBI DROP BUS Outputs (except
DACTIVE) Valid
2
20
ns
tZSBIDROP
REFCLK to All SBI DROP BUS Outputs (except
DACTIVE) Tristate
2
20
ns
Figure 32 SBI DROP BUS Timing
REFCLK
tPDACTIVE
DACTIVE
tPSBIDROP
DDATA[7:0]
DDP, DPL, DV5
tZSBIDROP
DDATA[7:0]
DDP, DPL, DV5
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Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
17.4 Alarm Interface (Figure 33)
(TA = -40°C to +85°C VDDall33 = 3.3V ±5%, VDD1V8 = 1.8V ±5%)
Table 42 Alarm Interface
Symbol
Description
Min
Max
Units
TPLOS
XCLK to LOS, LOS_L1 Output Prop. Time
-50
50
ns
Min
Max
Units
1
MHz
TCK Duty Cycle
40
60
%
TMS Set-up time to TCK
50
ns
TMS Hold time to TCK
50
ns
TDI Set-up time to TCK
50
ns
TDI Hold time to TCK
50
ns
TCK Low to TDO Valid
2
TRSTB Pulse Width
100
Figure 33 Alarm Interface Timing
XCLK
tPLOS
LOS
LOS_L1
17.5 JTAG Port Interface (Figure 34)
(TA = -40°C to +85°C VDDall33 = 3.3V ±5%, VDD1V8 = 1.8V ±5%)
Table 43 JTAG Port Interface
Symbol
Description
TCK Frequency
tSTMS
tHTMS
tSTDI
tHTDI
tPTDO
tVTRSTB
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Document No.: PMC-2012568, Issue 3
50
ns
ns
218
Octal Short-Haul E1/T1/J1 Line Interface Device
Telecom Standard Product Data Sheet
Released
Figure 34 JTAG Port Interface Timing
TCK
tS TMS
tH TMS
tS TDI
tH TDI
TMS
TDI
TCK
tP TDO
TDO
tV TRSTB
TRSTB
Notes on OCTLIU-SH Timing:
1. High pulse width is measured from the 1.4 Volt points of the rise and fall ramps. Low pulse
width is measured from the 1.4 Volt points of the fall and rise ramps.
2. When a set-up time is specified between an input and a clock, the set-up time is the time in
nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock.
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Octal Short-Haul E1/T1/J1 Line Interface Device
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Released
3. When a hold time is specified between an input and a clock, the hold time is the time in
nanoseconds from the 1.4 Volt point of the clock to the 1.4 Volt point of the input.
4. Output propagation delay time is the time in nanoseconds from the 1.4 Volt point of the
reference signal to the 1.4 Volt point of the output.
5. Maximum output propagation delays are measured with a 100 pF load on the SBI DROP
Bus outputs (except DACTIVE) and a 50 pF load on DACTIVE and all other outputs.
Minimum output propagation delays are measured with a 0 pF load on the outputs.
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Released
18
Ordering and Thermal Information
Table 44 Ordering Information
Part No.
Description
PM4319-BI
288-pin Tape Super Ball Grid Array (TSBGA)
Table 45 OCTLIU-SH Theta Jc
PART NO.
CASE TEMPERATURE
Theta Jc
PM4319-BI
-40°C to +85°C
1.0 °C/W
Table 46 OCTLIU-SH Junction Temperature
PM4319-BI
Maximum Junction Temperature for Long Term Reliability
110 °C
Table 47 OCTLIU-SH Theta Ja vs. Airflow
Forced Air (Linear Feet per Minute)
Part No.
Case
Temperature
Theta J-A at
2.5 Watts
Conv
100
200
300
400
500
PM4319-BI
-40 °C to
85°C
Dense Board1
32.8
30.1
28.3
27.2
26.7
26.5
13.7
12.0
10.8
10.0
9.4
9.0
2
JEDEC Board
Notes
1.
Dense Board is defined as a 3S3P board and consists of a 3x3 array of PM4319-BI devices located
as close to each other as board design rules allow. All PM4319-BI devices are assumed to be
dissipating maximum power. Theta J-A listed is for the device in the middle of the array.
2.
JEDEC Board Theta J-A is the measured value for a single thermal device in the same package on a
2S2P board following EIA/JESD 51-3.
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Released
19
Mechanical Information
aaa
2X
A1 BALL
CORNER
D1,M
C
A
D
B
A1 BALL PAD
CORNER
eee M
fff M
22 20 18 16 14 12 10 8
6
4
2
21 19 17 15 13 11 9
7
5
3
1
CAB
C
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
b
A1 BALL
INDICATOR
S
A
E
e
aaa
C
2X
A
E1,N
S
6.
e
A
TOP VIEW
BOTTOM VIEW
A1
bbb
C
A2
C
0.075 MIN
ddd
C
d
SEATING PLANE
SIDE VIEW
ccc
C
A-A SECTION VIEW
NOTES: 1) ALL DIMENSIONS IN MILLIMETER.
2) DIMENSION aaa DENOTES PACKAGE BODY PROFILE.
3) DIMENSION bbb DENOTES PARALLEL.
4) DIMENSION ccc DENOTES FLATNESS.
5) DIMENSION ddd DENOTES COPLANARITY.
6) DIAMETER OF SOLDER MASK OPENING IS 0.550 MM (SMD).
7) PACKAGE COMPLIANT TO JEDEC REGISTERED OUTLINE MO-192, VARIATION AAJ-1.
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Notes
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