LMX2515
PLLatinum™ Frequency Synthesizer System
with Integrated VCO
General Description
Features
LMX2515 is a highly integrated, high performance, low
power frequency synthesizer system optimized for Japan
PDC mobile handsets. Using a proprietary digital phase
locked loop technique, LMX2515 generates very stable, low
noise local oscillator signals for up and down conversion in
wireless communications devices.
n Small size
5.0 mm X 5.0 mm X 0.75 mm 28-Pin LLP Package
n RF Synthesizer System
Integrated RF VCO
Integrated Loop Filter
Low Spurious, Low Phase Noise Fractional-N RF PLL
Based on 10-Bit Delta Sigma Modulator
Frequency Resolution Down to 20 kHz
n Supports Various Reference Frequencies
12.6/14.4/25.2/26.0 MHz
n Fast Lock Time: 300 µs
n Low Current Consumption
n 2.5 V to 3.3 V operation
n Digital Filtered Lock Detect Output
n Hardware and Software Power Down Control
LMX2515 includes a voltage controlled oscillator (VCO), a
loop filter, and a fractional-N RF PLL based on a delta sigma
modulator. In concert these blocks form a closed loop RF
synthesizer system. The LMX2515LQ0701 supports the Japan PDC800 band and the LMX2515LQ1321 supports Japan PDC1500 band.
Serial data is transferred to the device via a three-wire
MICROWIRE interface (DATA, LE, CLK).
Operating supply voltage ranges from 2.5 V to 3.3 V.
LMX2515 features low current consumption.
LMX2515 is available in a 28-pin leadless leadframe package (LLP).
Applications
n Japan PDC systems at 800 MHz frequency band.
n Japan PDC systems at 1500 MHz frequency band.
Functional Block Diagram
20068807
FastLock™ is a trademark of National Semiconductor Corporation.
TRI-STATE ® is a registered trademark of National Semiconductor Corporation.
PLLatinum™ is a trademark of National Semiconductor Corporation.
© 2004 National Semiconductor Corporation
DS200688
www.national.com
LMX2515 PLLatinum Frequency Synthesizer System with Integrated VCO
April 2004
LMX2515
Connection Diagrams
28-Pin 5x5 LLP (LQ) Package
(LMX2515LQ0701 - Top View)
28-Pin 5x5 LLP (LQ) Package
(LMX2515LQ1321 - Top View)
20068802
20068811
Pin Descriptions
Pin Number
LMX2515LQ0701
Pin Number
LMX2515LQ1321
Name
1
1
OSCin
I
Reference frequency input
2
2
GND
—
Ground for digital circuitry
3
3
VDD
—
Supply voltage for analog circuitry
4
4
GND
—
Ground for analog circuitry
5
5
NC
—
Do not connect to any node on the printed circuit board.
6
6
NC
—
Do not connect to any node on the printed circuit board.
7
7
VDD
—
Supply voltage for RF analog circuitry
8
8
NC
—
Do not connect to any node on the printed circuit board.
L1
—
RF VCO tank pin. An external inductor is required
between pins L1 and L2 to set the resonant frequency of
LMX2515LQ0701 RF VCO.
NC
—
Do not connect to any node on the printed circuit board.
L2
—
RF VCO tank pin. An external inductor is required
between pins L1 and L2 to set the resonant frequency of
LMX2515LQ0701 RF VCO.
9
9
10
I/O
Description
10
NC
—
Do not connect to any node on the printed circuit board.
11
11
NC
—
Do not connect to any node on the printed circuit board.
12
12
NC
—
Do not connect to any node on the printed circuit board.
13
13
VDD
—
Supply voltage for RF analog circuitry
NC
—
Do not connect to any node on the printed circuit board.
14
15
14
RFout
O
RF VCO output for LMX2515LQ1321
15
VDD
—
Supply voltage for RF analog circuitry
RFout
O
RF VCO output for LMX2515LQ0701
NC
—
Do not connect to any node on the printed circuit board.
16
16
17
17
VDD
—
Supply voltage for analog circuitry
18
18
GND
—
Ground for digital circuitry
19
19
VCC
—
Supply voltage for digital circuitry
20
20
GND
—
Ground for digital circuitry
21
21
VCC
—
Supply voltage for digital circuitry
22
22
LE
I
MICROWIRE Latch Enable
23
23
DATA
I
MICROWIRE Data
www.national.com
2
LMX2515
Pin Descriptions
(Continued)
Pin Number
LMX2515LQ0701
Pin Number
LMX2515LQ1321
Name
I/O
Description
24
24
CLK
I
25
25
CE
I
26
26
GND
—
Ground for digital circuitry
27
27
LD
O
Lock detect pin
28
28
VCC
—
Supply voltage for digital circuitry
MICROWIRE Clock
Chip enable control pin
Ordering Information
Order Part Number
RF Min. (MHz)
RF Max. (MHz)
Package
Marking
Supplied As
768
RF Center
(MHz)
~0701
LMX2515LQX0701
633.15
25150701
4500 units on tape
and reel
LMX2515LQ0701
633.15
768
~0701
25150701
1000 units on tape
and reel
LMX2515LQX1321
1270.22
1394.95
~1321
25151321
4500 units on tape
and reel
LMX2515LQ1321
1270.22
1394.95
~1321
25151321
1000 units on tape
and reel
Part Number Description
20068803
3
www.national.com
LMX2515
Typical Application Circuit
LMX2515LQ0701 Application Circuit (Note 1)
20068804
LMX2515LQ1321 Application Circuit (Note 2)
20068812
Note 1: Refer to LMX2515LQ0701 Tuning Range vs. External Inductance plot to aid in selecting the appropriate external inductance, PCB trace and L1, for the
desired frequency range.
Note 2: No external inductance required.
www.national.com
4
Recommended Operating
Conditions
5)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Parameter
Symbol
Supply Voltage
VCC, VDD -0.5 to 3.6
Voltage on any pin with VI
GND
Storage Temperature
Range
Ratings
Units
Symbol
Min Typ Max Unit
Ambient Temperature
TA
-30 25
85
˚C
3.3
V
Note 3: Absolute Maximum Ratings indicate limits beyond which damage to
the device may occur. Recommended Operating Conditions indicate conditions for which the device is intended to be functional, but do not guarantee
specific performance limits. For guaranteed specifications and test conditions, refer to the Electrical Characteristics section. The guaranteed specifications apply only for the conditions listed.
V
-0.3 to VDD+0.3 V
-65 to 150
Parameter
Supply Voltage (to GND) VCC, VDD 2.5
-0.3 to VCC+0.3 V
TSTG
LMX2515
Absolute Maximum Ratings (Notes 3, 4,
˚C
Note 4: This device is a high performance RF integrated circuit with an ESD
rating < 2 kV and is ESD sensitive. Handling and assembly of this device
should be done at ESD protected workstations.
Note 5: GND = 0 V.
Electrical Characteristics (VIN = 2.8 V, refer to Typical Application Circuit; Limits in standard typeface are
for TA = 25 ˚C; Limits in boldface type apply over the operating temperature range from -20 ˚C ≤ TA ≤ 75 ˚C unless otherwise noted.)
Symbol
Parameter
Condition
Min
Typ
Max
Units
OB_CRL [1:0] = 11
11.5
13.0
13.3
mA
OB_CRL [1:0] = 00
10.0
11.5
11.8
mA
OB_CRL [1:0] = 11
16.0
17.5
17.8
mA
OB_CRL [1:0] = 00
14.2
15.6
15.9
mA
20
µA
14.4
26.0
MHz
0.5
VCC
Vp-p
MHz
ICC PARAMETERS
ICC + IDD
Supply Current
LMX2515LQ0701
LMX2515LQ1321
Power Down Current
CE = LOW or
RF_PD = 1
REFERENCE OSCILLATOR PARAMETERS
fOSCin
Reference Oscillator Input Frequency
(Note 6)
VOSCin
Reference Oscillator Input Sensitivity
12.6/14.4/25.2/26.0 MHz are
supported.
12.6
RF VCO
fRFout
PRFout
Frequency Range LMX2515LQ0701
633.15
768
LMX2515LQ1321
1270.22
1394.95
MHz
0
dBm
Output Power
LMX2515LQ0701
LMX2515LQ1321
Lock Time
OB_CRL [1:0] = 11
-6
-3
OB_CRL [1:0] = 10
-9
-6
-3
dBm
OB_CRL [1:0] = 01
-11
-8
-5
dBm
OB_CRL [1:0] = 00
-15
-12
-9
dBm
OB_CRL [1:0] = 11
-5
-2
1
dBm
OB_CRL [1:0] = 10
-7
-4
-1
dBm
OB_CRL [1:0] = 01
-10
-7
-4
dBm
OB_CRL [1:0] = 00
-13
-10
-7
dBm
Full frequency span in High
Speed Mode.
300
(Note 8)
µs
Full frequency span in
Normal Mode.
500
(Note 8)
µs
375
(Note 9)
µs
RMS Phase Error
1.3
5
degrees
www.national.com
LMX2515
Electrical Characteristics (VIN = 2.8 V, refer to Typical Application Circuit; Limits in standard typeface are for
TA = 25 ˚C; Limits in boldface type apply over the operating temperature range from -20 ˚C ≤ TA ≤ 75 ˚C unless otherwise
noted.) (Continued)
Symbol
Parameter
Condition
Phase Noise in Normal Mode.
Min
Typ
Max
Units
@ 25 kHz offset
-95
-93
-91
dBc/Hz
@ 50 kHz offset
-106
-103
-101
dBc/Hz
@ 100 kHz offset
-115
-113
-111
dBc/Hz
-135
-133
dBc/Hz
2nd Harmonic Suppression
-25
dBc
3rd Harmonic Suppression
-20
dBc
-45
dBc
-60
dBc
-69
dBc
-75
dBc
0.8 VCC
VCC
V
0.8 VDD
VDD
V
-0.3
0.2 VCC
V
RF VCO
L(f)RFout
@ 1 MHz offset
Spurious Tones
@ ≤ 25 kHz offset
@
@
@
25 kHz < offset ≤ 50 kHz
50 kHz < offset ≤ 100 kHz
offset > 100 kHz
DIGITAL INTERFACE (DATA, CLK, LE, LD, CE)
VIH
High-Level Input Voltage
VIL
Low-Level Input Voltage
-0.3
0.2 VDD
V
IIH
High-Level Input Current
-10
10
µA
IIL
Low-Level Input Current
-10
10
µA
VOH
VOL
Input Capacitance
3
pF
Rise/Fall Time
30
ns
High-Level Output Voltage
VCC - 0.4
V
VDD - 0.4
V
Low-Level Output Voltage
Output Capacitance
0.4
V
5
pF
MICROWIRE INTERFACE TIMING
tCS
Data to Clock Set Up Time
50
ns
tCH
Data to Clock Hold Time
10
ns
tCWH
Clock Pulse Width HIGH
50
ns
tCWL
Clock Pulse Width LOW
50
ns
tES
Clock to Latch Enable Set Up Time
50
ns
tEW
Latch Enable Pulse Width
50
ns
Note 6: The reference frequency must also be programmed using the OSC_FREQ control bit. For other reference frequencies, please contact National
Semiconductor.
Note 7: For other frequency ranges, please contact National Semiconductor.
Note 8: Lock time is defined as the time difference between the beginning of the frequency transition and the point at which the frequency remains within +/-1 kHz
of the final frequency.
Note 9: Lock time is defined as the time difference between the beginning of the frequency transition and the point at which the frequency remains within +/-3 kHz
of the final frequency.
Note 10: All limits are guaranteed. All electrical characteristics having room temperature limits are tested during production with TA = 25 ˚C or correlated using
Statistical Quality Control (SQC) methods. All hot and cold limits are guaranteed by correlating the electrical characteristics to process and temperature variations
and applying statistical process control.
www.national.com
6
LMX2515
Microwire Interface Timing Diagram
20068801
7
www.national.com
LMX2515
Typical Performance Characteristics
(Note 11)
LMX2515LQ0701 Tuning Range vs. External Inductance (Note 12)
VIN = 2.8 V
20068813
Note 11: Typical performance characteristics do not guarantee specific performance limits. For guaranteed specifications, refer to the Electrical Characteristics
section.
Note 12: The frequency range is defined as the difference between the highest frequency and the lowest frequency of a given unit. For a chosen external
inductance, the typical frequency range equals the difference between the Typical Maximum Frequency and the Typical Minimum Frequency. Typical frequency
range may be assumed on any unit with that chosen external inductance, even if the unit has worst case Maximum Frequency or worst case Minimum Frequency.
www.national.com
8
LMX2515
Functional Description
GENERAL
The LMX2515 is a highly integrated frequency synthesizer
system for Japan PDC wireless communication systems.
The LMX2515LQ0701 supports operation for 800 MHz band
and the LMX2515LQ1321 supports operation for 1500 MHz
band.
20068810
where Ctotal is the total capacitance of the VCO, including
the parasitic capacitance and the nominal self-tuning capacitance. Note, for the LMX2515LQ0701, the external inductance consists of the PCB traces and lumped element inductor. The output frequency tuning range can be optimized for
the specific application by selecting the appropriate external
inductance. Refer to LMX2515LQ0701 Tuning Range vs.
External Inductance plot to aid in selecting the appropriate
external inductance. Care should be taken to ensure proper
frequency coverage when choosing the tolerance of the
lumped element inductor.
The LMX2515 includes all functional blocks for the RF PLL
including RF VCO, frequency divider, PFD, and loop filter.
Only external passive elements for the RF VCO tank
(LMX2515LQ0701 only) and supply bypassing are required
to complete the RF synthesizer.
The LMX2515 uses a patent pending Fractional-N synthesizer architecture based on a delta sigma modulator to support fine frequency resolution. Four of the most common
reference frequencies for PDC applications, 12.6 MHz, 14.4
MHz, 25.2 MHz and 26.0 MHz, are supported. The unique
feature of this architecture is its low spurious modulation
effect.
The use of a fractional synthesizer based on delta sigma
modulator allows for fast lock-up and system set-up times,
which reduces system power consumption. The loop filter is
included in the circuit to minimize the external noise coupling
and reduce the form factor applicable to the board level
application.
RF_PLL SECTION
Frequency Selection
The divide ratio can be calculated using the following equations:
fVCO = {8 x RF_B + RF_A + (RF_FN / FD)} x (fOSC / R) where
(RF_A < RF_B) for LMX2515LQ1321
fVCO = {4 x RF_B + RF_A + (RF_FN / FD)} x (fOSC / R) where
(RF_A < RF_B) for LMX2515LQ0701
fVCO: Output frequency of voltage controlled oscillator (VCO)
20068805
FIGURE 1. External Inductor Connection
For the LMX2515LQ1321, the internal bonding-wires provide
the necessary inductance to set the VCO center frequency
and no external inductance is required.
In real implementation, the inductance of Lfixed and Lexternal
can vary from its nominal value. The LMX2515 utilizes a
built-in tracking algorithm to compensate for variations up to
± 15% and tunes the VCO to the required frequency. During
the frequency acquisition period, the loop bandwidth is extended to achieve the frequency lock. After the frequency
lock, the loop bandwidth of the PLL is set to the nominal
value and the phase lock is achieved. The transition between the two operating modes is very smooth and extremely fast to meet the stringent PDC requirements for lock
time and phase noise.
RF_B: Preset divide ratio of binary 4-bit programmable
counter (2 ≤ RF_B ≤ 15)
RF_A: Preset divide ratio of binary 3-bit swallow counter (0 ≤
RF_A ≤ 7 for LMX2515LQ1321 and 0 ≤ RF_A ≤ 3 for
LMX2515LQ0701)
RF_FN: Preset numerator of binary 10-bit modulus counter
(0 ≤ RF_FN < FD)
FD: Preset denominator for modulus counter (FD = fOSC/(R
X fCH) where fCH is the channel spacing)
fOSC: Reference oscillation frequency
R: Internal reference oscillator frequency divider (1 for 12.6
MHz and 14.4 MHz, 2 for 25.2 MHz and 26.0 MHz)
The denominator, FD, in the above equation is dependent on
the channel spacing and reference oscillator frequency. The
channel spacing will change based on the Rx/Tx and RF_SEL bits. Table 6 in the R0 Register section summarizes
the values of FD.
POWER DOWN MODE
The LMX2515 includes the power down mode to reduce the
power consumption. The LMX2515 enters the power down
mode either by taking the CE pin LOW or by setting the
RF_PD bit in the R0 register. If the CE pin is set LOW, the
circuit is powered down regardless of the register values.
When the CE pin is HIGH, the RF_PD bit controls power to
the RF circuitry. Data can be written to the registers even
when the CE pin is set LOW. The following truth table
summarizes the power down logic.
VCO Frequency Tuning
The center frequency of the LMX2515 RF VCO is determined by the resonant frequency of the tank circuit, illustrated in Figure 1. With an internal fixed bonding-wire inductor and an external inductor, the center frequency of the VCO
is given as follows:
9
www.national.com
LMX2515
Functional Description
LOCK DETECT MODE
The LD output can be used to indicate the lock status of the
PLL. Bit 6 in Register R1 determines the signal that appears
on the LD pin. When the PLL is not locked, the LD pin
remains LOW. After obtaining phase lock, the LD pin will
have a logical HIGH level. The LD output is always low when
the LD register bit is 0 and in power down mode.
(Continued)
TABLE 1. Power Down Modes
CE pin
RF_PD Bit
Mode
HIGH
0
Active
HIGH
1
Not Active
LOW
0
Not Active
LOW
1
Not Active
TABLE 3. Lock Detect Modes
LD Bit
Mode
VCO SELECTION
0
Disable (GND)
The RF_SEL bit must be used to select the RF VCO output.
When using the LMX2515LQ0701 the RF_SEL bit must be
set to "0". When using the LMX2515LQ1321 the RF_SEL bit
must be set to "1".
1
Enable
TABLE 4. Lock Detect Logic
TABLE 2. VCO Selection
RF_SEL Bit
Mode
0
LMX2515LQ0701
1
LMX2515LQ1321
RF-PLL Section
LD Output
Locked
HIGH
Not Locked
LOW
20068808
FIGURE 2. Lock Detect Timing Diagram Waveform (Notes 13, 14, 15, 16, 17)
Note 13: LD output becomes low when the phase error is larger than tW2.
Note 16: tW1 is 5 ns for LMX2515LQ1321 and 10 ns for LMX2515LQ0701.
tW2 is 10 ns for both devices.
Note 14: LD output becomes high when the phase error is less than tW1 for
four or more consecutive cycles.
Note 17: The lock detect comparison occurs with every 64th cycle of fR and
fN
Note 15: Phase Error is measured on leading edge. Only errors greater than
tW1 and tW2 are labeled.
www.national.com
10
LMX2515
Functional Description
(Continued)
20068809
FIGURE 3. Lock Detect Flow Diagram
MICROWIRE INTERFACE
The programmable register set is accessed via the
MICROWIRE serial interface. The interface is comprised of
three signal pins: CLK, DATA, and LE (Latch Enable). Serial
data is clocked into the 24-bit shift register on the rising edge
of the clock. The last bits decode the internal control register
address. When the latch enable (LE) transitions from LOW
to HIGH, data stored in the shift registers is loaded into the
corresponding control register. The data is loaded MSB first.
HIGH SPEED LOCK-UP MODE
Two frequency-locking modes are provided: a Normal mode
and a High Speed mode for faster lock times. The HS bit in
register R0 controls the locking mode.
TABLE 5. Lock-up Modes
HS Bit
Mode
0
Normal mode
1
High Speed mode
11
www.national.com
GENERAL PROGRAMMING INFORMATION
The serial interface has a 24-bit shift register to store the incoming data bits temporarily. The incoming data is first loaded into the
shift register from MSB to LSB. The data is shifted at the rising edge of the clock signal. When the latch enable signal transitions
from LOW to HIGH, the data stored in shift register is transferred to the proper register depending on the address bit setting. The
selection of the particular register is determined by the control bits indicated in boldface text.
At initial start-up, the MICROWIRE loading requires three default words (registers R2, loaded first, to R0, loaded last). After the
device has been initially programmed, the RF VCO frequency can be changed using a single register (R0).
The control register content map describes how the bits within each control register are allocated to the specific control functions.
COMPLETE REGISTER MAP
Register
LMX2515
Programming Description
MSB
23
SHIFT REGISTER BIT LOCATION
22
21
20 19
LSB
18 17 16 15 14 13 12 11 10 9 8 7 6
RF_B
[3:0]
RF_A
[2:0]
5
4
3
2
RF_FN
[9:0]
1
0
0
0
R0
RX/
(Default) TX
RF_ HS 0
PD
RF_
SEL
R1
SPI_
(Default) DEF
0
0
1
0
0
1
0
1
0
0
0
0
0
0 1 0 LD OB_
CRL
[1:0]
OSC_
FREQ
[1:0]
0
1
R2
1
(Default)
1
0
0
1
0
0
0
0
1
1
1
1
0
0 0 0 0
0
1
1
0
1
0
0
R3
1
0
0
0
0
1
1
0
1
0
0
0
0
0
0 0 0 0
0
1
1
0
1
R4
0
0
0
0
0
0
1
1
1
0
1
0
0
0
1 1 0 0
1
0
0
1
1
1
R5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 0 0 0
0
0
1
1
1
1
Note: R0 control register will be used when hot start frequency change.
Note: Boldface text represent address bits.
www.national.com
12
(Continued)
R0 REGISTER
The R0 register address bits (R0 [1:0]) are “00”.
The Rx/Tx bit selects between receive and transmit modes and, in conjunction with the RF VCO selection bit (RF_SEL), the
channel spacing to be synthesized.
The RF_PD bit selects the power down mode of the RF PLL and selected VCO.
The HS bit selects between normal and high speed locking mode.
The RF_SEL bit is set to "0" for the LMX2515LQ0701 and "1" for the LMX2515LQ1321.
The RF N counter consists of the 4-bit programmable counter (RF_B counter), the 3-bit swallow counter (RF_A counter) and the
10-bit delta sigma modulator (RF_FN counter). The equations for calculating the counter values are presented below.
R0 REGISTER
Register
MSB
23
R0
(Default)
RX/
TX
SHIFT REGISTER BIT LOCATION
22
21
20
19
18
17
16
15
14
13
12
11
10
LSB
9
8
7
6
5
4
3
Data Field
RF_
PD
HS
0
RF_
SEL
RF_B
[3:0]
RF_A
[2:0]
1
RF_FN
[9:0]
Functions
RX/TX
RX/TX Mode
0 = Rx
1 = Tx
RF_PD
Power Down of RF Synthesizer
0 = RF synthesizer on (Active mode)
1 = RF synthesizer powered down
HS
Locking Mode
0 = Normal Mode
1 = High Speed Mode
RF_SEL
RF VCO Selection
0 = LMX2515LQ0701
1 = LMX2515LQ1321
RF_B [3:0]
RF_B Counter
4-bit programmable counter
0 ≤ RF_B ≤ 15 for both bands
RF_A [2:0]
RF_A Counter
3-bit swallow counter
0 ≤ RF_A ≤ 7 for LMX2515LQ1321
0 ≤ RF_A ≤ 3 for LMX2515LQ0701
RF_FN [9:0]
RF_FN Counter
10-bit modulus counter
0 ≤ RF_FN < FD See Table 6 for FD values.
0
Symbol
Functions
RF N Divider
N = 8 x RF_B + RF_A + RF_FN/FD (LMX2515LQ1321)
N = 4 x RF_B + RF_A + RF_FN/FD (LMX2515LQ0701)
Modulus Counter
RF_FN
Programmable Counter
RF_B
Swallow Counter
RF_A
13
0
Address
Field
Name
Counter Name
2
0
www.national.com
LMX2515
Programming Description
LMX2515
Programming Description
(Continued)
Pulse Swallow Function
fVCO = {8 x RF_B + RF_A + (RF_FN / FD)} x fOSC / R where (RF_A < RF_B) for LMX2515LQ1321
fVCO = {4 x RF_B + RF_A + (RF_FN / FD)} x fOSC / R where (RF_A < RF_B) for LMX2515LQ0701
fVCO: Output frequency of voltage controlled oscillator (VCO)
RF_B: Preset divide ratio of binary 4-bit programmable counter (2 ≤ RF_B ≤ 15)
RF_A: Preset divide ratio of binary 3-bit swallow counter (0 ≤ RF_A ≤ 7 for LMX2515LQ1321 and 0 ≤ RF_A ≤ 3 for
LMX2515LQ0701)
RF_FN: Preset numerator of binary 10-bit modulus counter (0 ≤ RF_FN < FD)
FD: Preset denominator for modulus counter (FD = fOSC/(R x fCH) where fCH is the channel spacing)
fOSC: Reference oscillator frequency
R: Internal reference oscillator frequency divider
OSC_FREQ [1:0]
Reference Oscillator Frequency (MHz)
R Divider
00
12.6
1
01
14.4
1
10
25.2
2
11
26.0
2
The value of the denominator (FD) is depended on the channel spacing and reference oscillator frequency. Table 6 summarizes
the denominator values based on the settings of the Rx/Tx, RF_SEL, and OSC_FREQ [1:0] bits.
TABLE 6. Demonimator Values
Part Number
RF_SEL
Rx/Tx
OSC_FREQ [1:0]
Reference Oscillator
Frequency (MHz)
R
fCH (kHz)
Denominator
(FD)
LMX2515LQ0701
0
0
00
12.6
1
25.0
504
0
0
01
14.4
1
25.0
576
0
0
10
25.2
2
25.0
504
0
0
11
26.0
2
25.0
520
0
1
00
12.6
1
20.0
630
0
1
01
14.4
1
20.0
720
0
1
10
25.2
2
20.0
630
LMX2515LQ1321
www.national.com
0
1
11
26.0
2
20.0
650
1
0
00
12.6
1
25.0
504
1
0
01
14.4
1
25.0
576
1
0
10
25.2
2
25.0
504
1
0
11
26.0
2
25.0
520
1
1
00
12.6
1
22.22
567
1
1
01
14.4
1
22.22
648
1
1
10
25.2
2
22.22
567
1
1
11
26.0
2
22.22
585
14
(Continued)
R1 REGISTER
The R1 register address bits (R1 [1:0]) are “01”.
The SPI_DEF bit allows for the programming of words R3 to R5. Under most circumstances, the SPI_DEF bit should be set to
"1".
The LD bit sets the function of the lock detect pin. Enabling the lock detect function provides a digital lock detect output of the
active RF synthesizer at the LD pin.
The OB_CRL [1:0] bits determine the power level of the RF output buffer. The power level can be adjusted to best meet the
system requirement.
The reference frequency selection bits, OSC_FREQ [1:0], are used to set the reference clock and R divider for use with one of
the following reference frequencies: 12.6 MHz, 14.4 MHz, 25.2 MHz or 26.0 MHz. The LMX2515 uses the OSC_FREQ bits along
with the RF_SEL and RX/TX bits to determine the correct divide ratios needed to meet the required channel spacing for the mode
of operation selected. Refer to Table 6 for a summary of denominator values.
R1 REGISTER
Register
MSB
23
R1
(Default)
SPI_
DEF
SHIFT REGISTER BIT LOCATION
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
LSB
7
6
5
4
3
2
Data Field
0
0
1
0
0
1
0
1
0
0
0
0
Address
Field
0
0
0
1
0
LD
OB_
CRL
[1:0]
OSC_
FREQ
[1:0]
Name
Functions
SPI_DEF
Default Register Selection
0 = OFF (Use values set in R0 to R5)
1 = ON (Use default values set in R0 to R2)
LD
Lock Detect
0 = Disable (GND)
1 = Enable
OB_CRL [1:0]
Output Buffer Control
LMX2515LQ1321, LMX2515LQ0701
00 = -10 dBm, -12 dBm
01 = -7 dBm, -8 dBm
10 = -4 dBm, -6 dBm
11 = -2 dBm, -3 dBm
OSC_FREQ [1:0]
Reference Frequency Selection
00 = 12.6 MHz
01 = 14.4 MHz
10 = 25.2 MHz
11 = 26.0 MHz
15
1
0
1
www.national.com
LMX2515
Programming Description
(Continued)
R2 REGISTER
The R2 register address bits (R2 [1:0]) are “10”.
R2 REGISTER
Register
MSB
23
R2
(Default)
1
SHIFT REGISTER BIT LOCATION
22
21
20
19
18
17
16
15
14
13
12
11
10
9
LSB
8
7
6
5
4
3
2
Data Field
1
0
0
1
0
0
0
0
1
1
1
0
Address
Field
1
1
0
0
0
0
0
0
0
0
1
1
0
R3 REGISTER
The R3 register address bits (R3 [2:0]) are “011”. This register is only written to if the SPI_DEF bit is set to "0".
R3 REGISTER
Register
MSB
23
R3
1
SHIFT REGISTER BIT LOCATION
22
21
20
19
18
17
16
15
14
13
12
11
10
9
LSB
8
7
6
5
4
3
2
Data Field
0
0
0
0
1
1
0
1
0
0
1
0
Address
Field
0
0
0
0
0
0
0
0
1
1
0
1
2
1
1
R4 REGISTER
The R4 register address bits (R4 [3:0]) are “0111”. This register is only written to if the SPI_DEF bit is set to "0".
R4 REGISTER
Register
MSB
23
R4
0
SHIFT REGISTER BIT LOCATION
22
21
20
19
18
17
16
15
14
13
12
11
10
9
LSB
8
7
6
5
4
Data Field
0
0
0
0
0
1
1
1
0
3
0
Address
Field
1
0
0
0
1
1
0
0
1
0
0
1
1
1
R5 REGISTER
The R5 register address bits (R5 [4:0]) are “01111”. This register is only written to if the SPI_DEF bit is set to "0".
R5 REGISTER
Register
LMX2515
Programming Description
MSB
R5
0
23
SHIFT REGISTER BIT LOCATION
22
21
20
19
18
17
16
15
14
13
12
11
10
9
LSB
8
7
6
5
Data Field
www.national.com
0
0
0
0
0
0
0
0
0
4
3
2
1
0
Address Field
0
16
0
0
0
0
0
0
0
0
0
1
1
1
1
inches (millimeters) unless otherwise noted
28-Pin Leadless Leadframe Package (LLP)
NSC Package Number LQA28A
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
BANNED SUBSTANCE COMPLIANCE
National Semiconductor certifies that the products and packing materials meet the provisions of the Customer Products
Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification
(CSP-9-111S2) and contain no ‘‘Banned Substances’’ as defined in CSP-9-111S2.
National Semiconductor
Americas Customer
Support Center
Email: [email protected]
Tel: 1-800-272-9959
www.national.com
National Semiconductor
Europe Customer Support Center
Fax: +49 (0) 180-530 85 86
Email: [email protected]
Deutsch Tel: +49 (0) 69 9508 6208
English Tel: +44 (0) 870 24 0 2171
Français Tel: +33 (0) 1 41 91 8790
National Semiconductor
Asia Pacific Customer
Support Center
Email: [email protected]
National Semiconductor
Japan Customer Support Center
Fax: 81-3-5639-7507
Email: [email protected]
Tel: 81-3-5639-7560
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
LMX2515 PLLatinum Frequency Synthesizer System with Integrated VCO
Physical Dimensions