LP3927 Cellular/PCS System Power Management IC General Description Key Specifications The LP3927 system power management IC is designed for cellular/PCS handsets as well as other portable systems that require intelligent power management. Each device contains five low-dropout linear regulators (LDO’s), a reset timer, a power-up control logic, a general-purpose open drain output that can be used to light LEDs, and a CMOS rail-to-rail input/output operational amplifier. 3.0V to 5.5V Input Voltage Range Two 200 mA, Two 150 mA and One 100 mA LDO’s 100 mV typ Dropout Voltage @ IMAX 150 mA General-Purpose Open-drain programmable current sink for back light LED n Low Voltage Rail to Rail Input/Output Operational Amplifier n 28 pin LLP package Each linear regulator features an extremely low dropout voltage of 100 mV (typ) at maximum output current. LDO1 and LDO2 are powered on and off by either the KYBD or the VEXT pin. LDO3, LDO4 and LDO5 each have its independent enable pin. LDO1 and LDO4 are rated at 150 mA each, LDO2 and LDO5 are rated at 200 mA each and LDO3 is rated at 100 mA. All LDO’s are optimized for low noise and high isolation. The open drain output current sink can be programmed up to 150 mA by using an external low cost resistor. A single supply, low voltage operational amplifier has rail to rail input and output with 600 kHz of gain-bandwidth product. n n n n Applications n n n n Cellular/PCS handsets PDA’s, Palmtops, and portable terminals Single–Cell Li+ Systems 2- or 3- Cell NiMH, NiCd or Alkaline System Typical Application Circuit 20037901 VDD1, VDD2 and VDD3 must be tied together externally. Collectively called VDD. © 2002 National Semiconductor Corporation DS200379 www.national.com LP3927 Cellular/PCS System Power Management IC August 2002 LP3927 LP3927 Pin Out Diagram (Top View) 20037902 Output Current Rating and Voltage Options IMAX (mA) Voltage Options (V) LDO1 150 1.8, 1.9, 2.5, 2.6*, 2.7 LDO2 200 1.8, 2.85*, 2.9, 3.0 LDO3 100 2.7, 2.8, 2.9*, 3.0 LDO4 150 2.7, 2.8, 2.9*, 3.0 LDO5 200 2.7, 2.8, 2.9, 3.0* * denotes the voltage options that are available currently. For other options, please contact the National Semiconductor factory sales office/distributors for availability and specifications. Ordering Information LP3927 Supplied as LP3927 Supplied as Standard Optional 1000 Units, tape and 4500 Units, tape and LDO delay LDO delay reel reel LP3927ILQ-AH LP3927ILQX-AH LP3927ILQ-AJ LP3927ILQX-AJ X X For LDO delay options, please refer to Electrical Characteristics Table. www.national.com 2 VO1 (V) VO2 (V) VO3 (V) VO4 (V) VO5 (V) 2.6 2.85 2.9 2.9 3.0 TOP MARKING 3927AH 3927AJ LP3927 Pin Description Pin Name 1 VO1 150 mA, LDO1 output pin. 2 EN5 LDO5 enable input. 3 EN4 LDO4 enable input. 4 EN3 LDO3 enable input. 5 RST Externally pulled high, open drain output to processor/memory reset. 6 IRQ Externally pulled high, open drain output to processor interrupt indicating KYBD has gone high. 7 PS_HOLD 8 KYBD 9 D_GND 10 VEXT 11 BYP 12 TEST_MODE 13 LED_EN Functional Description Input from the processor to the LP3927. A HIGH indicates a steady supply of power is granted. Refer to ’Application Hints’ section for more detail. An active high input signal indicating the keyboard “On/Off” button has been asserted. Refer to ’Application Hints’ section for more detail. Digital ground, used primarily for the digital and DAC circuits. Active low input indicating a battery charger insertion Refer to ’Application Hints’ section for more detail. Reference bypass pin. Pin used for production testing, factory use only. This pin should be grounded in applications. LED driver enable input. 14 LED 15 LED_PGM LED driver, drain connection of the LED drive MOSFET. 16 OP_AMP_OUT 17 IN− − input of the Op-Amp. 18 IN+ + input of the Op-Amp. 19 OP_AMP_VDD 20 A_GND2 LED drive current programming pin. Operational amplifier output pin. Power supply pin for Op-Amp. Ground for analog. 21 VO5 22 VDD3 200 mA, LDO5 output pin. Input power pin for LDO5. VDD1, VDD2 and VDD3 must be tied together externally. 23 VO4 150 mA, LDO4 output pin. 24 VDD2 Input power pin for LDO3 and LDO4. VDD1, VDD2 and VDD3 must be tied together externally. 25 VO3 100 mA, LDO3 output pin. 26 A_GND1 27 VO2 200 mA, LDO2 output pin. 28 VDD1 Input power pin for LDO1 and LDO2. VDD1, VDD2 and VDD3 must be tied together externally. Ground for analog. 3 www.national.com LP3927 Functional Block Diagram 20037903 www.national.com 4 All other pins (Notes 1, 2 kV 2) Operating Ratings (Notes 1, 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. VDD1, VDD2, VDD3, KYBD, OP_AMP_VDD EN3, EN4, EN5 All pins except LED_PGM, BYP, op amp’s inputs & output −0.3V to 6.0V OP_AMP_OUT, IN-, IN+ -0.3V to 5.5V COUT: Capacitance Junction Temperature Storage Information 1.0 µF to 20.0 µF ESR ± 0.3V GND to GND SLUG 3.0V to 5.5V −0.3V to (VDD + 0.3V) 0.005Ω to 0.5Ω Junction Temperature 150˚C −40˚C to 125˚C Operating Temperature −65˚C to 150˚C −40˚C to 85˚C Thermal Resistance (Note 5) Soldering Temperature Pad Temperature θJA (LLP28) 235˚C Maximum Power Dissipation (Note 3) 30.8˚C/W Maximum Power Dissipation (Note 6) 2.6W 1.78W ESD (Note 4): KYBD 4 kV Electrical Characteristics, LDO’s Unless otherwise noted, VDD = VOUT(target) + 0.7V, CIN (VDD1, VDD2, VDD3) = 4.7 µF, COUT (VO1 to VO5) = 2.2 µF, Cbyp = 0.1 µF. Typical values and limits appearing in normal type apply for TJ = 25˚C. Limits appearing in boldface type apply over the entire junction temperature range for operation, −40˚C to +85˚C. (Notes 7, 8) Symbol Parameter Conditions Typical Limit Min Max Units VDD Input Voltage Range VDD1, VDD2, VDD3,KYBD 3 5.5 V ∆VOUT Output Voltage Tolerance IOUT = IMAX/2, VDD = 3.7V −2 +2 % Load Regulation IOUT = 100 µA to IMAX, VDD = 3.7V −2 +2 % Line Regulation VDD = VOUT(target) +0.7V to 5.5V IOUT = IMAX/2 −40 +40 mV −3.5 +3.5 % 170 200 mV 3.7 Total Accuracy Error VIN - VOUT Dropout Voltage IOUT = IMAX (Note 9) 100 eN Output Noise Voltage IOUT = 100 µA, 10 Hz ≤ f ≤ 100 kHz 27 CIN = 2.2µF, IOUT = IMAX, f = 100 Hz f = 1 kHz f = 10 kHz f = 100 kHz 45 45 30 10 30 PSRR Power Supply Ripple Rejection Ratio Cross Talk (Note 10) IQ Quiescent Current IOUT = 0, PS_HOLD = KYBD = 0 VEXT = VDD IGND Ground Current IOUT1 = IOUT2 = 1 mA, LDO3, LDO4, LDO5 OFF ISC Short Circuit Current Limit COUT Output Capacitor Capacitance RSHUNT VO2 - VO5 Output Shunt Resistor µVrms dB dB 5 8 µA 100 200 µA IOUT1, IOUT2, IOUT3, IOUT4, IOUT5 = IMAX 400 950 VOUT = 0V 400 ESR 70 5 % of IMAX 1 20 µF 5 500 mΩ 200 Ω www.national.com LP3927 Absolute Maximum Ratings LP3927 Electrical Characteristics, Digital Interface Symbol Parameter Conditions VOL Logic Low Output RST and IRQ ILOAD = 250 µA VIH Logic High Input KYBD and VEXT Limit Typical Min 150 0.7 VDD EN3–5, PS_HOLD Logic Low Input 0.85VDD KYBD and VEXT 0.2 VDD V 0.4 LED_EN Input Leakage Current mV V EN3–5, PS_HOLD ILEAKAGE Units 1.4 LED_EN VIL Max 0.2 VDD −10 VEXT, PS_HOLD, IRQ, KYBD, EN3–5, 0V ≤ VDD ≤ 5.5V +10 µA Electrical Characteristics, Error Flag Symbol Parameter VTh-H Error Flag High VTh-L Error Flag Low tDELAY-H Conditions Typical Vo1 and Vo2 Outputs (Note 11) (Note 12) tDELAY-L Limit Units Min Max 95 92 98 90 89 92 6 0 10 µs 6 0 10 µs % VOUT Keyboard Debounce Delay (Note 13) 32 16 64 ms VEXT Debounce Delay (Note 13) 32 16 64 ms RDELAY RST Reset Delay (Note 14) 20 10 40 ms tDELAY LDO Delay, standard (Note 15) 125 0 250 µs 10 5 20 ms (Note 16) 500 250 1000 ms LDO Delay, optional tHold-UP PS_HOLD Input Electrical Characteristics, Backlight LED Driver Symbol ILED Parameter Conditions Typical Drive Current VLED = 1V, RPGM = 130kΩ 150 Limit Min Max 125 175 Units mA Electrical Characteristics, Operational Amplifier Unless otherwise noted, VOP_AMP_VDD = 3.3V, VCM = VOUT = VOP_AMP_VDD/2 and RLOAD > 1 MΩ. Typical values and limits appearing in normal type apply for TJ = 25˚C. Limits appearing in boldface type apply over the entire junction temperature range for operation, −40˚C to +85˚C. (Note 7) Symbol Parameter Conditions Typical Limit Units Min Max 3 5.5 V 10 mV VDD OP_AMP_VDD 3.3 VOS Input Offset Voltage 1.2 TC VOS Offset Voltage Drift 10 µV/˚C IB Input Bias Current 0.2 nA IOS Input Offset Current 0.1 nA RIN Input Resistance >1 GΩ CMRR Common-Mode Rejection Ratio 0V ≤ VCM ≤ 2.7V 70 dB PSRR Power Supply Rejection Ratio VOP_AMP_VDD = 2.7V to 3.3V , VCM = 0 60 dB CIN Common-Mode Input Capacitor 3 pF www.national.com 6 LP3927 Electrical Characteristics, Operational Amplifier (Continued) Unless otherwise noted, VOP_AMP_VDD = 3.3V, VCM = VOUT = VOP_AMP_VDD/2 and RLOAD > 1 MΩ. Typical values and limits appearing in normal type apply for TJ = 25˚C. Limits appearing in boldface type apply over the entire junction temperature range for operation, −40˚C to +85˚C. (Note 7) Symbol Parameter Conditions Typical Limit Min Max Units VOUT Output Swing RLOAD = 2 kΩ IS Supply Current VOP_AMP_VDD = 3.0V SR Slew Rate 0.7 V/µs GBW Gain-Bandwidth Product 0.6 MHz 0.5 V 3.1 0.5 1.4 mA Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the Electrical Characteristics tables. Note 2: All voltages are with respect to the potential at the GND pin. Note 3: The Absolute Maximum power dissipation depends on the ambient temperature and can be calculated using the formula P = (TJ − TA)/θJA, (1) where TJ is the junction temperature, TA is the ambient temperature, and θJA is the junction-to-ambient thermal resistance. The 2.6W rating appearing under Absolute Maximum Ratings results from substituting the Absolute Maximum junction temperature, 150˚C, for TJ, 70˚C for TA, and 30.8˚C/W for θJA. More power can be dissipated safely at ambient temperatures below 70˚C. Less power can be dissipated safely at ambient temperatures above 70˚C. The Absolute Maximum power dissipation can be increased by 32.5 mW for each degree below 70˚C, and it must be derated by 32.5 mW for each degree above 70˚C. Note 4: The human-body model is used. The human-body model is 100 pF discharged through 1.5 kΩ. Note 5: This figure is taken from a thermal modeling result. The test board is a 4 layer FR-4 board measuring 101mm x 101mm x 1.6mm with a 3 x 3 array of thermal vias. The ground plane on the board is 50mm x 50mm. Ambient temperature in simulation is 22˚C, still air. Power dissipation is 1W. Note 6: Like the Absolute Maximum power dissipation, the maximum power dissipation for operation depends on the ambient temperature. The 1.78W rating appearing under Operating Ratings results from substituting the maximum junction temperature for operation, 125˚C, for TJ, 70˚C for TA, and 30.8˚C/W for θJA into (1) above. More power can be dissipated at ambient temperatures below 70˚C. Less power can be dissipated at ambient temperatures above 70˚C. The maximum power dissipation for operation can be increased by 32.5 mW for each degree below 70˚C, and it must be derated by 32.5 mW for each degree above 70˚C. Note 7: All limits guaranteed at room temperature (standard typeface) and at temperature extremes (bold typeface). All room temperature limits are 100% production tested or guaranteed through statistical analysis. All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods. Note 8: The target output voltage, which is labeled VOUT(target), is the desired or ideal output voltage. Note 9: Dropout voltage is the input-to-output voltage difference at which the output voltage is 100 mV below its nominal value. This specification does not apply in cases it implies operation with an input voltage below the 2.5V minimum appearing under Operating Ratings. For example, this specification does not apply for devices having 1.5V outputs because the specification would imply operation with an input voltage at or about 1.5V. Note 10: Pulsing the load of LDO X from 100µA to Imax and measuring its effects at the output of LDO Y. LDO Y enabled but under no load. Note 11: The error flags are internal to the chip. There is no external access to the signals. LDO1 error flag and the LDO2 error flag will go HIGH when the respective LDO reaches its VTh-H value. The error flags will go LOW when the respective LDO reaches its VTh-L value. Note 12: The tDELAY-H is the delay between LDO1 reaching its VTh-H and its error flag going HIGH. The tDELAY-L is the delay between LDO1 reaching its VTh-L and its error flag going LOW. Same delays apply to LDO2 and its error flag. Note 13: Refer to Timing Diagram. Note 14: The delay between LDO2 error flag HIGH and RST signal HIGH in the power up sequence. In the power down sequence, it is the delay between RST signal LOW and LDO2 disabled. Note 15: The delay between LDO1 error flag HIGH and LDO2 enable in power up sequence. In the power down sequence, it is the delay between LDO2 error flag LOW and LDO1 disable. For the optional LDO delay, please contact the factory for availability. Note 16: Time between RST high and PS_HOLD going high. 7 www.national.com LP3927 Typical Performance Characteristics Unless otherwise specified, CIN = 1 µF ceramic, CBYP = 0.01 µF, VDD = VOUT + 0.2V, TA = 25˚C, Enable pin is tied to VDD. PSRR vs Frequency LDO3 Enable Response (Cout=2.2µF) 20037909 20037908 LDO4 Enable Response (Cout=2.2µF) LDO5 Enable Response (Cout=2.2µF) 20037910 20037911 LDO2 (1.8V Option) Load Transient LDO2 (2.85V Option) Load Transient 20037929 www.national.com 20037930 8 LDO4 (2.8V Option) Load Transient LDO5 (3.0V Option) Load Transient 20037931 20037932 LDO2 (1.8V Option) Line Transient LDO2 (2.85V Option) Line Transient 20037933 20037934 LDO4 (2.8V Option) Line Transient LDO5 (3.0V Option) Line Transient 20037935 20037936 9 www.national.com LP3927 Typical Performance Characteristics Unless otherwise specified, CIN = 1 µF ceramic, CBYP = 0.01 µF, VDD = VOUT + 0.2V, TA = 25˚C, Enable pin is tied to VDD. (Continued) LP3927 Keyboard Start-Up/Shut-Down 20037925 Note: Diagram indicates Open Drain IRQ tied to VDD. *** = Internal signal 1. 2. 3. 4. Keyboard de-bounce delay, 32 msec typ. Delay between LDO1 reaching 95% of its output voltage and LDO2 enable, 125 µsec typical. Both LDO1 and LDO2 outputs reach 95% of respective output voltage, start RST timer. RST delay, 20 msec typical. 5. 6. 7. 8. 9. IRQ is active low. Keyboard press must be greater than 32 msec. PS_HOLD timer begins upon RST going high. Maximum of 500 msec period from RST going high to PS_HOLD going high. Response time from PS_HOLD going low to RST going low. 10. Delay between RST high-low transition to LDO2 disable. 11. Delay between LDO2 disable and LDO1 disable. www.national.com 10 LP3927 Keyboard Held at Start-Up/Shut-Down 20037926 Note: Diagram indicates Open Drain IRQ tied to VDD. *** = Internal signal 1. 2. 3. 4. 5. 6. 7. 8. 9. Keyboard de-bounce delay, 32msec typ. Delay between LDO1 reaching 95% of its output voltage and LDO2 enable. Both LDO1 and LDO2 outputs reach 95% of the respective output voltage, start RST timer. Reset delay. IRQ is active low. Keyboard press must be greater than 32 msec. PS_HOLD timer begins upon RST going high. Maximum of 500 msec period from RST going high to PS_HOLD going high. Response time from PS_HOLD going low to RST going low. 10. Delay between RST high-low transition to LDO2 disable. 11. Delay between LDO2 disable and LDO1 disable. 11 www.national.com LP3927 VEXT Detect Start-Up/Shut Down 20037927 Note: Diagram indicates Open Drain IRQ tied to VDD. *** = Internal signal 1. 2. 3. 4. 5. 6. 7. 8. 9. VEXT goes active low. VEXT 32 msec de-bounce period. Delay between LDO1 and LDO2 enables. Both LDO1 and LDO2 outputs reach 95% of respective output voltage, start Reset timer. Reset delay. Period between Reset and PS_HOLD going high is not relevant since VEXT is low PS_HOLD goes low but LDOs continue to run since VEXT is low. PS_HOLD is low and VEXT goes high, RST pin goes low. Delay between RST going low and LDO2 disabled. 10. Delay between LDO2 and LDO1 disabled. www.national.com 12 LP3927 VEXT Detect W/Keyboard Interrupts 20037928 Note: Diagram indicates Open Drain IRQ tied to VDD. *** = Internal signal 1. 2. 3. 4. 5. 6. 7. 8. 9. VEXT goes active low. VEXT 32 msec de-bounce period. Delay between LDO1 and LDO2 enable. Both LDO1 and LDO2 outputs reach 95% of respective output voltage, start Reset timer. Reset delay. Keyboard de-bounce delay. Keyboard pulse must be a minimum of 32 msec. PS_HOLD may go low after Key press, but LDOs stay on since VEXT is low. VEXT goes high, begin shutdown since PS_HOLD is low. 10. Delay between RST going low and LDO2 disabled. 11. Delay between LDO2 disable and LDO1 disabled. 13 www.national.com LP3927 This capacitor must be located a distance of not more than 1 cm from the input pin and returned to a clean analog ground. Any good quality ceramic, tantalum, or film capacitor may be used at the inputs. Application Hints LP3927 Function Description The LP3927 is designed for cellular/PCS handsets. The LDOs power the microprocessor, RF and digital sections of the phone. When a KYBD debounce of longer than 32 ms is detected by the LP3927, the IRQ signal is asserted and sent to the microprocessor. In addition, the KYBD signal turns on LDO1. When LDO1 reaches 95% of its output voltage option, a 125 µs delay (standard LDO delay. The optional LDO delay has a 10msec delay) takes place, and LDO2 turns on. When LDO2 reaches 95% of its output voltage option, RST goes high after a 20 ms delay. At this point, the microprocessor comes out of reset and the LP3927 starts the PS_HOLD timer. If PS_HOLD goes high before 500 ms, IRQ is de-asserted. If PS_HOLD stays low for longer than 500 ms, IRQ will still de-assert, but RST will also be asserted, and the part will power down. Important: Tantalum capacitors can suffer catastrophic failures due to surge current when connected to a low-impedance source of power (like a battery or a very large capacitor). If a tantalum capacitor is used at the input, it must be guaranteed by the manufacturer to have a surge current rating sufficient for the application. There are no requirements for the ESR on the input capacitor, but tolerance and termperature coefficient must be considered when selecting the capacitor to ensure the capacitance will be ≈ 1 µF over the entire operating temperature range. LDO Output Capacitor The LDOs are designed specifically to work with very small ceramic output capacitors. A ceramic capacitor (X7R, X5R, Z5U, or Y5V) in 1 µF to 20 µF range with 5 mΩ to 500 mΩ ESR range is suitable in the LP3927 application circuit. It may also be possible to use tantalum or film capacitors at the output, but these are not as attractive for reasons of size and cost. The output capacitor must meet the requirement for minimum amount of capacitance and also have an ESR (Equivalent Series Resistance) value which is within a stable range (5 mΩ to 500 mΩ). The power down sequence is the exact reverse of the power up sequence. PS_HOLD from the microprocessor goes low, indicating a request to turn the part off. This causes RST to go low. LDO2 will be turned off after a 20 ms delay. When LDO2 drops to 90% of its output voltage option, LDO1 will start to turn off after a 125 µs (or a 10msec) delay. Another KYBD debounce after power up does not necessary mean power down. Whenever LDO1 or LDO2 falls under 90% of the output voltage option, RST immediately goes low to bring PS_HOLD low in order to turn the part off. Plugging the charger into the cell phone will cause an external signal VEXT to toggle from high to low. The LP3927 will respond differently to this signal depending on the scenario: Case 1: If a charger is plugged into the cell phone after the phone is already on, the VEXT signal go from high to low. The LP3927 will acknowledge this signal but all other signals remain unchanged. Case 2: If a charger is plugged into the phone while the phone is off, VEXT signal goes from high to low and the LP3927 will proceed to turn LDO1 on after a 32 ms delay, and the identical power-up sequence follows. This case bypasses the power-up initiated by KYBD and IRQ. KYBD remains low and IRQ remains high at all time during power-up. When the charger is plugged in, the phone cannot be turned off unless both VEXT goes high and PS_HOLD goes low. LED Current Driver The LED pin on the LP3927 is an open-drain output that can provide up to 150 mA to drive backlight LEDs. It is turned on when the LED_EN pin is pulled high, and off when the LED_EN pin is pulled low. The external resistor RPGM connected to the LED_PGM pin programs the output current of LED. A 130 kΩ resistor sets the output current to 150 mA. An approximated equation between RPGM and ILED is: Operational Amplifier The LP3927 has an internal op amp with rail-to-rail input and output and a 600 kHz of gain-bandwidth product. Leadless Leadframe Package (LLP) The LP3927 is packaged in a 28-lead LLP package for enhanced thermal performance. The 28-lead LLP measures 5 mm x 5 mm x 0.75 mm. Its small size and low profile is ideal for handset applications and other portable applications that require power management. LDOs The LP3927 contains five LDOs. LDO1 and 2 are powered by the VDD1 line; LDO3 and 4 are powered by the VDD2 line; and LDO5 is powered by the VDD3 line. VDD1, VDD2 and VDD3 must be tied together externally. All five LDOs accept an input voltage from 3.0V to 5.5V. This accommodates the full usable range of a single Li-On battery. LDO1 and 4 each provide 150 mA of current. LDO2 and 5 each provide 200 mA of current. LDO3 provides 100 mA of current. The output of each LDO can be programmed to different voltage levels at the factory. Refer to “Output Current Rating and Voltage Options” Table for more details. Thermal Performance The LLP package is designed for enhanced thermal performance because of the exposed die attach pad at the bottom center of the package. It brings advantage to thermal performance by creating a very direct path for thermal dissipation. Compared to the traditional leaded packages where the die attach pad is embedded inside the mold compound, the LLP reduces a layer in the thermal path. The thermal advantage of the LLP package is fully realized only when the exposed die attach pad is soldered down to a thermal land on the PCB board and thermal vias are planted underneath the thermal land. Based on a LLP thermal mea- LDO Input Capacitor An input capacitance of ≈ 2.2 µF is required between each VDD input pins and ground. (The amount of the capacitance may be increased without limit). www.national.com 14 (Continued) Layout Consideration surement, junction to ambient thermal resistance (θJA) can be improved by as much as two times if a LLP is soldered on the board with thermal land and thermal vias than if not. The LP3927 has an exposed die attach pad located at the bottom center of the LLP package. It is imperative to create a thermal land on the PCB board when designing a PCB layout for the LLP package. The thermal land helps to conduct heat away from the die, and the land should be the same dimension as the exposed pad on the bottom of the LLP (1:1 ratio). The land should be on both the top and the bottom layer of the PCB board. In addition, thermal vias should be added inside the thermal land to conduct more heat away from the surface of the PCB to the ground plane. Typical pitch and outer diameter for these thermal vias are 1.27 mm and 0.33 mm respectively. Typical copper via barrel plating is 1 oz. although thicker copper may be used to improve thermal performance. The LP3927 bottom pad is connected to ground. Therefore, the thermal land and vias on the PCB board need to be connected to ground. For more information on board layout techniques, refer to Application Note 1187 “Leadless Leadframe Package (LLP).” The application note also discusses package handling, solder stencil, and assembly process. Consider the following equation: Where P is the power dissipated, TJ is the maximum junction temperature of the die, TA is the ambient temperature, and θJA is the thermal resistance of the package. TJ is specified at 150˚C. According to the above equation, in the case where the LP3927 is dissipating 3W of power, TA is limited to 32.6˚C when TJ of 125˚C and θJA of 30.8˚C/W are used in the equation. In order to operate at a higher ambient temperature, power dissipation has to be reduced. A curve of maximum power dissipation vs ambient temperature is provided below. Power Dissipation vs Ambient Temperature (θJA=30.8˚C/W) 20037915 15 www.national.com LP3927 Application Hints LP3927 Cellular/PCS System Power Management IC Physical Dimensions inches (millimeters) unless otherwise noted 28 Lead LLP Package NS Package Number lqa28A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Email: [email protected] www.national.com National Semiconductor Europe Fax: +49 (0) 180-530 85 86 Email: [email protected] Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: [email protected] National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.