2.5V, 2.0GHz ANY DIFF. IN-TO-LVDS Precision Edge™ PROGRAMMABLE CLOCK DIVIDER AND 1:2 SY89875U FINAL FANOUT BUFFER W/ INTERNAL TERMINATION FEATURES DESCRIPTION ■ Integrated programmable clock divider and 1:2 fanout buffer ■ Guaranteed AC performance over temperature and voltage: • > 2.0GHz fMAX • < 200ps tr/tf • < 15ps within device skew ■ Low jitter design: • < 10ps (pk-pk) total jitter • < 1ps (rms) cycle-to-cycle jitter ■ Unique input termination and VT Pin for DC-coupled and AC-coupled Inputs; CML, PECL, LVDS and HSTL ■ LVDS compatible outputs ■ TTL/CMOS inputs for select and reset ■ Parallel programming capability ■ Programmable divider ratios of 1, 2, 4, 8 and 16 ■ Low voltage operation 2.5V ■ Output disable function ■ –40°C to 85°C temperature range ■ Available in 16-pin (3mm × 3mm) MLF™ package This low-skew, low-jitter device is capable of accepting a high-speed (e.g., 622MHz or higher) CML, LVPECL, LVDS or HSTL clock input signal and dividing down the frequency using a programmable divider to create a lower speed version of the input clock. Available divider ratios are 2, 4, 8 and 16, or straight pass-through. The differential input buffer has a unique internal termination design that allows access to the termination network through a VT pin. This feature allows the device to easily interface to different logic standards. A VREF-AC reference is included for AC-coupled applications. The /RESET input asynchronously resets the divider. In the pass-through function (divide by 1) the /RESET synchronously enables or disables the outputs on the next falling edge of IN (rising edge of /IN). TYPICAL PERFORMANCE APPLICATIONS OC-12 to OC-3 Translator/Divider ■ SONET/SDH line cards ■ Transponders ■ High-end, multiprocessor servers CML/LVPECL/LVDS 622MHz Clock In FUNCTIONAL BLOCK DIAGRAM Divide-by-4 LVDS 155.5MHz Clock Out S2 622MHz In /RESET Enable IN FF Q0 Enable MUX /Q0 MUX 50 VT 50 /IN Q1 IN W Divided W 2, 4, 8 by /Q1 Q0 155.5MHz Out or 16 /IN S1 Decoder S0 /Q0 VREF_AC Precision Edge is a trademark of Micrel, Inc. MicroLeadFrame and MLF are trademarks of Amkor Technology, Inc. Rev.: A 1 Amendment: /1 Issue Date: February 2003 Precision Edge™ SY89875U Micrel S0 S1 VCC GND PACKAGE/ORDERING INFORMATION Ordering Information 16 15 14 13 Q0 1 12 IN /Q0 2 11 Q1 /Q1 3 4 10 9 VT VREF-AC /IN Part Number Package Type Operating Range Package Marking SY89875UMI MLF-16 Industrial 875U SY89875UMITR* MLF-16 Industrial 875U *Tape and Reel S2 NC VCC /RESET 5 6 7 8 16-Pin MLF™ (MLF-16) PIN DESCRIPTION Pin Number Pin Name Pin Function 12, 9 IN, /IN 1, 2, 3, 4 Q0, /Q0 Q1, /Q1 16, 15, 5 S0, S1, S2 6 NC 8 /RESET, /DISABLE LVTTL/CMOS Logic Levels: Internal 25kΩ pull-up resistor. Logic HIGH if left unconnected. Apply LOW to reset the divider (divided by 2, 4, 8 or 16 mode). Also acts as a disable/enable function. The reset and disable function occurs on the next high-to-low clock input transition. Input threshold is VCC/2. 10 VREF-AC Reference Voltage: Equal to VCC–1.4V (approx.). Used for AC-coupled applications only. Decouple the VREF–AC pin with a 0.01µF capacitor. See “Input Interface Applications” section. 11 VT 7, 14 VCC 13 GND Exposed Differential Input: Internal 50Ω termination resistors to VT input. Flexible input accepts any differential input. See “Input Interface Applications” section. Differential Buffered LVDS Outputs: Divided by 1, 2, 4, 8 or 16. See “Truth Table.” Unused output pairs must be terminated with 100Ω across the different pair. Select Pins: See “Truth Table.” LVTTL/CMOS logic levels. Internal 25kΩ pull-up resistor. Logic HIGH if left unconnected (divided by 16 mode.) Input threshold is VCC/2. No Connect. Termination Center-Tap: For CML or LVDS inputs, leave this pin floating. Otherwise, See Figures 4a to 4f, “Input Interface Applications” section. Positive Power Supply: Bypass with 0.1µF//0.01µF low ESR capacitor. Ground. Exposed pad must be connected to the same potential as the GND pin. TRUTH TABLE /RESET(1) S2 S1 S0 Outputs 1 0 X X Reference Clock (pass through) 1 1 0 0 Reference Clock ÷2 1 1 0 1 Reference Clock ÷4 1 1 1 0 Reference Clock ÷8 1 1 1 1 Reference Clock ÷16 0(1) X X X Q = LOW, /Q = HIGH Clock Disable Note 1. Reset/Disable function is asserted on the next clock input (IN, /IN) high-to-low transition. 2 Precision Edge™ SY89875U Micrel Absolute Maximum Ratings(Note 1) Operating Ratings(Note 2) Supply Voltage (VCC) .................................. –0.5V to +4.0V Input Voltage (VIN) .................................. –0.5V to VCC+0.3 ECL Output Current (IOUT) Continuous ......................................................... 50mA Surge ................................................................ 100mA Input Current IN, /IN (IIN) .......................................... ±50mA VT Current (IVT) ...................................................... ±100mA VREF-AC Sink/Source Current (IVREF-AC), Note 3 ....... ±2mA Lead Temperature (soldering 10 sec.) ...................... 220°C Storage Temperature (TS) ....................... –65°C to +150°C Supply Voltage (VCC) ........................................ +2.5V ±5% Ambient Temperature (TA) ......................... –40°C to +85°C Package Thermal Resistance MLF™ (θJA) Still-Air ............................................................. 60°C/W 500lfpm ............................................................ 54°C/W MLF™ (ψJB), Note 4 Junction-to-Board ............................................ 32°C/W Note 1. Note 2. Note 3. Note 4. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to ABSOLUTE MAXIMUM RATlNG conditions for extended periods may affect device reliability. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. Due to the limited drive capability use for input of the same package only. Junction-to-board resistance assumes exposed pad is soldered (or equivalent) to the device’s most negative potential on the PCB. DC ELECTRICAL CHARACTERISTICS(Notes 1, 2) TA= –40°C to +85°C; Unless otherwise stated. Symbol Parameter VCC Power Supply ICC Power Supply Current RIN Differential Input Resistance (IN, /IN) VIH Input High Voltage (IN, /IN) VIL Max Units 2.625 V 70 95 mA 80 100 120 Ω Note 3 0.1 – VCC+0.3 V Input Low Voltage (IN, /IN) Note 3 –0.3 – VCC+0.2 V VIN Input Voltage Swing Note 4 – 1.8 V VDIFF_IN Differential Input Voltage Swing Note 5 0.1 – 3.6 V |IIN| Input Current (IN, /IN) Note 3 – – 45 mA VREF–AC Reference Voltage Note 6 Note 1. Note 2. Note 3. Note 4. Note 5. Note 6. Condition Min Typ 2.375 No load, max. VCC VCC–1.525 VCC–1.425 VCC–1.325 V The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. Specification for packaged product only. Due to the internal termination (see Figure 2a) the input current depends on the applied voltages at IN, /IN and VT inputs. Do not apply a combination of voltages that causes the input current to exceed the maximum limit! See “Timing Diagram” for VIN definition. VIN (Max) is specified when VT is floating. See “Typical Operating Characteristics” section for VDIFF definition. Operating using VIN is limited to AC-coupled PECL or CML applications only. Connect directly to VT pin. 3 Precision Edge™ SY89875U Micrel LVDS DC ELECTRICAL CHARACTERISTICS(Notes 1, 2) VCC = 2.5V ±5%; TA = –40°C to +85°C; Unless otherwise stated. Symbol Parameter Condition Min Typ Max Units VOUT Output Voltage Swing Note 3, 4 250 350 400 mV VOH Output High Voltage Note 3 1.475 V VOL Output Low Voltage Note 3 0.925 VOCM Output Common Mode Voltage Note 4 1.125 1.375 V ∆VOCM Change in Common Mode Voltage –50 50 mV Note 1. Note 2. Note 3. Note 4. V The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. Specification for packaged product only. Measured as per Figure 2a, 100Ω across Q and /Q outputs. Measured as per Figure 2b. LVTTL/CMOS DC ELECTRICAL CHARACTERISTICS(Notes 1, 2) VCC = 2.5V ±5%; TA = –40°C to +85°C; Unless otherwise stated. Symbol Parameter VIH Input HIGH Voltage VIL Input LOW Voltage IIH Input HIGH Current IIL Input LOW Current Note 1. Note 2. Condition Min Typ Max 2.0 V 0.8 V 20 µA –300 µA –125 The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. Specification for packaged product only. 4 Units Precision Edge™ SY89875U Micrel AC ELECTRICAL CHARACTERISTICS(Notes 1, 2) VCC = 2.5V ±5%; TA = –40°C to +85°C; Unless otherwise stated. Symbol Parameter Condition Min Typ fMAX Maximum Input Frequency Output Swing ≥ 200mV 2.0 2.5 tPLH tPHL Differential Propagation Delay IN to Q Input Swing < 400mV 590 690 870 ps Input Swing ≥ 400mV 540 690 820 ps tSKEW Within-Device Skew (diff.) Note 3 5 15 ps Part-to-Part Skew (diff.) Note 3 280 ps tRR Reset Recovery Time Note 4 tJITTER Cycle-to-Cycle Jitter Note 5 1 ps(rms) Total Jitter Note 6 10 ps(pk-pk) tr,tf Note 1. Note 2. Note 3. Note 4. Note 5. Note 6. Max GHz 600 Rise/Fall Time (20% to 80%) 70 Units ps 120 200 ps Measured with 400mV input signal, 50% duty cycle, all outputs loaded with 100Ω across each output pair, unless otherwise stated. Specification for packaged product only. Skew is measured between outputs under identical transitions. See “Timing Diagram.” Cycle-to-cycle jitter definition: the variation in period between adjacent cycles over a random sample of adjacent cycle pairs. Tjitter_cc = Tn–Tn+1, where T is the time between rising edges of the output signal. Total jitter definition: with an ideal clock input of frequency ≤ fMAX, no more than one output edge in 1012 output edges will deviate by more than the specified peak-to-peak jitter value. TIMING DIAGRAM /RESET VCC/2 tRR IN VID /IN VIN Swing tPD /Q VOUT Swing Q 5 Precision Edge™ SY89875U Micrel TYPICAL OPERATING CHARACTERISTICS VCC = 2.5V, TA = 25°C, unless otherwise stated. Output Amplitude vs. Frequency 800 PROPAGATION DELAY (ps) 350 AMPLITUDE (mV) 300 250 200 150 100 50 0 0 750 700 650 600 550 500 0 500 100015002000250030003500 FREQUENCY (MHz) 200 400 600 800 1000 INPUT SWING (mV) IN to Q Propagation Delay vs. Temperature 60 OUTPUT DUTY CYCLE (mV) PROPAGATION DELAY (ps) 800 IN to Q Propagation Delay vs. Input Swing 750 700 650 600 550 500 -60 -40 -20 0 20 40 60 80 100 TEMPERATURE (°C) 55 50 45 40 0 6 Output Duty Cycle vs. Frequency 500 1000 1500 2000 2500 3000 FREQUENCY (MHz) Precision Edge™ SY89875U Micrel TYPICAL OPERATING CHARACTERISTICS (Continued) VCC = 2.5V, TA = 25°C, unless otherwise stated. 622MHz Output Output Swing (50mV/div.) Output Swing (50mV/div.) 1.25GHz Output TIME (300ps/div.) TIME (140ps/div.) Output Swing (50mV/div.) 2.5GHz Output TIME (80ps/div.) DEFINITION OF SINGLE-ENDED AND DIFFERENTIAL SWINGS VDIFF_IN, VDIFF_OUT 700mV (typical) VIN, VOUT 350mV (typical) Figure 1b. Differential Swing Figure 1a. Single-Ended Swing 7 Precision Edge™ SY89875U Micrel INPUT INTERFACE APPLICATIONS VCC VCC 1.86k 1.86k 1.86k 25kΩ R S0 S1 S2 /RESET 1.86k R IN 50Ω VT 50Ω GND GND /IN Figure 2b. Simplified TTL/CMOS Input Buffer Figure 2a. Simplified Differential Input Buffer LVDS OUTPUTS LVDS (Low Voltage Differential Swing) specifies a small swing of 350mV typical, on a nominal 1.25V common mode above ground. The common mode voltage has tight limits to permit large variations in ground between an LVDS driver and receiver. Also, change in common mode voltage, as a function of data input, is also kept tight, to keep EMI low. 50Ω vOD vOH, vOL 100Ω vOH, vOL 50Ω GND vOCM, ∆vOCM GND Figure 3b. LVDS Common Mode Measurement Figure 3a. LVDS Differential Measurement 8 Precision Edge™ SY89875U Micrel INPUT INTERFACE APPLICATIONS VCC VCC VCC VCC IN IN CML PECL /IN /IN GND VT NC /IN SY89875U SY89875U NC VCC IN CML GND VCC SY89875U GND VT VCC 0.01 VREF_AC VREF_AC m VCC Ð2V F 39 VCC VCC W VREF_AC NC 0.01µF Figure 4a. DC-Coupled CML Input Interface VT Figure 4b. AC-Coupled CML Input Interface Figure 4c. DC-Coupled PECL Input Interface VCC VCC VCC VCC IN IN IN PECL LVDS /IN /IN 50 HSTL W 50 W /IN SY89875U SY89875U SY89875U GND VCC VT GND NC VT NC VREF_AC VT NC GND GND VREF_AC GND 0.01µF Figure 4d. AC-Coupled CML Input Interface VREF_AC Figure 4e. LVDS Input Interface Figure 4f. HSTL Input Interface RELATED PRODUCT AND SUPPORT DOCUMENTATION Part Number Function Data Sheet Link SY89872U 2.5V, 2.5GHz Any Diff. In-to-LVDS Programmable Clock Divider/Fanout Buffer w/ Internal Termination http://www.micrel.com/product-info/products/sy89872u.shtml MLF™ Application Note http://www.amkor.com/products/notes_papers/mlf_appnote_0902.pdf New Products and Applications http://www.micrel.com/product-info/products/solutions.shtml HBW Solutions 9 Precision Edge™ SY89875U Micrel 16 LEAD MicroLeadFrame™ (MLF-16) 0.85 0.42 +0.18 –0.18 0.23 +0.07 –0.05 +0.15 –0.65 0.01 +0.04 –0.01 3.00BSC 1.60 +0.10 –0.10 0.65 +0.15 –0.65 0.42 0.20 REF. 2.75BSC PIN 1 ID +0.18 –0.18 N 16 1 1 0.50 DIA 2 2 2.75BSC 3.00BSC 3 3 1.60 +0.10 –0.10 4 4 12° max 0.5 BSC 0.42 +0.18 –0.18 SEATING PLANE 0.40 +0.05 –0.05 1.5 REF BOTTOM VIEW TOP VIEW CC 0.23 +0.07 –0.05 CL 4 0.01 +0.04 –0.01 SECTION "C-C" SCALE: NONE 0.5BSC 1. 2. 3. 4. DIMENSIONS ARE IN mm. DIE THICKNESS ALLOWABLE IS 0.305mm MAX. PACKAGE WARPAGE MAX 0.05mm. THIS DIMENSION APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.20mm AND 0.25mm FROM TIP. 5. APPLIES ONLY FOR TERMINALS FOR EVEN TERMINAL/SIDE Rev. 02 Package EP- Exposed Pad Die CompSide Island Heat Dissipation Heat Dissipation VEE Heavy Copper Plane VEE Heavy Copper Plane PCB Thermal Consideration for 16-Pin MLF™ Package (Always solder, or equivalent, the exposed pad to the PCB) Package Notes: Note 1. Note 2. MICREL, INC. TEL Package meets Level 2 moisture sensitivity classification, and are shipped in dry-pack form. Exposed pads must be soldered to a ground for proper thermal management. 1849 FORTUNE DRIVE SAN JOSE, CA 95131 USA + 1 (408) 944-0800 FAX + 1 (408) 944-0970 WEB http://www.micrel.com The information furnished by Micrel in this datasheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. © 2003 Micrel, Incorporated. 10